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authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>2016-11-07 02:20:02 +0100
committerThomas Petazzoni <thomas.petazzoni@free-electrons.com>2016-11-23 22:10:56 +0100
commit21cb9d4c8adb65ccfd64ed82ddff23e9fae4595d (patch)
treea96c51b634935a50baa50f15a36bb3fe8d820e96 /toolchain/toolchain-external/toolchain-external-linaro-arm/Config.in
parentf0f2498c7f4e0b6cb6afeb752d885bf9ea821b83 (diff)
downloadbuildroot-21cb9d4c8adb65ccfd64ed82ddff23e9fae4595d.tar.gz
buildroot-21cb9d4c8adb65ccfd64ed82ddff23e9fae4595d.zip
toolchain-external-linaro-arm: new package
This commit adds a new package for the Linaro external toolchain for the ARM architecture. The legacy implementation is removed. The comment about availability is duplicated for arm and armeb. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Romain Naour <romain.naour@gmail.com> Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be> Reviewed-by: Romain Naour <romain.naour@gmail.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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+comment "Linaro toolchains available for Cortex-A + EABIhf"
+ depends on BR2_arm
+ depends on !BR2_ARM_CPU_ARMV7A || !BR2_ARM_EABIHF
+ depends on !BR2_STATIC_LIBS
+
+config BR2_TOOLCHAIN_EXTERNAL_LINARO_ARM
+ bool "Linaro ARM 2016.05"
+ depends on BR2_arm
+ depends on BR2_ARM_CPU_ARMV7A
+ depends on BR2_HOSTARCH = "x86_64" || BR2_HOSTARCH = "x86"
+ depends on BR2_ARM_EABIHF
+ depends on !BR2_STATIC_LIBS
+ select BR2_TOOLCHAIN_EXTERNAL_GLIBC
+ select BR2_TOOLCHAIN_HAS_SSP
+ select BR2_TOOLCHAIN_HAS_NATIVE_RPC
+ select BR2_INSTALL_LIBSTDCPP
+ select BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_0
+ select BR2_TOOLCHAIN_GCC_AT_LEAST_5
+ select BR2_TOOLCHAIN_HAS_FORTRAN
+ help
+ Linaro toolchain for the ARM architecture. It uses Linaro
+ GCC 2016.05 (based on gcc 5.3.1), Linaro GDB 2016.05 (based on
+ GDB 7.11.1), glibc 2.21, Binutils 2016.05 (based on 2.25). It
+ generates code that runs on all Cortex-A profile devices,
+ but tuned for the Cortex-A9. The code generated is Thumb 2,
+ with the hard floating point calling convention, and uses
+ the VFPv3-D16 FPU instructions.
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