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| author | Vicente Olivert Riera <Vincent.Riera@imgtec.com> | 2017-06-28 16:17:11 +0100 |
|---|---|---|
| committer | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2017-07-16 16:45:22 +0200 |
| commit | 9a0a0a976bc1094719556065ab5e982c6ca27563 (patch) | |
| tree | 4cfa0f640d7a0e4e6642a4c603d5dd4f7d7bec48 /package/gcc | |
| parent | 2d8f3fc430fe4f16c570097cf3dc33aa78ccb702 (diff) | |
| download | buildroot-9a0a0a976bc1094719556065ab5e982c6ca27563.tar.gz buildroot-9a0a0a976bc1094719556065ab5e982c6ca27563.zip | |
arch/mips: add support for MIPS32 FP mode
MIPS32 support different FP modes (32,xx,64), so give the user the
opportunity to choose between them. That will cause host-gcc to be built
using the --with-fp-32=[32|xx|64] configure option. Also the
-mfp[32|xx|64] gcc option will be added to TARGET_CFLAGS and to the
toolchain wrapper.
FP mode option shouldn't be used for soft-float, so we add logic in the
toolchain wrapper if -msoft-float is among the arguments in order to not
append the -fp[[32|xx|64] option, otherwise the compilation may fail.
Information about FP modes here:
- https://sourceware.org/binutils/docs/as/MIPS-Options.html
- https://dmz-portal.imgtec.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking#5._Generating_modeless_code
Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Diffstat (limited to 'package/gcc')
| -rw-r--r-- | package/gcc/gcc.mk | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/package/gcc/gcc.mk b/package/gcc/gcc.mk index 7a62f4f7fc..67d3343efe 100644 --- a/package/gcc/gcc.mk +++ b/package/gcc/gcc.mk @@ -213,6 +213,9 @@ endif ifneq ($(call qstrip,$(BR2_GCC_TARGET_NAN)),) HOST_GCC_COMMON_CONF_OPTS += --with-nan=$(BR2_GCC_TARGET_NAN) endif +ifneq ($(call qstrip,$(BR2_GCC_TARGET_FP32_MODE)),) +HOST_GCC_COMMON_CONF_OPTS += --with-fp-32=$(BR2_GCC_TARGET_FP32_MODE) +endif ifneq ($(call qstrip,$(BR2_GCC_TARGET_CPU)),) ifneq ($(call qstrip,$(BR2_GCC_TARGET_CPU_REVISION)),) HOST_GCC_COMMON_CONF_OPTS += --with-cpu=$(call qstrip,$(BR2_GCC_TARGET_CPU)-$(BR2_GCC_TARGET_CPU_REVISION)) @@ -264,6 +267,7 @@ endif HOST_GCC_COMMON_WRAPPER_TARGET_ARCH := $(call qstrip,$(BR2_GCC_TARGET_ARCH)) HOST_GCC_COMMON_WRAPPER_TARGET_ABI := $(call qstrip,$(BR2_GCC_TARGET_ABI)) HOST_GCC_COMMON_WRAPPER_TARGET_NAN := $(call qstrip,$(BR2_GCC_TARGET_NAN)) +HOST_GCC_COMMON_WRAPPER_TARGET_FP32_MODE := $(call qstrip,$(BR2_GCC_TARGET_FP32_MODE)) HOST_GCC_COMMON_WRAPPER_TARGET_FPU := $(call qstrip,$(BR2_GCC_TARGET_FPU)) HOST_GCC_COMMON_WRAPPER_TARGET_FLOAT_ABI := $(call qstrip,$(BR2_GCC_TARGET_FLOAT_ABI)) HOST_GCC_COMMON_WRAPPER_TARGET_MODE := $(call qstrip,$(BR2_GCC_TARGET_MODE)) @@ -280,6 +284,9 @@ endif ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_NAN),) HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_NAN='"$(HOST_GCC_COMMON_WRAPPER_TARGET_NAN)"' endif +ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_FP32_MODE),) +HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_FP32_MODE='"$(HOST_GCC_COMMON_WRAPPER_TARGET_FP32_MODE)"' +endif ifneq ($(HOST_GCC_COMMON_WRAPPER_TARGET_FPU),) HOST_GCC_COMMON_TOOLCHAIN_WRAPPER_ARGS += -DBR_FPU='"$(HOST_GCC_COMMON_WRAPPER_TARGET_FPU)"' endif |
