From 40194fa7f34b2130afe4be5d02b41cd56be0f3a5 Mon Sep 17 00:00:00 2001 From: Rodrigo Alejandro Melo Date: Sun, 12 Feb 2017 21:37:55 -0300 Subject: Added analysis of examples with GHDL Some examples were corrected according GHDL complains. Corresponding traslated_examples were modified. Use of synopsys libraries was removed. Translation of gh_fifo_async16_sr.vhd fails (complains about 'unsigned'). The problem was comented. --- examples/ifchain.vhd | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'examples/ifchain.vhd') diff --git a/examples/ifchain.vhd b/examples/ifchain.vhd index 651947a..dbc0a98 100644 --- a/examples/ifchain.vhd +++ b/examples/ifchain.vhd @@ -1,9 +1,11 @@ LIBRARY IEEE; -USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all; +USE IEEE.std_logic_1164.all; + entity test is port( clk, rstn : in std_logic ); end test; + architecture rtl of test is type t is array (3 downto 0) of std_logic_vector(31 downto 0); signal a : std_logic_vector(3 downto 0); @@ -11,12 +13,13 @@ architecture rtl of test is signal status : std_logic; signal c : t; begin + process(clk) begin if clk'event and clk = '1' then if b(1) & a(3 downto 2) = "001" then - status <= "1"; - c(0) <= x"FFFF"; - end if; + status <= '1'; + c(0) <= x"FFFFFFFF"; + end if; end if; end process; -- cgit v1.2.1