From 9023ec57a1d34bffd6d331a26877dacd37d5ca4f Mon Sep 17 00:00:00 2001 From: Rodrigo Alejandro Melo Date: Tue, 21 Nov 2017 13:22:39 -0300 Subject: Experimental support of exponentiation --- examples/expr.vhd | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'examples/expr.vhd') diff --git a/examples/expr.vhd b/examples/expr.vhd index 81e8ab1..827c433 100644 --- a/examples/expr.vhd +++ b/examples/expr.vhd @@ -2,15 +2,20 @@ library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -entity expr is port( reset, sysclk, ival : in std_logic); +entity expr is +generic(SIZE: positive:=2**8-1); +port(reset, sysclk, ival : in std_logic); end expr; + architecture rtl of expr is + constant SIZE_OF : positive:=2**8-1; signal foo : std_logic_vector(13 downto 0); signal baz : std_logic_vector(2 downto 0); signal bam : std_logic_vector(22 downto 0); signal out_i : std_logic_vector(5 downto 3); signal input_status : std_logic_vector(8 downto 0); signal enable, debug, aux, outy, dv, value : std_logic; + signal expo : std_logic_vector(2**3-1 downto 0); begin -- drive input status input_status <= -- top bits @@ -36,4 +41,6 @@ begin bam(foo'range) <= foo; end if; end process; + + --expo <= std_logic_vector(to_unsigned(2**4, 2**8)); end rtl; -- cgit v1.2.1