From 436f8a18014bc0614e3181ee1fd2679d682eea07 Mon Sep 17 00:00:00 2001
From: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
Date: Fri, 24 Nov 2017 13:27:34 -0300
Subject: Implemented a mechanism to exclude files in the main Makefile

---
 Makefile | 31 ++++++++++++++++++++-----------
 1 file changed, 20 insertions(+), 11 deletions(-)

(limited to 'Makefile')

diff --git a/Makefile b/Makefile
index 0c29395..666dae0 100644
--- a/Makefile
+++ b/Makefile
@@ -1,29 +1,38 @@
 #!/usr/bin/make
 
-VHDLS  = $(wildcard examples/*.vhd)
-VHDLS := $(notdir $(VHDLS))
-VHDLS := $(filter-out todo.vhd,$(VHDLS))
+TEMP     = temp
+
+EXCLUDE  = $(shell cat examples/.exclude)
+EXCLUDE := $(basename $(EXCLUDE))
+EXCLUDE := $(addsuffix .vhd,$(EXCLUDE))
+
+VHDLS    = $(wildcard examples/*.vhd)
+VHDLS   := $(notdir $(VHDLS))
+
+ifndef WIP
+VHDLS   := $(filter-out $(EXCLUDE),$(VHDLS))
+DIFFOPT  = --exclude-from=examples/.exclude
+else
+DIFFOPT  = --exclude=Makefile
+endif
 
 all: diff
 
 translate:
 	@make -C src
 	@make -C examples
-	@mkdir -p temp/verilog
+	@rm -fr $(TEMP)/verilog
+	@mkdir $(TEMP)/verilog
 	@echo "##### Translating Examples #####################################"
 	@cd examples; $(foreach VHDL,$(VHDLS), echo "Translating: $(VHDL)";\
-	../src/vhd2vl --quiet $(VHDL) ../temp/verilog/$(basename $(VHDL)).v;)
+	../src/vhd2vl --quiet $(VHDL) ../$(TEMP)/verilog/$(basename $(VHDL)).v;)
 	@make -C translated_examples
 
 diff: translate
 	@echo "##### Diff #####################################################"
-	diff -u --exclude=Makefile translated_examples temp/verilog
+	diff -u $(DIFFOPT) translated_examples $(TEMP)/verilog
 	@echo "PASS"
 
-todo:
-	@make -C src
-	src/vhd2vl --quiet examples/todo.vhd temp/todo.v
-
 clean:
 	make -C src clean
-	rm -fr temp
+	rm -fr $(TEMP)
-- 
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