From 5857951169357d6ad64aac9dee3f864d4fddf65b Mon Sep 17 00:00:00 2001
From: Rodrigo Alejandro Melo <rmelo@inti.gob.ar>
Date: Fri, 1 Dec 2017 17:51:10 -0300
Subject: Added support for REM

It works as MOD. MOD is bad implemented, but useful when the two operand
has the same sign.
---
 examples/genericmap.vhd          | 2 +-
 examples/todo.vhd                | 9 ++-------
 src/vhd2vl.l                     | 1 +
 src/vhd2vl.y                     | 5 +++--
 translated_examples/genericmap.v | 2 +-
 5 files changed, 8 insertions(+), 11 deletions(-)

diff --git a/examples/genericmap.vhd b/examples/genericmap.vhd
index 876f159..3038f88 100644
--- a/examples/genericmap.vhd
+++ b/examples/genericmap.vhd
@@ -3,7 +3,7 @@ USE IEEE.std_logic_1164.all;
 entity genericmap is
 generic(
   rst_val   : std_logic := '0';
-  thing_size: integer := 201;
+  thing_size: integer := 201 rem 2;
   bus_width : integer := 201 mod 32);
 port(
   clk, rstn : in std_logic;
diff --git a/examples/todo.vhd b/examples/todo.vhd
index a5d4de5..7b05d2a 100644
--- a/examples/todo.vhd
+++ b/examples/todo.vhd
@@ -20,9 +20,6 @@ architecture rtl of todo is
    signal int : integer;
    signal uns : unsigned(7 downto 0);
 
-   -- unexpected NAME at "rem"
-   --constant VALUE : positive := 9 rem 2;
-
    constant BYTES  : positive:=4;
    constant WIDTH  : positive:=BYTES*8;
    signal index    : natural range 0 to BYTES-1;
@@ -30,8 +27,8 @@ architecture rtl of todo is
 
    -- (others => (others => '0')) must be replaced by an initial block with a for
    -- or something similar.
-   type ff_array is array (0 to 255) of std_logic_vector(7 downto 0);
-   signal data_r : ff_array :=(others => (others => '0'));
+   --type ff_array is array (0 to 255) of std_logic_vector(7 downto 0);
+   --signal data_r : ff_array :=(others => (others => '0'));
 begin
    --**************************************************************************
    -- Wrong translations
@@ -69,8 +66,6 @@ begin
 --        i => "00000000" & X"11", -- But here fail
 --        o => open
 --      );
-   -- unexpected NAME, expecting WHEN or ';'
-   --int <= 9 rem 2;
    -- Unsupported generate with boolean?
 --   in_by_level:
 --   if INBYLEVEL generate
diff --git a/src/vhd2vl.l b/src/vhd2vl.l
index 9719206..36ac4ee 100644
--- a/src/vhd2vl.l
+++ b/src/vhd2vl.l
@@ -126,6 +126,7 @@ int scan_int(char *s);
 "xor" { return XOR; }
 "xnor" { return XNOR; }
 "mod" { return MOD; }
+"rem" { return RW_REM; }
 "**" { return POW; }
 "event" { return EVENT; }
 "rising_edge" { return POSEDGE;}
diff --git a/src/vhd2vl.y b/src/vhd2vl.y
index 682c802..41d6b80 100644
--- a/src/vhd2vl.y
+++ b/src/vhd2vl.y
@@ -867,7 +867,7 @@ slist *emit_io_list(slist *sl)
 %token <txt> SELECT OTHERS PROCESS VARIABLE CONSTANT
 %token <txt> IF THEN ELSIF ELSE CASE WHILE
 %token <txt> FOR LOOP GENERATE
-%token <txt> AFTER AND OR XOR MOD POW
+%token <txt> AFTER AND OR XOR MOD RW_REM POW
 %token <txt> LASTVALUE EVENT POSEDGE NEGEDGE
 %token <txt> STRING NAME RANGE NULLV OPEN
 %token <txt> CONVFUNC_1 CONVFUNC_2 BASED FLOAT LEFT
@@ -906,7 +906,7 @@ slist *emit_io_list(slist *sl)
 %left XOR
 %left XNOR
 %left AND
-%left MOD
+%left MOD RW_REM
 /* Comparison: */
 %left '<'  '>'  BIGEQ  LESSEQ  NOTEQ  EQUAL
 %left  '+'  '-'  '&'
@@ -2357,6 +2357,7 @@ expr : signal {
      | expr '*' expr {$$=addexpr($1,'*'," * ",$3);}
      | expr '/' expr {$$=addexpr($1,'/'," / ",$3);}
      | expr MOD expr {$$=addexpr($1,'%'," % ",$3);}
+     | expr RW_REM expr {$$=addexpr($1,'%'," % ",$3);}
      | NOT expr {$$=addexpr(NULL,'~'," ~",$2);}
      | expr AND expr {$$=addexpr($1,'&'," & ",$3);}
      | expr OR expr {$$=addexpr($1,'|'," | ",$3);}
diff --git a/translated_examples/genericmap.v b/translated_examples/genericmap.v
index 37bc95d..4214c40 100644
--- a/translated_examples/genericmap.v
+++ b/translated_examples/genericmap.v
@@ -27,7 +27,7 @@ output wire eno
 );
 
 parameter rst_val=1'b0;
-parameter [31:0] thing_size=201;
+parameter [31:0] thing_size=201 % 2;
 parameter [31:0] bus_width=201 % 32;
 // Outputs
 
-- 
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