From 286f3665632a2fae3c84179cca173cfbda23b390 Mon Sep 17 00:00:00 2001 From: Rodrigo Alejandro Melo Date: Thu, 16 Feb 2017 11:56:53 -0300 Subject: File names changed to be more GitHub friendly * changes -> CHANGELOG.md * GPLv2.txt -> LICENSE * README.txt -> README.md --- CHANGELOG.md | 130 +++++++++++++++++++++++ GPLv2.txt | 339 ----------------------------------------------------------- LICENSE | 339 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ README.md | 111 +++++++++++++++++++ README.txt | 111 ------------------- changes | 130 ----------------------- 6 files changed, 580 insertions(+), 580 deletions(-) create mode 100644 CHANGELOG.md delete mode 100644 GPLv2.txt create mode 100644 LICENSE create mode 100644 README.md delete mode 100644 README.txt delete mode 100644 changes diff --git a/CHANGELOG.md b/CHANGELOG.md new file mode 100644 index 0000000..95fcb08 --- /dev/null +++ b/CHANGELOG.md @@ -0,0 +1,130 @@ +Changes 2.4 to 2.5 (Larry Doolittle, September 2015) + +Coding: + * Use $(CC) in makefile + * Trivial fix to yacc grammar, was causing FTBFS with recent bison + * Eliminate a couple of unused variables + + +Changes 2.3 to 2.4 (Larry Doolittle, November 2010) + +Grammar: + * drop DOS-style returns at end of comments + * allow FLOAT in expressions (maybe a mistake) + * fixed regression in "others" handling since 2.1 + * don't crash with "others" in instantiation (Verilog result is still broken) + (the following were submitted by Shankar Giri) + * Verilog 2001 module declaration (runtime selectable, use -g2001) + * named generate block support for XST compatibility + * support for array of vectors + * some generic enhancements on architecture body + +Coding: + * CLI enhancement (added more switches) + * factor out push_clkedge(), pull_clkedge() + * fully const-correct + * minor whitespace and coding style cleanup + + +Changes 2.2 to 2.3 (Larry Doolittle, May 2010) + +Grammar: + * add array type (not well tested) + * add octal strings (O"777") + * add one more "rem" + * accept octal and hex strings as "when" values + * accept constants, bit ranges, and "open" in port mappings + * accept a single un-named generic map item + * accept conv_integer function, treated as a no-op + * accept ports with default values, but ignore default and give a warning + * accept integer ranges, but ignore the range and give a warning + +Coding: + * list def.h properly in makefile + * factor out new_vrange(), addnest(), setup_port() + + +Changes 1.2 to 2.2 (Larry Doolittle, February 2009) + +Merge extensive changes from Mark Gonzales' version 2.0. Thanks, Mark! + +Grammar: + * add XNOR + * add hex strings (X"f0f0") + * remove UNIT reserved words, and actually emit timescale directive + * case statements without "when others" + * add a few more "rem"s to the grammar + * add resize to the CONVFUNC_2 list + * handle one-bit enumeration bit range correctly (no more [0]) + * some gratuitous changes in output whitespace + +Coding: + * clean up GENERIC pattern + * debug and clean up slist routines and their usage + * wrap malloc with xmalloc to exit if out of memory + * update Free Software Foundation address + + +Changes 2.0 to 2.1 (Steve Haynal, unreleased?) + +Presumably useful to Steve, but everything is too strange or scary +for me (Larry Doolittle) to understand and incorporate. Sorry, Steve, +maybe I'll get something from your work on my next iteration. People +interested in the following features (incomplete list) should contact +the developers directly: + * lower-cased identifiers in translated Verilog + * parses VHDL packages + * parses many VHDL functions and macros + * floating-point "after" construct parsed but ignored + + +Changes 1.0 to 2.0 (Mark Gonzales, June 2006) + +Grammar: + * FOR LOOP + * FOR GENERATE and IF GENERATE + * natural, integer, time types + * based numbers (16#55aa#) + * expressions can now include VHDL type conversion functions, mod operator, numbers + * now can tolerate comments in the middle of expressions + * expressions can now be used in subscripts and vector range definitions + * width on (others => 'x') can now be an expression + * uses always @(*) when creating some combinational always blocks + * variable initialization support + * constant can be initialized by an expression + * GENERIC definitions for entity are now translated into Verilog + parameter definitions, and GENERIC MAPs on instances are translated + into Verilog in-line explicit parameter definitions. + * allow entity declarations and architectures in separate files + +Operation: + * new -d option for trace parse - to debug grammar errors + +Coding: + * introduce slist data structure to build resulting Verilog + + +Changes 1.0 to 1.2 (Larry Doolittle, May 2005) + +Grammar: + * allow NATURAL as an expression terminal symbol + * allow (name'event and exprc) as process sensitivity + * allow IS syntactic sugar in COMPONENT declaration + * add a bunch of "rem"s to the grammar + * handle inout better + * treat "signed", "unsigned", "boolean" as synonyms for "std_logic" and "std_logic_vector" + +Operation: + * more complete handling of argc/argv + * if error happened, return 1 from main and remove incorrect/incomplete output files + * avoid insinuating that output Verilog is covered by GPL + +Coding: + * increase gcc warning level + * add required #includes + * remove spurious commas in bison token lists + * drop worthless malloc() casts; see C-faq/q7.7 + * prototype yylex and yyerror + * add braces around confusing if/else chain + +Original 1.0 (Vincenzo Liguori, February 2001) diff --git a/GPLv2.txt b/GPLv2.txt deleted file mode 100644 index d511905..0000000 --- a/GPLv2.txt +++ /dev/null @@ -1,339 +0,0 @@ - GNU GENERAL PUBLIC LICENSE - Version 2, June 1991 - - Copyright (C) 1989, 1991 Free Software Foundation, Inc., - 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The licenses for most software are designed to take away your -freedom to share and change it. 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The Free Software Foundation may publish revised and/or new versions +of the General Public License from time to time. Such new versions will +be similar in spirit to the present version, but may differ in detail to +address new problems or concerns. + +Each version is given a distinguishing version number. If the Program +specifies a version number of this License which applies to it and "any +later version", you have the option of following the terms and conditions +either of that version or of any later version published by the Free +Software Foundation. If the Program does not specify a version number of +this License, you may choose any version ever published by the Free Software +Foundation. + + 10. If you wish to incorporate parts of the Program into other free +programs whose distribution conditions are different, write to the author +to ask for permission. For software which is copyrighted by the Free +Software Foundation, write to the Free Software Foundation; we sometimes +make exceptions for this. Our decision will be guided by the two goals +of preserving the free status of all derivatives of our free software and +of promoting the sharing and reuse of software generally. + + NO WARRANTY + + 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY +FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN +OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES +PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED +OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS +TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE +PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, +REPAIR OR CORRECTION. + + 12. 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It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/README.md b/README.md new file mode 100644 index 0000000..dcc3b3c --- /dev/null +++ b/README.md @@ -0,0 +1,111 @@ +VHD2VL v2.5 README.txt + +Vhd2vl is designed to translate synthesizable VHDL into Verilog 2001. +It does not support the full VHDL grammar - most of the testbench +related features have been left out. See the examples and +translated_examples directories for examples of what vhd2vl can do. + +Vhd2vl does a pretty good job of translating, but you should ALWAYS +test the generated Verilog, ideally by using a formal verification +tool to compare it to the original VHDL! + +A similar but more sophisticated effort is embedded in Icarus Verilog +as vhdlpp, mostly by Maciej Suminski. If hands-free use of VHDL in a +(Icarus) Verilog environment is the goal, that's probably a better tool. +If you want to convert a bit of VHDL to Verilog, and will then maintain +that Verilog as source, vhd2vl probably makes more sense, if for no other +reason than it conserves comments. It's good that both options exist! + +The home page for (at least for this version of) vhd2vl is + http://doolittle.icarus.com/~larry/vhd2vl/ + + +1.0 HOW TO BUILD AND INSTALL vhd2vl: + +To build, just type 'make' in the src directory. + +This version of vhd2vl has been tested with GNU Bison versions 2.5 and +3.0.2, and GNU Flex versions 2.5.35 and 2.5.39. No problems have been +reported with other fairly recent versions. + +To install, copy the resulting src/vhd2vl file to someplace in +your $PATH, like $HOME/bin or /usr/local/bin. + + +2.0 HOW TO USE vhd2vl: + + vhd2vl VHDL_file.vhd > translated_file.v +or + vhd2vl VHDL_file.vhd translated_file.v +The two are equivalent when everything works. The latter has some +advantages when handling errors within a Makefile. + +There are a few options available on the command line: + -d turn on debugging within the yacc (bison) parser + -g1995 (default) use traditional Verilog module declaration style + -g2001 use Verilog-2001 module declaration style + + +3.0 TROUBLESHOOTING: + +If vhd2vl complains about a syntax error, this is usually due to a +VHDL construct that vhd2vl cannot translate. Try commenting out the +offending line, and running vhd2vl again. You can then edit the +Verilog output file and manually translate the offending line of VHDL. + +Comments in the middle of statements sometimes confuse vhd2vl. This +is a "feature" of the logic that copies comments from VHDL to Verilog. +If vhd2vl complains about a syntax error caused by a comment, just +move that comment out of the middle of the statement and try again. + +The grammar has rules that recognize common ways of writing clocked +processes. Your code might contain clocked processes that do not match +any of the templates in the grammar. This usually causes vhd2vl to +complain about a clock'event expression in a process. If this +happens, a minor rewrite of that process will let you work around the +problem. + +If you need to look at the VHDL grammar, make puts a copy of it in +vhd2vl.output. If you need to change the grammar, then running vhd2vl +with the '-d' option will cause vhd2vl to trace how it is parsing the +input file. See the bison documentation for more details. + +To test a copy of vhd2vl for regressions against the example code shipped, + mkdir test + (cd examples && for f in *.vhd; do vhd2vl $f ../test/${f%%.vhd}.v; done) + diff -u translated_examples test | less +from this directory using a Bourne-style shell. + + +4.0 MISSING FEATURES AND KNOWN INCORRECT OUTPUT: + +String types: awkward, because Verilog strings need predefined length + +Attribute: easy to parse, but I'm not sure what Verilog construct + to turn it into. It smells like a parameter, not an (* attribute *). + +Multiple actions in one process, as used in DDR logic? + +Exit statement incompletely converted to disable statement + (see examples/bigfile.vhd) + +Part select expression zz(31+k downto k) should convert to zz[31+k+:32] + (see examples/for.vhd) + +variables not handled right, show up as declarations within always blocks + (see examples/for.vhd) + +Conversion functions (resize, to_unsigned, conv_integer) are parsed, but + their semantics are ignored: resize(foo,n), to_unsigned(foo,n), and + conv_integer(foo) are treated as equivalent to (foo). + +VHDL is case insensitive, vhd2vl is case retentive, and Verilog is case + sensitive. If you're sloppy with case in the original VHDL, the + resulting Verilog will have compile-time warnings or errors. See + the comments about vhd2vl-2.1 in the changes file. + +Doesn't necessarily get clock edge sensitivities right if there is more + than one clock in the list + +Totally broken handling of text in generic mappings, as Xilinx is wont to + use for their primitives and wrappers diff --git a/README.txt b/README.txt deleted file mode 100644 index dcc3b3c..0000000 --- a/README.txt +++ /dev/null @@ -1,111 +0,0 @@ -VHD2VL v2.5 README.txt - -Vhd2vl is designed to translate synthesizable VHDL into Verilog 2001. -It does not support the full VHDL grammar - most of the testbench -related features have been left out. See the examples and -translated_examples directories for examples of what vhd2vl can do. - -Vhd2vl does a pretty good job of translating, but you should ALWAYS -test the generated Verilog, ideally by using a formal verification -tool to compare it to the original VHDL! - -A similar but more sophisticated effort is embedded in Icarus Verilog -as vhdlpp, mostly by Maciej Suminski. If hands-free use of VHDL in a -(Icarus) Verilog environment is the goal, that's probably a better tool. -If you want to convert a bit of VHDL to Verilog, and will then maintain -that Verilog as source, vhd2vl probably makes more sense, if for no other -reason than it conserves comments. It's good that both options exist! - -The home page for (at least for this version of) vhd2vl is - http://doolittle.icarus.com/~larry/vhd2vl/ - - -1.0 HOW TO BUILD AND INSTALL vhd2vl: - -To build, just type 'make' in the src directory. - -This version of vhd2vl has been tested with GNU Bison versions 2.5 and -3.0.2, and GNU Flex versions 2.5.35 and 2.5.39. No problems have been -reported with other fairly recent versions. - -To install, copy the resulting src/vhd2vl file to someplace in -your $PATH, like $HOME/bin or /usr/local/bin. - - -2.0 HOW TO USE vhd2vl: - - vhd2vl VHDL_file.vhd > translated_file.v -or - vhd2vl VHDL_file.vhd translated_file.v -The two are equivalent when everything works. The latter has some -advantages when handling errors within a Makefile. - -There are a few options available on the command line: - -d turn on debugging within the yacc (bison) parser - -g1995 (default) use traditional Verilog module declaration style - -g2001 use Verilog-2001 module declaration style - - -3.0 TROUBLESHOOTING: - -If vhd2vl complains about a syntax error, this is usually due to a -VHDL construct that vhd2vl cannot translate. Try commenting out the -offending line, and running vhd2vl again. You can then edit the -Verilog output file and manually translate the offending line of VHDL. - -Comments in the middle of statements sometimes confuse vhd2vl. This -is a "feature" of the logic that copies comments from VHDL to Verilog. -If vhd2vl complains about a syntax error caused by a comment, just -move that comment out of the middle of the statement and try again. - -The grammar has rules that recognize common ways of writing clocked -processes. Your code might contain clocked processes that do not match -any of the templates in the grammar. This usually causes vhd2vl to -complain about a clock'event expression in a process. If this -happens, a minor rewrite of that process will let you work around the -problem. - -If you need to look at the VHDL grammar, make puts a copy of it in -vhd2vl.output. If you need to change the grammar, then running vhd2vl -with the '-d' option will cause vhd2vl to trace how it is parsing the -input file. See the bison documentation for more details. - -To test a copy of vhd2vl for regressions against the example code shipped, - mkdir test - (cd examples && for f in *.vhd; do vhd2vl $f ../test/${f%%.vhd}.v; done) - diff -u translated_examples test | less -from this directory using a Bourne-style shell. - - -4.0 MISSING FEATURES AND KNOWN INCORRECT OUTPUT: - -String types: awkward, because Verilog strings need predefined length - -Attribute: easy to parse, but I'm not sure what Verilog construct - to turn it into. It smells like a parameter, not an (* attribute *). - -Multiple actions in one process, as used in DDR logic? - -Exit statement incompletely converted to disable statement - (see examples/bigfile.vhd) - -Part select expression zz(31+k downto k) should convert to zz[31+k+:32] - (see examples/for.vhd) - -variables not handled right, show up as declarations within always blocks - (see examples/for.vhd) - -Conversion functions (resize, to_unsigned, conv_integer) are parsed, but - their semantics are ignored: resize(foo,n), to_unsigned(foo,n), and - conv_integer(foo) are treated as equivalent to (foo). - -VHDL is case insensitive, vhd2vl is case retentive, and Verilog is case - sensitive. If you're sloppy with case in the original VHDL, the - resulting Verilog will have compile-time warnings or errors. See - the comments about vhd2vl-2.1 in the changes file. - -Doesn't necessarily get clock edge sensitivities right if there is more - than one clock in the list - -Totally broken handling of text in generic mappings, as Xilinx is wont to - use for their primitives and wrappers diff --git a/changes b/changes deleted file mode 100644 index 95fcb08..0000000 --- a/changes +++ /dev/null @@ -1,130 +0,0 @@ -Changes 2.4 to 2.5 (Larry Doolittle, September 2015) - -Coding: - * Use $(CC) in makefile - * Trivial fix to yacc grammar, was causing FTBFS with recent bison - * Eliminate a couple of unused variables - - -Changes 2.3 to 2.4 (Larry Doolittle, November 2010) - -Grammar: - * drop DOS-style returns at end of comments - * allow FLOAT in expressions (maybe a mistake) - * fixed regression in "others" handling since 2.1 - * don't crash with "others" in instantiation (Verilog result is still broken) - (the following were submitted by Shankar Giri) - * Verilog 2001 module declaration (runtime selectable, use -g2001) - * named generate block support for XST compatibility - * support for array of vectors - * some generic enhancements on architecture body - -Coding: - * CLI enhancement (added more switches) - * factor out push_clkedge(), pull_clkedge() - * fully const-correct - * minor whitespace and coding style cleanup - - -Changes 2.2 to 2.3 (Larry Doolittle, May 2010) - -Grammar: - * add array type (not well tested) - * add octal strings (O"777") - * add one more "rem" - * accept octal and hex strings as "when" values - * accept constants, bit ranges, and "open" in port mappings - * accept a single un-named generic map item - * accept conv_integer function, treated as a no-op - * accept ports with default values, but ignore default and give a warning - * accept integer ranges, but ignore the range and give a warning - -Coding: - * list def.h properly in makefile - * factor out new_vrange(), addnest(), setup_port() - - -Changes 1.2 to 2.2 (Larry Doolittle, February 2009) - -Merge extensive changes from Mark Gonzales' version 2.0. Thanks, Mark! - -Grammar: - * add XNOR - * add hex strings (X"f0f0") - * remove UNIT reserved words, and actually emit timescale directive - * case statements without "when others" - * add a few more "rem"s to the grammar - * add resize to the CONVFUNC_2 list - * handle one-bit enumeration bit range correctly (no more [0]) - * some gratuitous changes in output whitespace - -Coding: - * clean up GENERIC pattern - * debug and clean up slist routines and their usage - * wrap malloc with xmalloc to exit if out of memory - * update Free Software Foundation address - - -Changes 2.0 to 2.1 (Steve Haynal, unreleased?) - -Presumably useful to Steve, but everything is too strange or scary -for me (Larry Doolittle) to understand and incorporate. Sorry, Steve, -maybe I'll get something from your work on my next iteration. People -interested in the following features (incomplete list) should contact -the developers directly: - * lower-cased identifiers in translated Verilog - * parses VHDL packages - * parses many VHDL functions and macros - * floating-point "after" construct parsed but ignored - - -Changes 1.0 to 2.0 (Mark Gonzales, June 2006) - -Grammar: - * FOR LOOP - * FOR GENERATE and IF GENERATE - * natural, integer, time types - * based numbers (16#55aa#) - * expressions can now include VHDL type conversion functions, mod operator, numbers - * now can tolerate comments in the middle of expressions - * expressions can now be used in subscripts and vector range definitions - * width on (others => 'x') can now be an expression - * uses always @(*) when creating some combinational always blocks - * variable initialization support - * constant can be initialized by an expression - * GENERIC definitions for entity are now translated into Verilog - parameter definitions, and GENERIC MAPs on instances are translated - into Verilog in-line explicit parameter definitions. - * allow entity declarations and architectures in separate files - -Operation: - * new -d option for trace parse - to debug grammar errors - -Coding: - * introduce slist data structure to build resulting Verilog - - -Changes 1.0 to 1.2 (Larry Doolittle, May 2005) - -Grammar: - * allow NATURAL as an expression terminal symbol - * allow (name'event and exprc) as process sensitivity - * allow IS syntactic sugar in COMPONENT declaration - * add a bunch of "rem"s to the grammar - * handle inout better - * treat "signed", "unsigned", "boolean" as synonyms for "std_logic" and "std_logic_vector" - -Operation: - * more complete handling of argc/argv - * if error happened, return 1 from main and remove incorrect/incomplete output files - * avoid insinuating that output Verilog is covered by GPL - -Coding: - * increase gcc warning level - * add required #includes - * remove spurious commas in bison token lists - * drop worthless malloc() casts; see C-faq/q7.7 - * prototype yylex and yyerror - * add braces around confusing if/else chain - -Original 1.0 (Vincenzo Liguori, February 2001) -- cgit v1.2.1