From 1f2227ab5d4f17cb11a170e24a3cea499db1ce45 Mon Sep 17 00:00:00 2001 From: Rodrigo Alejandro Melo Date: Sun, 26 Nov 2017 10:15:11 -0300 Subject: Fixed partselect example --- examples/partselect.vhd | 4 ++-- translated_examples/partselect.v | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/examples/partselect.vhd b/examples/partselect.vhd index 564f820..86dc073 100644 --- a/examples/partselect.vhd +++ b/examples/partselect.vhd @@ -21,8 +21,8 @@ begin if rising_edge(clk_i) then big_sig(31 downto 24) <= big_sig(7 downto 0); big_var(31 downto 24) := big_var(7 downto 0); - lit_sig(i*3 to i*3+7) <= lit_sig(0 to 7); - lit_var(j*3 to j*3+8) <= lit_var(j*0 to 8+j*0); + lit_sig(i*3 to i*3+7) <= lit_sig(0 to 7); + lit_var(j*3 to j*3+8) := lit_var(j*0 to 8+j*0); -- big_sig(i*3+8 downto i*3) <= big_sig(8 downto 0); big_var(j*3+8 downto j*3) := big_var(j*0+8 downto j*0); diff --git a/translated_examples/partselect.v b/translated_examples/partselect.v index 7c8640a..11ec901 100644 --- a/translated_examples/partselect.v +++ b/translated_examples/partselect.v @@ -20,7 +20,7 @@ wire [31:0] i = 8; big_sig[31:24] <= big_sig[7:0]; big_var[31:24] = big_var[7:0]; lit_sig[i * 3 +: 7 + 1] <= lit_sig[0:7]; - lit_var[j * 3 +: 8 + 1] <= lit_var[j * 0 +: 8 + 1]; + lit_var[j * 3 +: 8 + 1] = lit_var[j * 0 +: 8 + 1]; // big_sig[i * 3 + 8 -: 8 + 1] <= big_sig[8:0]; big_var[j * 3 + 8 -: 8 + 1] = big_var[j * 0 + 8 -: 8 + 1]; -- cgit v1.2.1