| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Added support for REM | Rodrigo Alejandro Melo | 2017-12-01 | 1 | -1/+1 |
| * | Fixed scientific notation when the sign of the exponent is used | Rodrigo Alejandro Melo | 2017-12-01 | 1 | -0/+2 |
| * | Add testcase for underscore in NATURAL | Larry Doolittle | 2017-11-28 | 1 | -1/+2 |
| * | Added support to entity instantiations | Rodrigo Alejandro Melo | 2017-11-28 | 1 | -0/+4 |
| * | Don't ship translated_examples/todo.v | Larry Doolittle | 2017-11-27 | 1 | -50/+0 |
| * | Moved unsupported commented things to todo.vhd | Rodrigo Alejandro Melo | 2017-11-27 | 4 | -5/+50 |
| * | sort lists in Makefiles | Larry Doolittle | 2017-11-27 | 1 | -1/+1 |
| * | Examples: match case of module name in filename | Larry Doolittle | 2017-11-26 | 1 | -0/+0 |
| * | Renamed generic to withselect | Rodrigo Alejandro Melo | 2017-11-26 | 1 | -1/+1 |
| * | Renamed while to whileloop | Rodrigo Alejandro Melo | 2017-11-26 | 1 | -1/+1 |
| * | Renamed gh_fifo_async16_sr to fifo | Rodrigo Alejandro Melo | 2017-11-26 | 1 | -5/+4 |
| * | Renamed generate to forgen and for to forloop | Rodrigo Alejandro Melo | 2017-11-26 | 2 | -2/+2 |
| * | Merge pull request #8 from ldoolitt/exclude | Rodrigo A. Melo | 2017-11-26 | 2 | -8/+2 |
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| | * | Changed translated_examples/Makefile to analyze individually again | Rodrigo Alejandro Melo | 2017-11-26 | 1 | -6/+2 |
| | * | Simplified iverilog check | Rodrigo Alejandro Melo | 2017-11-24 | 2 | -4/+2 |
| * | | Fixed partselect example | Rodrigo Alejandro Melo | 2017-11-26 | 1 | -1/+1 |
| * | | Correct selection of -: vs. +: | Larry Doolittle | 2017-11-25 | 4 | -26/+28 |
| * | | Add missing CONVFUNC_1 to grammar | Larry Doolittle | 2017-11-24 | 1 | -1/+3 |
| * | | Turn off debug prints and fix warnings | Larry Doolittle | 2017-11-23 | 2 | -7/+16 |
| * | | First stupid attempt to finish part select | Larry Doolittle | 2017-11-23 | 4 | -30/+37 |
| * | | Added partselect example | Rodrigo Alejandro Melo | 2017-11-23 | 1 | -0/+27 |
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| * | Allow second argument to CONVFUNC_2 to be expr | Larry Doolittle | 2017-11-22 | 1 | -1/+1 |
| * | Experimental support of exponentiation | Rodrigo Alejandro Melo | 2017-11-21 | 1 | -0/+4 |
| * | Adding support for while loop | Larry Doolittle | 2017-11-20 | 1 | -0/+26 |
| * | Simple fix to genericmap example | Larry Doolittle | 2017-11-18 | 1 | -2/+2 |
| * | Fix capitalization of iverilog | Larry Doolittle | 2017-11-17 | 1 | -1/+1 |
| * | Modified the Makefile to run GHDl and iVerilog always but only if installed | Rodrigo Alejandro Melo | 2017-11-17 | 1 | -0/+14 |
| * | Removed extra parentheses when parentheses are used | Rodrigo Alejandro Melo | 2017-11-17 | 2 | -2/+2 |
| * | Removed unuseful parentheses | Rodrigo Alejandro Melo | 2017-11-17 | 8 | -39/+39 |
| * | Parentheses were removed for CONVFUNC_1 (ex. to_integer) | Rodrigo Alejandro Melo | 2017-11-17 | 1 | -2/+2 |
| * | Added (partial) support for to_integer function | Rodrigo Alejandro Melo | 2017-11-16 | 1 | -2/+2 |
| * | Changes on genericmap due to unsupported port assignment | Rodrigo Alejandro Melo | 2017-11-16 | 1 | -2/+2 |
| * | Changes on translated_examples (dsp and ifchain2) due to previous changes in ... | Rodrigo Alejandro Melo | 2017-11-16 | 2 | -2/+2 |
| * | Squelch some trailing whitespace | Larry Doolittle | 2017-11-12 | 1 | -4/+4 |
| * | Rework some examples so resulting Verilog compiles | Larry Doolittle | 2017-11-10 | 4 | -4/+83 |
| * | New make target: verilogcheck | Larry Doolittle | 2017-11-10 | 2 | -0/+25 |
| * | New rem before END PROCESS | Larry Doolittle | 2017-11-10 | 1 | -0/+36 |
| * | Experiment with OTHERS logic | Larry Doolittle | 2017-11-09 | 1 | -0/+16 |
| * | Fixes in examples and translated examples to avoid some complains of iVerilog | Rodrigo Alejandro Melo | 2017-02-19 | 4 | -8/+7 |
| * | Promoted unsupported BASED NUMBER from warning to error | Rodrigo Alejandro Melo | 2017-02-19 | 1 | -1/+1 |
| * | Modified to use ',' to separate sensitivity list in verilog 2001 | Rodrigo Alejandro Melo | 2017-02-17 | 7 | -19/+19 |
| * | Changed translated_examples due that Verilog 2001 is now the default | Rodrigo Alejandro Melo | 2017-02-17 | 13 | -455/+162 |
| * | Added command line option --quiet | Rodrigo Alejandro Melo | 2017-02-17 | 13 | -273/+0 |
| * | Added analysis of examples with GHDL | Rodrigo Alejandro Melo | 2017-02-14 | 5 | -14/+14 |
| * | Added scientific notation supports for integers and floats | Rodrigo Alejandro Melo | 2017-02-09 | 1 | -0/+36 |
| * | Space deleted in the <size>'<radix><number> notation | Rodrigo Alejandro Melo | 2017-02-09 | 11 | -246/+246 |
| * | vhd2vl-2.5 | Larry Doolittle | 2015-09-20 | 12 | -24/+24 |
| * | vhd2vl-2.4 | Larry Doolittle | 2015-09-20 | 12 | -68/+107 |
| * | vhd2vl-2.3 | Larry Doolittle | 2015-09-20 | 12 | -22/+244 |
| * | vhd2vl-2.2 | Larry Doolittle | 2015-09-20 | 11 | -0/+1727 |
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index : vhdl2vl | |
| vhdl2vl | Raptor Computing Systems |
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path: root/translated_examples
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