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* Added support for REMRodrigo Alejandro Melo2017-12-011-2/+3
| | | | | It works as MOD. MOD is bad implemented, but useful when the two operand has the same sign.
* Remove redundant bison ruleLarry Doolittle2017-11-281-4/+1
| | | | | Nicely reduces number of shift/reduce conflicts back to 2. I like having a good regression test suite!
* Recover centralized xmallocLarry Doolittle2017-11-281-11/+12
| | | | Now with its sibling xrealloc
* C code passes -Wstrict-prototypesLarry Doolittle2017-11-281-1/+1
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* More consistency in warning messagesLarry Doolittle2017-11-271-1/+1
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* Rewrite slist_check_diff() string handlingLarry Doolittle2017-11-271-21/+56
| | | | Need to be totally safe, never create an unexplained fault
* Update copyright datesLarry Doolittle2017-11-261-2/+2
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* Correct selection of -: vs. +:Larry Doolittle2017-11-251-11/+13
| | | | | Adds new updown field to struct vrange Both cases exercised by examples/partselect.vhd
* Add missing CONVFUNC_1 to grammarLarry Doolittle2017-11-241-0/+3
| | | | Allows completion of dsp.vhd changes from previous commit
* Turn off debug prints and fix warningsLarry Doolittle2017-11-231-5/+7
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* First stupid attempt to finish part selectLarry Doolittle2017-11-231-14/+18
| | | | | No attempt to figure out -: vs. +: Already yields much better results on test files
* Fill in size_expr with reduced diffLarry Doolittle2017-11-231-22/+26
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* Experiment towards indexed part selectLarry Doolittle2017-11-231-5/+90
| | | | No change in stdout, just lots of chatter on stderr
* Allow second argument to CONVFUNC_2 to be exprLarry Doolittle2017-11-221-2/+2
| | | | | Adds one more shift/reduce conflict. Include test case.
* Merge branch 'exponentiation'Larry Doolittle2017-11-221-1/+6
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| * Supports for exponentiation at the lex layerRodrigo Alejandro Melo2017-11-221-4/+5
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| * Experimental support of exponentiationRodrigo Alejandro Melo2017-11-211-0/+4
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* | Improve c89 compatibilityLarry Doolittle2017-11-211-9/+9
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* Add development hook for visualising slistsLarry Doolittle2017-11-201-0/+48
| | | | Use case is disabled, so no default effect.
* Adding support for while loopLarry Doolittle2017-11-201-1/+14
| | | | | Supplied by jeinstei Labelling of the loop is still unsupported.
* Beginning support for assertionsLarry Doolittle2017-11-181-0/+18
| | | | Based on work by jeinstei
* Removed extra parentheses when parentheses are usedRodrigo Alejandro Melo2017-11-171-1/+2
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* Removed unuseful parenthesesRodrigo Alejandro Melo2017-11-171-1/+1
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* Used addnest function to replace code for BITVECTRodrigo Alejandro Melo2017-11-171-9/+2
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* Parentheses were removed for CONVFUNC_1 (ex. to_integer)Rodrigo Alejandro Melo2017-11-171-2/+2
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* New rem before END PROCESSLarry Doolittle2017-11-101-5/+5
| | | | With test case!
* Experiment with OTHERS logicLarry Doolittle2017-11-091-14/+11
| | | | | | Makes sign extension idiom work in my code base Test case added, doesn't break any others Please test on your code!
* use enum for slist typeLarry Doolittle2017-11-091-21/+31
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* one more rem in generic patternLarry Doolittle2017-11-091-4/+4
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* Improved WARNING messages indicationRodrigo Alejandro Melo2017-02-191-18/+14
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* Promoted unsupported BASED NUMBER from warning to errorRodrigo Alejandro Melo2017-02-191-4/+5
| | | | | Because the resulting verilog had the unsupported notation BASE#NUMBER#. Moreover, the 'ERROR:' string was added when an error is informed.
* Fixed warnig in vhd2vl.y introduced in the previous commitRodrigo Alejandro Melo2017-02-171-9/+7
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* Modified to use ',' to separate sensitivity list in verilog 2001Rodrigo Alejandro Melo2017-02-171-3/+12
| | | | Changes applied to translated_examples.
* Changed vhd2vl version to 3.0Rodrigo Alejandro Melo2017-02-171-2/+4
| | | | Added Rodrigo A. Melo as contributor.
* Changed default Verilog version to 2001Rodrigo Alejandro Melo2017-02-171-19/+13
| | | | | Source code which use this parameter was changed. Variable vlog_ver is assigned with 1995 and 2001. Previously, 0 and 1 were used.
* Added command line option --quietRodrigo Alejandro Melo2017-02-171-9/+13
| | | | | Used to avoid header on the generated verilog file. Is a problem for regression tests. Header was removed from translated_examples.
* New command line parsing using getoptRodrigo Alejandro Melo2017-02-161-27/+50
| | | | | * -d is now --debug * -g1995 and -g2001 are now --std 1995|2001
* Added scientific notation supports for integers and floatsRodrigo Alejandro Melo2017-02-091-0/+10
| | | | | Also support was added for real numbers especially thinking in generics. Files called scientific.vhd and scientific.v were added for test.
* Space deleted in the <size>'<radix><number> notationRodrigo Alejandro Melo2017-02-091-4/+4
| | | | | | | It seems to be the more common approach and the VHDL notation BASE#NUMBER# is translated without spaces. On the other hand, the space gives an error with Yosys synthesizer. Files on translated_examples were modified.
* vhd2vl-2.5Larry Doolittle2015-09-201-18/+24
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* vhd2vl-2.4Larry Doolittle2015-09-201-103/+315
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* vhd2vl-2.3Larry Doolittle2015-09-201-113/+183
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* vhd2vl-2.2Larry Doolittle2015-09-201-0/+2145
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