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* Added support for REMRodrigo Alejandro Melo2017-12-012-8/+3
* Fixed scientific notation when the sign of the exponent is usedRodrigo Alejandro Melo2017-12-012-2/+3
* Added unsupported things to todo.vhdRodrigo Alejandro Melo2017-12-012-2/+37
* Add testcase for underscore in NATURALLarry Doolittle2017-11-281-1/+2
* Added support to entity instantiationsRodrigo Alejandro Melo2017-11-282-7/+8
* Take two files out of exclude listLarry Doolittle2017-11-271-2/+0
* Moved unsupported commented things to todo.vhdRodrigo Alejandro Melo2017-11-274-4/+14
* Examples: match case of module name in filenameLarry Doolittle2017-11-261-0/+0
* Renamed generic to withselectRodrigo Alejandro Melo2017-11-261-3/+4
* Renamed while to whileloopRodrigo Alejandro Melo2017-11-261-4/+3
* Deleted from todo.vhd a testcase that now is supportedRodrigo Alejandro Melo2017-11-261-4/+1
* Renamed gh_fifo_async16_sr to fifoRodrigo Alejandro Melo2017-11-261-18/+16
* Unexcluded partselectRodrigo Alejandro Melo2017-11-261-2/+1
* Renamed generate to forgen and for to forloopRodrigo Alejandro Melo2017-11-262-14/+17
* Merge pull request #8 from ldoolitt/excludeRodrigo A. Melo2017-11-262-3/+7
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| * Renamed .exclude to excludeRodrigo Alejandro Melo2017-11-251-0/+0
| * Removed Makefile from examples/.excludeRodrigo Alejandro Melo2017-11-241-1/+0
| * Implemented a mechanism to exclude files in the main MakefileRodrigo Alejandro Melo2017-11-241-0/+5
| * Simplified iverilog checkRodrigo Alejandro Melo2017-11-241-3/+3
* | Fixed partselect exampleRodrigo Alejandro Melo2017-11-261-2/+2
* | Correct selection of -: vs. +:Larry Doolittle2017-11-251-1/+3
* | Add missing CONVFUNC_1 to grammarLarry Doolittle2017-11-241-1/+1
* | Fixed dsp.vhdRodrigo Alejandro Melo2017-11-241-13/+15
* | Turn off debug prints and fix warningsLarry Doolittle2017-11-232-2/+7
* | First stupid attempt to finish part selectLarry Doolittle2017-11-234-5/+12
* | Added partselect exampleRodrigo Alejandro Melo2017-11-231-0/+30
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* Allow second argument to CONVFUNC_2 to be exprLarry Doolittle2017-11-221-1/+1
* Experimental support of exponentiationRodrigo Alejandro Melo2017-11-211-1/+8
* Adding support for while loopLarry Doolittle2017-11-201-0/+28
* Align the prototypes for dsp in dsp and genericmapLarry Doolittle2017-11-202-4/+3
* Beginning support for assertionsLarry Doolittle2017-11-181-0/+1
* Simple fix to genericmap exampleLarry Doolittle2017-11-181-2/+2
* Modified the Makefile to run GHDl and iVerilog always but only if installedRodrigo Alejandro Melo2017-11-171-1/+3
* Added (partial) support for to_integer functionRodrigo Alejandro Melo2017-11-161-2/+6
* Changes on genericmap due to unsupported port assignmentRodrigo Alejandro Melo2017-11-162-5/+24
* The resulting files of the GHDL analysis were moved to temp/vhdlRodrigo Alejandro Melo2017-11-161-2/+5
* Added the special file examples/todo.vhdRodrigo Alejandro Melo2017-11-161-0/+20
* Examples were corrected according to GHDL complainsRodrigo Alejandro Melo2017-11-165-8/+10
* Squelch some trailing whitespaceLarry Doolittle2017-11-124-17/+16
* Rework some examples so resulting Verilog compilesLarry Doolittle2017-11-104-7/+94
* New make target: verilogcheckLarry Doolittle2017-11-102-0/+23
* New rem before END PROCESSLarry Doolittle2017-11-101-0/+32
* Experiment with OTHERS logicLarry Doolittle2017-11-091-0/+17
* Fixes in examples and translated examples to avoid some complains of iVerilogRodrigo Alejandro Melo2017-02-194-14/+14
* Promoted unsupported BASED NUMBER from warning to errorRodrigo Alejandro Melo2017-02-191-1/+1
* Added analysis of examples with GHDLRodrigo Alejandro Melo2017-02-1413-33/+37
* Added scientific notation supports for integers and floatsRodrigo Alejandro Melo2017-02-091-0/+13
* vhd2vl-2.4Larry Doolittle2015-09-201-0/+3
* vhd2vl-2.3Larry Doolittle2015-09-201-0/+205
* vhd2vl-2.2Larry Doolittle2015-09-2011-0/+1314
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