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-rw-r--r--examples/genericmap.vhd2
-rw-r--r--examples/todo.vhd9
2 files changed, 3 insertions, 8 deletions
diff --git a/examples/genericmap.vhd b/examples/genericmap.vhd
index 876f159..3038f88 100644
--- a/examples/genericmap.vhd
+++ b/examples/genericmap.vhd
@@ -3,7 +3,7 @@ USE IEEE.std_logic_1164.all;
entity genericmap is
generic(
rst_val : std_logic := '0';
- thing_size: integer := 201;
+ thing_size: integer := 201 rem 2;
bus_width : integer := 201 mod 32);
port(
clk, rstn : in std_logic;
diff --git a/examples/todo.vhd b/examples/todo.vhd
index a5d4de5..7b05d2a 100644
--- a/examples/todo.vhd
+++ b/examples/todo.vhd
@@ -20,9 +20,6 @@ architecture rtl of todo is
signal int : integer;
signal uns : unsigned(7 downto 0);
- -- unexpected NAME at "rem"
- --constant VALUE : positive := 9 rem 2;
-
constant BYTES : positive:=4;
constant WIDTH : positive:=BYTES*8;
signal index : natural range 0 to BYTES-1;
@@ -30,8 +27,8 @@ architecture rtl of todo is
-- (others => (others => '0')) must be replaced by an initial block with a for
-- or something similar.
- type ff_array is array (0 to 255) of std_logic_vector(7 downto 0);
- signal data_r : ff_array :=(others => (others => '0'));
+ --type ff_array is array (0 to 255) of std_logic_vector(7 downto 0);
+ --signal data_r : ff_array :=(others => (others => '0'));
begin
--**************************************************************************
-- Wrong translations
@@ -69,8 +66,6 @@ begin
-- i => "00000000" & X"11", -- But here fail
-- o => open
-- );
- -- unexpected NAME, expecting WHEN or ';'
- --int <= 9 rem 2;
-- Unsupported generate with boolean?
-- in_by_level:
-- if INBYLEVEL generate
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