1 files changed, 1 insertions, 1 deletions
diff --git a/Makefile b/Makefile
index 1d18df6..d378edb 100644
--- a/Makefile
+++ b/Makefile
@@ -22,7 +22,7 @@ translate:
 	@make -C src
 	@make -C examples
 	@rm -fr $(TEMP)/verilog
-	@mkdir $(TEMP)/verilog
+	@mkdir -p $(TEMP)/verilog
 	@echo "##### Translating Examples #####################################"
 	@cd examples; $(foreach VHDL,$(VHDLS), echo "Translating: $(VHDL)";\
 	../src/vhd2vl --quiet $(VHDL) ../$(TEMP)/verilog/$(basename $(VHDL)).v;)