diff options
| -rw-r--r-- | examples/while.vhd | 28 | ||||
| -rw-r--r-- | src/vhd2vl.l | 1 | ||||
| -rw-r--r-- | src/vhd2vl.y | 15 | ||||
| -rw-r--r-- | translated_examples/while.v | 26 |
4 files changed, 69 insertions, 1 deletions
diff --git a/examples/while.vhd b/examples/while.vhd new file mode 100644 index 0000000..5d2ee9e --- /dev/null +++ b/examples/while.vhd @@ -0,0 +1,28 @@ +library IEEE; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity whilep is port( + A : in integer; + Z : out std_logic_vector(3 downto 0) +); +end whilep; + +architecture rtl of whilep is +begin + + +process (A) + variable I : integer range 0 to 4; +begin + Z <= "0000"; + I := 0; + while (I <= 3) loop + if (A = I) then + Z(I) <= '1'; + end if; + I := I + 1; + end loop; +end process; + +end rtl; diff --git a/src/vhd2vl.l b/src/vhd2vl.l index 4253fd4..d2cda55 100644 --- a/src/vhd2vl.l +++ b/src/vhd2vl.l @@ -114,6 +114,7 @@ void getbasedstring(unsigned skip); "then" { return THEN; } "elsif" { return ELSIF; } "else" { return ELSE; } +"while" { return WHILE; } "case" { return CASE; } "after" { return AFTER; } "and" { return AND; } diff --git a/src/vhd2vl.y b/src/vhd2vl.y index bbf01f1..4c34720 100644 --- a/src/vhd2vl.y +++ b/src/vhd2vl.y @@ -705,7 +705,7 @@ slist *emit_io_list(slist *sl) %token <txt> ARCHITECTURE COMPONENT OF ARRAY %token <txt> SIGNAL BEGN NOT WHEN WITH EXIT %token <txt> SELECT OTHERS PROCESS VARIABLE CONSTANT -%token <txt> IF THEN ELSIF ELSE CASE +%token <txt> IF THEN ELSIF ELSE CASE WHILE %token <txt> FOR LOOP GENERATE %token <txt> AFTER AND OR XOR MOD %token <txt> LASTVALUE EVENT POSEDGE NEGEDGE @@ -1808,6 +1808,19 @@ p_body : rem {$$=$1;} sl=addtxt(sl,"end\n"); $$=addsl(sl,$15); /* p_body:2 */ } +/* 1 2 3 4 5 6 7 8 9 10 11*/ + | rem WHILE exprc LOOP doindent p_body unindent END LOOP ';' p_body { + slist *sl; + sl=addsl($1,indents[indent]); + sl=addtxt(sl,"while "); + sl=addtxt(sl,"("); + sl=addsl(sl,$3); /* exprc */ + sl=addtxt(sl,") begin\n"); + sl=addsl(sl,$6); /* p_body:1 */ + sl=addsl(sl,indents[indent]); + sl=addtxt(sl,"end\n"); + $$=addsl(sl,$11); /* p_body:2 */ + } /* 1 2 3 4 5 6 7 8 9 10 */ | rem CASE signal IS rem cases END CASE ';' p_body { slist *sl; diff --git a/translated_examples/while.v b/translated_examples/while.v new file mode 100644 index 0000000..0464707 --- /dev/null +++ b/translated_examples/while.v @@ -0,0 +1,26 @@ +// no timescale needed + +module whilep( +input wire [31:0] A, +output reg [3:0] Z +); + + + + + + always @(A) begin : P1 + reg [31:0] I; + + Z <= 4'b0000; + I = 0; + while ((I <= 3)) begin + if((A == I)) begin + Z[I] <= 1'b1; + end + I = I + 1; + end + end + + +endmodule |
