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-rw-r--r--README.txt21
-rw-r--r--changes8
-rw-r--r--src/makefile2
-rw-r--r--src/vhd2vl.l2
-rw-r--r--src/vhd2vl.y42
-rw-r--r--translated_examples/based.v4
-rw-r--r--translated_examples/bigfile.v4
-rw-r--r--translated_examples/clk.v4
-rw-r--r--translated_examples/counters.v4
-rw-r--r--translated_examples/expr.v4
-rw-r--r--translated_examples/for.v4
-rw-r--r--translated_examples/generate.v4
-rw-r--r--translated_examples/generic.v4
-rw-r--r--translated_examples/genericmap.v4
-rw-r--r--translated_examples/gh_fifo_async16_sr.v4
-rw-r--r--translated_examples/ifchain.v4
-rw-r--r--translated_examples/test.v4
17 files changed, 73 insertions, 50 deletions
diff --git a/README.txt b/README.txt
index f5806aa..dcc3b3c 100644
--- a/README.txt
+++ b/README.txt
@@ -1,4 +1,4 @@
-VHD2VL v2.4 README.txt
+VHD2VL v2.5 README.txt
Vhd2vl is designed to translate synthesizable VHDL into Verilog 2001.
It does not support the full VHDL grammar - most of the testbench
@@ -9,6 +9,13 @@ Vhd2vl does a pretty good job of translating, but you should ALWAYS
test the generated Verilog, ideally by using a formal verification
tool to compare it to the original VHDL!
+A similar but more sophisticated effort is embedded in Icarus Verilog
+as vhdlpp, mostly by Maciej Suminski. If hands-free use of VHDL in a
+(Icarus) Verilog environment is the goal, that's probably a better tool.
+If you want to convert a bit of VHDL to Verilog, and will then maintain
+that Verilog as source, vhd2vl probably makes more sense, if for no other
+reason than it conserves comments. It's good that both options exist!
+
The home page for (at least for this version of) vhd2vl is
http://doolittle.icarus.com/~larry/vhd2vl/
@@ -17,9 +24,9 @@ The home page for (at least for this version of) vhd2vl is
To build, just type 'make' in the src directory.
-This version of vhd2vl has been tested with GNU Bison 2.3, and
-GNU Flex version 2.5.35. No problems have been reported with other
-fairly recent versions.
+This version of vhd2vl has been tested with GNU Bison versions 2.5 and
+3.0.2, and GNU Flex versions 2.5.35 and 2.5.39. No problems have been
+reported with other fairly recent versions.
To install, copy the resulting src/vhd2vl file to someplace in
your $PATH, like $HOME/bin or /usr/local/bin.
@@ -33,7 +40,7 @@ or
The two are equivalent when everything works. The latter has some
advantages when handling errors within a Makefile.
-There are a few of options available on the command line:
+There are a few options available on the command line:
-d turn on debugging within the yacc (bison) parser
-g1995 (default) use traditional Verilog module declaration style
-g2001 use Verilog-2001 module declaration style
@@ -53,7 +60,7 @@ move that comment out of the middle of the statement and try again.
The grammar has rules that recognize common ways of writing clocked
processes. Your code might contain clocked processes that do not match
-any of the templates in the grammar. This usually causes VHD2VL to
+any of the templates in the grammar. This usually causes vhd2vl to
complain about a clock'event expression in a process. If this
happens, a minor rewrite of that process will let you work around the
problem.
@@ -63,7 +70,7 @@ vhd2vl.output. If you need to change the grammar, then running vhd2vl
with the '-d' option will cause vhd2vl to trace how it is parsing the
input file. See the bison documentation for more details.
-To test a copy of vhdl for regressions against the example code shipped,
+To test a copy of vhd2vl for regressions against the example code shipped,
mkdir test
(cd examples && for f in *.vhd; do vhd2vl $f ../test/${f%%.vhd}.v; done)
diff -u translated_examples test | less
diff --git a/changes b/changes
index bfe69d6..95fcb08 100644
--- a/changes
+++ b/changes
@@ -1,3 +1,11 @@
+Changes 2.4 to 2.5 (Larry Doolittle, September 2015)
+
+Coding:
+ * Use $(CC) in makefile
+ * Trivial fix to yacc grammar, was causing FTBFS with recent bison
+ * Eliminate a couple of unused variables
+
+
Changes 2.3 to 2.4 (Larry Doolittle, November 2010)
Grammar:
diff --git a/src/makefile b/src/makefile
index ac564a4..fe8806b 100644
--- a/src/makefile
+++ b/src/makefile
@@ -14,7 +14,7 @@ STANDARD =
#STANDARD = --std=c99 -D_POSIX_C_SOURCE -D_BSD_SOURCE
vhd2vl : lex.yy.c vhd2vl.tab.c
- gcc ${STANDARD} ${WARNS} -O2 -g -o vhd2vl lex.yy.c vhd2vl.tab.c -lfl
+ $(CC) ${STANDARD} ${WARNS} -O2 -g -o vhd2vl lex.yy.c vhd2vl.tab.c -lfl
vhd2vl.tab.c : vhd2vl.y def.h
bison -d -v -t vhd2vl.y
diff --git a/src/vhd2vl.l b/src/vhd2vl.l
index d3604c3..661824f 100644
--- a/src/vhd2vl.l
+++ b/src/vhd2vl.l
@@ -126,6 +126,8 @@ void getbasedstring(unsigned skip);
"resize" { return CONVFUNC_2;}
"to_unsigned" { return CONVFUNC_2;}
"conv_integer" { return CONVFUNC_1;}
+"left" { return LEFT;}
+"high" { return LEFT;}
\"[ \!#-~]*\" |
\'[01xz]\' { getstring(1); return STRING;}
diff --git a/src/vhd2vl.y b/src/vhd2vl.y
index b4d6274..afe5917 100644
--- a/src/vhd2vl.y
+++ b/src/vhd2vl.y
@@ -1,10 +1,10 @@
/*
- vhd2vl v2.4
+ vhd2vl v2.5
VHDL to Verilog RTL translator
Copyright (C) 2001 Vincenzo Liguori - Ocean Logic Pty Ltd - http://www.ocean-logic.com
Modifications (C) 2006 Mark Gonzales - PMC Sierra Inc
Modifications (C) 2010 Shankar Giri
- Modifications (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
+ Modifications (C) 2002, 2005, 2008-2010, 2015 Larry Doolittle - LBNL
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
@@ -702,7 +702,7 @@ slist *emit_io_list(slist *sl)
%token <txt> AFTER AND OR XOR MOD
%token <txt> LASTVALUE EVENT POSEDGE NEGEDGE
%token <txt> STRING NAME RANGE NULLV OPEN
-%token <txt> CONVFUNC_1 CONVFUNC_2 BASED FLOAT
+%token <txt> CONVFUNC_1 CONVFUNC_2 BASED FLOAT LEFT
%token <n> NATURAL
%type <n> trad
@@ -1105,8 +1105,8 @@ vec_range : simple_expr updown simple_expr {
}
;
-updown : DOWNTO {$$=-1}
- | TO {$$=1}
+updown : DOWNTO {$$=-1;}
+ | TO {$$=1;}
;
/* Architecture */
@@ -1130,12 +1130,7 @@ a_decl : {$$=NULL;}
| a_decl SIGNAL s_list ':' type ';' rem {
sglist *sg;
slist *sl;
- int size;
- if($5->vtype==tSUBSCRIPT)
- size=1;
- else
- size=-1;
sl=$1;
sg=$3;
for(;;){
@@ -1158,12 +1153,7 @@ a_decl : {$$=NULL;}
| a_decl SIGNAL s_list ':' type ':' '=' expr ';' rem {
sglist *sg;
slist *sl;
- int size;
- if($5->vtype==tSUBSCRIPT)
- size=1;
- else
- size=-1;
sl=$1;
sg=$3;
for(;;){
@@ -1653,7 +1643,7 @@ with_item : expr delay WHEN wlist {
$$=addtxt(sl,";\n");
}
-p_decl : rem {$$=$1}
+p_decl : rem {$$=$1;}
| rem VARIABLE s_list ':' type ';' p_decl {
slist *sl;
sglist *sg, *p;
@@ -2308,6 +2298,22 @@ simple_expr : signal {
e->sl=addval(NULL,$1);
$$=e;
}
+ | NAME '\'' LEFT {
+ /* lookup NAME and get its left */
+ sglist *sg = NULL;
+ if((sg=lookup(io_list,$1))==NULL) {
+ sg=lookup(sig_list,$1);
+ }
+ if(sg) {
+ expdata *e;
+ e=xmalloc(sizeof(expdata));
+ e->sl=addwrap("(",sg->range->nhi,")"); /* XXX left vs. high? */
+ $$=e;
+ } else {
+ fprintf(stderr,"Undefined left \"%s'left\" on line %d\n",$1,lineno);
+ YYABORT;
+ }
+ }
| simple_expr '+' simple_expr {
$$=addexpr($1,'+'," + ",$3);
}
@@ -2397,7 +2403,7 @@ int status;
outfile = "-";
}
- printf("// File %s translated with vhd2vl v2.4 VHDL to Verilog RTL translator\n", sourcefile);
+ printf("// File %s translated with vhd2vl v2.5 VHDL to Verilog RTL translator\n", sourcefile);
printf("// vhd2vl settings:\n"
"// * Verilog Module Declaration Style: %s\n\n",
vlog_ver ? "2001" : "1995");
@@ -2407,7 +2413,7 @@ int status;
"// http://www.ocean-logic.com\n"
"// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc\n"
"// Modifications (C) 2010 Shankar Giri\n"
-"// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL\n"
+"// Modifications Copyright (C) 2002, 2005, 2008-2010, 2015 Larry Doolittle - LBNL\n"
"// http://doolittle.icarus.com/~larry/vhd2vl/\n"
"//\n", stdout);
fputs(
diff --git a/translated_examples/based.v b/translated_examples/based.v
index 1589453..9e28f9b 100644
--- a/translated_examples/based.v
+++ b/translated_examples/based.v
@@ -1,4 +1,4 @@
-// File based.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// File based.vhd translated with vhd2vl v2.5 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
@@ -7,7 +7,7 @@
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
-// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
+// Modifications Copyright (C) 2002, 2005, 2008-2010, 2015 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
diff --git a/translated_examples/bigfile.v b/translated_examples/bigfile.v
index c124c42..4fee00f 100644
--- a/translated_examples/bigfile.v
+++ b/translated_examples/bigfile.v
@@ -1,4 +1,4 @@
-// File bigfile.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// File bigfile.vhd translated with vhd2vl v2.5 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
@@ -7,7 +7,7 @@
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
-// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
+// Modifications Copyright (C) 2002, 2005, 2008-2010, 2015 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
diff --git a/translated_examples/clk.v b/translated_examples/clk.v
index b7e1571..41797b7 100644
--- a/translated_examples/clk.v
+++ b/translated_examples/clk.v
@@ -1,4 +1,4 @@
-// File clk.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// File clk.vhd translated with vhd2vl v2.5 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
@@ -7,7 +7,7 @@
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
-// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
+// Modifications Copyright (C) 2002, 2005, 2008-2010, 2015 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
diff --git a/translated_examples/counters.v b/translated_examples/counters.v
index 277e707..23fc54a 100644
--- a/translated_examples/counters.v
+++ b/translated_examples/counters.v
@@ -1,4 +1,4 @@
-// File counters.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// File counters.vhd translated with vhd2vl v2.5 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
@@ -7,7 +7,7 @@
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
-// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
+// Modifications Copyright (C) 2002, 2005, 2008-2010, 2015 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
diff --git a/translated_examples/expr.v b/translated_examples/expr.v
index 4d66026..43f6221 100644
--- a/translated_examples/expr.v
+++ b/translated_examples/expr.v
@@ -1,4 +1,4 @@
-// File expr.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// File expr.vhd translated with vhd2vl v2.5 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
@@ -7,7 +7,7 @@
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
-// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
+// Modifications Copyright (C) 2002, 2005, 2008-2010, 2015 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
diff --git a/translated_examples/for.v b/translated_examples/for.v
index 1c47083..a79e5e1 100644
--- a/translated_examples/for.v
+++ b/translated_examples/for.v
@@ -1,4 +1,4 @@
-// File for.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// File for.vhd translated with vhd2vl v2.5 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
@@ -7,7 +7,7 @@
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
-// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
+// Modifications Copyright (C) 2002, 2005, 2008-2010, 2015 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
diff --git a/translated_examples/generate.v b/translated_examples/generate.v
index 9dcdf2b..29fbe5d 100644
--- a/translated_examples/generate.v
+++ b/translated_examples/generate.v
@@ -1,4 +1,4 @@
-// File generate.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// File generate.vhd translated with vhd2vl v2.5 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
@@ -7,7 +7,7 @@
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
-// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
+// Modifications Copyright (C) 2002, 2005, 2008-2010, 2015 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
diff --git a/translated_examples/generic.v b/translated_examples/generic.v
index c5cf39f..ca6e298 100644
--- a/translated_examples/generic.v
+++ b/translated_examples/generic.v
@@ -1,4 +1,4 @@
-// File generic.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// File generic.vhd translated with vhd2vl v2.5 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
@@ -7,7 +7,7 @@
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
-// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
+// Modifications Copyright (C) 2002, 2005, 2008-2010, 2015 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
diff --git a/translated_examples/genericmap.v b/translated_examples/genericmap.v
index f66d2f8..26573b9 100644
--- a/translated_examples/genericmap.v
+++ b/translated_examples/genericmap.v
@@ -1,4 +1,4 @@
-// File genericmap.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// File genericmap.vhd translated with vhd2vl v2.5 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
@@ -7,7 +7,7 @@
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
-// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
+// Modifications Copyright (C) 2002, 2005, 2008-2010, 2015 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
diff --git a/translated_examples/gh_fifo_async16_sr.v b/translated_examples/gh_fifo_async16_sr.v
index cb358a7..2f711a9 100644
--- a/translated_examples/gh_fifo_async16_sr.v
+++ b/translated_examples/gh_fifo_async16_sr.v
@@ -1,4 +1,4 @@
-// File gh_fifo_async16_sr.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// File gh_fifo_async16_sr.vhd translated with vhd2vl v2.5 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
@@ -7,7 +7,7 @@
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
-// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
+// Modifications Copyright (C) 2002, 2005, 2008-2010, 2015 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
diff --git a/translated_examples/ifchain.v b/translated_examples/ifchain.v
index 459c0ed..abfd6bf 100644
--- a/translated_examples/ifchain.v
+++ b/translated_examples/ifchain.v
@@ -1,4 +1,4 @@
-// File ifchain.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// File ifchain.vhd translated with vhd2vl v2.5 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
@@ -7,7 +7,7 @@
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
-// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
+// Modifications Copyright (C) 2002, 2005, 2008-2010, 2015 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
diff --git a/translated_examples/test.v b/translated_examples/test.v
index d11e643..7e51bc0 100644
--- a/translated_examples/test.v
+++ b/translated_examples/test.v
@@ -1,4 +1,4 @@
-// File test.vhd translated with vhd2vl v2.4 VHDL to Verilog RTL translator
+// File test.vhd translated with vhd2vl v2.5 VHDL to Verilog RTL translator
// vhd2vl settings:
// * Verilog Module Declaration Style: 1995
@@ -7,7 +7,7 @@
// http://www.ocean-logic.com
// Modifications Copyright (C) 2006 Mark Gonzales - PMC Sierra Inc
// Modifications (C) 2010 Shankar Giri
-// Modifications Copyright (C) 2002, 2005, 2008-2010 Larry Doolittle - LBNL
+// Modifications Copyright (C) 2002, 2005, 2008-2010, 2015 Larry Doolittle - LBNL
// http://doolittle.icarus.com/~larry/vhd2vl/
//
// vhd2vl comes with ABSOLUTELY NO WARRANTY. Always check the resulting
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