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author | Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | 2017-12-01 13:33:48 -0300 |
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committer | Rodrigo Alejandro Melo <rmelo@inti.gob.ar> | 2017-12-01 13:33:48 -0300 |
commit | 4aa6f8e07914cb1aa8cde5da5e3512c0f717f737 (patch) | |
tree | f9d23d9d42f4a8b22dcd272715af11c962097c15 /translated_examples/Scientific.v | |
parent | 5ac1f1eba35fec83789c635b7b145474a77a5fde (diff) | |
download | vhdl2vl-4aa6f8e07914cb1aa8cde5da5e3512c0f717f737.tar.gz vhdl2vl-4aa6f8e07914cb1aa8cde5da5e3512c0f717f737.zip |
Fixed scientific notation when the sign of the exponent is used
Removed the testcase of todo.vhd.
Diffstat (limited to 'translated_examples/Scientific.v')
-rw-r--r-- | translated_examples/Scientific.v | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/translated_examples/Scientific.v b/translated_examples/Scientific.v index 9cd85a2..9f725ab 100644 --- a/translated_examples/Scientific.v +++ b/translated_examples/Scientific.v @@ -6,6 +6,8 @@ input wire clk parameter [31:0] exp1=25e6; parameter [31:0] exp2=25E6; parameter exp3=25.0e6; +parameter exp4=50.0e+3; +parameter exp5=50.0e-3; |