vhdl2vl/translated_examples/Makefile, branch master vhdl2vl https://git.raptorcs.com/git/vhdl2vl/atom?h=master 2017-11-27T17:11:09+00:00 sort lists in Makefiles 2017-11-27T17:11:09+00:00 Larry Doolittle ldoolitt@recycle.lbl.gov 2017-11-27T17:11:09+00:00 urn:sha1:936beabe02c132b7b519fa800b3c9cc5a9d8449d Changed translated_examples/Makefile to analyze individually again 2017-11-26T13:03:33+00:00 Rodrigo Alejandro Melo rodrigomelo9@gmail.com 2017-11-26T13:03:33+00:00 urn:sha1:4d76e5796e9bcaf5b615ffe6050b2811bad0f97d Simplified iverilog check 2017-11-24T16:26:51+00:00 Rodrigo Alejandro Melo rmelo@inti.gob.ar 2017-11-24T16:26:51+00:00 urn:sha1:508777e34fe7ff0a1580695a18924768dca0ab59 Fix capitalization of iverilog 2017-11-18T05:26:10+00:00 Larry Doolittle ldoolitt@recycle.lbl.gov 2017-11-18T05:26:10+00:00 urn:sha1:7727267d7ca0cd48d26aae12da622bae4fb7c2cb Modified the Makefile to run GHDl and iVerilog always but only if installed 2017-11-17T18:15:54+00:00 Rodrigo Alejandro Melo rmelo@inti.gob.ar 2017-11-17T18:15:54+00:00 urn:sha1:891255b54058e74df28d5c8630d11c86a6333899