From fc6e00ae5e6af2a8a5475cf7e977747003697837 Mon Sep 17 00:00:00 2001 From: Raptor Engineering Development Team Date: Sat, 30 Dec 2017 18:34:14 -0600 Subject: =?UTF-8?q?Add=20initial=20Talos=E2=84=A2=20II=20front=20panel=20c?= =?UTF-8?q?ontrol=20logic=20Add=20initial=20Talos=E2=84=A2=20II=20system?= =?UTF-8?q?=20control=20logic?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Makefile | 4 +- main.v | 113 ++++++++++++++++++++++++++++++++++++++++++++++++++------ system_fpga.pcf | 26 ++++++++++++- 3 files changed, 128 insertions(+), 15 deletions(-) diff --git a/Makefile b/Makefile index 30b70a8..63a0469 100644 --- a/Makefile +++ b/Makefile @@ -22,11 +22,11 @@ YOSYS_ICE40_SIM_LIB = $(shell yosys-config --datdir/ice40/cells_sim.v) .PRECIOUS: system_fpga_%.int -system_fpga_%.tmg: system_fpga_%.int +system_fpga_%.tmg: system_fpga_%.int system_fpga.pcf echo "Total path delay: inf ns (0.0 MHz)" > $@ -icetime -tmd hx1k -p system_fpga.pcf -P vq100 $< > $@ 2>&1 -system_fpga_%.int: system_fpga.blif +system_fpga_%.int: system_fpga.blif system_fpga.pcf echo "" > $@ -arachne-pnr -s $* -d 1k -P vq100 -m $(MAX_FPGA_ROUTE_PASSES) -p system_fpga.pcf $< -o $@ diff --git a/main.v b/main.v index 3b85894..2cae787 100644 --- a/main.v +++ b/main.v @@ -58,7 +58,7 @@ module system_fpga_top inout i2c_scl, inout i2c_sda, - // Second CPU Present Detection + // Second CPU presence detect input wire cpub_present_n, output wire cpub_clk_oea, output wire cpub_clk_oeb, @@ -71,11 +71,38 @@ module system_fpga_top output wire usbhub_rst, output wire cpu_stby_rst, - // Reserved for Future Use + // Reserved for future use output wire dual_5v_ctrl, - output wire window_open_n + output wire window_open_n, + + // BMC system reset signalling + output wire bmc_system_reset_request_n, + + // Component disable lines + output wire pmc_disable_n, + + // System status lines + input wire nic1_act_led_n, + input wire nic2_act_led_n, + input wire nic1_link_led_n, + input wire nic2_link_led_n, + input wire nic1_green_led_n, + input wire nic2_green_led_n, + input wire bmc_uid_led_req, + + // Front panel indicators + output wire panel_nic1_led_cathode, + output wire panel_nic2_led_cathode, + output wire panel_uid_led, + + // Front panel switches + input wire panel_reset_in_l, + + // FlexVer™ connections + input wire flexver_reset_in_l ); + // I2C pin control lines wire i2c_scl_in; wire i2c_scl_out; wire i2c_scl_direction; @@ -129,8 +156,9 @@ module system_fpga_top reg operation_err = 1'b0; reg err_found = 1'b0; wire clear_err = 1'b0; + wire master_reset_reqest; - // i2c signals + // I2C signals wire i2c_read_req; reg [7:0] i2c_data_to_master = 8'b00000000; wire [7:0] i2c_data_from_master; @@ -146,6 +174,12 @@ module system_fpga_top reg [15:0] i2c_pg_reg = 1'b0; reg i2c_clr_err = 1'b0; + // Front panel control signals + wire panel_nic1_led_cathode_std; + wire panel_nic2_led_cathode_std; + wire panel_uid_led_std; + reg [2:0] bmc_startup_kr = 3'b000; + // Divide input 33MHz clock down to 4.125MHz reg [2:0] clock_divider; always @(posedge lpc_clock) begin @@ -173,6 +207,39 @@ module system_fpga_top .data_valid(i2c_data_valid), .data_from_master(i2c_data_from_master) ); + + // Generate BMC startup "Knight Rider" display for front panel + wire slow_clk; + reg [24:0] slow_clk_counter; + always @(posedge clk_in) begin + slow_clk_counter <= slow_clk_counter + 1; + end + assign slow_clk = slow_clk_counter[24]; + + reg [1:0] bmc_startup_kr_state = 0; + always @(posedge slow_clk) begin + case (bmc_startup_kr_state) + 0: begin + bmc_startup_kr <= 3'b100; + bmc_startup_kr_state <= 1; + end + 1: begin + bmc_startup_kr <= 3'b010; + bmc_startup_kr_state <= 2; + end + 2: begin + bmc_startup_kr <= 3'b001; + bmc_startup_kr_state <= 3; + end + 3: begin + bmc_startup_kr <= 3'b010; + bmc_startup_kr_state <= 0; + end + default: begin + bmc_startup_kr_state = 0; + end + endcase + end assign i2c_rst = 1'b0; // Handle I2C @@ -192,24 +259,24 @@ module system_fpga_top else if (i2c_read_req == 1'b1) begin i2c_reg_cur <= i2c_reg_cur + 1; end - case(i2c_reg_cur) - i2c_clr_err_addr : begin + case (i2c_reg_cur) + i2c_clr_err_addr: begin i2c_data_to_master <= 8'b11111111; end - i2c_pg_reg_addr1 : begin + i2c_pg_reg_addr1: begin i2c_data_to_master <= i2c_pg_reg[15:8]; end - i2c_pg_reg_addr2 : begin + i2c_pg_reg_addr2: begin i2c_data_to_master <= i2c_pg_reg[7:0]; end - i2c_status_reg_addr : begin + i2c_status_reg_addr: begin // TODO add CPU1 presence detect i2c_data_to_master <= {3'b000, wait_err, operation_err, err_found, sysen_buf, sysgood_buf}; end - i2c_version_reg_addr : begin + i2c_version_reg_addr: begin i2c_data_to_master <= fpga_version; end - default : begin + default: begin i2c_data_to_master <= 8'b00000000; end endcase @@ -548,11 +615,33 @@ module system_fpga_top assign usbhub_rst = sysgood_buf & bmc_software_pg; assign fan_rst = ~bmc_vr_pg; - // debug_in override allows non-BMC control of CPLD + // debug_in override allows non-BMC control of FPGA assign sysen_buf = sysen | ~debug_in; // assign sysen_buf = ~debug_in; + // Enable V5_0_DUAL rail assign dual_5v_ctrl = 1'b0; + + // Enable PMC + assign pmc_disable_n = 1'b1; + + // Not used assign window_open_n = 1'b0; + + // Generate standard front panel NIC activity indications + assign panel_nic1_led_cathode_std = (nic1_link_led_n & nic1_green_led_n) & ~nic1_act_led_n; + assign panel_nic2_led_cathode_std = (nic2_link_led_n & nic2_green_led_n) & ~nic2_act_led_n; + + // Wire up UID request to front panel + assign panel_uid_led_std = bmc_uid_led_req; + + // Assign front panel indicators according to BMC status + assign panel_nic1_led_cathode = (bmc_software_pg)?panel_nic1_led_cathode_std:bmc_startup_kr[0]; + assign panel_nic2_led_cathode = (bmc_software_pg)?panel_nic2_led_cathode_std:bmc_startup_kr[1]; + assign panel_uid_led = (bmc_software_pg)?panel_uid_led_std:bmc_startup_kr[2]; + + // Generate master reset request signals + assign master_reset_reqest = ~(panel_reset_in_l & flexver_reset_in_l); + assign bmc_system_reset_request_n = ~master_reset_reqest; endmodule diff --git a/system_fpga.pcf b/system_fpga.pcf index 51ecc68..89976b9 100644 --- a/system_fpga.pcf +++ b/system_fpga.pcf @@ -73,4 +73,28 @@ set_io cpu_stby_rst 54 # Reserved set_io dual_5v_ctrl 80 -set_io window_open_n 99 \ No newline at end of file +set_io window_open_n 99 + +# BMC system reset signalling +set_io bmc_system_reset_request_n 12 + +# Component disable lines +set_io pmc_disable_n 21 + +# System status lines +set_io nic1_act_led_n 93 +set_io nic2_act_led_n 96 +set_io nic1_link_led_n 94 +set_io nic2_link_led_n 97 +set_io nic1_green_led_n 2 +set_io nic2_green_led_n 3 +set_io bmc_uid_led_req 90 + +# Front panel indicators +set_io panel_nic1_led_cathode 91 +set_io panel_nic2_led_cathode 95 +set_io panel_uid_led 89 + +# Front panel switches +set_io panel_reset_in_l 73 +set_io flexver_reset_in_l 74 \ No newline at end of file -- cgit v1.2.1