| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Convert combinatorial logic to registered logic to work around apparent Yosys... | Raptor Engineering Development Team | 2018-01-12 | 1 | -110/+173 |
| * | Add vendor ID registers | Raptor Engineering Development Team | 2017-12-31 | 1 | -3/+22 |
| * | Add initial Talos™ II front panel control logic | Raptor Engineering Development Team | 2017-12-30 | 1 | -12/+101 |
| * | Initial buildable variant for Talos™ II | Raptor Engineering Development Team | 2017-12-30 | 1 | -0/+558 |
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index : talos-system-fpga | |
| Talos™ II FPGA sources | Raptor Computing Systems |
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