| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add pullup on FlexVer™ reset linev1.00 | Raptor Engineering Development Team | 2018-01-23 | 1 | -2/+12 |
| * | Separate BMC status and chassis reset request lines | Raptor Engineering Development Team | 2018-01-22 | 2 | -16/+8 |
| * | Remove DD1 VCS overcurrent bug hack | Raptor Engineering Development Team | 2018-01-22 | 2 | -11/+1 |
| * | Add I2C write capability | Raptor Engineering Development Team | 2018-01-19 | 3 | -7/+63 |
| * | Switch U-Boot phase indicators to staggered fader | Raptor Engineering Development Team | 2018-01-17 | 1 | -6/+37 |
| * | Indicate BMC boot phase as follows: | Raptor Engineering Development Team | 2018-01-17 | 1 | -6/+48 |
| * | Correct polarity of BMC boot complete signal | Raptor Engineering Development Team | 2018-01-17 | 2 | -9/+39 |
| * | Fix power rails not going offline on system shutdown | Raptor Engineering Development Team | 2018-01-17 | 1 | -2/+2 |
| * | Speed BMC boot pattern up somewhat | Raptor Engineering Development Team | 2018-01-17 | 1 | -2/+2 |
| * | Enable network link and activity LEDs on front and rear panel | Raptor Engineering Development Team | 2018-01-17 | 1 | -12/+77 |
| * | Expose power good/enable busses to I2C for debugging and diagnostic purposes | Raptor Engineering Development Team | 2018-01-16 | 1 | -0/+16 |
| * | Use open drain output on CPU standby reset line | Raptor Engineering Development Team | 2018-01-16 | 1 | -2/+15 |
| * | Take fan controller out of reset when BMC power good is established | Raptor Engineering Development Team | 2018-01-13 | 1 | -2/+2 |
| * | Convert combinatorial logic to registered logic to work around apparent Yosys... | Raptor Engineering Development Team | 2018-01-12 | 3 | -113/+201 |
| * | Fix license template in Makefile | Raptor Engineering Development Team | 2018-01-07 | 1 | -3/+20 |
| * | Add vendor ID registers | Raptor Engineering Development Team | 2017-12-31 | 1 | -3/+22 |
| * | Properly generate programming file | Raptor Engineering Development Team | 2017-12-30 | 1 | -2/+2 |
| * | Add initial Talos™ II front panel control logic | Raptor Engineering Development Team | 2017-12-30 | 3 | -15/+128 |
| * | Remove spurious power_sequencer.v file | Raptor Engineering Development Team | 2017-12-30 | 2 | -224/+2 |
| * | Initial buildable variant for Talos™ II | Raptor Engineering Development Team | 2017-12-30 | 6 | -621/+847 |
| * | Initial conversion pass VHDL to Verilog | Raptor Engineering Development Team | 2017-12-29 | 9 | -1603/+1038 |
| * | Prepare files for Talos™ II modifications | Raptor Engineering Development Team | 2017-12-29 | 3 | -130/+130 |
| * | Initial import of Romulus support files | IBM | 2017-12-29 | 4 | -0/+1603 |
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index : talos-system-fpga | |
| Talos™ II FPGA sources | Raptor Computing Systems |
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