diff options
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 19 |
1 files changed, 16 insertions, 3 deletions
@@ -1,6 +1,6 @@ # This file is part of the Talos™ II system FPGA implementation # -# © 2017 - 2018 Raptor Engineering, LLC +# © 2017 - 2019 Raptor Engineering, LLC # All Rights Reserved # # Redistribution and use in source and binary forms, with or without modification, @@ -25,6 +25,8 @@ MAX_FPGA_ROUTE_PASSES = 100 +SOURCE_FILES = main.v i2c_slave.v + # Default seed #ARACHNE_PNR_SEED = 1 @@ -84,8 +86,8 @@ endif system_fpga.ex: system_fpga.int icebox_explain system_fpga.int > system_fpga.ex -system_fpga.blif: main.v i2c_slave.v - yosys -l yosys.log -q -p "synth_ice40 -top system_fpga_top -blif system_fpga.blif" main.v i2c_slave.v +system_fpga.blif: $(SOURCE_FILES) + yosys -l yosys.log -q -p "synth_ice40 -top system_fpga_top -blif system_fpga.blif" $(SOURCE_FILES) system_fpga.bin: system_fpga.int icepack system_fpga.int system_fpga.bin @@ -97,6 +99,17 @@ system_fpga.rom: blank.rom system_fpga.bin cp blank.rom system_fpga.rom dd if=system_fpga.bin of=system_fpga.rom conv=notrunc +system_fpga_test.vcd: $(SOURCE_FILES) testbench.v + rm -f system_fpga_sim + rm -f system_fpga.vcd + /usr/bin/iverilog -DSIMULATION -o system_fpga_sim $(SOURCE_FILES) testbench.v + ./system_fpga_sim + +simulate: system_fpga_test.vcd + +simulate_view: system_fpga_test.vcd + gtkwave system_fpga_test.vcd + all: system_fpga.rom dump_toolchain_info: |
