diff options
-rw-r--r-- | i2c_slave.vhd (renamed from I2C_slave.vhd) | 0 | ||||
-rw-r--r-- | pwrseq.vhd (renamed from PWRseq_Romulus.vhd) | 6 | ||||
-rw-r--r-- | top.vhd (renamed from Romulus_CPLD_TOP.vhd) | 254 |
3 files changed, 130 insertions, 130 deletions
diff --git a/I2C_slave.vhd b/i2c_slave.vhd index 80871a6..80871a6 100644 --- a/I2C_slave.vhd +++ b/i2c_slave.vhd diff --git a/PWRseq_Romulus.vhd b/pwrseq.vhd index a718bfd..39b0f08 100644 --- a/PWRseq_Romulus.vhd +++ b/pwrseq.vhd @@ -2,7 +2,7 @@ library IEEE; use IEEE.numeric_std.ALL;
use IEEE.STD_LOGIC_1164.ALL;
-entity PWRseq_Romulus is
+entity pwrseq is
generic (rail_size : integer);
Port (EN : out STD_LOGIC_VECTOR (rail_size-1 downto 0) := (others=>'0');
PGOOD_A : in STD_LOGIC_VECTOR (rail_size-1 downto 0);
@@ -11,9 +11,9 @@ entity PWRseq_Romulus is SCL: inout STD_LOGIC;
SDA: inout STD_LOGIC;
CLK_IN: in STD_LOGIC);
-end PWRseq_Romulus;
+end pwrseq;
-architecture Behavioral of PWRseq_Romulus is
+architecture Behavioral of pwrseq is
--Input output buffers and synchronizers
--constant rail_size : integer := EN'LENGTH;
signal EN_BUF : STD_LOGIC_VECTOR (rail_size-1 downto 0) := (others => '0');
diff --git a/Romulus_CPLD_TOP.vhd b/top.vhd index f797f9e..6f70ea0 100644 --- a/Romulus_CPLD_TOP.vhd +++ b/top.vhd @@ -4,7 +4,7 @@ use IEEE.STD_LOGIC_1164.ALL; library machxo2;
use machxo2.all;
-entity Romulus_CPLD_TOP is
+entity FPGA_TOP is
Port ( SYSEN : in STD_LOGIC;
SYSGOOD: out STD_LOGIC := '0';
DEBUG_IN: in STD_LOGIC;
@@ -76,9 +76,9 @@ entity Romulus_CPLD_TOP is );
-end Romulus_CPLD_TOP;
+end FPGA_TOP;
-architecture Behavioral of Romulus_CPLD_TOP is
+architecture Behavioral of FPGA_TOP is
--FUTURE update version
constant cpld_version : STD_LOGIC_VECTOR (7 downto 0) := "00000101";
constant rail_size : integer := 15;
@@ -114,17 +114,17 @@ architecture Behavioral of Romulus_CPLD_TOP is -- signal FIRST_DELAY : STD_LOGIC := '1';
signal CLEAR_ERR : STD_LOGIC := '0';
- --i2c signals - signal i2c_read_req : STD_LOGIC; - signal i2c_data_to_master : STD_LOGIC_VECTOR(7 downto 0) := "00000000"; - signal i2c_data_from_master : STD_LOGIC_VECTOR(7 downto 0); - signal i2c_data_valid : STD_LOGIC; - signal i2c_rst : STD_LOGIC := '0'; - signal i2c_reg_cur : UNSIGNED(7 downto 0) := "00000000"; + --i2c signals
+ signal i2c_read_req : STD_LOGIC;
+ signal i2c_data_to_master : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
+ signal i2c_data_from_master : STD_LOGIC_VECTOR(7 downto 0);
+ signal i2c_data_valid : STD_LOGIC;
+ signal i2c_rst : STD_LOGIC := '0';
+ signal i2c_reg_cur : UNSIGNED(7 downto 0) := "00000000";
constant i2c_addr : STD_LOGIC_VECTOR (6 downto 0) := "0110001";
- constant i2c_clr_err_addr : UNSIGNED (7 downto 0) := "00000011"; - constant i2c_pg_reg_addr1 : UNSIGNED (7 downto 0) := "00000101"; - constant i2c_pg_reg_addr2 : UNSIGNED (7 downto 0) := i2c_pg_reg_addr1 + 1; + constant i2c_clr_err_addr : UNSIGNED (7 downto 0) := "00000011";
+ constant i2c_pg_reg_addr1 : UNSIGNED (7 downto 0) := "00000101";
+ constant i2c_pg_reg_addr2 : UNSIGNED (7 downto 0) := i2c_pg_reg_addr1 + 1;
constant i2c_status_reg_addr : UNSIGNED (7 downto 0) := i2c_pg_reg_addr2 + 1;
constant i2c_version_reg_addr: UNSIGNED (7 downto 0) := "00000000";
signal i2c_pg_reg : STD_LOGIC_VECTOR(15 downto 0) := (others=>'0');
@@ -138,7 +138,7 @@ architecture Behavioral of Romulus_CPLD_TOP is OSC: out STD_LOGIC;
SEDSTDBY: out STD_LOGIC);
end component;
- attribute NOM_FREQ : string; + attribute NOM_FREQ : string;
attribute NOM_FREQ of OSC1 : label is "4.16";
@@ -163,7 +163,7 @@ begin -- CLK_DIV <= STD_LOGIC(CLK_REG(2));
-- Power Sequencer Instance
--- SEQ1: entity work.PWRseq_Romulus
+-- SEQ1: entity work.pwrseq
-- generic map(rail_size)
-- port map(
-- EN => EN_BUF,
@@ -176,48 +176,48 @@ begin -- CLK_IN => CLK_IN
-- );
- --I2C device -I2C_SLAVE: entity work.I2C_slave generic map(i2c_addr) port map( - SCL, SDA, CLK_IN, i2c_rst, - i2c_read_req,i2c_data_to_master, - i2c_data_valid,i2c_data_from_master); - - i2c_rst <= '0'; - ---Handle I2C - --2 8-bit registers with PGOOD state on error - process (CLK_IN) - begin - if (rising_edge(CLK_IN)) then - i2c_clr_err <= '0'; + --I2C device
+I2C_SLAVE: entity work.I2C_slave generic map(i2c_addr) port map(
+ SCL, SDA, CLK_IN, i2c_rst,
+ i2c_read_req,i2c_data_to_master,
+ i2c_data_valid,i2c_data_from_master);
+
+ i2c_rst <= '0';
+
+--Handle I2C
+ --2 8-bit registers with PGOOD state on error
+ process (CLK_IN)
+ begin
+ if (rising_edge(CLK_IN)) then
+ i2c_clr_err <= '0';
if i2c_data_valid = '1' then
- -- data from master is register to be read + -- data from master is register to be read
i2c_reg_cur <= unsigned(i2c_data_from_master);
--pulse clear err signal if i2c master reads register 0x03
if(unsigned(i2c_data_from_master) = i2c_clr_err_addr) then
i2c_clr_err <= '1';
- end if; - elsif i2c_read_req = '1' then - i2c_reg_cur <= i2c_reg_cur + 1; - end if; - + end if;
+ elsif i2c_read_req = '1' then
+ i2c_reg_cur <= i2c_reg_cur + 1;
+ end if;
+
case i2c_reg_cur is
when i2c_clr_err_addr =>
- i2c_data_to_master <= "11111111"; - when i2c_pg_reg_addr1 => - i2c_data_to_master <= i2c_pg_reg(15 downto 8); - when i2c_pg_reg_addr2 => - i2c_data_to_master <= i2c_pg_reg(7 downto 0); + i2c_data_to_master <= "11111111";
+ when i2c_pg_reg_addr1 =>
+ i2c_data_to_master <= i2c_pg_reg(15 downto 8);
+ when i2c_pg_reg_addr2 =>
+ i2c_data_to_master <= i2c_pg_reg(7 downto 0);
when i2c_status_reg_addr =>
- --FUTURE add CPU1 Present detect + --FUTURE add CPU1 Present detect
i2c_data_to_master <= "000" & WAIT_ERR & OPERATION_ERR & ERR_FOUND & SYSEN_BUF & SYSGOOD_BUF;
when i2c_version_reg_addr =>
- i2c_data_to_master <= cpld_version; - when others => - i2c_data_to_master <= "00000000"; - end case; - end if; + i2c_data_to_master <= cpld_version;
+ when others =>
+ i2c_data_to_master <= "00000000";
+ end case;
+ end if;
end process;
process (CLK_IN)
@@ -247,102 +247,102 @@ I2C_SLAVE: entity work.I2C_slave generic map(i2c_addr) port map( DELAY_DONE(0) <= '1';
end if;
elsif (PG_S2(1) = '1' and EN_BUF(1) = '1' and DELAY_DONE(1) = '0') then
- W_COUNT <= (others => '0'); - D_COUNT <= D_COUNT+1; - if (D_COUNT(16) = '1') then - D_COUNT <= (others => '0'); - DELAY_DONE(1) <= '1'; + W_COUNT <= (others => '0');
+ D_COUNT <= D_COUNT+1;
+ if (D_COUNT(16) = '1') then
+ D_COUNT <= (others => '0');
+ DELAY_DONE(1) <= '1';
end if;
elsif (PG_S2(2) = '1' and EN_BUF(2) = '1' and DELAY_DONE(2) = '0') then
- W_COUNT <= (others => '0'); - D_COUNT <= D_COUNT+1; - if (D_COUNT(16) = '1') then - D_COUNT <= (others => '0'); - DELAY_DONE(2) <= '1'; + W_COUNT <= (others => '0');
+ D_COUNT <= D_COUNT+1;
+ if (D_COUNT(16) = '1') then
+ D_COUNT <= (others => '0');
+ DELAY_DONE(2) <= '1';
end if;
elsif (PG_S2(3) = '1' and EN_BUF(3) = '1' and DELAY_DONE(3) = '0') then
- W_COUNT <= (others => '0'); - D_COUNT <= D_COUNT+1; - if (D_COUNT(16) = '1') then - D_COUNT <= (others => '0'); - DELAY_DONE(3) <= '1'; + W_COUNT <= (others => '0');
+ D_COUNT <= D_COUNT+1;
+ if (D_COUNT(16) = '1') then
+ D_COUNT <= (others => '0');
+ DELAY_DONE(3) <= '1';
end if;
elsif (PG_S2(4) = '1' and EN_BUF(4) = '1' and DELAY_DONE(4) = '0') then
- W_COUNT <= (others => '0'); - D_COUNT <= D_COUNT+1; - if (D_COUNT(16) = '1') then - D_COUNT <= (others => '0'); - DELAY_DONE(4) <= '1'; + W_COUNT <= (others => '0');
+ D_COUNT <= D_COUNT+1;
+ if (D_COUNT(16) = '1') then
+ D_COUNT <= (others => '0');
+ DELAY_DONE(4) <= '1';
end if;
elsif (PG_S2(5) = '1' and EN_BUF(5) = '1' and DELAY_DONE(5) = '0') then
- W_COUNT <= (others => '0'); - D_COUNT <= D_COUNT+1; - if (D_COUNT(16) = '1') then - D_COUNT <= (others => '0'); - DELAY_DONE(5) <= '1'; - end if; + W_COUNT <= (others => '0');
+ D_COUNT <= D_COUNT+1;
+ if (D_COUNT(16) = '1') then
+ D_COUNT <= (others => '0');
+ DELAY_DONE(5) <= '1';
+ end if;
elsif (PG_S2(6) = '1' and EN_BUF(6) = '1' and DELAY_DONE(6) = '0') then
- W_COUNT <= (others => '0'); - D_COUNT <= D_COUNT+1; - if (D_COUNT(16) = '1') then - D_COUNT <= (others => '0'); - DELAY_DONE(6) <= '1'; - end if; + W_COUNT <= (others => '0');
+ D_COUNT <= D_COUNT+1;
+ if (D_COUNT(16) = '1') then
+ D_COUNT <= (others => '0');
+ DELAY_DONE(6) <= '1';
+ end if;
elsif (PG_S2(7) = '1' and EN_BUF(7) = '1' and DELAY_DONE(7) = '0') then
- W_COUNT <= (others => '0'); - D_COUNT <= D_COUNT+1; - if (D_COUNT(16) = '1') then - D_COUNT <= (others => '0'); - DELAY_DONE(7) <= '1'; - end if; + W_COUNT <= (others => '0');
+ D_COUNT <= D_COUNT+1;
+ if (D_COUNT(16) = '1') then
+ D_COUNT <= (others => '0');
+ DELAY_DONE(7) <= '1';
+ end if;
elsif (PG_S2(8) = '1' and EN_BUF(8) = '1' and DELAY_DONE(8) = '0') then
- W_COUNT <= (others => '0'); - D_COUNT <= D_COUNT+1; - if (D_COUNT(16) = '1') then - D_COUNT <= (others => '0'); - DELAY_DONE(8) <= '1'; - end if; + W_COUNT <= (others => '0');
+ D_COUNT <= D_COUNT+1;
+ if (D_COUNT(16) = '1') then
+ D_COUNT <= (others => '0');
+ DELAY_DONE(8) <= '1';
+ end if;
elsif (PG_S2(9) = '1' and EN_BUF(9) = '1' and DELAY_DONE(9) = '0') then
- W_COUNT <= (others => '0'); - D_COUNT <= D_COUNT+1; - if (D_COUNT(16) = '1') then - D_COUNT <= (others => '0'); - DELAY_DONE(9) <= '1'; + W_COUNT <= (others => '0');
+ D_COUNT <= D_COUNT+1;
+ if (D_COUNT(16) = '1') then
+ D_COUNT <= (others => '0');
+ DELAY_DONE(9) <= '1';
end if;
elsif (PG_S2(10) = '1' and EN_BUF(10) = '1' and DELAY_DONE(10) = '0') then
- W_COUNT <= (others => '0'); - D_COUNT <= D_COUNT+1; - if (D_COUNT(16) = '1') then - D_COUNT <= (others => '0'); - DELAY_DONE(10) <= '1'; - end if; + W_COUNT <= (others => '0');
+ D_COUNT <= D_COUNT+1;
+ if (D_COUNT(16) = '1') then
+ D_COUNT <= (others => '0');
+ DELAY_DONE(10) <= '1';
+ end if;
elsif (PG_S2(11) = '1' and EN_BUF(11) = '1' and DELAY_DONE(11) = '0') then
- W_COUNT <= (others => '0'); - D_COUNT <= D_COUNT+1; - if (D_COUNT(16) = '1') then - D_COUNT <= (others => '0'); - DELAY_DONE(11) <= '1'; - end if; + W_COUNT <= (others => '0');
+ D_COUNT <= D_COUNT+1;
+ if (D_COUNT(16) = '1') then
+ D_COUNT <= (others => '0');
+ DELAY_DONE(11) <= '1';
+ end if;
elsif (PG_S2(12) = '1' and EN_BUF(12) = '1' and DELAY_DONE(12) = '0') then
- W_COUNT <= (others => '0'); - D_COUNT <= D_COUNT+1; - if (D_COUNT(16) = '1') then - D_COUNT <= (others => '0'); - DELAY_DONE(12) <= '1'; - end if; + W_COUNT <= (others => '0');
+ D_COUNT <= D_COUNT+1;
+ if (D_COUNT(16) = '1') then
+ D_COUNT <= (others => '0');
+ DELAY_DONE(12) <= '1';
+ end if;
elsif (PG_S2(13) = '1' and EN_BUF(13) = '1' and DELAY_DONE(13) = '0') then
- W_COUNT <= (others => '0'); - D_COUNT <= D_COUNT+1; - if (D_COUNT(16) = '1') then - D_COUNT <= (others => '0'); - DELAY_DONE(13) <= '1'; - end if; + W_COUNT <= (others => '0');
+ D_COUNT <= D_COUNT+1;
+ if (D_COUNT(16) = '1') then
+ D_COUNT <= (others => '0');
+ DELAY_DONE(13) <= '1';
+ end if;
elsif (PG_S2(14) = '1' and EN_BUF(14) = '1' and DELAY_DONE(14) = '0') then
- W_COUNT <= (others => '0'); - D_COUNT <= D_COUNT+1; - if (D_COUNT(16) = '1') then - D_COUNT <= (others => '0'); - DELAY_DONE(14) <= '1'; + W_COUNT <= (others => '0');
+ D_COUNT <= D_COUNT+1;
+ if (D_COUNT(16) = '1') then
+ D_COUNT <= (others => '0');
+ DELAY_DONE(14) <= '1';
end if;
-- Error Checks
@@ -506,10 +506,10 @@ I2C_SLAVE: entity work.I2C_slave generic map(i2c_addr) port map( --Enable outputs
-- Shut everything off if ann error has occurred
-- Otherwise, if system enable is up, then enable short delay is done after previous rail
- -- Otherwise, disable after next rail goes down + -- Otherwise, disable after next rail goes down
EN_BUF(0) <= (SYSEN_S2 or PG_S2(1)) and not ERR_FOUND;
- EN_BUF(1) <= ((SYSEN_S2 and DELAY_DONE(0)) or PG_S2(2)) and not ERR_FOUND; - EN_BUF(2) <= ((SYSEN_S2 and DELAY_DONE(1)) or PG_S2(3)) and not ERR_FOUND; + EN_BUF(1) <= ((SYSEN_S2 and DELAY_DONE(0)) or PG_S2(2)) and not ERR_FOUND;
+ EN_BUF(2) <= ((SYSEN_S2 and DELAY_DONE(1)) or PG_S2(3)) and not ERR_FOUND;
EN_BUF(3) <= ((SYSEN_S2 and DELAY_DONE(2)) or PG_S2(4)) and not ERR_FOUND;
EN_BUF(4) <= ((SYSEN_S2 and DELAY_DONE(3)) or PG_S2(5)) and not ERR_FOUND;
EN_BUF(5) <= ((SYSEN_S2 and DELAY_DONE(4)) or PG_S2(6)) and not ERR_FOUND;
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