Add initial pre-PAR simulation framework from internal files

1 files changed, 6 insertions, 6 deletions

diff --git a/main.v b/main.v
index 07ae362..43f8667 100644
--- a/main.v
+++ b/main.v
@@ -59,8 +59,8 @@ module system_fpga_top
 
 		// Second CPU presence detect
 		input wire cpub_present_l,
-		output wire cpub_clk_oea,
-		output wire cpub_clk_oeb,
+		output reg cpub_clk_oea,
+		output reg cpub_clk_oeb,
 
 		// Resets
 		output reg lpc_rst,
@@ -75,7 +75,7 @@ module system_fpga_top
 		output reg window_open_n,
 
 		// BMC system reset signalling
-		inout bmc_system_reset_request_n,
+		output reg bmc_system_reset_request_n,
 
 		// Component disable lines
 		output reg pmc_disable_n,
@@ -290,9 +290,9 @@ module system_fpga_top
 	reg [7:0] i2c_write_reg_latch = 0;
 
 	// Front panel control signals
-	wire panel_nic1_led_cathode_std;
-	wire panel_nic2_led_cathode_std;
-	wire panel_uid_led_std;
+	reg panel_nic1_led_cathode_std;
+	reg panel_nic2_led_cathode_std;
+	reg panel_uid_led_std;
 	reg [2:0] bmc_startup_kr = 3'b000;
 	reg [2:0] bmc_startup_fader = 3'b000;
 	reg [2:0] bmc_startup_staggered_fader = 3'b000;