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authorRaptor Engineering Development Team <support@raptorengineering.com>2018-01-19 07:09:07 -0600
committerRaptor Engineering Development Team <support@raptorengineering.com>2018-01-19 07:09:07 -0600
commit080b8788b19cfcfdfd1a5c42b8a23558c3767ee2 (patch)
treeace2e1aad387e7902f841dd4322f8750785bf955 /i2c_slave.v
parent1a342cd81411efb03fc3827ee160ed3fbf06f7ef (diff)
downloadtalos-system-fpga-080b8788b19cfcfdfd1a5c42b8a23558c3767ee2.zip
talos-system-fpga-080b8788b19cfcfdfd1a5c42b8a23558c3767ee2.tar.gz
Add I2C write capability
Add front panel LED override
Diffstat (limited to 'i2c_slave.v')
-rw-r--r--i2c_slave.v11
1 files changed, 9 insertions, 2 deletions
diff --git a/i2c_slave.v b/i2c_slave.v
index 14c97f6..ca1b687 100644
--- a/i2c_slave.v
+++ b/i2c_slave.v
@@ -1,5 +1,5 @@
// Copyright © 2014-2016 Peter Samarin
-// Copyright © 2017 Raptor Engineering, LLC
+// Copyright © 2017-2018 Raptor Engineering, LLC
// All Rights Reserved
//
// See I2C_SLAVE_LICENSE file for licensing details
@@ -20,7 +20,8 @@ module i2c_slave(
output wire read_req,
input wire [7:0] data_to_master,
output wire data_valid,
- output wire [7:0] data_from_master
+ output wire [7:0] data_from_master,
+ output wire [7:0] write_cycle_count
);
parameter [6:0] SLAVE_ADDR = 0;
@@ -47,6 +48,7 @@ module i2c_slave(
reg scl_falling_reg = 1'b0; // Address and data received from master
reg [6:0] addr_reg = 1'b0;
reg [7:0] data_reg = 1'b0; // Delayed SCL (by 1 clock cycle, and by 2 clock cycles)
+ reg [7:0] wr_cyc_count_reg = 8'b00000000;
reg scl_reg = 1'b1;
reg scl_prev_reg = 1'b1; // Slave writes on scl
wire scl_wen_reg = 1'b0;
@@ -110,6 +112,7 @@ module i2c_slave(
if (start_reg == 1'b1) begin
state_reg <= i2c_get_address_and_cmd;
bits_processed_reg <= 0;
+ wr_cyc_count_reg <= 0;
end
end
i2c_get_address_and_cmd : begin
@@ -163,6 +166,7 @@ module i2c_slave(
end
if (bits_processed_reg == 7) begin
data_valid_reg <= 1'b1;
+ wr_cyc_count_reg <= wr_cyc_count_reg + 1;
end
end
if (scl_falling_reg == 1'b1 && bits_processed_reg == 8) begin
@@ -231,10 +235,12 @@ module i2c_slave(
if (start_reg == 1'b1) begin
state_reg <= i2c_get_address_and_cmd;
bits_processed_reg <= 0;
+ wr_cyc_count_reg <= 0;
end
if (stop_reg == 1'b1) begin
state_reg <= i2c_idle;
bits_processed_reg <= 0;
+ wr_cyc_count_reg <= 0;
end
if (rst == 1'b1) begin
state_reg <= i2c_idle;
@@ -254,6 +260,7 @@ module i2c_slave(
// Master writes
assign data_valid = data_valid_reg;
assign data_from_master = data_reg;
+ assign write_cycle_count = wr_cyc_count_reg;
// Master reads
assign read_req = read_req_reg;
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