talos-skiboot/include, branch 04-16-2019

Expose PNOR Flash partitions to host MTD driver via devicetree

2019-04-24T08:01:49+00:00

Signed-off-by: Timothy Pearson

Write boot progress to LPC port 80h

2019-04-24T08:01:48+00:00

This is an adaptation of what we currently do for op_display() on FSP machines, inventing an encoding for what we can write into the single byte at LPC port 80h. Port 80h is often used on x86 systems to indicate boot progress/status and dates back a decent amount of time. Since a byte isn't exactly very expressive for everything that can go on (and wrong) during boot, it's all about compromise. Some systems (such as Zaius/Barreleye G2) have a physical dual 7 segment display that display these codes. So far, this has only been driven by hostboot (see hostboot commit 90ec2e65314c). Signed-off-by: Stewart Smith

asm/head.S: set POWER9 radix HID bit at entry

2019-04-17T05:56:34+00:00

When running in virtual memory mode, the radix MMU hid bit should not be changed, so set this in the initial boot SPR setup. As a side effect, fast reboot also has HID0:RADIX bit set by the shared spr init, so no need for an explicit call. Signed-off-by: Nicholas Piggin Signed-off-by: Stewart Smith

chiptod: Remove unused prototype from header

2019-04-16T23:26:40+00:00

There is prototype for chiptod_reset_tb() in include/chiptod.h. However no definition is ever provided, nor is it ever used. Remove the prototype. Signed-off-by: Jordan Niethe Signed-off-by: Stewart Smith

hw/npu2: Dump (more) npu2 registers on link error and HMIs

2019-04-09T00:50:55+00:00

We were already logging some NPU registers during an HMI. This patch cleans up a bit how it is done and separates what is global from what is specific to nvlink or opencapi. Since we can now receive an error interrupt when an opencapi link goes down unexpectedly, we also dump the NPU state but we limit it to the registers of the brick which hit the error. The list of registers to dump was worked out with the hw team to allow for proper debugging. For each register, we print the name as found in the NPU workbook, the scom address and the register value. Signed-off-by: Frederic Barrat Reviewed-by: Andrew Donnellan Signed-off-by: Stewart Smith

hw/npu2: Report errors to the OS if an OpenCAPI brick is fenced

2019-04-09T00:50:55+00:00

Now that the NPU may report interrupts due to the link going down unexpectedly, report those errors to the OS when queried by the 'next_error' PHB callback. The hardware doesn't support recovery of the link when it goes down unexpectedly. So we report the PHB as dead, so that the OS can log the proper message, notify the drivers and take the devices down. Signed-off-by: Frederic Barrat Reviewed-by: Andrew Donnellan Signed-off-by: Stewart Smith

hw/npu2: Setup an error interrupt on some opencapi FIRs

2019-04-09T00:50:55+00:00

Many errors reported in the NPU FIR2 register, mostly catching unexpected errors on the opencapi link are defined as 'brick fatal' in the workbook, yet the default action is set to system checkstop. It's possible to see those errors during AFU development, where the AFU may send unexpected packets on the link, therefore triggering those errors. Checkstopping the system in this case is clearly extreme, as the error could be contained to the brick and proper analysis of a checkstop is not trivial outside of a bringup environment. This patch changes the default action of those errors so that the NPU will raise an interrupt instead. Follow-up patches will log proper information so that the error can be debugged and linux can catch the event. Signed-off-by: Frederic Barrat Reviewed-by: Andrew Donnellan Signed-off-by: Stewart Smith

hw/npu2: Use NVLink irq setup for OpenCAPI

2019-04-09T00:50:55+00:00

Start using the irq setup code from NVLink for OpenCAPI, since the 2 versions are so close. There are only 2 differences: - the NPU may trigger more interrupts for OpenCAPI, 35 vs. 23, though none are configured to be triggered for now. - we need to enable the 4 translation faults interrupts for OpenCAPI. Signed-off-by: Frederic Barrat Signed-off-by: Andrew Donnellan Signed-off-by: Stewart Smith

hw/npu2: Fix OpenCAPI PE assignment

2019-04-09T00:50:55+00:00

When we support mixing NVLink and OpenCAPI devices on the same NPU, we're going to have to share the same range of 16 PE numbers between NVLink and OpenCAPI PHBs. For OpenCAPI devices, PE assignment is only significant for determining which System Interrupt Log register is used for a particular brick - unlike NVLink, it doesn't play any role in determining how links are fenced. Split the PE range into a lower half which is used for NVLink, and an upper half that is used for OpenCAPI, with a fixed PE number assigned per brick. As the PE assignment for OpenCAPI devices is fixed, set the PE once during device init and then ignore calls to the set_pe() operation. Suggested-by: Frederic Barrat Signed-off-by: Andrew Donnellan Signed-off-by: Stewart Smith

opal-api: Reserve 2 OPAL API calls for future OpenCAPI LPC use

2019-04-09T00:50:55+00:00

OpenCAPI Lowest Point of Coherency (LPC) memory is going to require some extra OPAL calls to set up NPU BARs. These calls will most likely be called OPAL_NPU_LPC_ALLOC and OPAL_NPU_LPC_RELEASE, we're not quite ready to upstream that code yet though. Reserve 171 and 172 for this purpose. Signed-off-by: Andrew Donnellan Signed-off-by: Stewart Smith