talos-skiboot/core, branch master

Disable fast reset unless explicitly enabled

2018-04-30T08:55:48+00:00

Fast reset causes the OCC to randomly stop communicating with the BMC, leading to a fan control failure and possible second CPU guard due to the resultant FSI bus communication issues. Disable until Issue 1699 (https://github.com/openbmc/openbmc/issues/1699) is fixed

Mark all partitions except full PNOR and boot kernel firmware read only

2018-04-30T08:55:23+00:00

Expose PNOR Flash partitions to host MTD driver via devicetree

2018-04-30T08:55:23+00:00

Signal skiboot completion to BMC when done

2018-04-30T08:55:22+00:00

OPAL_PCI_SET_POWER_STATE: fix locking in error paths

2018-04-30T00:52:06+00:00

Otherwise we could exit OPAL holding locks, potentially leading to all sorts of problems later on. Cc: stable # 5.3+ Fixes: 7a3e2c4ee3aa0 Signed-off-by: Stewart Smith

core/pci-dt-slots: Fix devfn lookup

2018-04-30T00:50:11+00:00

We only want to use the device part of the bdfn when looking up the switch down port. The required bit twiddling happens inside find_devfn() and the masking here is broken since: a) Keeps the fn part of the bdfn, and b) Masks off part of the device number. This breaks looking up the slot information in some cases. Fixes: 6878b806682f ("pci-dt-slot: Big ol' cleanup") Signed-off-by: Oliver O'Halloran Signed-off-by: Stewart Smith

opal/hmi: Generate one event per core for processor recovery.

2018-04-24T05:11:50+00:00

Processor recovery is per core error. All threads on that core receive HMI. All threads don't need to generate HMI event for same error. Let thread 0 only generate the event. Signed-off-by: Mahesh Salgaonkar Signed-off-by: Stewart Smith

opal:hmi: Add missing processor recovery reason string.

2018-04-24T05:11:50+00:00

With this patch now we see reason string printed for CORE_WOF[43] bit. [ 477.352234986,7] HMI: [Loc: U78D3.001.WZS004A-P1-C48]: P:8 C:22 T:3: Processor recovery occurred. [ 477.352240742,7] HMI: Core WOF = 0x0000000000100000 recovered error: [ 477.352242181,7] HMI: PC - Thread hang recovery Signed-off-by: Mahesh Salgaonkar Signed-off-by: Stewart Smith

pci-dt-slot: Big ol' cleanup

2018-04-23T05:06:59+00:00

The underlying data that we get from HDAT can only really describe a PCIe system. As such we can simplify the devicetree slot lookup code by only caring about the important cases, namly, root ports and switch downstream ports. This also fixes a bug where root port didn't get a Slot label applied which results in devices under that port not having ibm,loc-code set. This results in the EEH core being unable to report the location of EEHed devices under that port. Signed-off-by: Oliver O'Halloran Signed-off-by: Stewart Smith

sensors: Dont add DTS sensors when OCC inband sensors are available

2018-04-19T23:56:06+00:00

There are two sets of core temperature sensors today. One is DTS scom based core temperature sensors and the second group is the sensors provided by OCC. DTS is the highest temperature among the different temperature zones in the core while OCC core temperature sensors are the average temperature of the core. DTS sensors are read directly by the host by SCOMing the DTS sensors while OCC sensors are read and updated by OCC to main memory. Reading DTS sensors by SCOMing is a heavy and slower operation as compared to reading OCC sensors which is as good as reading memory. So dont add DTS sensors when OCC sensors are available. Signed-off-by: Shilpasri G Bhat Acked-by: Vaidyanathan Srinivasan Signed-off-by: Stewart Smith