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<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_hcd_core_startclocks_errors.xml $ -->
<!-- -->
<!-- OpenPOWER sbe Project -->
<!-- -->
<!-- Contributors Listed Below - COPYRIGHT 2015,2016 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
<!-- you may not use this file except in compliance with the License. -->
<!-- You may obtain a copy of the License at -->
<!-- -->
<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
<!-- -->
<!-- Unless required by applicable law or agreed to in writing, software -->
<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
<!-- implied. See the License for the specific language governing -->
<!-- permissions and limitations under the License. -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
<!-- Error definitions for p9_hcd_cache_startclocks procedures -->
<hwpErrors>
<!-- ********************************************************************* -->
<hwpError>
<sbeError/>
<rc>RC_PMPROC_CORECPLTALIGN_TIMEOUT</rc>
<description>
core chiplets alignment timed out.
</description>
<ffdc>CORECPLTSTAT0</ffdc>
</hwpError>
<!-- ********************************************************************* -->
<hwpError>
<sbeError/>
<rc>RC_PMPROC_QUADCPLTALIGN_FAILED</rc>
<description>
quad chiplets alignment failed.
</description>
<ffdc>QUADCPLTSTAT0</ffdc>
</hwpError>
<!-- ********************************************************************* -->
<hwpError>
<sbeError/>
<rc>RC_PMPROC_CORECPLTALIGN_FAILED</rc>
<description>
core chiplets alignment failed.
</description>
<ffdc>CORECPLTSTAT0</ffdc>
</hwpError>
<!-- ********************************************************************* -->
<hwpError>
<sbeError/>
<rc>RC_PMPROC_CORE_XSTOP</rc>
<description>
core checkstops.
</description>
<ffdc>COREXFIR</ffdc>
</hwpError>
<!-- ********************************************************************* -->
<hwpError>
<sbeError/>
<rc>RC_PMPROC_CORECLKSYNC_TIMEOUT</rc>
<description>
core clock sync done timed out.
</description>
<ffdc>COREPPMCACSR</ffdc>
</hwpError>
<!-- ********************************************************************* -->
<hwpError>
<sbeError/>
<rc>RC_PMPROC_CORECLKSTART_FAILED</rc>
<description>
core clock start failed.
</description>
<ffdc>CORECLKSTAT</ffdc>
</hwpError>
<!-- ********************************************************************* -->
<hwpError>
<sbeError/>
<rc>RC_PMPROC_CORECLKSTART_TIMEOUT</rc>
<description>
core clock start timed out.
</description>
<ffdc>CORECPLTSTAT</ffdc>
<callout>
<childTargets>
<parent>PROC_CHIP_IN_ERROR</parent>
<childType>TARGET_TYPE_EX_CHIPLET</childType>
<childNumber>EX_NUMBER_IN_ERROR</childNumber>
</childTargets>
<priority>HIGH</priority>
</callout>
<deconfigure>
<childTargets>
<parent>PROC_CHIP_IN_ERROR</parent>
<childType>TARGET_TYPE_EX_CHIPLET</childType>
<childNumber>EX_NUMBER_IN_ERROR</childNumber>
</childTargets>
</deconfigure>
<gard>
<childTargets>
<parent>PROC_CHIP_IN_ERROR</parent>
<childType>TARGET_TYPE_EX_CHIPLET</childType>
<childNumber>EX_NUMBER_IN_ERROR</childNumber>
</childTargets>
</gard>
</hwpError>
<!-- ********************************************************************* -->
</hwpErrors>
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