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path: root/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml
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<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
<!-- This is an automatically generated prolog.                             -->
<!--                                                                        -->
<!-- $Source: src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_dpll_setup_errors.xml $ -->
<!--                                                                        -->
<!-- OpenPOWER sbe Project                                                  -->
<!--                                                                        -->
<!-- Contributors Listed Below - COPYRIGHT 2015,2016                        -->
<!-- [+] International Business Machines Corp.                              -->
<!--                                                                        -->
<!--                                                                        -->
<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
<!-- you may not use this file except in compliance with the License.       -->
<!-- You may obtain a copy of the License at                                -->
<!--                                                                        -->
<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
<!--                                                                        -->
<!-- Unless required by applicable law or agreed to in writing, software    -->
<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
<!-- implied. See the License for the specific language governing           -->
<!-- permissions and limitations under the License.                         -->
<!--                                                                        -->
<!-- IBM_PROLOG_END_TAG                                                     -->
<!-- Error definitions for p9 dpll_setup procedures -->
<hwpErrors>
  <!-- ********************************************************************* -->
  <hwpError>
    <sbeError/>
    <rc>RC_PMPROC_DPLL_LOCK_TIMEOUT</rc>
    <description>
        DPLL is not locking.
    </description>
    <ffdc>EQQPPMDPLLSTAT</ffdc>
    <callout>
      <childTargets>
        <parent>PROC_CHIP_IN_ERROR</parent>
        <childType>TARGET_TYPE_EX_CHIPLET</childType>
        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
      </childTargets>
      <priority>HIGH</priority>
    </callout>
    <deconfigure>
      <childTargets>
        <parent>PROC_CHIP_IN_ERROR</parent>
        <childType>TARGET_TYPE_EX_CHIPLET</childType>
        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
      </childTargets>
    </deconfigure>
    <gard>
      <childTargets>
        <parent>PROC_CHIP_IN_ERROR</parent>
        <childType>TARGET_TYPE_EX_CHIPLET</childType>
        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
      </childTargets>
    </gard>
  </hwpError>
  <!-- ********************************************************************* -->
  <hwpError>
    <sbeError/>
    <rc>RC_PMPROC_DPLLCLKSTART_TIMEOUT</rc>
    <description>
        dpll clock start timed out.
    </description>
    <ffdc>EQCPLTSTAT</ffdc>
    <callout>
      <childTargets>
        <parent>PROC_CHIP_IN_ERROR</parent>
        <childType>TARGET_TYPE_EX_CHIPLET</childType>
        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
      </childTargets>
      <priority>HIGH</priority>
    </callout>
    <deconfigure>
      <childTargets>
        <parent>PROC_CHIP_IN_ERROR</parent>
        <childType>TARGET_TYPE_EX_CHIPLET</childType>
        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
      </childTargets>
    </deconfigure>
    <gard>
      <childTargets>
        <parent>PROC_CHIP_IN_ERROR</parent>
        <childType>TARGET_TYPE_EX_CHIPLET</childType>
        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
      </childTargets>
    </gard>
  </hwpError>
  <!-- ********************************************************************* -->
  <hwpError>
    <sbeError/>
    <rc>RC_PMPROC_DPLLCLKSTART_FAILED</rc>
    <description>
        dpll clock start failed.
    </description>
    <ffdc>EQCLKSTAT</ffdc>
  </hwpError>
  <!-- ********************************************************************* -->
  <hwpError>
    <sbeError/>
    <rc>RC_PMPROC_ANEPCLKSTART_TIMEOUT</rc>
    <description>
        anep clock start timed out.
    </description>
    <ffdc>EQCPLTSTAT</ffdc>
    <callout>
      <childTargets>
        <parent>PROC_CHIP_IN_ERROR</parent>
        <childType>TARGET_TYPE_EX_CHIPLET</childType>
        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
      </childTargets>
      <priority>HIGH</priority>
    </callout>
    <deconfigure>
      <childTargets>
        <parent>PROC_CHIP_IN_ERROR</parent>
        <childType>TARGET_TYPE_EX_CHIPLET</childType>
        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
      </childTargets>
    </deconfigure>
    <gard>
      <childTargets>
        <parent>PROC_CHIP_IN_ERROR</parent>
        <childType>TARGET_TYPE_EX_CHIPLET</childType>
        <childNumber>EX_NUMBER_IN_ERROR</childNumber>
      </childTargets>
    </gard>
  </hwpError>
  <!-- ********************************************************************* -->
</hwpErrors>
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