1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
|
/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/import/chips/p9/procedures/hwp/perv/p9_sbe_gear_switcher.C $ */
/* */
/* OpenPOWER sbe Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2016 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
//------------------------------------------------------------------------------
/// @file p9_sbe_gear_switcher.C
///
/// @brief Modules for I2C Bit rate divisor setting
/// And stop sequence on I2C
//------------------------------------------------------------------------------
// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com>
// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com>
// *HWP Team : Perv
// *HWP Level : 2
// *HWP Consumed by : SBE
//------------------------------------------------------------------------------
//## auto_generated
#include "p9_sbe_gear_switcher.H"
#include "p9_misc_scom_addresses.H"
#include "p9_perv_scom_addresses.H"
enum P9_SBE_GEAR_SWITCHER_Private_Constants
{
DEFAULT_MB_BIT_RATE_DIVISOR = 0x00000000,
BUS_STATUS_BUSY_POLL_COUNT = 64
};
/// @brief --adjust I2C bit rate divisor setting in I2CM B mode reg
///
/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target
/// @return FAPI2_RC_SUCCESS if success, else error code.
fapi2::ReturnCode p9_sbe_gear_switcher_apply_i2c_bit_rate_divisor_setting(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
{
fapi2::buffer<uint64_t> l_read_scratch_reg = 0;
uint16_t l_mb_bit_rate_divisor = 0;
FAPI_DBG("Entering ...");
FAPI_INF("Check Mailbox for Valid I2C bit rate divisor setting");
//Getting SCRATCH_REGISTER_2 register value
FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_2_SCOM,
l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_2
if ( !l_read_scratch_reg )
{
FAPI_INF("Set with Default value if Mailbox empty");
//Setting MODE_REGISTER_B register value
//PIB.MODE_REGISTER_B = DEFAULT_MB_BIT_RATE_DIVISOR
FAPI_TRY(fapi2::putScom(i_target_chip, PU_MODE_REGISTER_B,
DEFAULT_MB_BIT_RATE_DIVISOR));
}
else
{
l_read_scratch_reg.extractToRight<0, 16>(l_mb_bit_rate_divisor);
FAPI_INF("Adjust I2C bit rate divisor setting in I2CM B Mode Reg");
//Setting MODE_REGISTER_B register value
//PIB.MODE_REGISTER_B = l_mb_bit_rate_divisor
FAPI_TRY(fapi2::putScom(i_target_chip, PU_MODE_REGISTER_B,
l_mb_bit_rate_divisor));
}
FAPI_DBG("Exiting ...");
fapi_try_exit:
return fapi2::current_err;
}
/// @brief --send a stop sequence on I2C
/// --poll for stop command completion
/// --check for magic number
///
/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target
/// @return FAPI2_RC_SUCCESS if success, else error code.
fapi2::ReturnCode p9_sbe_gear_switcher_i2c_stop_sequence(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
{
uint8_t l_read_attr = 0;
fapi2::buffer<uint64_t> l_data64;
int l_timeout = 0;
FAPI_DBG("Entering ...");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_BACKUP_SEEPROM_SELECT, i_target_chip,
l_read_attr));
// WRITE Control register
// enable enhance mode
// Point to port_0 where the Primary SEEPROM Sits
FAPI_INF("Send a STOP sequence on I2C");
//Setting CONTROL_REGISTER_B register value
FAPI_TRY(fapi2::getScom(i_target_chip, PU_CONTROL_REGISTER_B, l_data64));
l_data64.setBit<3>(); //PIB.CONTROL_REGISTER_B.PIB_CNTR_REG_BIT_WITHSTOP_0 = 1
//PIB.CONTROL_REGISTER_B.PIB_CNTR_REG_PORT_NUMBER_0 = l_read_attr
l_data64.insertFromRight<18, 5>(l_read_attr);
l_data64.setBit<26>(); //PIB.CONTROL_REGISTER_B.ENH_MODE_0 = 1
FAPI_TRY(fapi2::putScom(i_target_chip, PU_CONTROL_REGISTER_B, l_data64));
FAPI_INF("Poll for stop command completion");
l_timeout = BUS_STATUS_BUSY_POLL_COUNT;
//UNTIL STATUS_REGISTER_B.BUS_STATUS_BUSY_0 == 0
while (l_timeout != 0)
{
//Getting STATUS_REGISTER_B register value
FAPI_TRY(fapi2::getScom(i_target_chip, PU_STATUS_REGISTER_B, l_data64));
//bool l_poll_data = PIB.STATUS_REGISTER_B.BUS_STATUS_BUSY_0
bool l_poll_data = l_data64.getBit<44>();
if (l_poll_data == 0)
{
break;
}
--l_timeout;
}
FAPI_INF("Loop Count :%d", l_timeout);
FAPI_ASSERT(l_timeout > 0,
fapi2::BUS_STATUS_BUSY_0(),
"ERROR:BUS_STSTUS_BUSY_0 NOT SET TO 0");
FAPI_DBG("Exiting ...");
fapi_try_exit:
return fapi2::current_err;
}
|
