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/**
* @file plat_hw_access.H
*
* @brief Define platform specific calls for hardware accesses.
*/
#ifndef PLATHWACCESS_H_
#define PLATHWACCESS_H_
#include <plat_includes.H>
/// PIB Error Mask
#define PLAT_SET_PIB_ERROR_MASK(_m_mask) \
{ /* Read MSR */ \
uint32_t msr_data = mfmsr(); \
/* Set SEM field */ \
msr_data &= ~(BITS(0,8)); \
msr_data |= (uint32_t)(i_mask << 24); \
/* Write MSR */ \
mtmsr(msr_data); \
};
#define PLAT_GET_PIB_ERROR_MASK(_m_mask) \
uint8_t _m_mask; \
uint32_t _sem = mfmsr(); \
_m_mask = (uint8_t)((_sem & MSR_SEM) >> (32-(MSR_SEM_START_BIT + MSR_SEM_LEN)));
// Building block PPE instructions
#define PPE_MFMSR(_m_data) \
asm volatile \
( \
"mfmsr %[data] \n" \
: [data]"=&r"(*_m_data) \
: "[data]"(*_m_data) \
);
#define PPE_MTMSR(_m_data) \
asm volatile \
( \
"mtmsr %[data] \n" \
: [data]"=&r"(*_m_data) \
: "[data]"(*_m_data) \
);
/// GetScom
#define PLAT_GETSCOM(_m_rc, _m_base, _m_offset, _m_data) \
_m_rc = getscom(_m_base.getAddressOverlay(), (0 == _m_base.getAddressOverlay())?_m_offset:(uint32_t)(_m_offset & BITS(40,24)), _m_data);
/// PutScom
#define PLAT_PUTSCOM(_m_rc, _m_base, _m_offset, _m_data) \
_m_rc = putscom(_m_base.getAddressOverlay(), (0 == _m_base.getAddressOverlay())?_m_offset:(uint32_t)(_m_offset & BITS(40,24)), _m_data);
/// GetCFAM
#define PLAT_GETCFAM(_m_base, _m_offset, _m_data) \
static_assert( K == TARGET_TYPE_NONE, \
"getCfamRegister is not supported by PPE platforms")
/// PutCFAM
#define PLAT_PUTCFAM(_m_base, _m_offset, _m_data) \
static_assert( K == TARGET_TYPE_NONE, \
"putCfamRegister is not supported by PPE platforms")
/// ModifyCFAM
#define PLAT_MODCFAM(_m_base, _m_offset, _m_data, _m_mode) \
static_assert( K == TARGET_TYPE_NONE, \
"modifyCfamRegister is not supported by PPE platforms")
#endif // PLATHWACCESS_H_
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