ROOT_CTRL_REGISTERS_CFAM
PERV_ROOT_CTRL0_FSI
PERV_ROOT_CTRL1_FSI
PERV_ROOT_CTRL2_FSI
PERV_ROOT_CTRL3_FSI
PERV_ROOT_CTRL4_FSI
PERV_ROOT_CTRL5_FSI
PERV_ROOT_CTRL6_FSI
PERV_ROOT_CTRL7_FSI
PERV_ROOT_CTRL8_FSI
PERV_CTRL_REGISTERS_CFAM
PERV_PERV_CTRL0_FSI
PERV_PERV_CTRL1_FSI
FSI2PIB_STATUS
PERV_FSI2PIB_STATUS_FSI
OSC_SWITCH_SENSE_REGISTER_CFAM
PERV_SNS1LTH_FSI
OSC_SWITCH_SENSE_REGISTER
PERV_SNS1LTH_SCOM
OSC_ERROR_HOLD
PERV_TP_OSCERR_HOLD
ROOT_CTRL_REGISTERS
PERV_ROOT_CTRL0_SCOM
PERV_ROOT_CTRL1_SCOM
PERV_ROOT_CTRL2_SCOM
PERV_ROOT_CTRL3_SCOM
PERV_ROOT_CTRL4_SCOM
PERV_ROOT_CTRL5_SCOM
PERV_ROOT_CTRL6_SCOM
PERV_ROOT_CTRL7_SCOM
PERV_ROOT_CTRL8_SCOM
PERV_CTRL_REGISTERS
PERV_PERV_CTRL0_SCOM
PERV_PERV_CTRL1_SCOM
NET_CTRL_REGISTERS
PERV_NET_CTRL0
PERV_NET_CTRL1
CPLT_CTRL_REGISTERS
PERV_CPLT_CTRL0
PERV_CPLT_CTRL1
CPLT_CONFIG_REGISTERS
PERV_CPLT_CONF0
PERV_CPLT_CONF1
OTHER_CPLT_REGISTERS
PERV_CPLT_STAT0
PERV_CPLT_MASK0
PLL_LOCK_REG
PERV_PLL_LOCK_REG
I2C_REGISTERS
PU_CONTROL_REGISTER_B
PU_STATUS_REGISTER_B
PU_COMMAND_REGISTER_B
PU_MODE_REGISTER_B
PU_WATER_MARK_REGISTER_B
PU_INTERRUPT_MASK_REGISTER_READ_B
PU_INTERRUPT_COND_B
PU_INTERRUPTS_B
PU_STATUS_REGISTER_ENGINE_B
PU_EXTENDED_STATUS_B
PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B
PU_I2C_BUSY_REGISTER_B
PIBMEM_REGISTERS
PU_PIBMEM_CONTROL_REGISTER
PU_PIBMEM_STATUS_REG
PU_PIBMEM_REPAIR_REGISTER_0
PU_PIBMEM_REPAIR_REGISTER_1
PU_PIBMEM_REPAIR_REGISTER_2
PU_PIBMEM_REPAIR_REGISTER_3
OTPROM_STATUS
PU_STATUS_REGISTER
OPCG_CTRL_REGISTERS
PERV_OPCG_ALIGN
PERV_OPCG_REG0
PERV_OPCG_REG1
PERV_OPCG_REG2
CC_STATUS_REGISTERS
PERV_SCAN_REGION_TYPE
PERV_CLK_REGION
PERV_CLOCK_STAT_SL
PERV_CLOCK_STAT_NSL
PERV_CLOCK_STAT_ARY
PERV_BIST
ERROR_STATUS_OF_CC
PERV_ERROR_STATUS
CC_REGISTERS
PERV_XSTOP1
PERV_XSTOP2
PERV_XSTOP3
PERV_OPCG_CAPT1
PERV_OPCG_CAPT2
PERV_OPCG_CAPT3
PERV_DBG_CBS_CC
SBE_EXTERNAL_SCOMMABLE_REGISTERS
PU_PPE_XIDBGPRO
PU_PPE_XIRAMEDR
PU_PPE_XIRAMDBG
PU_PPE_XIRAMGA
PU_PPE_XIRAMRA
PU_PPE_XIXCR
RC_ARY_ERR
ary_thold status not matching the expected value in clock start stop sequence
TARGET_CHIPLET
NET_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CPLT_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CPLT_CONFIG_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
OTHER_CPLT_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
OPCG_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CC_STATUS_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
ERROR_STATUS_OF_CC
TARGET_CHIPLET
TARGET_TYPE_PERV
CC_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
READ_CLK_ARY
RC_NSL_ERR
nsl_thold status not matching the expected value in clock start stop sequence
TARGET_CHIPLET
NET_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CPLT_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CPLT_CONFIG_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
OTHER_CPLT_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
OPCG_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CC_STATUS_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
ERROR_STATUS_OF_CC
TARGET_CHIPLET
TARGET_TYPE_PERV
CC_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
READ_CLK_NSL
RC_SL_ERR
sl_thold status not matching the expected value in clock start stop sequence
TARGET_CHIPLET
NET_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CPLT_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CPLT_CONFIG_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
OTHER_CPLT_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
OPCG_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CC_STATUS_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
ERROR_STATUS_OF_CC
TARGET_CHIPLET
TARGET_TYPE_PERV
CC_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
READ_CLK_SL
RC_CPLT_NOT_ALIGNED_ERR
Chiplet not aligned
TARGET_CHIPLET
NET_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CPLT_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CPLT_CONFIG_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
OTHER_CPLT_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
OPCG_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CC_STATUS_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
ERROR_STATUS_OF_CC
TARGET_CHIPLET
TARGET_TYPE_PERV
CC_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
PERV_CPLT_STAT0
LOOP_COUNT
HW_DELAY
RC_CPLT_OPCG_DONE_NOT_SET_ERR
Chiplet OPCG_DONE not set after clock start/stop command
TARGET_CHIPLET
NET_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CPLT_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CPLT_CONFIG_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
OTHER_CPLT_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
OPCG_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CC_STATUS_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
ERROR_STATUS_OF_CC
TARGET_CHIPLET
TARGET_TYPE_PERV
CC_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
PERV_CPLT_STAT0
LOOP_COUNT
HW_DELAY
RC_NEST_ARY_ERR
ary_thold status not matching the expected value in clock start stop sequence
TARGET_CHIPLET
NET_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CPLT_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CPLT_CONFIG_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
OTHER_CPLT_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
OPCG_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CC_STATUS_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
ERROR_STATUS_OF_CC
TARGET_CHIPLET
TARGET_TYPE_PERV
CC_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
READ_CLK_ARY
RC_NEST_NSL_ERR
nsl_thold status not matching the expected value in clock start stop sequence
TARGET_CHIPLET
NET_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CPLT_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CPLT_CONFIG_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
OTHER_CPLT_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
OPCG_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CC_STATUS_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
ERROR_STATUS_OF_CC
TARGET_CHIPLET
TARGET_TYPE_PERV
CC_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
READ_CLK_NSL
RC_NEST_SL_ERR
sl_thold status not matching the expected value in clock start stop sequence
TARGET_CHIPLET
NET_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CPLT_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CPLT_CONFIG_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
OTHER_CPLT_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
OPCG_CTRL_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
CC_STATUS_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
ERROR_STATUS_OF_CC
TARGET_CHIPLET
TARGET_TYPE_PERV
CC_REGISTERS
TARGET_CHIPLET
TARGET_TYPE_PERV
READ_CLK_SL