ATTR_PROC_DPLL_DIVIDER TARGET_TYPE_PROC_CHIP The product of the DPLL internal prescalar divide (CD_DIV124_DC) and the output divider(CD_DPLLOUT124_DC). This estalishes the step size of the DPLL in terms of this number divided into the processor reference clock. if 0, consuming procedures will assume a default of 8. Provided to override default value uint32 ATTR_STOPGPE_BOOT_COPIER_IVPR_OFFSET TARGET_TYPE_PROC_CHIP Set by p9_hcode_image build with the offset value from the HOMER base where the SGPE Boot Copier interrupt vectors reside. This value must be 512B aligned. The HOMER base address will be pre-establish in PBABAR0 so the address needs to be off the form 0x8XXXXX00. The SGPE will be Sreset after this value is established. uint32 ATTR_PSTATEGPE_BOOT_COPIER_IVPR_OFFSET TARGET_TYPE_PROC_CHIP Set by p9_hcode_image build with the offset value from the HOMER base where the PGPE Boot Copier interrupt vectors reside. This value must be 512B aligned. The HOMER base address will be pre-establish in PBABAR0 so the address needs to be off the form 0x8XXXXX00. The PGPE will be Sreset after this value is established uint32 ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG TARGET_TYPE_PROC_CHIP Flag storage to have the Special Wakeup procedure ignore a checkstop condition. uint8 ATTR_OCC_LFIR TARGET_TYPE_PROC_CHIP The attribute stores the Local FIR value of OCC taken during the reset phase. uint64 ATTR_PBA_LFIR TARGET_TYPE_PROC_CHIP The attribute stores the Local FIR value of PBA taken during the reset phase. uint64 ATTR_PM_FIRINIT_DONE_ONCE_FLAG TARGET_TYPE_PROC_CHIP 0 = OCC has never been loaded and FIR Masks have never been initialized, 1 = FIR masks have been initialized and the hardware should reflect correct values, 2 = FIR masks have been initialized but the current hardware state is the reset value uint8 ATTR_QUAD_PPM_ERRMASK TARGET_TYPE_EQ The error mask value that has to be restored to the PPM ERRMASK register for the Quad. This value will be stored during the reset phase when the ERRMASK will be cleared as part of the cleanup action. uint32 ATTR_CORE_PPM_ERRMASK TARGET_TYPE_CORE The error mask value that has to be restored to the PPM ERRMASK register for the CORE. This value will be stored during the reset phase when the ERRMASK will be cleared as part of the cleanup action. uint32 ATTR_CME_LOCAL_FIRMASK TARGET_TYPE_EX The FIR mask value that has to be restored to the CME FIR register. This value will be stored during the reset phase when the FIRMASK will be cleared as part of the cleanup action. uint32 ATTR_L2_HASCLOCKS TARGET_TYPE_EX Indicates the L2 region has clocks running and scommable uint8 ATTR_L3_HASCLOCKS TARGET_TYPE_EX Indicates the L3 region has clocks running and scommable uint8 ATTR_C0_EXEC_HASCLOCKS TARGET_TYPE_EX Indicates the execution units in core 0 have clocks running and scommable uint8 ATTR_C1_EXEC_HASCLOCKS TARGET_TYPE_EX Indicates the execution units in core 1 have clocks running and scommable uint8 ATTR_C0_PC_HASCLOCKS TARGET_TYPE_EX Indicates the core pervasive unit in core 0 has clocks running and scommable uint8 ATTR_C1_PC_HASCLOCKS TARGET_TYPE_EX Indicates the core pervasive unit in core 1 has clocks running and scommable uint8 ATTR_L2_HASPOWER TARGET_TYPE_EX Indicates L2 has power and has valid latch state that could be scanned uint8 ATTR_L3_HASPOWER TARGET_TYPE_EX Indicates L3 has power and has valid latch state that could be scanned uint8 ATTR_C0_HASPOWER TARGET_TYPE_EX Indicates core 0 has power and has valid latch state that could be scanned uint8 ATTR_C1_HASPOWER TARGET_TYPE_EX Indicates core 1 has power and has valid latch state that could be scanned uint8 ATTR_PM_SPIPSS_FRAME_SIZE TARGET_TYPE_PROC_CHIP Number of data bits per individual SPIPSS transaction (also referred to as frame) during chip select assertion. Supported values: 0x20 (32d) Chip Select assertion duration is frame_size + 2 uint8 ATTR_PM_SPIPSS_IN_DELAY TARGET_TYPE_PROC_CHIP Number of SPI clocks after chip select to wait before capturing MISO input. Supported values: 0x000 to spi_frame_size. Values beyond spi_frame_size result in the input not being captured uint8 ATTR_PM_SPIPSS_CLOCK_POLARITY TARGET_TYPE_PROC_CHIP SPIPSS Clock Polarity CPOL=0 means that clk idle is deasserted, CPOH=1 means that clk idle is asserted uint8 CPOL=0, CPOH=1 ATTR_PM_SPIPSS_CLOCK_PHASE TARGET_TYPE_PROC_CHIP SPIPSS clock phase CPHA=0 means to change/sample values of data signals on first edge, otherwise on 2nd uint8 FIRSTEDGE=0, SECONDEDGE=1 ATTR_PM_SPIPSS_CLOCK_DIVIDER TARGET_TYPE_PROC_CHIP SPI clock speed divider to divide the nest_nclk/4 mesh clock, which results in a divider = ((nest_freq / (SPI_freq*8)) - 1) uint16 ATTR_PM_SPIPSS_INTER_FRAME_DELAY_SETTING TARGET_TYPE_PROC_CHIP Delay is computed as: (value * ~100ns_hang_pulse) +0/-~100ns_hang_pulse time 0x00000: Wait 1 PSS Clock 0x00001 - 0x1FFFF: value = number of ~100ns_hang_pulses For values greater than 0x00000, the actual delay is 1 PSS Clock + the time delay designated by the value defined. Max. delay at 0x1FFFF: 13.1ms + 1 PSSI clock cycle. uint32 ATTR_PSTATES_ENABLED TARGET_TYPE_PROC_CHIP Indicator that all relevant attributes and required data for Pstates to be enabled is present and valid Producer: p9_build_pstate_datablock Consumers: p9_pm_pstate_gpe_init uint8 FALSE=0, TRUE=1 ATTR_RESCLK_ENABLED TARGET_TYPE_PROC_CHIP Indicator that all relevant attributes and required data for Resonant Clocking to be enabled is present and valid Producer: p9_build_pstate_datablock Consumers: p9_hcode_image_build -> PGPE Header CME Header uint8 FALSE=0, TRUE=1 ATTR_VDM_ENABLED TARGET_TYPE_PROC_CHIP Indicator that all relevant attributes and required data for Voltage Droop Monitors (VDM) to be enabled is present and valid Producer: p9_build_pstate_datablock Consumers: p9_hcode_image_build -> SGPE Header CME Header uint8 FALSE=0, TRUE=1 ATTR_IVRM_ENABLED TARGET_TYPE_PROC_CHIP Indicator that all relevant attributes and required data for Internal Voltage Regulator Macros (IVRMs) to be enabled is present and valid Producer: p9_build_pstate_datablock Consumers: p9_hcode_image_build -> PGPE Header CME Header uint8 FALSE=0, TRUE=1 ATTR_WOF_ENABLED TARGET_TYPE_PROC_CHIP Indicator that all relevent attributes and required data for WOF to be enabled is present and valid Producer: p9_build_pstate_datablock Consumers: p9_hcode_image_build -> PGPE Header CME Header uint8 FALSE=0, TRUE=1 ATTR_CORE_INSIDE_SPECIAL_WAKEUP TARGET_TYPE_CORE Indicates that a special wakeup is in progress for a core. Producer: p9_cpu_special_wakeup_core.C Consumers: p9_cpu_special_wakeup_core.C uint8 FALSE=0, TRUE=1 ATTR_EX_INSIDE_SPECIAL_WAKEUP TARGET_TYPE_EX Indicates that a special wakeup is in progress for an EX. Producer: p9_cpu_special_wakeup_ex.C Consumers: p9_cpu_special_wakeup_ex.C uint8 FALSE=0, TRUE=1 ATTR_EQ_INSIDE_SPECIAL_WAKEUP TARGET_TYPE_EQ Indicates that a special wakeup is in progress for an EQ Producer: p9_cpu_special_wakeup_eq.C Consumers: p9_cpu_special_wakeup_eq.C uint8 FALSE=0, TRUE=1