ATTR_FREQ_PB_MHZ
TARGET_TYPE_SYSTEM
The frequency of a processor's nest mesh clock, in MHz.
This is the same for all chips in the system.
Provided by the MRW.
uint32
1600 = 1600,
1866 = 1866,
2000 = 2000,
2133 = 2133,
2400 = 2400
freq_pb_mhz
ATTR_FREQ_MCA_MHZ
TARGET_TYPE_SYSTEM
The frequency of the memory controller channel. In synchronous mode,
this is equivalent to ATTR_FREQ_PB_MHZ. This may be independently set
per pair of memory channels if operating in asynchronous mode,
but this configuration is not anticipated. This clock drives the MCU queues,
and all the associated logic that drives the inputs to the DMI and reads
its outputs.
uint32
2000 = 2000,
2400 = 2400
ATTR_FREQ_O_MHZ
TARGET_TYPE_PROC_CHIP
The frequency of a processor's Obus mesh clocks, in MHz.
Provided by the MRW.
uint32
4
ATTR_FREQ_A_MHZ
TARGET_TYPE_SYSTEM
The frequency of a processor's Abus, in MHz.
This is the same for all chips in the system.
Provided by the MRW.
uint32
ATTR_FREQ_X_MHZ
TARGET_TYPE_SYSTEM
The frequency of a processor's Xbus mesh clocks, in MHz.
This is the same for all chips in the system.
uint32
ATTR_FREQ_CORE_FLOOR_MHZ
TARGET_TYPE_SYSTEM
The lowest frequency that a core can be set to in MHz.
This is the same for all cores in the system.
Provided by the MVPD #V and is calculated as the max of the
Power Save frequencies.
uint32
ATTR_FREQ_CORE_NOMINAL_MHZ
TARGET_TYPE_SYSTEM
The nominal core frequency in MHz.
This is the same for all cores in the system.
Provided by the #V bucket of module VPD.
uint32
ATTR_FREQ_CORE_CEILING_MHZ
TARGET_TYPE_SYSTEM
The maximum core frequency in MHz.
This is the same for all cores in the system.
Provided by the #V bucket of module VPD and is calculated
as the minimum of the turbo frequencies.
uint32
ATTR_PM_SAFE_FREQUENCY_MHZ
TARGET_TYPE_SYSTEM
Frequency (in MHz) to move to if the Power Management function fails.
This is the same for all cores in the system.
Provided by the MRW.
uint32
ATTR_PM_SAFE_VOLTAGE_MV
TARGET_TYPE_SYSTEM
Voltage (in mV) to move to if the Power Management function fails.
Provided by the MRW.
uint32
ATTR_FREQ_PCIE_MHZ
TARGET_TYPE_SYSTEM
The frequency of a processor's PCI-e bus in MHz.
This is the same for all PCI-e busses in the system.
Provided by the MRW.
uint32
ATTR_DD1_SLOW_PCI_REF_CLOCK
TARGET_TYPE_SYSTEM
MRW control to permit Normal (100 MHz) or Slow (94 MHz) operation
of PCIE reference clock. On Nimbus DD1 HW, Slow operation is required
to achieve Gen4 operation.
Provided by the MRW.
uint8
NORMAL = 0x00,
SLOW = 0x01
ATTR_PROC_FABRIC_ASYNC_SAFE_MODE
TARGET_TYPE_SYSTEM
Set to force all fabric asynchronous boundary crossings into safe mode.
uint8
PERFORMANCE_MODE = 0x0,
SAFE_MODE = 0x1
ATTR_PROC_FABRIC_A_BUS_WIDTH
TARGET_TYPE_SYSTEM
Processor SMP A bus width.
Provided by the MRW.
uint8
2_BYTE = 0x01,
4_BYTE = 0x02
ATTR_PROC_FABRIC_X_BUS_WIDTH
TARGET_TYPE_SYSTEM
Processor SMP X bus width.
Provided by the MRW.
uint8
2_BYTE = 0x01,
4_BYTE = 0x02
ATTR_PROC_FABRIC_CORE_FLOOR_RATIO
TARGET_TYPE_SYSTEM
Processor SMP core floor/nest frequency ratio
uint8
RATIO_8_8 = 0x0,
RATIO_7_8 = 0x1,
RATIO_6_8 = 0x2,
RATIO_5_8 = 0x3,
RATIO_4_8 = 0x4,
RATIO_2_8 = 0x5
ATTR_PROC_FABRIC_CORE_CEILING_RATIO
TARGET_TYPE_SYSTEM
Processor SMP core celing/nest frequency ratio
uint8
RATIO_8_8 = 0x0,
RATIO_7_8 = 0x1,
RATIO_6_8 = 0x2,
RATIO_5_8 = 0x3,
RATIO_4_8 = 0x4,
RATIO_2_8 = 0x5
ATTR_PROC_FABRIC_PUMP_MODE
TARGET_TYPE_SYSTEM
Processor SMP Fabric broadcast scope configuration.
CHIP_IS_NODE = MODE1 = default
CHIP_IS_GROUP = MODE2
Provided by the MRW.
uint8
CHIP_IS_NODE = 0x01,
CHIP_IS_GROUP = 0x02
ATTR_PROC_FABRIC_CCSM_MODE
TARGET_TYPE_SYSTEM
Processor SMP topology configuration.
0 = default = 1 or 2 hop topology (PHYP image spans system)
Provided by the MRW.
uint8
OFF = 0x0
ATTR_OPTICS_CONFIG_MODE
TARGET_TYPE_OBUS
Per-link optics configuration
0 = default = SMP
1 = CAPI 2.0
2 = NV 2.0
3 = OPENCAPI
Provided by the MRW.
uint8
SMP = 0x0,
CAPI = 0x1,
NV = 0x2,
OCAPI = 0x3
ATTR_PROC_FABRIC_SMP_OPTICS_MODE
TARGET_TYPE_SYSTEM
Processor SMP optics mode.
0 = default = Optics_is_X_bus
1 = Optics_is_A_bus
Provided by the MRW.
uint8
OPTICS_IS_X_BUS = 0x0,
OPTICS_IS_A_BUS = 0x1
ATTR_PROC_FABRIC_OPTICS_CONFIG_MODE
TARGET_TYPE_PROC_CHIP
Per-link optics configuration
0 = default = SMP
1 = CAPI 2.0
2 = NV 2.0
uint8
SMP = 0x0,
CAPI = 0x1,
NV = 0x2
4
ATTR_PROC_FABRIC_CAPI_MODE
TARGET_TYPE_SYSTEM
Processor CAPI attachement protocol mode.
0 = default = no: SMPA CAPI attachement
1 = yes: SMPA CAPI attachement
Provided by the MRW.
uint8
OFF = 0x0,
ON = 0x1
ATTR_FABRIC_PRESENT_GROUPS
TARGET_TYPE_SYSTEM
Bit mask of group IDs which will be present in the fully configured
CEC configuration.
Bit 0 -> group 0 present
Bit 1 -> group 1 present
...
Bit 6 -> group 6 present
Bit 7 -> group 7 present
uint8
ATTR_PROC_FABRIC_SYSTEM_ID
TARGET_TYPE_PROC_CHIP
Logical fabric system ID associated with this chip.
Provided by the MRW.
uint32
ATTR_FABRIC_ADDR_EXTENSION_GROUP_ID
TARGET_TYPE_SYSTEM
Address extension enable value for RA 15:18
uint8
ATTR_FABRIC_ADDR_EXTENSION_CHIP_ID
TARGET_TYPE_SYSTEM
Address extension enable value for RA 19:21
uint8
ATTR_PROC_FABRIC_GROUP_ID
TARGET_TYPE_PROC_CHIP
Logical fabric group ID associated with this chip.
Directly drives programming of pervasive group ID registers (PIR).
Compared with ATTR_PROC_EFF_FABRIC_GROUP_ID to configure FBC XOR masking.
Provided by the MRW.
uint8
ATTR_PROC_EFF_FABRIC_GROUP_ID
TARGET_TYPE_PROC_CHIP
Effective fabric group ID associated with this chip.
Directly drives programming of chip memory map layout.
Compared with ATTR_PROC_FABRIC_GROUP_ID to configure FBC XOR masking.
uint8
ATTR_PROC_FABRIC_CHIP_ID
TARGET_TYPE_PROC_CHIP
Logical fabric chip ID associated with this chip.
Directly drives programming of pervasive chip ID registers (PIR).
Compared with ATTR_PROC_EFF_FABRIC_CHIP_ID to configure FBC XOR masking.
Provided by the MRW.
uint8
ATTR_PROC_EFF_FABRIC_CHIP_ID
TARGET_TYPE_PROC_CHIP
Effective fabric chip ID associated with this chip.
Directly drives programming of chip memory map layout.
Compared with ATTR_PROC_FABRIC_CHIP_ID to configure FBC XOR masking.
uint8
ATTR_PROC_FABRIC_SYSTEM_MASTER_CHIP
TARGET_TYPE_PROC_CHIP
Indicates if the given chip should serve as the fabric system master.
uint8
FALSE = 0x0,
TRUE = 0x1
ATTR_PROC_FABRIC_GROUP_MASTER_CHIP
TARGET_TYPE_PROC_CHIP
Indicates if the given chip should serve as the fabric group master.
uint8
FALSE = 0x0,
TRUE = 0x1
ATTR_PROC_FABRIC_LINK_ACTIVE
TARGET_TYPE_XBUS,TARGET_TYPE_OBUS
Indicates if the endpoint target is actively being used as a fabric link
uint8
FALSE = 0x0,
TRUE = 0x1
ATTR_LINK_TRAIN
TARGET_TYPE_XBUS,TARGET_TYPE_OBUS
Indicates which sublinks should be initialized/trained
uint8
BOTH = 0x0,
EVEN_ONLY = 0x1,
ODD_ONLY = 0x2,
NONE = 0x3
ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG
TARGET_TYPE_PROC_CHIP
For each fabric X link on this chip, specifies whether or not the chip at the
receiving end of the link is present and configured
uint8
7
FALSE = 0x0,
TRUE = 0x1,
EVEN_ONLY = 0x2,
ODD_ONLY = 0x3
ATTR_PROC_FABRIC_X_LINKS_CNFG
TARGET_TYPE_PROC_CHIP
Contains the total number of active X links on this chip
uint8
ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG
TARGET_TYPE_PROC_CHIP
For each fabric A link on this chip, specifies whether or not the chip at the
receiving end of the link is present and configured
uint8
4
FALSE = 0x0,
TRUE = 0x1,
EVEN_ONLY = 0x2,
ODD_ONLY = 0x3
ATTR_PROC_FABRIC_A_LINKS_CNFG
TARGET_TYPE_PROC_CHIP
Contains the total number of active A links on this chip
uint8
ATTR_PROC_FABRIC_X_ATTACHED_CHIP_ID
TARGET_TYPE_PROC_CHIP
For each fabric X link on this chip, specifies the fabric ID of the chip at the
receiving end of the link. Should be considered valid only if corresponding
ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG index is true.
uint8
7
ATTR_PROC_FABRIC_X_ATTACHED_LINK_ID
TARGET_TYPE_PROC_CHIP
For each fabric X link on this chip, specifies the link ID of the chip at the
receiving end of the link. Should be considered valid only if corresponding
ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG index is true.
uint8
7
ATTR_PROC_FABRIC_A_ATTACHED_CHIP_ID
TARGET_TYPE_PROC_CHIP
For each fabric A link on this chip, specifies the fabric ID of the chip at the
receiving end of the link. Should be considered valid only if corresponding
ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG index is true.
uint8
4
ATTR_PROC_FABRIC_A_ATTACHED_LINK_ID
TARGET_TYPE_PROC_CHIP
For each fabric A link on this chip, specifies the link ID of the chip at the
receiving end of the link. Should be considered valid only if corresponding
ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG index is true.
uint8
4
ATTR_PROC_FABRIC_X_AGGREGATE
TARGET_TYPE_PROC_CHIP
Indicates if X links on this chip should be configured in aggregate mode.
uint8
OFF = 0x0,
ON = 0x1
ATTR_PROC_FABRIC_X_ADDR_DIS
TARGET_TYPE_PROC_CHIP
Indicates if link should be used to carry data only (in aggregate configurations).
Should be considered valid only if corresponding ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG
index is true.
uint8
7
OFF = 0x0,
ON = 0x1
ATTR_PROC_FABRIC_X_LINK_DELAY
TARGET_TYPE_PROC_CHIP
Average of local/remote end link delay counter values.
Used to designate coherent link in aggregate configurations.
Should be considered valid only if corresponding ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG
index is true.
uint32
7
OFF = 0x0,
ON = 0x1
ATTR_PROC_FABRIC_A_AGGREGATE
TARGET_TYPE_PROC_CHIP
Indicates if A links on this chip should be configured in aggregate mode.
uint8
OFF = 0x0,
ON = 0x1
ATTR_PROC_FABRIC_A_ADDR_DIS
TARGET_TYPE_PROC_CHIP
Indicates if link should be used to carry data only (in aggregate configurations).
Should be considered valid only if corresponding ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG
index is true.
uint8
4
OFF = 0x0,
ON = 0x1
ATTR_PROC_FABRIC_A_LINK_DELAY
TARGET_TYPE_PROC_CHIP
Average of local/remote end link delay counter values.
Used to designate coherent link in aggregate configurations.
Should be considered valid only if corresponding ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG
index is true.
uint32
4
OFF = 0x0,
ON = 0x1
ATTR_PROC_EPS_GB_PERCENTAGE
TARGET_TYPE_SYSTEM
Guardband percentage to apply to baseline epsilon calculations
Set by p9_fbc_eff_config.
int8
ATTR_PROC_EPS_TABLE_TYPE
TARGET_TYPE_SYSTEM
Processor epsilon table type.
Used to calculate the processor nest epsilon register values.
Provided by the MRW.
uint8
EPS_TYPE_LE = 0x01,
EPS_TYPE_HE = 0x02,
EPS_TYPE_HE_F8 = 0x03
ATTR_PROC_EPS_READ_CYCLES_T0
TARGET_TYPE_SYSTEM
Calculated read tier0 epsilon protection count.
uint32
ATTR_PROC_EPS_READ_CYCLES_T1
TARGET_TYPE_SYSTEM
Calculated read tier1 epsilon protection count.
uint32
ATTR_PROC_EPS_READ_CYCLES_T2
TARGET_TYPE_SYSTEM
Calculated read tier2 epsilon protection count.
uint32
ATTR_PROC_EPS_WRITE_CYCLES_T1
TARGET_TYPE_SYSTEM
Calculated write tier1 epsilon protection count.
uint32
ATTR_PROC_EPS_WRITE_CYCLES_T2
TARGET_TYPE_SYSTEM
Calculated write tier2 epsilon protection count.
uint32
ATTR_DMI_REFCLOCK_SWIZZLE
TARGET_TYPE_DMI
Define DMI Ref clock/Swizzle for Centaur.
Mapper from DMI unit id -> ROOT CNTL 6 refclk drive enable bit
consumer: p9_cen_ref_clk_enable
uint8
ATTR_SYSTEM_IPL_PHASE
TARGET_TYPE_SYSTEM
Define context for current phase of system IPL.
uint8
HB_IPL = 0x1,HB_RUNTIME = 0x2,CACHE_CONTAINED = 0x4,CHIP_CONTAINED = 0x8,NONHB_IPL = 0x10
ATTR_IS_MPIPL
TARGET_TYPE_SYSTEM
Indicates if current IPL is memory-preserving
uint8
FALSE = 0x0,
TRUE = 0x1
ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET
TARGET_TYPE_SYSTEM
XSCOM BAR base address offset
creator: platform
consumer: p9_sbe_scominit
firmware notes:
Defines 16GB range (size implied) mapped for XSCOM usage
Attribute holds offset (relative to chip MMIO origin) to program into
chip address range field of BAR -- RA bits 22:29
(excludes system/memory select/group/chip fields)
uint64
ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET
TARGET_TYPE_SYSTEM
LPC BAR base address offset
creator: platform
consumer: p9_sbe_scominit
firmware notes:
Defines 4GB range (size implied) mapped for LPC usage
Attribute holds offset (relative to chip MMIO origin) to program into
chip address range field of BAR -- RA bits 22:31
(excludes system/memory select/group/chip fields)
uint64
ATTR_MAX_INTERLEAVE_GROUP_SIZE
TARGET_TYPE_SYSTEM
The physical capacity of each msel region is 4_TB without extended addressing.
This attribute defines the maximum addressable space to be used within each msel,
which may be lower than the physical capacity.
uint64
ATTR_MEM_MIRROR_PLACEMENT_POLICY
TARGET_TYPE_SYSTEM
Define placement policy/scheme for non-mirrored/mirrored memory
layout
NORMAL = non-mirrored start: 0, mirrored start: 1024TB
FLIPPED = mirrored start: 0, non-mirrored start: 512TB
Set by platform.
Used by mss_eff_grouping.
uint8
NORMAL = 0x0,
FLIPPED = 0x1
ATTR_PROC_MEM_BASES
TARGET_TYPE_PROC_CHIP
The address where each memory group starts in the non-mirrored
memory groups stack. This address is determined by the memory
grouping process based on the sizes of the memory groups formed
in each processor.
Set by p9_mss_eff_grouping.
uint64
8
ATTR_PROC_MEM_SIZES
TARGET_TYPE_PROC_CHIP
The memory size of each non-mirrored memory group in the
non-mirrored memory groups stack. This size is determined by
the memory grouping process based on the amount of memory
behind the ports that are grouped together.
Set by p9_mss_eff_grouping.
uint64
8
ATTR_PROC_MIRROR_BASES
TARGET_TYPE_PROC_CHIP
The address where each memory group starts in the mirrored
memory groups stack. This address is determined by
the memory grouping process based on the sizes of the memory
groups formed in each processor.
Set by p9_mss_eff_grouping.
uint64
4
ATTR_PROC_MIRROR_SIZES
TARGET_TYPE_PROC_CHIP
The memory size of each memory group in the mirrored memory
groups stack. This size is determined by the memory grouping
process based on the amount of memory behind the ports that are
grouped together.
Set by p9_mss_eff_grouping.
uint64
4
ATTR_MSS_INTERLEAVE_ENABLE
TARGET_TYPE_SYSTEM
Used in the setting of groups. It is a bit vector. If the value
BITWISE_AND 0x01 = 0x01 then groups of 1 are enabled,
if the value BITWISE_AND 0x02 = 0x02, then groups of 2 are possible,
if the value BITWISE_AND 0x04 = 0x04, then group of 3 are possible,
if the value BITWISE_AND 0x08 = 0x08, then groups of 4 are possible,
if the value BITWISE_AND 0x20 = 0x20, then groups of 6 are possible,
if the value BITWISE_AND 0x80 = 0x80, then groups of 8 are possible.
If no groups can formed according to this input, then an error will
be thrown.
Provided by the MRW
uint8
ATTR_MSS_INTERLEAVE_GRANULARITY
TARGET_TYPE_SYSTEM
Determines the stride covered by each granule in an interleaving
group. The default stride -- 128B -- is the only value intended for
production FW use. All other combinations are for experimental
performance evaluation.
Regardless of this attribute value, groups of size 1, 3, and 6
will be forced to 128B stride based on the logic capabilities.
uint8
128_B = 0x00,
256_B = 0x01,
512_B = 0x02,
1_KB = 0x03,
2_KB = 0x04,
4_KB = 0x05,
8_KB = 0x06,
16_KB = 0x07,
32_KB = 0x08
ATTR_MSS_MEM_MC_IN_GROUP
TARGET_TYPE_PROC_CHIP
An 8 bit vector that would be a designation of which MC (Nimbus MCA or
Cumulus MI) are involved in the group.
So the bits would represent
Nimbus Cumulus
Bit 0 MCA0 MI0
Bit 1 MCA1 MI1
.....
Bit 7 MCA7 MI7
Set by p9_mss_eff_grouping
uint8
8
ATTR_MSS_MCS_GROUP_32
TARGET_TYPE_PROC_CHIP
creator:- mss_eff_grouping
consumer:- mss_setup_bars
Data Structure from eff grouping to setup bars to help determine
different groups
Non-Mirroring array[0-7] [0.20]: 0-- Port size; 1-- No of ports in group; 2-- Total group size of non-mirroring;
3-- Base address; 4-11-- PortID number in group;
12-- Alt Memory valid(0); 13-- Alt Memory valid (1);
14-- Alt Group size (0); 15-- Alt Group size(1);
16-- Alt Base address (0); 17-- Alt Base address (1);
18-- SMF Memory Valid
19-- SMF Group Size (size[22:35] in lower bits)
20-- SMF Base Address (addr[22:35] in lower bits)
Mirroring array[8-15] [0:20]: 0-- Port size; 1-- No of ports in group; 2-- Total group size of mirroring;
3-- Base address; 4-11-- PortID number;
12-- Alt Memory valid(0); 13-- Alt Memory valid (1);
14-- Alt Group size (0); 15-- Alt Group size(1);
16-- Alt Base address (0); 17-- Alt Base address (1);
18-- SMF Memory Valid
19-- SMF Group Size (size[22:35] in lower bits)
20-- SMF Base Address (addr[22:35] in lower bits)
Measured in GB
uint32
16,21
ATTR_MSS_MEM_IPL_COMPLETE
TARGET_TYPE_PROC_CHIP
Creator:- mss_setup_bars
A numerical number indicating if the memory procedures are complete.
written by mss_setup_bars when the bars are now functional in the
processor.
uint8
ATTR_MRW_HW_MIRRORING_ENABLE
TARGET_TYPE_SYSTEM
REQUIRED/TRUE: HW mirroring is enabled, and all channels are required
to be part of a mirrored group.
REQUESTED : HW mirroring is enabled. Mirroring will be configured for
groups which support it, but not all channels are required
to be mirrored.
FALSE : HW mirroring is disabled.
Provided by the MRW.
uint8
FALSE = 0, TRUE = 1, REQUESTED = 2
ATTR_PROC_NHTM_BAR_BASE_ADDR
TARGET_TYPE_PROC_CHIP
The base address where the NHTM traces start. They are
calculated based on the NHTM trace size requested by user.
This address in memory will be the location where NHTM0/1
traces are output.
Set by p9_mss_eff_grouping.
Used by p9_setup_bars and p9_htm_setup.
uint64
ATTR_PROC_NHTM_BAR_SIZE
TARGET_TYPE_PROC_CHIP
The amount of memory a user can reserve to store NHTM traces.
This amount will be used to store both NHTM0 and NHTM1 traces.
Used by p9_mss_eff_grouping.
uint64
256_GB = 0x0000004000000000,
128_GB = 0x0000002000000000,
64_GB = 0x0000001000000000,
32_GB = 0x0000000800000000,
16_GB = 0x0000000400000000,
8_GB = 0x0000000200000000,
4_GB = 0x0000000100000000,
2_GB = 0x0000000080000000,
1_GB = 0x0000000040000000,
512_MB = 0x0000000020000000,
256_MB = 0x0000000010000000,
128_MB = 0x0000000008000000,
64_MB = 0x0000000004000000,
32_MB = 0x0000000002000000,
16_MB = 0x0000000001000000,
ZERO = 0x0000000000000000
ATTR_PROC_CHTM_BAR_BASE_ADDR
TARGET_TYPE_PROC_CHIP
The base addresses where the CHTM traces start. They are
calculated based on the CHTM trace sizes requested by users.
There are 24 different CHTM regions, thus 24 different sizes.
Each region is to store HTM trace for a core.
Set by p9_mss_eff_grouping.
Used by p9_setup_bars.
uint64
24
ATTR_PROC_CHTM_BAR_SIZES
TARGET_TYPE_PROC_CHIP
The amount of memory a user can reserve to store CHTM traces.
There are 24 cores, thus 24 different sizes.
Used by p9_mss_eff_grouping.
uint64
256_GB = 0x0000004000000000,
128_GB = 0x0000002000000000,
64_GB = 0x0000001000000000,
32_GB = 0x0000000800000000,
16_GB = 0x0000000400000000,
8_GB = 0x0000000200000000,
4_GB = 0x0000000100000000,
2_GB = 0x0000000080000000,
1_GB = 0x0000000040000000,
512_MB = 0x0000000020000000,
256_MB = 0x0000000010000000,
128_MB = 0x0000000008000000,
64_MB = 0x0000000004000000,
32_MB = 0x0000000002000000,
16_MB = 0x0000000001000000,
ZERO = 0x0000000000000000
24
ATTR_PROC_SMF_BAR_BASE_ADDR
TARGET_TYPE_PROC_CHIP
The base address where the SMF bar starts.It is
calculated based on the SMF size requested by users.
Set by p9_mss_eff_grouping.
uint64
ATTR_PROC_SMF_BAR_SIZE
TARGET_TYPE_PROC_CHIP
The total amount of memory a user has requested to reserve for
secure memory functions. Minimum requirement of 256MB.
Used by p9_mss_eff_grouping.
uint64
256_GB = 0x0000004000000000,
128_GB = 0x0000002000000000,
64_GB = 0x0000001000000000,
32_GB = 0x0000000800000000,
16_GB = 0x0000000400000000,
8_GB = 0x0000000200000000,
4_GB = 0x0000000100000000,
2_GB = 0x0000000080000000,
1_GB = 0x0000000040000000,
512_MB = 0x0000000020000000,
256_MB = 0x0000000010000000,
ZERO = 0x0000000000000000
ATTR_SMF_CONFIG
TARGET_TYPE_SYSTEM
Controls the enabling and disabling of smf.
Used by unit initfiles, p9_mss_eff_grouping.
uint8
DISABLED = 0x00,
ENABLED = 0x01
ATTR_SMF_ENABLED
TARGET_TYPE_SYSTEM
True if smf config is enabled and smf is supported in the
chip ec level. Set by p9_mss_eff_grouping.
uint8
FALSE = 0x00,
TRUE = 0x01
ATTR_PROC_OCC_SANDBOX_BASE_ADDR
TARGET_TYPE_PROC_CHIP
The base address where the OCC sandbox starts. It is
calculated based on the OCC sandbox size requested by users.
Set by p9_mss_eff_grouping.
uint64
ATTR_PROC_OCC_SANDBOX_SIZE
TARGET_TYPE_PROC_CHIP
The amount of memory a user can reserve to store OCC sandbox
functions.
Used by p9_mss_eff_grouping.
uint64
256_GB = 0x0000004000000000,
128_GB = 0x0000002000000000,
64_GB = 0x0000001000000000,
32_GB = 0x0000000800000000,
16_GB = 0x0000000400000000,
8_GB = 0x0000000200000000,
4_GB = 0x0000000100000000,
2_GB = 0x0000000080000000,
1_GB = 0x0000000040000000,
512_MB = 0x0000000020000000,
256_MB = 0x0000000010000000,
128_MB = 0x0000000008000000,
64_MB = 0x0000000004000000,
32_MB = 0x0000000002000000,
16_MB = 0x0000000001000000,
ZERO = 0x0000000000000000
ATTR_PROC_MEM_BASES_ACK
TARGET_TYPE_PROC_CHIP
The actual non-mirrored base addresses of the groups formed
by the memory grouping process. These values correspond to
the BAR programming and would be acknowleged on the fabric.
Set by p9_mss_eff_grouping.
Used by p9_setup_bars.
uint64
8
ATTR_PROC_MEM_SIZES_ACK
TARGET_TYPE_PROC_CHIP
The actual non-mirrored memory sizes of the groups formed
by the memory grouping process. These values correspond to
the BAR programming.
Set by p9_mss_eff_grouping.
Used by p9_setup_bars.
uint64
8
ATTR_PROC_MIRROR_BASES_ACK
TARGET_TYPE_PROC_CHIP
The actual mirrored base addresses of the groups formed
by the memory grouping process. These values correspond to
the BAR programming and would be acknowleged on the fabric.
Set by p9_mss_eff_grouping.
Used by p9_setup_bars.
uint64
4
ATTR_PROC_MIRROR_SIZES_ACK
TARGET_TYPE_PROC_CHIP
The actual mirrored memory sizes of the groups formed
by the memory grouping process. These values correspond to
the BAR programming.
Set by p9_mss_eff_grouping.
Used by p9_setup_bars.
uint64
4
ATTR_HTM_QUEUES
TARGET_TYPE_PROC_CHIP
The number of HTM queues to be reserved for each port in order
to improve HTM trace performance.
This number is calculated in memory grouping process when the
HTM trace spaces are determined.
Set by p9_mss_eff_grouping.
Used by p9_htm_setup.
uint8
8
ATTR_ENABLE_MEM_EARLY_DATA_SCOM
TARGET_TYPE_SYSTEM
Enable early data from Memory. This also enable cp_me from L3.
uint8
OFF = 0x0,
ON = 0x1