ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE TARGET_TYPE_PROC_CHIP Returns true if the core trace arrays are dumpable via SCOM. Nimbus EC 0x20 or greater ENUM_ATTR_NAME_NIMBUS 0x20 GREATER_THAN_OR_EQUAL ATTR_CHIP_EC_FEATURE_TEST1 TARGET_TYPE_PROC_CHIP, TARGET_TYPE_MEMBUF_CHIP Returns if a chip contains the TEST1 feature. True if either: Centaur EC 10 Cumulus EC greater than 30 ENUM_ATTR_NAME_CENTAUR 0x10 EQUAL ENUM_ATTR_NAME_CUMULUS 0x30 GREATER_THAN ATTR_CHIP_EC_FEATURE_TEST2 TARGET_TYPE_PROC_CHIP, TARGET_TYPE_MEMBUF_CHIP Returns if a chip contains the TEST2 feature. True if: Murano EC less than 20 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_VITL_CLK_SETUP TARGET_TYPE_PROC_CHIP Nimbus DD1 for differentiating present/functional targets. True if: Nimbus EC less than 20 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_FSI_GP_SHADOWS_OVERWRITE TARGET_TYPE_PROC_CHIP DD1 attribute for assigning flushvalues to root_ctrl and perv_ctrl registers. True if: Nimbus EC less than 20 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_N3_FLUSH_MODE TARGET_TYPE_PROC_CHIP DD1 update : Flush mode not initiated for N3. True if: Nimbus EC less than 20 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_VITL_CLOCK_GATING TARGET_TYPE_PROC_CHIP DD1 only: disable local clock gating VITAL. This is used by the procedure for p9_sbe_tp_chiplet_init1 and p9_Sbe_chiplet_reset. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_SDISN_SETUP TARGET_TYPE_PROC_CHIP Sdis_n set or clear : flushing LCBES condition woraround. True if: Nimbus EC less than 20 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW396520 TARGET_TYPE_PROC_CHIP DD1 only: enable workarounds for HW396520 (skip flushmode inhibit drop) ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW388878 TARGET_TYPE_PROC_CHIP DD1 only: enable workarounds for HW388878 (VCS) ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW376651 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: enable workarounds for HW376651 Masks ahash parity error checker to avoid FiR when running EX1 only configs ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW389511 TARGET_TYPE_PROC_CHIP DD1 only: enable workarounds for HW389511 (PPM Reg collision) ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW386013 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: enable workarounds for HW386013 in FBC initfile pb_cfg_cent_opt3_mode must be configured as an smp to allow vas data ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW378025 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: enable workarounds for HW378025 in INT initfile Shared credits in ATX can only be updated when clockgate is disabled ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW930007 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: enable workarounds for HW930007 in INT initfile ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW372116 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: enable workarounds for HW372116 in INT initfile Remote Ld credit in PC should be set to zero to avoid ATX dropped commands ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW395947 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: enable workarounds for HW395947 in INT initfile Workaround for relaxed write ordering causing SBT entry corruption ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW397255 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: enable workaround for HW395947 Disable cross-chip MC sync propogation ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_PSI_HALF_SPEED TARGET_TYPE_PROC_CHIP Nimbus DD1 only: enable half speed PSI link operation due to relaxed chip timing closure ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_LPC_RESET_GPIO TARGET_TYPE_PROC_CHIP DD1 only: to do an LPC reset set the GPIO bits ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_MSS_UT_EC_NIMBUS_LESS_THAN_TWO_OH TARGET_TYPE_PROC_CHIP Attribute used only for memory subsystem unit tests. Tells us whether the chip EC we're running on is less than 2.0 and we're on a Nimbus ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_MCBIST_END_OF_RANK TARGET_TYPE_PROC_CHIP MCBIST has a bug where it won't detect the end of a rank properly for a 1R DIMM during super-fast read. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_MSS_WR_VREF TARGET_TYPE_PROC_CHIP In DD1 Nimbus in the WR VREF algorithm, certain work-arounds are needed ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_MSS_DQS_POLARITY TARGET_TYPE_PROC_CHIP For Monza DDR port 2, one pair of DQS P/N is swapped polarity. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_MSS_VREF_DAC TARGET_TYPE_PROC_CHIP VREF DAC work-around for Nimbus DD1.0 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_MSS_WAT_DEBUG_ATTN TARGET_TYPE_PROC_CHIP WAT Debug Attention work-around for Nimbus DD1.0 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE TARGET_TYPE_PROC_CHIP Data integrity issue requires us to disable clockgate in read array for Nimbus DD1.0 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_MSS_TRAINING_BAD_BITS TARGET_TYPE_PROC_CHIP For Nimbus pre DD1.02 we want to pass DDR training if we see 'correctable' errors. This isn't the case for post-DD1.02 where we want to pass/fail training based on the results from the PHY itself ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN