ATTR_CHIP_EC_FEATURE_P9N_DD1_SPY_NAMES TARGET_TYPE_PROC_CHIP Returns true if spy name has changed from dd1 to dd2. Less than Nimbus ec 0x20 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_P9N_DD2_SPY_NAMES TARGET_TYPE_PROC_CHIP Returns true if spy name has changed from dd1 to dd2. Greater than or equal to 0x20 ENUM_ATTR_NAME_NIMBUS 0x20 GREATER_THAN_OR_EQUAL ATTR_CHIP_EC_FEATURE_P9_NDL_IOVALID TARGET_TYPE_PROC_CHIP Returns true if the chip has NDL IOValid bits P9N dd2 ENUM_ATTR_NAME_NIMBUS 0x20 GREATER_THAN_OR_EQUAL ATTR_CHIP_EC_FEATURE_EARLYMODE_FIX TARGET_TYPE_PROC_CHIP Returns true if MPW2 bits should be set ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE TARGET_TYPE_PROC_CHIP Returns true if the core trace arrays are dumpable via SCOM. Nimbus EC 0x20 or greater ENUM_ATTR_NAME_NIMBUS 0x20 GREATER_THAN_OR_EQUAL ATTR_CHIP_EC_FEATURE_TEST1 TARGET_TYPE_PROC_CHIP, TARGET_TYPE_MEMBUF_CHIP Returns if a chip contains the TEST1 feature. True if either: Centaur EC 10 Cumulus EC greater than 30 ENUM_ATTR_NAME_CENTAUR 0x10 EQUAL ENUM_ATTR_NAME_CUMULUS 0x30 GREATER_THAN ATTR_CHIP_EC_FEATURE_TEST2 TARGET_TYPE_PROC_CHIP, TARGET_TYPE_MEMBUF_CHIP Returns if a chip contains the TEST2 feature. True if: Murano EC less than 20 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_FSI_GP_SHADOWS_OVERWRITE TARGET_TYPE_PROC_CHIP DD1 attribute for assigning flushvalues to root_ctrl and perv_ctrl registers. True if: Nimbus EC less than 20 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_N3_FLUSH_MODE TARGET_TYPE_PROC_CHIP DD1 update : Flush mode not initiated for N3. True if: Nimbus EC less than 20 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_VITL_CLOCK_GATING TARGET_TYPE_PROC_CHIP DD1 only: disable local clock gating VITAL. This is used by the procedure for p9_sbe_tp_chiplet_init1 and p9_Sbe_chiplet_reset. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_SDISN_SETUP TARGET_TYPE_PROC_CHIP Sdis_n set or clear : flushing LCBES condition woraround. True if: Nimbus EC less than 20 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_THREAD_REBALANCING TARGET_TYPE_PROC_CHIP Nimbus DD1 only: Thread rebalancing to lower SMT level not supported. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW407180 TARGET_TYPE_PROC_CHIP Filter pll setting differences. Cumulus matches nimbus dd2. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW365079 TARGET_TYPE_PROC_CHIP DD1 only config, issue: HW365079 Planning on enabling it with an irritator. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW367017 TARGET_TYPE_PROC_CHIP HW367017 P9N DD1 Collision with scrubber correcting a CE and a castout operation, resulting in cache corruption Scrubbing off for DD2 as well, HW405443 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN_OR_EQUAL ATTR_CHIP_EC_FEATURE_HW393692 TARGET_TYPE_PROC_CHIP HW393692 - need to turn off NCU hardware checker (fir bit 2) for illegal tlbies/slbie formats for DD1. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW372146 TARGET_TYPE_PROC_CHIP HW372146 For turning off clock gating on nctlbsm ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW405413 TARGET_TYPE_PROC_CHIP HW405413 : NCU sends data out of order ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW367321 TARGET_TYPE_PROC_CHIP HW367321 clock gating bug on err_rpt ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW254454 TARGET_TYPE_PROC_CHIP HW254454: In P9 DD1, DRAM_ABIST_DONE_DC is unused; SRAM_ABIST_DONE_DC is shared by sram and edram ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW376110 TARGET_TYPE_PROC_CHIP HW376110 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW375534 TARGET_TYPE_PROC_CHIP Max 24 64-byte read buffers (HW375534) ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW366164 TARGET_TYPE_PROC_CHIP HW366164 - SRQ Fullness Control ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW366248 TARGET_TYPE_PROC_CHIP FOR P9N DD1 Prefetch Limit needs to be scan init to 0 because SCOM is broken (HW366248) Always OR-ed with previous value. Essentially we can only set bits, not clear. So we want to scan init to 0. these are n1 n3 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW395756 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW395756 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW396288 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW396288 - Dispatch Serialize all mtmsrd ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW394497 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW394497 - Turn all mtfpscr/mffspcr ops Dispatch Serialize to enable speculative FPSCR. (HW374002) ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW394447_HW394186 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW394447 / HW394186 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW393129 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW393129 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW393318 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW393318 - Turn all decimal quad ops Dispatch Serialize. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW393547 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW393547 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW393929_HW394578 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW393929 / HW394578 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW362088 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW362088 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW391334_HW391367 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW391334 / HW391367 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW387890 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW387890 NOTE: should be turned back off if LSU gets stuck in a cyclical ntc_plz loop. This switch was added in RITB as part of a large, multiple-fix solution for the cycling ntc_plz with DEFAULT=OFF. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW384613 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW384613 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW373955 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW373955 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW381889 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW381889 - Disable TM ROT mode ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW379315 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW379315 - Fix tiered hangbuster triggering ntc_plz ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW347876 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW347876 - default not correct ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_DISABLE_PAGE_WALK_CACHE_HITS TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW373955 - In Radix Mode: Page Walk Cache unsupported HW361596 / HW371500 / HW373955 - In SDR1 mode and UPRT=1 mode: Disable Page Walk Cache hits ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_RFC02491 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: DD1 Defer -ldmx not supported (i.e. Garbage Collection RFC02491) ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW359913_HW356752 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW359913 / HW356752 ltptr not supported - will be treated as an illegal instruction ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW364229 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW364229 - enb_reduce_spec mode, causes a tlbie hang ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW330187 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW330187 - Instruction Fusion not supported ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW371453 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW371453 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW379562 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW379562 - Turn off store-forward to LQ ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW376310 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW376310 - Disable forcing TM loads to miss the DDIR1 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW371047 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW371047 - TMDIR disabled due to multi-threaded issue. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW373589 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW373589 - Reject 2nd of lqarx pair ops if they are on back-to-back cycles. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW373167 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW373167 - Problems with arbitrating between NTC and NTC+1 flush requests when one is recoverable and the other involves trechkpt. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW372808 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW372808 - TM hwsync does not wait on load ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW372208 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW372208 - larx missed bad dval ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW373137 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW373137 - Stop prefetch and invalidate erat collison causing erat multihits ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW371867 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW371867 - Performance enhancement that is too buggy to leave enabled ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW368478 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW368478 - S2Q clock gate has to be disabled ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW360131 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW360131 - POR value is an invalid combination and is not represented in the dial. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW370085 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW370085 - IFU can send an erroneous 2nd "force miss" to the LSU on a shared translation, causing an unnecessary table walk. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW369677 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW369677 - Dynamic set delete not implemented ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW367863 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW367863 - Workaround when EAT thinks it's empty and IDU still reports that it's out of itags. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW365384 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW365384 - data prefetch clock gate needed ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW365576 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW365576 - Need to disable reset of LRQ deallocate bit ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW365510 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW365510 - TM merging in the LRQ not supported - disable with chicken switch ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_DISABLE_SPEC_STWCX TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW353069 / HW358383 / HW358418 / HW358662 / HW358824 / HW363605 Not doing Performance: MB State - Need to disable speculative stwcx ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW363926 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW363926 - Workaround for clockgating bug for Local Very Good Mode (performance) ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW339090_HW354135 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW339090 / HW354135 - Branch flush performance ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW361821 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW361821 - Icache way prediction must be disabled for all SMT modes except SMT1 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW380199 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW380199 - L2 store reordering induced consistency bug Only set at safest risk level ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW396388 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW396388 - Disable recovery by default ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW399524 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW399524 disable functionality, can only be enabled on non-FP/VMX tests ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW375255 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW375255; Defer to DD2: Rd mach goes inactive without sending PF data bypass to L2 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_SRAM_RELAXED_SETTINGS TARGET_TYPE_PROC_CHIP Nimbus DD1 only: adjust/relax SRAM timing parameters ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW369979 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW369979; Defer to DD2: [GRUB multi chiplet] l3_fir_reg_l3_hw_control_err L3 FIR bit 24 (mask control_err(2) by setting dial: err_rpt0_mask(2) to ON) ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW378093 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW378093; Defer to DD2: edram_info_capture_cfg defaults to wrong value ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW288205_HW392168 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW288205 (P8 CQ) : L3 PF Hang fix. Change behavior of L3 Prefetch Back-off mechanism HW392168 (P9 CQ) : This bug existed in P8 and was set to 0x4. The bug was not fixed ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW406803 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: HW406803 : bug with calculating home region for LCO's using wrong bit44 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW392009 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: Enable work around for HW392009 Auto Special Wakeup Disables [LMCR(12:13)]. Do not scan flush to 1s. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW377094 TARGET_TYPE_PROC_CHIP DD1 only: HW377094 L2 stq and ncu stq deadlock. g/ord_g causes artificial dependency between barrier and snptlbcmp in NCU while lfsr bits being reused in L2 stq causes entry to never be selected due to high priority ld-hit-st override. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW398015 TARGET_TYPE_PROC_CHIP DD1 only: HW398015 work around ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW396393 TARGET_TYPE_PROC_CHIP DD1 only: HW396393 rare TM fail condition. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW374111 TARGET_TYPE_PROC_CHIP DD1 only: HW374111 snapshot doesn't work for domestic copy that hits the L2 cache. all 16 RC machines need to turn off clock gating ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW373819 TARGET_TYPE_PROC_CHIP DD1 only: HW373819 PEC SBCE could cause coherency problems when running in conjunction with copy/paste ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW371141_HW371628 TARGET_TYPE_PROC_CHIP DD1 only: HW371141 lvext causes unforseen cgc lockouts, bad for performance HW371628 coherency hole in LVEXT also found must turn off LVEXT. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW370687 TARGET_TYPE_PROC_CHIP DD1 only: HW370687 xlate_addr_to_id clock gating bug ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW370692 TARGET_TYPE_PROC_CHIP DD1 only: HW370692 deadlock allowing snptlbcmp to pass around stcxf ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW394803 TARGET_TYPE_PROC_CHIP DD1 only: HW394803 - Fatal Venus: Critical section fail ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW370984 TARGET_TYPE_PROC_CHIP DD1 only: HW370984 - No wakeup from hypdbell to core 1 stopped in level 2 ESL=0 (SMT1 test) ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW376874 TARGET_TYPE_PROC_CHIP DD1 only: HW376874 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW319315 TARGET_TYPE_PROC_CHIP DD1 only: mask TFAC parity errors (HW319315) ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW385178 TARGET_TYPE_PROC_CHIP DD1 only: enable workarounds for HW385178 - Force SMT4 mode for Stop 1 and 2 SPR loss ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW393734 TARGET_TYPE_PROC_CHIP DD1 only: enable workarounds for HW393734 - Stop2 hang workaround ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW396520 TARGET_TYPE_PROC_CHIP DD1 only: enable workarounds for HW396520 (skip flushmode inhibit drop) ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW388878 TARGET_TYPE_PROC_CHIP DD1 only: enable workarounds for HW388878 (VCS) ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW376651 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: enable workarounds for HW376651 Masks ahash parity error checker to avoid FiR when running EX1 only configs ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW389511 TARGET_TYPE_PROC_CHIP DD1 only: enable workarounds for HW389511 (PPM Reg collision) ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW386013 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: enable workarounds for HW386013 in FBC initfile pb_cfg_cent_opt3_mode must be configured as an smp to allow vas data ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW407123 TARGET_TYPE_PROC_CHIP Nimbus DD1,DD2: enable workarounds for HW407123 in FBC initfile Slow down xlink cmd rate to work around broken single link credit dial that would have prevented rcmd overflows ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN_OR_EQUAL ATTR_CHIP_EC_FEATURE_HW378025 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: enable workarounds for HW378025 in INT initfile Shared credits in ATX can only be updated when clockgate is disabled ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW930007 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: enable workarounds for HW930007 in INT initfile ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW372116 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: enable workarounds for HW372116 in INT initfile Remote Ld credit in PC should be set to zero to avoid ATX dropped commands ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW395947 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: enable workarounds for HW395947 in INT initfile Workaround for relaxed write ordering causing SBT entry corruption ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW408972 TARGET_TYPE_PROC_CHIP Nimbus DD1,DD2: enable workarounds for HW408972 in INT initfile Workaround for missing escalation bug with group interrupts ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN_OR_EQUAL ATTR_CHIP_EC_FEATURE_HW397255 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: enable workaround for HW395947 Disable cross-chip MC sync propogation ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_PSI_HALF_SPEED TARGET_TYPE_PROC_CHIP Nimbus DD1 only: enable half speed PSI link operation due to relaxed chip timing closure ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_LPC_RESET_GPIO TARGET_TYPE_PROC_CHIP DD1 only: to do an LPC reset set the GPIO bits ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_PCIE_LOCK_PHASE_ROTATOR TARGET_TYPE_PROC_CHIP DD1.00 only: lock phase rotator ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_PCIE_DISABLE_FDDC TARGET_TYPE_PROC_CHIP DD1.01/DD1.02 only: disable DDC ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_SLOW_PCI_REF_CLOCK_ENABLE TARGET_TYPE_PROC_CHIP DD1 only: enable use of SS PLL to provide reduced frequency reference clock (94 MHz, instead of nominal 100 MHz) for PCI PLL ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW396230_SCAN_ONLY TARGET_TYPE_PROC_CHIP Nimbus DD1 only: set L3/NCU skip group scope via scan only ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW396230_SCOM TARGET_TYPE_PROC_CHIP Nimbus DD2+: able to set L3/NCU skip group scope via SCOM ENUM_ATTR_NAME_NIMBUS 0x20 GREATER_THAN_OR_EQUAL ENUM_ATTR_NAME_CUMULUS 0x10 GREATER_THAN_OR_EQUAL ATTR_CHIP_EC_FEATURE_OPTIMAL_LCO_SCAN_ONLY TARGET_TYPE_PROC_CHIP Nimbus DD1 only: set the optimal dial setups for LCO's ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_OPTIMAL_LCO_SCOM TARGET_TYPE_PROC_CHIP Nimbus DD2+: set the optimal dial setups for LCO's ENUM_ATTR_NAME_NIMBUS 0x20 GREATER_THAN_OR_EQUAL ENUM_ATTR_NAME_CUMULUS 0x10 GREATER_THAN_OR_EQUAL ATTR_CHIP_EC_FEATURE_OPTIMAL_LARX_STCX_PERF TARGET_TYPE_PROC_CHIP Nimbus DD2+: set the optimal dial setups for larx/stcx ENUM_ATTR_NAME_NIMBUS 0x20 GREATER_THAN_OR_EQUAL ENUM_ATTR_NAME_CUMULUS 0x10 GREATER_THAN_OR_EQUAL ATTR_CHIP_EC_FEATURE_HW383616 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: enable workaround for HW383616 Restrict GP/SP high water mark ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW384245 TARGET_TYPE_PROC_CHIP Nimbus DD1 only: enable workaround for HW384245 Restrict TL DOB limit ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW401184 TARGET_TYPE_PROC_CHIP Nimbus DD1: Silent Baron: TB and DEC SPRs stray apart with TOD enabled ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW401249 TARGET_TYPE_PROC_CHIP Nimbus DD1: mask EC local error from CC ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW397147 TARGET_TYPE_PROC_CHIP Nimbus DD1: Tired Grandpa -- CHKSW_DONT_PRIORITIZE_BRQ_MF ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW399388 TARGET_TYPE_PROC_CHIP Nimbus DD1: Intense Skunk -- CS_LOW_POWER_PRIORITY_MODE_DIS ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW399609 TARGET_TYPE_PROC_CHIP Nimbus DD1: Rich Starlight -- increase core hang limit to engage L2 random block gather LFSR ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW387254 TARGET_TYPE_PROC_CHIP Nimbus DD1: IMA interval timer overcounts based on missing edge detect ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW399919 TARGET_TYPE_PROC_CHIP Nimbus DD1: Major Queen ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW401811 TARGET_TYPE_PROC_CHIP Nimbus DD1: Silly Plutonium ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW400898 TARGET_TYPE_PROC_CHIP Nimbus DD1: Hungry Shark ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW398269 TARGET_TYPE_PROC_CHIP Nimbus DD1: Reckless Carpenter ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW399765 TARGET_TYPE_PROC_CHIP Nimbus DD1: NCU AMO load ordering error ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW363780> TARGET_TYPE_PROC_CHIP Nimbus DD1: NPU incorrectly asserts FIR for any rcmd snoops that misses its table lookup, includes commands that it does not master ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW403465> TARGET_TYPE_PROC_CHIP Nimbus DD1: L1 access latency increases when data footprint should still be within L1 cache size. Revert L1 LRU changes ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW402145> TARGET_TYPE_PROC_CHIP Nimbus DD1: Husky Dinosaur ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW393578> TARGET_TYPE_PROC_CHIP Nimbus DD1: Red Snow ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW403075> TARGET_TYPE_PROC_CHIP Nimbus DD1: Icy Sapphire ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW399624> TARGET_TYPE_PROC_CHIP Nimbus DD1: Needy Kitten ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW405851> TARGET_TYPE_PROC_CHIP Nimbus DD1: Distant Supernova ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW395939 TARGET_TYPE_PROC_CHIP For DD1, VAS has no BAR disable bit. Adding attribute to enable non zero init for the MMIO BARs. Issue HW395939 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW403585> TARGET_TYPE_PROC_CHIP Nimbus DD1: Treacherous Dolphin ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW402019_PIBRESET_DELAY TARGET_TYPE_PROC_CHIP Nimbus DD1 only: Adding delay to wait for pibreset to complete ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_NDD1_ABIST_PARALLEL TARGET_TYPE_PROC_CHIP Nimbus DD1: set ABIST engines to PARALLEL mode. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_SETUP_BARS_NPU_DD1_ADDR TARGET_TYPE_PROC_CHIP DD1 only: Use the DD1 register addresses for the PHY0 BAR registers, PHY1 BAR registers, and MMIO BAR registers ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW397129> TARGET_TYPE_PROC_CHIP Attribute for if we need a workaround for re-enabling the MC fastpath since on Nimbus DD1 is gets disabled. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_MSS_UT_EC_NIMBUS_LESS_THAN_TWO_OH TARGET_TYPE_PROC_CHIP Attribute used only for memory subsystem unit tests. Tells us whether the chip EC we're running on is less than 2.0 and we're on a Nimbus ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_MCBIST_END_OF_RANK TARGET_TYPE_PROC_CHIP MCBIST has a bug where it won't detect the end of a rank properly for a 1R DIMM during super-fast read. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_MSS_WR_VREF TARGET_TYPE_PROC_CHIP In DD1 Nimbus in the WR VREF algorithm, certain work-arounds are needed ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_MSS_DQS_POLARITY TARGET_TYPE_PROC_CHIP For Monza DDR port 2, one pair of DQS P/N is swapped polarity. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_MSS_VREF_DAC TARGET_TYPE_PROC_CHIP VREF DAC work-around for Nimbus DD1.0 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_MSS_WAT_DEBUG_ATTN TARGET_TYPE_PROC_CHIP WAT Debug Attention work-around for Nimbus DD1.0 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE TARGET_TYPE_PROC_CHIP Data integrity issue requires us to disable clockgate in read array for Nimbus DD1.0 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW400075 TARGET_TYPE_PROC_CHIP Addresses issue where MDI bit was getting wrong values with threadmill and transactional data resulting in coherency issues. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW398139 TARGET_TYPE_PROC_CHIP Avoid powerbus early hangs by enabling prefetch drops to break out of fairness issue with prefetch ops ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_MSS_TRAINING_BAD_BITS TARGET_TYPE_PROC_CHIP For Nimbus pre DD1.02 we want to pass DDR training if we see 'correctable' errors. This isn't the case for post-DD1.02 where we want to pass/fail training based on the results from the PHY itself ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW400932 TARGET_TYPE_PROC_CHIP ATAG info corruption on presp issue requires us to disable clockgate for Nimbus DD1.0 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW401780 TARGET_TYPE_PROC_CHIP Need AMO caching disabled for multiple defects until Nimbus DD2.0 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW406577 TARGET_TYPE_PROC_CHIP Noise window disabled in DD1 because continually reocurring intermittent UE's can cause us to hang on refreshes. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_MSS_CHECK_DISABLE_HW_VREF_CAL TARGET_TYPE_PROC_CHIP In below DD2 Nimbus, the HW VREF calibration needs to be checked against the chip subversion to see if it can be run. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_MSS_RUN_RD_CTR_WOKRAROUND TARGET_TYPE_PROC_CHIP In below DD2 Nimbus, a workaround after read centering might need to be run. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_MSS_ODT_CONFIG TARGET_TYPE_PROC_CHIP For Nimbus pre DD2.** we need to swap ODT2 and ODT3 values in the DDRPHY_SEQ_ODT_RD/WR_CONFIG registers due to a PHY erratum. Post DD2.** will have a hardware enabled fix for this (HW389360). ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_MSS_BLUE_WATERFALL_ADJUST TARGET_TYPE_PROC_CHIP In DD1.** Nimbus, the blue waterfall can calibrate to an incorrect value. In DD2 Nimbus, This isn't the case as the HW will not allow this calibration value ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_MSS_CHECK_DIABLE_RD_VREF_CAL_VREFSENSE TARGET_TYPE_PROC_CHIP In below DD2 Nimbus, the RD VREF cal VREF sense needs to be checked against the chip subversion to see if it should be run. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_RNG_ADAPTEST_SETTINGS TARGET_TYPE_PROC_CHIP The Random number generator has different settings in dd1 and dd2 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW403701 TARGET_TYPE_PROC_CHIP Nimbus DD1: Reduce rng pace from 2000->300 to work around grant unfairness ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW406130 TARGET_TYPE_PROC_CHIP Nimbus DD1: Reduce number of active DMA read requests down from 16->8 to work around erat access count bug ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW389045 TARGET_TYPE_PROC_CHIP Nimbus DD1: Update the TSEL shadow copy by scanning as it't not connected to the SCOM reg. ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_RING_SAVE_MPIPL TARGET_TYPE_PROC_CHIP For Nimbus DD2 we no longer need a workaround for Ring Save in MPIPL ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_HW404176_ASSERT_SCAN_CLK TARGET_TYPE_PROC_CHIP Only MC in Cumulus need to generate scan clock in even cycle instead of odd ENUM_ATTR_NAME_CUMULUS 0x10 GREATER_THAN_OR_EQUAL ATTR_CHIP_EC_FEATURE_HW406337 TARGET_TYPE_PROC_CHIP Cumulus only dropping MC chiplet fence during arrayinit ENUM_ATTR_NAME_CUMULUS 0x10 GREATER_THAN_OR_EQUAL ATTR_CHIP_EC_FEATURE_DD1_ANALOG TARGET_TYPE_PROC_CHIP DD1 update : Scan init VDM and IVRM latch workarounds. True if: Nimbus EC less than 20 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_DD1_DPLL_SETTINGS TARGET_TYPE_PROC_CHIP DD1 update : Scan init DPL Jump Values (SCOMMABLE in DD2). True if: Nimbus EC less than 20 ENUM_ATTR_NAME_NIMBUS 0x20 LESS_THAN ATTR_CHIP_EC_FEATURE_POSTDD1N_DPLL_SETTINGS TARGET_TYPE_PROC_CHIP Post DD1 update : Used for new DD2 settings such as ..._EXTERNAL_JUMP_VALUES latch is new for DD2. True if: Nimbus EC greater than or equal to 20 ENUM_ATTR_NAME_NIMBUS 0x20 GREATER_THAN_OR_EQUAL