/* IBM_PROLOG_BEGIN_TAG                                                   */
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/* $Source: src/import/chips/p9/procedures/hwp/core/p9_hcd_core_arrayinit.C $ */
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/* OpenPOWER sbe Project                                                  */
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/* IBM_PROLOG_END_TAG                                                     */
///
/// @file  p9_hcd_core_arrayinit.C
/// @brief Core Initialize arrays
///
/// Procedure Summary:
///   Use ABIST engine to zero out all arrays
///   Upon completion, scan0 flush all rings except Vital,Repair,GPTR,and TIME

// *HWP HWP Owner          : David Du      <daviddu@us.ibm.com>
// *HWP Backup HWP Owner   : Greg Still    <stillgs@us.ibm.com>
// *HWP FW Owner           : Sangeetha T S <sangeet2@in.ibm.com>
// *HWP Team               : PM
// *HWP Consumed by        : SBE:CME
// *HWP Level              : 2

//------------------------------------------------------------------------------
// Includes
//------------------------------------------------------------------------------

#include <p9_quad_scom_addresses.H>
#include <p9_perv_sbe_cmn.H>
#include <p9_hcd_common.H>
#include "p9_hcd_core_arrayinit.H"

//------------------------------------------------------------------------------
// Constant Definitions
//------------------------------------------------------------------------------

enum P9_HCD_CORE_ARRAYINIT_Private_Constants
{
    REGIONS_EXCEPT_VITAL = 0x7FF,
    LOOP_COUNTER = 0x0000000000042FFF,
    SELECT_SRAM = 0x1,
    SELECT_EDRAM = 0x0,
    START_ABIST_MATCH_VALUE = 0x0000000F00000000
};

//------------------------------------------------------------------------------
// Procedure: Core Initialize arrays
//------------------------------------------------------------------------------

fapi2::ReturnCode
p9_hcd_core_arrayinit(
    const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
{
    FAPI_INF(">>p9_hcd_core_arrayinit");
    fapi2::buffer<uint64_t>                     l_data64;

#if not defined(P9_HCD_STOP_SKIP_FLUSH) || not defined(P9_HCD_STOP_SKIP_ARRAYINIT)
    fapi2::Target<fapi2::TARGET_TYPE_PERV> l_perv =
        i_target.getParent<fapi2::TARGET_TYPE_PERV>();
#endif

    FAPI_DBG("Assert sdis_n(flushing LCBES condition) via CPLT_CONF0[34]");
    FAPI_TRY(putScom(i_target, C_CPLT_CONF0_OR, MASK_SET(34)));

#ifndef P9_HCD_STOP_SKIP_ARRAYINIT

    FAPI_DBG("Arrayinit all regions except vital");
    FAPI_TRY(p9_perv_sbe_cmn_array_init_module(l_perv,
             REGIONS_EXCEPT_VITAL,
             LOOP_COUNTER,
             SELECT_SRAM,
             SELECT_EDRAM,
             START_ABIST_MATCH_VALUE));

#endif

#ifndef P9_HCD_STOP_SKIP_FLUSH

    //--------------------------------------------
    // perform scan0 module for pervasive chiplet
    //--------------------------------------------
    // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the longest
    // ring is defined by P9_HCD_SCAN_FUNC_REPEAT. When the design ALWAYS has
    // all stumps less than 8191, the loop can be removed.

    FAPI_DBG("Scan0 region:all_but_pll type:all_but_gptr_repr_time rings");

    for(uint32_t l_loop = 0; l_loop < P9_HCD_SCAN_FUNC_REPEAT; l_loop++)
        FAPI_TRY(p9_perv_sbe_cmn_scan0_module(l_perv,
                                              p9hcd::SCAN0_REGION_ALL_BUT_PLL,
                                              p9hcd::SCAN0_TYPE_ALL_BUT_GPTR_REPR_TIME));

#endif

    FAPI_DBG("Drop sdis_n(flushing LCBES condition) via CPLT_CONF0[34]");
    FAPI_TRY(putScom(i_target, C_CPLT_CONF0_CLEAR, MASK_SET(34)));

//#if not defined(P9_HCD_STOP_SKIP_FLUSH) || not defined(P9_HCD_STOP_SKIP_ARRAYINIT)
fapi_try_exit:
//#endif

    FAPI_INF("<<p9_hcd_core_arrayinit");
    return fapi2::current_err;
}