/* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ /* $Source: src/import/chips/p9/common/include/p9_quad_scom_addresses_fld.H $ */ /* */ /* OpenPOWER sbe Project */ /* */ /* Contributors Listed Below - COPYRIGHT 2015,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ /* You may obtain a copy of the License at */ /* */ /* http://www.apache.org/licenses/LICENSE-2.0 */ /* */ /* Unless required by applicable law or agreed to in writing, software */ /* distributed under the License is distributed on an "AS IS" BASIS, */ /* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ /* implied. See the License for the specific language governing */ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ /// /// @file p9_quad_scom_addresses_fld.H /// @brief Defines constants for scom addresses /// // *HWP HWP Owner: Ben Gass // *HWP FW Owner: Thi Tran // *HWP Team: SOA // *HWP Level: 1 // *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE #include #ifndef __P9_QUAD_SCOM_ADDRESSES_FLD_H #define __P9_QUAD_SCOM_ADDRESSES_FLD_H #include #include REG64_FLD( EQ_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR ); REG64_FLD( EQ_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN ); REG64_FLD( EQ_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR ); REG64_FLD( EQ_ADDR_TRAP_REG_RESERVED_LAST_LT , 17 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RESERVED_LAST_LT ); REG64_FLD( EQ_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR ); REG64_FLD( EQ_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN ); REG64_FLD( EQ_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY ); REG64_FLD( EQ_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR ); REG64_FLD( EQ_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION ); REG64_FLD( EQ_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER ); REG64_FLD( EX_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR ); REG64_FLD( EX_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN ); REG64_FLD( EX_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR ); REG64_FLD( EX_ADDR_TRAP_REG_RESERVED_LAST_LT , 17 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESERVED_LAST_LT ); REG64_FLD( EX_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR ); REG64_FLD( EX_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN ); REG64_FLD( EX_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY ); REG64_FLD( EX_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR ); REG64_FLD( EX_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION ); REG64_FLD( EX_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER ); REG64_FLD( C_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR ); REG64_FLD( C_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN ); REG64_FLD( C_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR ); REG64_FLD( C_ADDR_TRAP_REG_RESERVED_LAST_LT , 17 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESERVED_LAST_LT ); REG64_FLD( C_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR ); REG64_FLD( C_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN ); REG64_FLD( C_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY ); REG64_FLD( C_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR ); REG64_FLD( C_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION ); REG64_FLD( C_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER ); REG64_FLD( EQ_ASSIST_INTERRUPT_REG_ATTN , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ATTN ); REG64_FLD( EQ_ASSIST_INTERRUPT_REG_RECOV , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RECOV ); REG64_FLD( EQ_ASSIST_INTERRUPT_REG_XSTOP , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSTOP ); REG64_FLD( EX_ASSIST_INTERRUPT_REG_ATTN , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ATTN ); REG64_FLD( EX_ASSIST_INTERRUPT_REG_RECOV , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RECOV ); REG64_FLD( EX_ASSIST_INTERRUPT_REG_XSTOP , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSTOP ); REG64_FLD( C_ASSIST_INTERRUPT_REG_ATTN , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ATTN ); REG64_FLD( C_ASSIST_INTERRUPT_REG_RECOV , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RECOV ); REG64_FLD( C_ASSIST_INTERRUPT_REG_XSTOP , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_XSTOP ); REG64_FLD( EQ_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASK ); REG64_FLD( EQ_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASK_LEN ); REG64_FLD( EX_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASK ); REG64_FLD( EX_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASK_LEN ); REG64_FLD( C_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MASK ); REG64_FLD( C_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MASK_LEN ); REG64_FLD( EQ_ATOMIC_LOCK_REG_ENABLE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( EQ_ATOMIC_LOCK_REG_ID , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ID ); REG64_FLD( EQ_ATOMIC_LOCK_REG_ID_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ID_LEN ); REG64_FLD( EQ_ATOMIC_LOCK_REG_ACTIVITY , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACTIVITY ); REG64_FLD( EQ_ATOMIC_LOCK_REG_ACTIVITY_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACTIVITY_LEN ); REG64_FLD( EX_ATOMIC_LOCK_REG_ENABLE , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( EX_ATOMIC_LOCK_REG_ID , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ID ); REG64_FLD( EX_ATOMIC_LOCK_REG_ID_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ID_LEN ); REG64_FLD( EX_ATOMIC_LOCK_REG_ACTIVITY , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACTIVITY ); REG64_FLD( EX_ATOMIC_LOCK_REG_ACTIVITY_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACTIVITY_LEN ); REG64_FLD( C_ATOMIC_LOCK_REG_ENABLE , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( C_ATOMIC_LOCK_REG_ID , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ID ); REG64_FLD( C_ATOMIC_LOCK_REG_ID_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ID_LEN ); REG64_FLD( C_ATOMIC_LOCK_REG_ACTIVITY , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACTIVITY ); REG64_FLD( C_ATOMIC_LOCK_REG_ACTIVITY_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACTIVITY_LEN ); REG64_FLD( EQ_ATTN_INTERRUPT_REG_ATTN , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ATTN ); REG64_FLD( EX_ATTN_INTERRUPT_REG_ATTN , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ATTN ); REG64_FLD( C_ATTN_INTERRUPT_REG_ATTN , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ATTN ); REG64_FLD( EQ_BIST_TC_START_TEST_DC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TC_START_TEST_DC ); REG64_FLD( EQ_BIST_TC_SRAM_ABIST_MODE_DC , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TC_SRAM_ABIST_MODE_DC ); REG64_FLD( EQ_BIST_TC_EDRAM_ABIST_MODE_DC , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TC_EDRAM_ABIST_MODE_DC ); REG64_FLD( EQ_BIST_TC_IOBIST_MODE_DC , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TC_IOBIST_MODE_DC ); REG64_FLD( EQ_BIST_PERV , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PERV ); REG64_FLD( EQ_BIST_UNIT1 , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT1 ); REG64_FLD( EQ_BIST_UNIT2 , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT2 ); REG64_FLD( EQ_BIST_UNIT3 , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT3 ); REG64_FLD( EQ_BIST_UNIT4 , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT4 ); REG64_FLD( EQ_BIST_UNIT5 , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT5 ); REG64_FLD( EQ_BIST_UNIT6 , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT6 ); REG64_FLD( EQ_BIST_UNIT7 , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT7 ); REG64_FLD( EQ_BIST_UNIT8 , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT8 ); REG64_FLD( EQ_BIST_UNIT9 , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT9 ); REG64_FLD( EQ_BIST_UNIT10 , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT10 ); REG64_FLD( EQ_BIST_STROBE_WINDOW_EN , 48 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STROBE_WINDOW_EN ); REG64_FLD( EX_BIST_TC_START_TEST_DC , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TC_START_TEST_DC ); REG64_FLD( EX_BIST_TC_SRAM_ABIST_MODE_DC , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TC_SRAM_ABIST_MODE_DC ); REG64_FLD( EX_BIST_TC_EDRAM_ABIST_MODE_DC , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TC_EDRAM_ABIST_MODE_DC ); REG64_FLD( EX_BIST_TC_IOBIST_MODE_DC , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TC_IOBIST_MODE_DC ); REG64_FLD( EX_BIST_PERV , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PERV ); REG64_FLD( EX_BIST_UNIT1 , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT1 ); REG64_FLD( EX_BIST_UNIT2 , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT2 ); REG64_FLD( EX_BIST_UNIT3 , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT3 ); REG64_FLD( EX_BIST_UNIT4 , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT4 ); REG64_FLD( EX_BIST_UNIT5 , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT5 ); REG64_FLD( EX_BIST_UNIT6 , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT6 ); REG64_FLD( EX_BIST_UNIT7 , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT7 ); REG64_FLD( EX_BIST_UNIT8 , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT8 ); REG64_FLD( EX_BIST_UNIT9 , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT9 ); REG64_FLD( EX_BIST_UNIT10 , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT10 ); REG64_FLD( EX_BIST_STROBE_WINDOW_EN , 48 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STROBE_WINDOW_EN ); REG64_FLD( C_BIST_TC_START_TEST_DC , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TC_START_TEST_DC ); REG64_FLD( C_BIST_TC_SRAM_ABIST_MODE_DC , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TC_SRAM_ABIST_MODE_DC ); REG64_FLD( C_BIST_TC_EDRAM_ABIST_MODE_DC , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TC_EDRAM_ABIST_MODE_DC ); REG64_FLD( C_BIST_TC_IOBIST_MODE_DC , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TC_IOBIST_MODE_DC ); REG64_FLD( C_BIST_PERV , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PERV ); REG64_FLD( C_BIST_UNIT1 , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT1 ); REG64_FLD( C_BIST_UNIT2 , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT2 ); REG64_FLD( C_BIST_UNIT3 , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT3 ); REG64_FLD( C_BIST_UNIT4 , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT4 ); REG64_FLD( C_BIST_UNIT5 , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT5 ); REG64_FLD( C_BIST_UNIT6 , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT6 ); REG64_FLD( C_BIST_UNIT7 , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT7 ); REG64_FLD( C_BIST_UNIT8 , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT8 ); REG64_FLD( C_BIST_UNIT9 , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT9 ); REG64_FLD( C_BIST_UNIT10 , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT10 ); REG64_FLD( C_BIST_STROBE_WINDOW_EN , 48 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STROBE_WINDOW_EN ); REG64_FLD( EQ_CC_ATOMIC_LOCK_REG_ENABLE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( EQ_CC_ATOMIC_LOCK_REG_ID , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ID ); REG64_FLD( EQ_CC_ATOMIC_LOCK_REG_ID_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ID_LEN ); REG64_FLD( EQ_CC_ATOMIC_LOCK_REG_ACTIVITY , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACTIVITY ); REG64_FLD( EQ_CC_ATOMIC_LOCK_REG_ACTIVITY_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACTIVITY_LEN ); REG64_FLD( EX_CC_ATOMIC_LOCK_REG_ENABLE , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( EX_CC_ATOMIC_LOCK_REG_ID , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ID ); REG64_FLD( EX_CC_ATOMIC_LOCK_REG_ID_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ID_LEN ); REG64_FLD( EX_CC_ATOMIC_LOCK_REG_ACTIVITY , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACTIVITY ); REG64_FLD( EX_CC_ATOMIC_LOCK_REG_ACTIVITY_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACTIVITY_LEN ); REG64_FLD( C_CC_ATOMIC_LOCK_REG_ENABLE , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( C_CC_ATOMIC_LOCK_REG_ID , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ID ); REG64_FLD( C_CC_ATOMIC_LOCK_REG_ID_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ID_LEN ); REG64_FLD( C_CC_ATOMIC_LOCK_REG_ACTIVITY , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACTIVITY ); REG64_FLD( C_CC_ATOMIC_LOCK_REG_ACTIVITY_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACTIVITY_LEN ); REG64_FLD( EQ_CC_PROTECT_MODE_REG_READ_ENABLE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_READ_ENABLE ); REG64_FLD( EQ_CC_PROTECT_MODE_REG_WRITE_ENABLE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WRITE_ENABLE ); REG64_FLD( EX_CC_PROTECT_MODE_REG_READ_ENABLE , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_READ_ENABLE ); REG64_FLD( EX_CC_PROTECT_MODE_REG_WRITE_ENABLE , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WRITE_ENABLE ); REG64_FLD( C_CC_PROTECT_MODE_REG_READ_ENABLE , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_READ_ENABLE ); REG64_FLD( C_CC_PROTECT_MODE_REG_WRITE_ENABLE , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WRITE_ENABLE ); REG64_FLD( EQ_CLK_REGION_CLOCK_CMD , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CLOCK_CMD ); REG64_FLD( EQ_CLK_REGION_CLOCK_CMD_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CLOCK_CMD_LEN ); REG64_FLD( EQ_CLK_REGION_SLAVE_MODE , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SLAVE_MODE ); REG64_FLD( EQ_CLK_REGION_MASTER_MODE , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASTER_MODE ); REG64_FLD( EQ_CLK_REGION_CLOCK_PERV , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CLOCK_PERV ); REG64_FLD( EQ_CLK_REGION_CLOCK_UNIT1 , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT1 ); REG64_FLD( EQ_CLK_REGION_CLOCK_UNIT2 , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT2 ); REG64_FLD( EQ_CLK_REGION_CLOCK_UNIT3 , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT3 ); REG64_FLD( EQ_CLK_REGION_CLOCK_UNIT4 , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT4 ); REG64_FLD( EQ_CLK_REGION_CLOCK_UNIT5 , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT5 ); REG64_FLD( EQ_CLK_REGION_CLOCK_UNIT6 , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT6 ); REG64_FLD( EQ_CLK_REGION_CLOCK_UNIT7 , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT7 ); REG64_FLD( EQ_CLK_REGION_CLOCK_UNIT8 , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT8 ); REG64_FLD( EQ_CLK_REGION_CLOCK_UNIT9 , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT9 ); REG64_FLD( EQ_CLK_REGION_CLOCK_UNIT10 , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT10 ); REG64_FLD( EQ_CLK_REGION_SEL_THOLD_SL , 48 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEL_THOLD_SL ); REG64_FLD( EQ_CLK_REGION_SEL_THOLD_NSL , 49 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEL_THOLD_NSL ); REG64_FLD( EQ_CLK_REGION_SEL_THOLD_ARY , 50 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEL_THOLD_ARY ); REG64_FLD( EQ_CLK_REGION_CLOCK_PULSE_USE_EVEN , 52 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CLOCK_PULSE_USE_EVEN ); REG64_FLD( EX_CLK_REGION_CLOCK_CMD , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CLOCK_CMD ); REG64_FLD( EX_CLK_REGION_CLOCK_CMD_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CLOCK_CMD_LEN ); REG64_FLD( EX_CLK_REGION_SLAVE_MODE , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SLAVE_MODE ); REG64_FLD( EX_CLK_REGION_MASTER_MODE , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASTER_MODE ); REG64_FLD( EX_CLK_REGION_CLOCK_PERV , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CLOCK_PERV ); REG64_FLD( EX_CLK_REGION_CLOCK_UNIT1 , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT1 ); REG64_FLD( EX_CLK_REGION_CLOCK_UNIT2 , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT2 ); REG64_FLD( EX_CLK_REGION_CLOCK_UNIT3 , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT3 ); REG64_FLD( EX_CLK_REGION_CLOCK_UNIT4 , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT4 ); REG64_FLD( EX_CLK_REGION_CLOCK_UNIT5 , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT5 ); REG64_FLD( EX_CLK_REGION_CLOCK_UNIT6 , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT6 ); REG64_FLD( EX_CLK_REGION_CLOCK_UNIT7 , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT7 ); REG64_FLD( EX_CLK_REGION_CLOCK_UNIT8 , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT8 ); REG64_FLD( EX_CLK_REGION_CLOCK_UNIT9 , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT9 ); REG64_FLD( EX_CLK_REGION_CLOCK_UNIT10 , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT10 ); REG64_FLD( EX_CLK_REGION_SEL_THOLD_SL , 48 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEL_THOLD_SL ); REG64_FLD( EX_CLK_REGION_SEL_THOLD_NSL , 49 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEL_THOLD_NSL ); REG64_FLD( EX_CLK_REGION_SEL_THOLD_ARY , 50 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEL_THOLD_ARY ); REG64_FLD( EX_CLK_REGION_CLOCK_PULSE_USE_EVEN , 52 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CLOCK_PULSE_USE_EVEN ); REG64_FLD( C_CLK_REGION_CLOCK_CMD , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CLOCK_CMD ); REG64_FLD( C_CLK_REGION_CLOCK_CMD_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CLOCK_CMD_LEN ); REG64_FLD( C_CLK_REGION_SLAVE_MODE , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SLAVE_MODE ); REG64_FLD( C_CLK_REGION_MASTER_MODE , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MASTER_MODE ); REG64_FLD( C_CLK_REGION_CLOCK_PERV , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CLOCK_PERV ); REG64_FLD( C_CLK_REGION_CLOCK_UNIT1 , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT1 ); REG64_FLD( C_CLK_REGION_CLOCK_UNIT2 , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT2 ); REG64_FLD( C_CLK_REGION_CLOCK_UNIT3 , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT3 ); REG64_FLD( C_CLK_REGION_CLOCK_UNIT4 , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT4 ); REG64_FLD( C_CLK_REGION_CLOCK_UNIT5 , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT5 ); REG64_FLD( C_CLK_REGION_CLOCK_UNIT6 , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT6 ); REG64_FLD( C_CLK_REGION_CLOCK_UNIT7 , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT7 ); REG64_FLD( C_CLK_REGION_CLOCK_UNIT8 , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT8 ); REG64_FLD( C_CLK_REGION_CLOCK_UNIT9 , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT9 ); REG64_FLD( C_CLK_REGION_CLOCK_UNIT10 , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT10 ); REG64_FLD( C_CLK_REGION_SEL_THOLD_SL , 48 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEL_THOLD_SL ); REG64_FLD( C_CLK_REGION_SEL_THOLD_NSL , 49 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEL_THOLD_NSL ); REG64_FLD( C_CLK_REGION_SEL_THOLD_ARY , 50 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEL_THOLD_ARY ); REG64_FLD( C_CLK_REGION_CLOCK_PULSE_USE_EVEN , 52 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CLOCK_PULSE_USE_EVEN ); REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_PERV , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_PERV ); REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_UNIT1 , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT1 ); REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_UNIT2 , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT2 ); REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_UNIT3 , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT3 ); REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_UNIT4 , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT4 ); REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_UNIT5 , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT5 ); REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_UNIT6 , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT6 ); REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_UNIT7 , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT7 ); REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_UNIT8 , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT8 ); REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_UNIT9 , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT9 ); REG64_FLD( EQ_CLOCK_STAT_ARY_STATUS_UNIT10 , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT10 ); REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_PERV , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_PERV ); REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_UNIT1 , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT1 ); REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_UNIT2 , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT2 ); REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_UNIT3 , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT3 ); REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_UNIT4 , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT4 ); REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_UNIT5 , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT5 ); REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_UNIT6 , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT6 ); REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_UNIT7 , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT7 ); REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_UNIT8 , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT8 ); REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_UNIT9 , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT9 ); REG64_FLD( EX_CLOCK_STAT_ARY_STATUS_UNIT10 , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT10 ); REG64_FLD( C_CLOCK_STAT_ARY_STATUS_PERV , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_PERV ); REG64_FLD( C_CLOCK_STAT_ARY_STATUS_UNIT1 , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT1 ); REG64_FLD( C_CLOCK_STAT_ARY_STATUS_UNIT2 , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT2 ); REG64_FLD( C_CLOCK_STAT_ARY_STATUS_UNIT3 , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT3 ); REG64_FLD( C_CLOCK_STAT_ARY_STATUS_UNIT4 , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT4 ); REG64_FLD( C_CLOCK_STAT_ARY_STATUS_UNIT5 , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT5 ); REG64_FLD( C_CLOCK_STAT_ARY_STATUS_UNIT6 , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT6 ); REG64_FLD( C_CLOCK_STAT_ARY_STATUS_UNIT7 , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT7 ); REG64_FLD( C_CLOCK_STAT_ARY_STATUS_UNIT8 , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT8 ); REG64_FLD( C_CLOCK_STAT_ARY_STATUS_UNIT9 , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT9 ); REG64_FLD( C_CLOCK_STAT_ARY_STATUS_UNIT10 , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT10 ); REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_PERV , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_PERV ); REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_UNIT1 , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT1 ); REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_UNIT2 , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT2 ); REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_UNIT3 , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT3 ); REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_UNIT4 , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT4 ); REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_UNIT5 , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT5 ); REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_UNIT6 , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT6 ); REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_UNIT7 , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT7 ); REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_UNIT8 , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT8 ); REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_UNIT9 , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT9 ); REG64_FLD( EQ_CLOCK_STAT_NSL_STATUS_UNIT10 , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT10 ); REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_PERV , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_PERV ); REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_UNIT1 , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT1 ); REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_UNIT2 , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT2 ); REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_UNIT3 , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT3 ); REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_UNIT4 , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT4 ); REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_UNIT5 , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT5 ); REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_UNIT6 , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT6 ); REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_UNIT7 , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT7 ); REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_UNIT8 , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT8 ); REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_UNIT9 , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT9 ); REG64_FLD( EX_CLOCK_STAT_NSL_STATUS_UNIT10 , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT10 ); REG64_FLD( C_CLOCK_STAT_NSL_STATUS_PERV , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_PERV ); REG64_FLD( C_CLOCK_STAT_NSL_STATUS_UNIT1 , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT1 ); REG64_FLD( C_CLOCK_STAT_NSL_STATUS_UNIT2 , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT2 ); REG64_FLD( C_CLOCK_STAT_NSL_STATUS_UNIT3 , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT3 ); REG64_FLD( C_CLOCK_STAT_NSL_STATUS_UNIT4 , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT4 ); REG64_FLD( C_CLOCK_STAT_NSL_STATUS_UNIT5 , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT5 ); REG64_FLD( C_CLOCK_STAT_NSL_STATUS_UNIT6 , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT6 ); REG64_FLD( C_CLOCK_STAT_NSL_STATUS_UNIT7 , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT7 ); REG64_FLD( C_CLOCK_STAT_NSL_STATUS_UNIT8 , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT8 ); REG64_FLD( C_CLOCK_STAT_NSL_STATUS_UNIT9 , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT9 ); REG64_FLD( C_CLOCK_STAT_NSL_STATUS_UNIT10 , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT10 ); REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_PERV , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_PERV ); REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_UNIT1 , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT1 ); REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_UNIT2 , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT2 ); REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_UNIT3 , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT3 ); REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_UNIT4 , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT4 ); REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_UNIT5 , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT5 ); REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_UNIT6 , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT6 ); REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_UNIT7 , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT7 ); REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_UNIT8 , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT8 ); REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_UNIT9 , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT9 ); REG64_FLD( EQ_CLOCK_STAT_SL_STATUS_UNIT10 , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATUS_UNIT10 ); REG64_FLD( EX_CLOCK_STAT_SL_STATUS_PERV , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_PERV ); REG64_FLD( EX_CLOCK_STAT_SL_STATUS_UNIT1 , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT1 ); REG64_FLD( EX_CLOCK_STAT_SL_STATUS_UNIT2 , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT2 ); REG64_FLD( EX_CLOCK_STAT_SL_STATUS_UNIT3 , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT3 ); REG64_FLD( EX_CLOCK_STAT_SL_STATUS_UNIT4 , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT4 ); REG64_FLD( EX_CLOCK_STAT_SL_STATUS_UNIT5 , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT5 ); REG64_FLD( EX_CLOCK_STAT_SL_STATUS_UNIT6 , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT6 ); REG64_FLD( EX_CLOCK_STAT_SL_STATUS_UNIT7 , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT7 ); REG64_FLD( EX_CLOCK_STAT_SL_STATUS_UNIT8 , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT8 ); REG64_FLD( EX_CLOCK_STAT_SL_STATUS_UNIT9 , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT9 ); REG64_FLD( EX_CLOCK_STAT_SL_STATUS_UNIT10 , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATUS_UNIT10 ); REG64_FLD( C_CLOCK_STAT_SL_STATUS_PERV , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_PERV ); REG64_FLD( C_CLOCK_STAT_SL_STATUS_UNIT1 , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT1 ); REG64_FLD( C_CLOCK_STAT_SL_STATUS_UNIT2 , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT2 ); REG64_FLD( C_CLOCK_STAT_SL_STATUS_UNIT3 , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT3 ); REG64_FLD( C_CLOCK_STAT_SL_STATUS_UNIT4 , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT4 ); REG64_FLD( C_CLOCK_STAT_SL_STATUS_UNIT5 , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT5 ); REG64_FLD( C_CLOCK_STAT_SL_STATUS_UNIT6 , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT6 ); REG64_FLD( C_CLOCK_STAT_SL_STATUS_UNIT7 , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT7 ); REG64_FLD( C_CLOCK_STAT_SL_STATUS_UNIT8 , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT8 ); REG64_FLD( C_CLOCK_STAT_SL_STATUS_UNIT9 , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT9 ); REG64_FLD( C_CLOCK_STAT_SL_STATUS_UNIT10 , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATUS_UNIT10 ); REG64_FLD( EX_CME_LCL_DBG_EN , 0 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_EN ); REG64_FLD( EX_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_HALT_ON_XSTOP ); REG64_FLD( EX_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); REG64_FLD( EX_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_RESERVED3 ); REG64_FLD( EX_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_EN_INTR_ADDR ); REG64_FLD( EX_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_EN_TRACE_EXTRA ); REG64_FLD( EX_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_EN_TRACE_STALL ); REG64_FLD( EX_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_EN_WAIT_CYCLES ); REG64_FLD( EX_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_EN_FULL_SPEED ); REG64_FLD( EX_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_RESERVED9 ); REG64_FLD( EX_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL ); REG64_FLD( EX_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); REG64_FLD( EX_CME_LCL_DBG_RESERVED12_15 , 12 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_RESERVED12_15 ); REG64_FLD( EX_CME_LCL_DBG_RESERVED12_15_LEN , 4 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_RESERVED12_15_LEN ); REG64_FLD( EX_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( EX_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( EX_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); REG64_FLD( EX_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL ); REG64_FLD( EX_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( EX_CME_LCL_DBG_HALT_INPUT , 24 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_HALT_INPUT ); REG64_FLD( EQ_CME_LCL_EIMR_INTERRUPT_MASK , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_MASK ); REG64_FLD( EQ_CME_LCL_EIMR_INTERRUPT_MASK_LEN , 44 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_MASK_LEN ); REG64_FLD( EX_CME_LCL_EIMR_INTERRUPT_MASK , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_MASK ); REG64_FLD( EX_CME_LCL_EIMR_INTERRUPT_MASK_LEN , 44 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_MASK_LEN ); REG64_FLD( EQ_CME_LCL_EINR_INTERRUPT_INPUT , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_INPUT ); REG64_FLD( EQ_CME_LCL_EINR_INTERRUPT_INPUT_LEN , 44 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_INPUT_LEN ); REG64_FLD( EX_CME_LCL_EINR_INTERRUPT_INPUT , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_INPUT ); REG64_FLD( EX_CME_LCL_EINR_INTERRUPT_INPUT_LEN , 44 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_INPUT_LEN ); REG64_FLD( EQ_CME_LCL_EIPR_INTERRUPT_POLARITY , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_POLARITY ); REG64_FLD( EQ_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN , 44 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_POLARITY_LEN ); REG64_FLD( EX_CME_LCL_EIPR_INTERRUPT_POLARITY , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_POLARITY ); REG64_FLD( EX_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN , 44 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_POLARITY_LEN ); REG64_FLD( EQ_CME_LCL_EISR_DEBUGGER , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DEBUGGER ); REG64_FLD( EQ_CME_LCL_EISR_DEBUG_TRIGGER , 1 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DEBUG_TRIGGER ); REG64_FLD( EQ_CME_LCL_EISR_QUAD_CHECKSTOP , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_QUAD_CHECKSTOP ); REG64_FLD( EQ_CME_LCL_EISR_PVREF_FAIL , 3 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PVREF_FAIL ); REG64_FLD( EQ_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( EQ_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_CORE_CHECKSTOP ); REG64_FLD( EQ_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DROPOUT_DETECT ); REG64_FLD( EQ_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( EQ_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( EQ_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_BCE_TIMEOUT ); REG64_FLD( EQ_CME_LCL_EISR_DOORBELL3_C0 , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DOORBELL3_C0 ); REG64_FLD( EQ_CME_LCL_EISR_DOORBELL3_C1 , 11 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DOORBELL3_C1 ); REG64_FLD( EQ_CME_LCL_EISR_PC_INTR_PENDING_C0 , 12 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PC_INTR_PENDING_C0 ); REG64_FLD( EQ_CME_LCL_EISR_PC_INTR_PENDING_C1 , 13 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PC_INTR_PENDING_C1 ); REG64_FLD( EQ_CME_LCL_EISR_SPECIAL_WAKEUP_C0 , 14 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SPECIAL_WAKEUP_C0 ); REG64_FLD( EQ_CME_LCL_EISR_SPECIAL_WAKEUP_C1 , 15 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SPECIAL_WAKEUP_C1 ); REG64_FLD( EQ_CME_LCL_EISR_REG_WAKEUP_C0 , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_REG_WAKEUP_C0 ); REG64_FLD( EQ_CME_LCL_EISR_REG_WAKEUP_C1 , 17 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_REG_WAKEUP_C1 ); REG64_FLD( EQ_CME_LCL_EISR_DOORBELL2_C0 , 18 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DOORBELL2_C0 ); REG64_FLD( EQ_CME_LCL_EISR_DOORBELL2_C1 , 19 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DOORBELL2_C1 ); REG64_FLD( EQ_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 , 20 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PC_PM_STATE_ACTIVE_C0 ); REG64_FLD( EQ_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 , 21 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PC_PM_STATE_ACTIVE_C1 ); REG64_FLD( EQ_CME_LCL_EISR_L2_PURGE_DONE , 22 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_L2_PURGE_DONE ); REG64_FLD( EQ_CME_LCL_EISR_NCU_PURGE_DONE , 23 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_NCU_PURGE_DONE ); REG64_FLD( EQ_CME_LCL_EISR_CHTM_PURGE_DONE_C0 , 24 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_CHTM_PURGE_DONE_C0 ); REG64_FLD( EQ_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( EQ_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_BCE_BUSY_LOW ); REG64_FLD( EQ_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_FINAL_VDM_DATA01 ); REG64_FLD( EQ_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( EQ_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_COMM_RECVD ); REG64_FLD( EQ_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_COMM_SEND_ACK ); REG64_FLD( EQ_CME_LCL_EISR_COMM_SEND_NACK , 31 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_COMM_SEND_NACK ); REG64_FLD( EQ_CME_LCL_EISR_SPARE_32_33 , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SPARE_32_33 ); REG64_FLD( EQ_CME_LCL_EISR_SPARE_32_33_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SPARE_32_33_LEN ); REG64_FLD( EQ_CME_LCL_EISR_PMCR_UPDATE_C0 , 34 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PMCR_UPDATE_C0 ); REG64_FLD( EQ_CME_LCL_EISR_PMCR_UPDATE_C1 , 35 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PMCR_UPDATE_C1 ); REG64_FLD( EQ_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DOORBELL0_C0 ); REG64_FLD( EQ_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DOORBELL0_C1 ); REG64_FLD( EQ_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INTERCME_DIRECT_IN_1_2 ); REG64_FLD( EQ_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( EQ_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DOORBELL1_C0 ); REG64_FLD( EQ_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DOORBELL1_C1 ); REG64_FLD( EQ_CME_LCL_EISR_RESERVED_42_43 , 42 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RESERVED_42_43 ); REG64_FLD( EQ_CME_LCL_EISR_RESERVED_42_43_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RESERVED_42_43_LEN ); REG64_FLD( EX_CME_LCL_EISR_DEBUGGER , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DEBUGGER ); REG64_FLD( EX_CME_LCL_EISR_DEBUG_TRIGGER , 1 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DEBUG_TRIGGER ); REG64_FLD( EX_CME_LCL_EISR_QUAD_CHECKSTOP , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_QUAD_CHECKSTOP ); REG64_FLD( EX_CME_LCL_EISR_PVREF_FAIL , 3 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PVREF_FAIL ); REG64_FLD( EX_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( EX_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_CORE_CHECKSTOP ); REG64_FLD( EX_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DROPOUT_DETECT ); REG64_FLD( EX_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( EX_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( EX_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_BCE_TIMEOUT ); REG64_FLD( EX_CME_LCL_EISR_DOORBELL3_C0 , 10 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DOORBELL3_C0 ); REG64_FLD( EX_CME_LCL_EISR_DOORBELL3_C1 , 11 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DOORBELL3_C1 ); REG64_FLD( EX_CME_LCL_EISR_PC_INTR_PENDING_C0 , 12 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PC_INTR_PENDING_C0 ); REG64_FLD( EX_CME_LCL_EISR_PC_INTR_PENDING_C1 , 13 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PC_INTR_PENDING_C1 ); REG64_FLD( EX_CME_LCL_EISR_SPECIAL_WAKEUP_C0 , 14 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SPECIAL_WAKEUP_C0 ); REG64_FLD( EX_CME_LCL_EISR_SPECIAL_WAKEUP_C1 , 15 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SPECIAL_WAKEUP_C1 ); REG64_FLD( EX_CME_LCL_EISR_REG_WAKEUP_C0 , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_REG_WAKEUP_C0 ); REG64_FLD( EX_CME_LCL_EISR_REG_WAKEUP_C1 , 17 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_REG_WAKEUP_C1 ); REG64_FLD( EX_CME_LCL_EISR_DOORBELL2_C0 , 18 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DOORBELL2_C0 ); REG64_FLD( EX_CME_LCL_EISR_DOORBELL2_C1 , 19 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DOORBELL2_C1 ); REG64_FLD( EX_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 , 20 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PC_PM_STATE_ACTIVE_C0 ); REG64_FLD( EX_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 , 21 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PC_PM_STATE_ACTIVE_C1 ); REG64_FLD( EX_CME_LCL_EISR_L2_PURGE_DONE , 22 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_L2_PURGE_DONE ); REG64_FLD( EX_CME_LCL_EISR_NCU_PURGE_DONE , 23 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_NCU_PURGE_DONE ); REG64_FLD( EX_CME_LCL_EISR_CHTM_PURGE_DONE_C0 , 24 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_CHTM_PURGE_DONE_C0 ); REG64_FLD( EX_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( EX_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_BCE_BUSY_LOW ); REG64_FLD( EX_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_FINAL_VDM_DATA01 ); REG64_FLD( EX_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( EX_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_COMM_RECVD ); REG64_FLD( EX_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_COMM_SEND_ACK ); REG64_FLD( EX_CME_LCL_EISR_COMM_SEND_NACK , 31 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_COMM_SEND_NACK ); REG64_FLD( EX_CME_LCL_EISR_SPARE_32_33 , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SPARE_32_33 ); REG64_FLD( EX_CME_LCL_EISR_SPARE_32_33_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SPARE_32_33_LEN ); REG64_FLD( EX_CME_LCL_EISR_PMCR_UPDATE_C0 , 34 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PMCR_UPDATE_C0 ); REG64_FLD( EX_CME_LCL_EISR_PMCR_UPDATE_C1 , 35 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PMCR_UPDATE_C1 ); REG64_FLD( EX_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DOORBELL0_C0 ); REG64_FLD( EX_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DOORBELL0_C1 ); REG64_FLD( EX_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INTERCME_DIRECT_IN_1_2 ); REG64_FLD( EX_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( EX_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DOORBELL1_C0 ); REG64_FLD( EX_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DOORBELL1_C1 ); REG64_FLD( EX_CME_LCL_EISR_RESERVED_42_43 , 42 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_RESERVED_42_43 ); REG64_FLD( EX_CME_LCL_EISR_RESERVED_42_43_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_RESERVED_42_43_LEN ); REG64_FLD( EQ_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_STATUS ); REG64_FLD( EQ_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_STATUS_LEN ); REG64_FLD( EX_CME_LCL_EISTR_INTERRUPT_STATUS , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_STATUS ); REG64_FLD( EX_CME_LCL_EISTR_INTERRUPT_STATUS_LEN , 44 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_STATUS_LEN ); REG64_FLD( EQ_CME_LCL_EITR_INTERRUPT_TYPE , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_TYPE ); REG64_FLD( EQ_CME_LCL_EITR_INTERRUPT_TYPE_LEN , 44 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_TYPE_LEN ); REG64_FLD( EX_CME_LCL_EITR_INTERRUPT_TYPE , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_TYPE ); REG64_FLD( EX_CME_LCL_EITR_INTERRUPT_TYPE_LEN , 44 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_TYPE_LEN ); REG64_FLD( EX_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( EX_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); REG64_FLD( EX_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT ); REG64_FLD( EX_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); REG64_FLD( EX_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN ); REG64_FLD( EX_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_EX , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( EQ_CME_LCL_ICRR_COMM_RECV , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_COMM_RECV ); REG64_FLD( EQ_CME_LCL_ICRR_COMM_RECV_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_COMM_RECV_LEN ); REG64_FLD( EX_CME_LCL_ICRR_COMM_RECV , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_COMM_RECV ); REG64_FLD( EX_CME_LCL_ICRR_COMM_RECV_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_COMM_RECV_LEN ); REG64_FLD( EX_CME_LCL_ICSR_COMM_SEND , 0 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_COMM_SEND ); REG64_FLD( EX_CME_LCL_ICSR_COMM_SEND_LEN , 32 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_COMM_SEND_LEN ); REG64_FLD( EX_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( EX_CME_LCL_PECESR0_PECE_C_N_T0_LEN , 6 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( EX_CME_LCL_PECESR0_PECE_C_N_T1 , 8 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( EX_CME_LCL_PECESR0_PECE_C_N_T1_LEN , 6 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( EX_CME_LCL_PECESR0_PECE_C_N_T2 , 16 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( EX_CME_LCL_PECESR0_PECE_C_N_T2_LEN , 6 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( EX_CME_LCL_PECESR0_PECE_C_N_T3 , 24 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( EX_CME_LCL_PECESR0_PECE_C_N_T3_LEN , 6 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( EX_CME_LCL_PECESR0_USE_PECE , 32 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( EX_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( EX_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( EX_CME_LCL_PECESR1_PECE_C_N_T0_LEN , 6 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( EX_CME_LCL_PECESR1_PECE_C_N_T1 , 8 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( EX_CME_LCL_PECESR1_PECE_C_N_T1_LEN , 6 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( EX_CME_LCL_PECESR1_PECE_C_N_T2 , 16 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( EX_CME_LCL_PECESR1_PECE_C_N_T2_LEN , 6 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( EX_CME_LCL_PECESR1_PECE_C_N_T3 , 24 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( EX_CME_LCL_PECESR1_PECE_C_N_T3_LEN , 6 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( EX_CME_LCL_PECESR1_USE_PECE , 32 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( EX_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( EQ_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); REG64_FLD( EQ_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); REG64_FLD( EQ_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); REG64_FLD( EQ_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); REG64_FLD( EQ_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( EQ_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PM_EXIT_C1_ACTUAL ); REG64_FLD( EQ_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RESERVED_6_8 ); REG64_FLD( EQ_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RESERVED_6_8_LEN ); REG64_FLD( EQ_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( EQ_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( EQ_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PCBMUX_GRANT_C1 ); REG64_FLD( EQ_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RESERVED_12_15 ); REG64_FLD( EQ_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( EQ_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( EQ_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); REG64_FLD( EQ_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RESERVED_18_29 ); REG64_FLD( EQ_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RESERVED_18_29_LEN ); REG64_FLD( EQ_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); REG64_FLD( EQ_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( EQ_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( EQ_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PC_UNMASKED_ATTN_C1 ); REG64_FLD( EQ_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PM_STATE_ACTIVE_C0 ); REG64_FLD( EQ_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PM_STATE_ACTIVE_C1 ); REG64_FLD( EQ_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PM_STATE_C0 ); REG64_FLD( EQ_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PM_STATE_C0_LEN ); REG64_FLD( EQ_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PM_STATE_C1 ); REG64_FLD( EQ_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PM_STATE_C1_LEN ); REG64_FLD( EQ_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PM_STATE_ALL_HV_C0 ); REG64_FLD( EQ_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PM_STATE_ALL_HV_C1 ); REG64_FLD( EQ_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PC_INSTR_RUNNING_C0 ); REG64_FLD( EQ_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PC_INSTR_RUNNING_C1 ); REG64_FLD( EQ_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PC_NON_HV_RUNNING_C0 ); REG64_FLD( EQ_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); REG64_FLD( EQ_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( EQ_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); REG64_FLD( EQ_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ALLOW_REG_WAKEUP_C0 ); REG64_FLD( EQ_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ALLOW_REG_WAKEUP_C1 ); REG64_FLD( EX_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); REG64_FLD( EX_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); REG64_FLD( EX_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); REG64_FLD( EX_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); REG64_FLD( EX_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( EX_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PM_EXIT_C1_ACTUAL ); REG64_FLD( EX_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_RESERVED_6_8 ); REG64_FLD( EX_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_RESERVED_6_8_LEN ); REG64_FLD( EX_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( EX_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( EX_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PCBMUX_GRANT_C1 ); REG64_FLD( EX_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_RESERVED_12_15 ); REG64_FLD( EX_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( EX_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( EX_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); REG64_FLD( EX_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_RESERVED_18_29 ); REG64_FLD( EX_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_RESERVED_18_29_LEN ); REG64_FLD( EX_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); REG64_FLD( EX_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( EX_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( EX_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PC_UNMASKED_ATTN_C1 ); REG64_FLD( EX_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PM_STATE_ACTIVE_C0 ); REG64_FLD( EX_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PM_STATE_ACTIVE_C1 ); REG64_FLD( EX_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PM_STATE_C0 ); REG64_FLD( EX_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PM_STATE_C0_LEN ); REG64_FLD( EX_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PM_STATE_C1 ); REG64_FLD( EX_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PM_STATE_C1_LEN ); REG64_FLD( EX_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PM_STATE_ALL_HV_C0 ); REG64_FLD( EX_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PM_STATE_ALL_HV_C1 ); REG64_FLD( EX_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PC_INSTR_RUNNING_C0 ); REG64_FLD( EX_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PC_INSTR_RUNNING_C1 ); REG64_FLD( EX_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PC_NON_HV_RUNNING_C0 ); REG64_FLD( EX_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); REG64_FLD( EX_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( EX_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); REG64_FLD( EX_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ALLOW_REG_WAKEUP_C0 ); REG64_FLD( EX_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ALLOW_REG_WAKEUP_C1 ); REG64_FLD( EX_CME_LCL_TSEL_FIT_SEL , 0 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_FIT_SEL ); REG64_FLD( EX_CME_LCL_TSEL_FIT_SEL_LEN , 4 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_FIT_SEL_LEN ); REG64_FLD( EX_CME_LCL_TSEL_WATCHDOG_SEL , 4 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL ); REG64_FLD( EX_CME_LCL_TSEL_WATCHDOG_SEL_LEN , 4 , SH_UNT_EX , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL_LEN ); REG64_FLD( EQ_CME_SCOM_AFSR_INST_CYCLE_SAMPLE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST_CYCLE_SAMPLE ); REG64_FLD( EQ_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST_CYCLE_SAMPLE_LEN ); REG64_FLD( EQ_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_AVG_CYCLE_SAMPLE ); REG64_FLD( EQ_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_AVG_CYCLE_SAMPLE_LEN ); REG64_FLD( EQ_CME_SCOM_AFSR_SAMPLE_VALID , 63 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SAMPLE_VALID ); REG64_FLD( EX_CME_SCOM_AFSR_INST_CYCLE_SAMPLE , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST_CYCLE_SAMPLE ); REG64_FLD( EX_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST_CYCLE_SAMPLE_LEN ); REG64_FLD( EX_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE , 32 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_AVG_CYCLE_SAMPLE ); REG64_FLD( EX_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_AVG_CYCLE_SAMPLE_LEN ); REG64_FLD( EX_CME_SCOM_AFSR_SAMPLE_VALID , 63 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SAMPLE_VALID ); REG64_FLD( EQ_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_MAX_CYCLE_SAMPLE ); REG64_FLD( EQ_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN , 20 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_MAX_CYCLE_SAMPLE_LEN ); REG64_FLD( EQ_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_MIN_CYCLE_SAMPLE ); REG64_FLD( EQ_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN , 20 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_MIN_CYCLE_SAMPLE_LEN ); REG64_FLD( EX_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MAX_CYCLE_SAMPLE ); REG64_FLD( EX_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN , 20 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MAX_CYCLE_SAMPLE_LEN ); REG64_FLD( EX_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MIN_CYCLE_SAMPLE ); REG64_FLD( EX_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN , 20 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MIN_CYCLE_SAMPLE_LEN ); REG64_FLD( EQ_CME_SCOM_BCEBAR0_BASE , 8 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_BASE ); REG64_FLD( EQ_CME_SCOM_BCEBAR0_BASE_LEN , 36 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_BASE_LEN ); REG64_FLD( EQ_CME_SCOM_BCEBAR0_RD_SCOPE , 57 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_RD_SCOPE ); REG64_FLD( EQ_CME_SCOM_BCEBAR0_RD_SCOPE_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_RD_SCOPE_LEN ); REG64_FLD( EQ_CME_SCOM_BCEBAR0_WR_SCOPE , 59 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_WR_SCOPE ); REG64_FLD( EQ_CME_SCOM_BCEBAR0_VG_TARGET_SEL , 60 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VG_TARGET_SEL ); REG64_FLD( EQ_CME_SCOM_BCEBAR0_SIZE , 61 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SIZE ); REG64_FLD( EQ_CME_SCOM_BCEBAR0_SIZE_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SIZE_LEN ); REG64_FLD( EX_CME_SCOM_BCEBAR0_BASE , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_BASE ); REG64_FLD( EX_CME_SCOM_BCEBAR0_BASE_LEN , 36 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_BASE_LEN ); REG64_FLD( EX_CME_SCOM_BCEBAR0_RD_SCOPE , 57 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_RD_SCOPE ); REG64_FLD( EX_CME_SCOM_BCEBAR0_RD_SCOPE_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_RD_SCOPE_LEN ); REG64_FLD( EX_CME_SCOM_BCEBAR0_WR_SCOPE , 59 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_WR_SCOPE ); REG64_FLD( EX_CME_SCOM_BCEBAR0_VG_TARGET_SEL , 60 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_VG_TARGET_SEL ); REG64_FLD( EX_CME_SCOM_BCEBAR0_SIZE , 61 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SIZE ); REG64_FLD( EX_CME_SCOM_BCEBAR0_SIZE_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SIZE_LEN ); REG64_FLD( EQ_CME_SCOM_BCEBAR1_BASE , 8 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_BASE ); REG64_FLD( EQ_CME_SCOM_BCEBAR1_BASE_LEN , 36 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_BASE_LEN ); REG64_FLD( EQ_CME_SCOM_BCEBAR1_RD_SCOPE , 57 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_RD_SCOPE ); REG64_FLD( EQ_CME_SCOM_BCEBAR1_RD_SCOPE_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_RD_SCOPE_LEN ); REG64_FLD( EQ_CME_SCOM_BCEBAR1_WR_SCOPE , 59 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_WR_SCOPE ); REG64_FLD( EQ_CME_SCOM_BCEBAR1_VG_TARGET_SEL , 60 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VG_TARGET_SEL ); REG64_FLD( EQ_CME_SCOM_BCEBAR1_SIZE , 61 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SIZE ); REG64_FLD( EQ_CME_SCOM_BCEBAR1_SIZE_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SIZE_LEN ); REG64_FLD( EX_CME_SCOM_BCEBAR1_BASE , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_BASE ); REG64_FLD( EX_CME_SCOM_BCEBAR1_BASE_LEN , 36 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_BASE_LEN ); REG64_FLD( EX_CME_SCOM_BCEBAR1_RD_SCOPE , 57 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_RD_SCOPE ); REG64_FLD( EX_CME_SCOM_BCEBAR1_RD_SCOPE_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_RD_SCOPE_LEN ); REG64_FLD( EX_CME_SCOM_BCEBAR1_WR_SCOPE , 59 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_WR_SCOPE ); REG64_FLD( EX_CME_SCOM_BCEBAR1_VG_TARGET_SEL , 60 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_VG_TARGET_SEL ); REG64_FLD( EX_CME_SCOM_BCEBAR1_SIZE , 61 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SIZE ); REG64_FLD( EX_CME_SCOM_BCEBAR1_SIZE_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SIZE_LEN ); REG64_FLD( EQ_CME_SCOM_BCECSR_BUSY , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_BUSY ); REG64_FLD( EQ_CME_SCOM_BCECSR_ERROR , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR ); REG64_FLD( EQ_CME_SCOM_BCECSR_RNW , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RNW ); REG64_FLD( EQ_CME_SCOM_BCECSR_BARSEL , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_BARSEL ); REG64_FLD( EQ_CME_SCOM_BCECSR_PRIORITY , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PRIORITY ); REG64_FLD( EQ_CME_SCOM_BCECSR_INJECT_ERR , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INJECT_ERR ); REG64_FLD( EQ_CME_SCOM_BCECSR_TYPE , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TYPE ); REG64_FLD( EQ_CME_SCOM_BCECSR_TYPE_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TYPE_LEN ); REG64_FLD( EQ_CME_SCOM_BCECSR_NUM_BLOCKS , 17 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NUM_BLOCKS ); REG64_FLD( EQ_CME_SCOM_BCECSR_NUM_BLOCKS_LEN , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NUM_BLOCKS_LEN ); REG64_FLD( EQ_CME_SCOM_BCECSR_SBASE , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SBASE ); REG64_FLD( EQ_CME_SCOM_BCECSR_SBASE_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SBASE_LEN ); REG64_FLD( EQ_CME_SCOM_BCECSR_MBASE , 42 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MBASE ); REG64_FLD( EQ_CME_SCOM_BCECSR_MBASE_LEN , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MBASE_LEN ); REG64_FLD( EX_CME_SCOM_BCECSR_BUSY , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_BUSY ); REG64_FLD( EX_CME_SCOM_BCECSR_ERROR , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ERROR ); REG64_FLD( EX_CME_SCOM_BCECSR_RNW , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RNW ); REG64_FLD( EX_CME_SCOM_BCECSR_BARSEL , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_BARSEL ); REG64_FLD( EX_CME_SCOM_BCECSR_PRIORITY , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PRIORITY ); REG64_FLD( EX_CME_SCOM_BCECSR_INJECT_ERR , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INJECT_ERR ); REG64_FLD( EX_CME_SCOM_BCECSR_TYPE , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TYPE ); REG64_FLD( EX_CME_SCOM_BCECSR_TYPE_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TYPE_LEN ); REG64_FLD( EX_CME_SCOM_BCECSR_NUM_BLOCKS , 17 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NUM_BLOCKS ); REG64_FLD( EX_CME_SCOM_BCECSR_NUM_BLOCKS_LEN , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NUM_BLOCKS_LEN ); REG64_FLD( EX_CME_SCOM_BCECSR_SBASE , 28 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SBASE ); REG64_FLD( EX_CME_SCOM_BCECSR_SBASE_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SBASE_LEN ); REG64_FLD( EX_CME_SCOM_BCECSR_MBASE , 42 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MBASE ); REG64_FLD( EX_CME_SCOM_BCECSR_MBASE_LEN , 22 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MBASE_LEN ); REG64_FLD( EQ_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_C0_DROPOUT_EVENT_COUNT ); REG64_FLD( EQ_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( EQ_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_C0_DROPOUT_INAROW_COUNT ); REG64_FLD( EQ_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( EQ_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_C1_DROPOUT_EVENT_COUNT ); REG64_FLD( EQ_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( EQ_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_C1_DROPOUT_INAROW_COUNT ); REG64_FLD( EQ_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( EX_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_C0_DROPOUT_EVENT_COUNT ); REG64_FLD( EX_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( EX_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_C0_DROPOUT_INAROW_COUNT ); REG64_FLD( EX_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( EX_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_C1_DROPOUT_EVENT_COUNT ); REG64_FLD( EX_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( EX_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_C1_DROPOUT_INAROW_COUNT ); REG64_FLD( EX_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( EQ_CME_SCOM_EIIR_DEBUGGER , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DEBUGGER ); REG64_FLD( EQ_CME_SCOM_EIIR_DEBUG_TRIGGER , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DEBUG_TRIGGER ); REG64_FLD( EQ_CME_SCOM_EIIR_BCE_TIMEOUT , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_BCE_TIMEOUT ); REG64_FLD( EQ_CME_SCOM_EIIR_PC_INTR_PENDING_C0 , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PC_INTR_PENDING_C0 ); REG64_FLD( EQ_CME_SCOM_EIIR_PC_INTR_PENDING_C1 , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PC_INTR_PENDING_C1 ); REG64_FLD( EQ_CME_SCOM_EIIR_SPECIAL_WAKEUP_C0 , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPECIAL_WAKEUP_C0 ); REG64_FLD( EQ_CME_SCOM_EIIR_SPECIAL_WAKEUP_C1 , 15 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPECIAL_WAKEUP_C1 ); REG64_FLD( EQ_CME_SCOM_EIIR_REG_WAKEUP_C0 , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_REG_WAKEUP_C0 ); REG64_FLD( EQ_CME_SCOM_EIIR_REG_WAKEUP_C1 , 17 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_REG_WAKEUP_C1 ); REG64_FLD( EQ_CME_SCOM_EIIR_PC_PM_STATE_ACTIVE_C0 , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PC_PM_STATE_ACTIVE_C0 ); REG64_FLD( EQ_CME_SCOM_EIIR_PC_PM_STATE_ACTIVE_C1 , 21 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PC_PM_STATE_ACTIVE_C1 ); REG64_FLD( EQ_CME_SCOM_EIIR_L2_PURGE_DONE , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L2_PURGE_DONE ); REG64_FLD( EQ_CME_SCOM_EIIR_NCU_PURGE_DONE , 23 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NCU_PURGE_DONE ); REG64_FLD( EQ_CME_SCOM_EIIR_CHTM_PURGE_DONE_C0 , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CHTM_PURGE_DONE_C0 ); REG64_FLD( EQ_CME_SCOM_EIIR_CHTM_PURGE_DONE_C1 , 25 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( EX_CME_SCOM_EIIR_DEBUGGER , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DEBUGGER ); REG64_FLD( EX_CME_SCOM_EIIR_DEBUG_TRIGGER , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DEBUG_TRIGGER ); REG64_FLD( EX_CME_SCOM_EIIR_BCE_TIMEOUT , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_BCE_TIMEOUT ); REG64_FLD( EX_CME_SCOM_EIIR_PC_INTR_PENDING_C0 , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PC_INTR_PENDING_C0 ); REG64_FLD( EX_CME_SCOM_EIIR_PC_INTR_PENDING_C1 , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PC_INTR_PENDING_C1 ); REG64_FLD( EX_CME_SCOM_EIIR_SPECIAL_WAKEUP_C0 , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SPECIAL_WAKEUP_C0 ); REG64_FLD( EX_CME_SCOM_EIIR_SPECIAL_WAKEUP_C1 , 15 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SPECIAL_WAKEUP_C1 ); REG64_FLD( EX_CME_SCOM_EIIR_REG_WAKEUP_C0 , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_REG_WAKEUP_C0 ); REG64_FLD( EX_CME_SCOM_EIIR_REG_WAKEUP_C1 , 17 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_REG_WAKEUP_C1 ); REG64_FLD( EX_CME_SCOM_EIIR_PC_PM_STATE_ACTIVE_C0 , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PC_PM_STATE_ACTIVE_C0 ); REG64_FLD( EX_CME_SCOM_EIIR_PC_PM_STATE_ACTIVE_C1 , 21 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PC_PM_STATE_ACTIVE_C1 ); REG64_FLD( EX_CME_SCOM_EIIR_L2_PURGE_DONE , 22 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L2_PURGE_DONE ); REG64_FLD( EX_CME_SCOM_EIIR_NCU_PURGE_DONE , 23 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NCU_PURGE_DONE ); REG64_FLD( EX_CME_SCOM_EIIR_CHTM_PURGE_DONE_C0 , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CHTM_PURGE_DONE_C0 ); REG64_FLD( EX_CME_SCOM_EIIR_CHTM_PURGE_DONE_C1 , 25 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( EQ_CME_SCOM_FLAGS_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_DATA ); REG64_FLD( EQ_CME_SCOM_FLAGS_DATA_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_DATA_LEN ); REG64_FLD( EX_CME_SCOM_FLAGS_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_DATA ); REG64_FLD( EX_CME_SCOM_FLAGS_DATA_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_DATA_LEN ); REG64_FLD( EQ_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DROPOUT_EVENT_THRESHOLD ); REG64_FLD( EQ_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); REG64_FLD( EQ_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DROPOUT_INAROW_THRESHOLD ); REG64_FLD( EQ_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); REG64_FLD( EQ_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DROPOUT_TIMER_MODE ); REG64_FLD( EQ_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DROPOUT_CHAR_MODE ); REG64_FLD( EQ_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); REG64_FLD( EQ_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( EQ_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_CORE_DROPOUT_ENABLE ); REG64_FLD( EQ_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( EQ_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_CACHE_DROPOUT_ENABLE ); REG64_FLD( EQ_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SPARE ); REG64_FLD( EQ_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DROPOUT_NOTIFY_ENABLE ); REG64_FLD( EQ_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SPARE41_43 ); REG64_FLD( EQ_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SPARE41_43_LEN ); REG64_FLD( EQ_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DROPOUT_SAMPLE_RATE ); REG64_FLD( EQ_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); REG64_FLD( EX_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DROPOUT_EVENT_THRESHOLD ); REG64_FLD( EX_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); REG64_FLD( EX_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DROPOUT_INAROW_THRESHOLD ); REG64_FLD( EX_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); REG64_FLD( EX_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DROPOUT_TIMER_MODE ); REG64_FLD( EX_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DROPOUT_CHAR_MODE ); REG64_FLD( EX_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); REG64_FLD( EX_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( EX_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_CORE_DROPOUT_ENABLE ); REG64_FLD( EX_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( EX_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_CACHE_DROPOUT_ENABLE ); REG64_FLD( EX_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SPARE ); REG64_FLD( EX_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DROPOUT_NOTIFY_ENABLE ); REG64_FLD( EX_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SPARE41_43 ); REG64_FLD( EX_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SPARE41_43_LEN ); REG64_FLD( EX_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DROPOUT_SAMPLE_RATE ); REG64_FLD( EX_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); REG64_FLD( EQ_CME_SCOM_LFIR_PPE_INTERNAL_ERROR , 0 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_PPE_INTERNAL_ERROR ); REG64_FLD( EQ_CME_SCOM_LFIR_PPE_EXTERNAL_ERROR , 1 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_PPE_EXTERNAL_ERROR ); REG64_FLD( EQ_CME_SCOM_LFIR_PPE_PROGRESS_ERROR , 2 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_PPE_PROGRESS_ERROR ); REG64_FLD( EQ_CME_SCOM_LFIR_PPE_BREAKPOINT_ERROR , 3 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_PPE_BREAKPOINT_ERROR ); REG64_FLD( EQ_CME_SCOM_LFIR_PPE_WATCHDOG , 4 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_PPE_WATCHDOG ); REG64_FLD( EQ_CME_SCOM_LFIR_PPE_HALTED , 5 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_PPE_HALTED ); REG64_FLD( EQ_CME_SCOM_LFIR_PPE_DEBUG_TRIGGER , 6 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_PPE_DEBUG_TRIGGER ); REG64_FLD( EQ_CME_SCOM_LFIR_SRAM_UE , 7 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_SRAM_UE ); REG64_FLD( EQ_CME_SCOM_LFIR_SRAM_CE , 8 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_SRAM_CE ); REG64_FLD( EQ_CME_SCOM_LFIR_SRAM_SCRUB_ERR , 9 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_SRAM_SCRUB_ERR ); REG64_FLD( EQ_CME_SCOM_LFIR_BCE_ERROR , 10 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_BCE_ERROR ); REG64_FLD( EQ_CME_SCOM_LFIR_SPARE11 , 11 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_SPARE11 ); REG64_FLD( EQ_CME_SCOM_LFIR_SPARE12 , 12 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_SPARE12 ); REG64_FLD( EQ_CME_SCOM_LFIR_C0_IVRM_DROPOUT , 13 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_C0_IVRM_DROPOUT ); REG64_FLD( EQ_CME_SCOM_LFIR_C1_IVRM_DROPOUT , 14 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_C1_IVRM_DROPOUT ); REG64_FLD( EQ_CME_SCOM_LFIR_CACHE_IVRM_DROPOUT , 15 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_CACHE_IVRM_DROPOUT ); REG64_FLD( EQ_CME_SCOM_LFIR_EXTREME_DROOP_ERR , 16 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_EXTREME_DROOP_ERR ); REG64_FLD( EQ_CME_SCOM_LFIR_LARGE_DROOP_ERR , 17 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_LARGE_DROOP_ERR ); REG64_FLD( EQ_CME_SCOM_LFIR_SMALL_DROOP_ERR , 18 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_SMALL_DROOP_ERR ); REG64_FLD( EQ_CME_SCOM_LFIR_UNEXPECTED_DROOP_ENCODE , 19 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_UNEXPECTED_DROOP_ENCODE ); REG64_FLD( EQ_CME_SCOM_LFIR_FIR_PARITY_ERR_DUP , 20 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR_DUP ); REG64_FLD( EQ_CME_SCOM_LFIR_FIR_PARITY_ERR , 21 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR ); REG64_FLD( EX_CME_SCOM_LFIR_PPE_INTERNAL_ERROR , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PPE_INTERNAL_ERROR ); REG64_FLD( EX_CME_SCOM_LFIR_PPE_EXTERNAL_ERROR , 1 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PPE_EXTERNAL_ERROR ); REG64_FLD( EX_CME_SCOM_LFIR_PPE_PROGRESS_ERROR , 2 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PPE_PROGRESS_ERROR ); REG64_FLD( EX_CME_SCOM_LFIR_PPE_BREAKPOINT_ERROR , 3 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PPE_BREAKPOINT_ERROR ); REG64_FLD( EX_CME_SCOM_LFIR_PPE_WATCHDOG , 4 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PPE_WATCHDOG ); REG64_FLD( EX_CME_SCOM_LFIR_PPE_HALTED , 5 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PPE_HALTED ); REG64_FLD( EX_CME_SCOM_LFIR_PPE_DEBUG_TRIGGER , 6 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PPE_DEBUG_TRIGGER ); REG64_FLD( EX_CME_SCOM_LFIR_SRAM_UE , 7 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SRAM_UE ); REG64_FLD( EX_CME_SCOM_LFIR_SRAM_CE , 8 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SRAM_CE ); REG64_FLD( EX_CME_SCOM_LFIR_SRAM_SCRUB_ERR , 9 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SRAM_SCRUB_ERR ); REG64_FLD( EX_CME_SCOM_LFIR_BCE_ERROR , 10 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_BCE_ERROR ); REG64_FLD( EX_CME_SCOM_LFIR_SPARE11 , 11 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE11 ); REG64_FLD( EX_CME_SCOM_LFIR_SPARE12 , 12 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE12 ); REG64_FLD( EX_CME_SCOM_LFIR_C0_IVRM_DROPOUT , 13 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_C0_IVRM_DROPOUT ); REG64_FLD( EX_CME_SCOM_LFIR_C1_IVRM_DROPOUT , 14 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_C1_IVRM_DROPOUT ); REG64_FLD( EX_CME_SCOM_LFIR_CACHE_IVRM_DROPOUT , 15 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CACHE_IVRM_DROPOUT ); REG64_FLD( EX_CME_SCOM_LFIR_EXTREME_DROOP_ERR , 16 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_EXTREME_DROOP_ERR ); REG64_FLD( EX_CME_SCOM_LFIR_LARGE_DROOP_ERR , 17 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_LARGE_DROOP_ERR ); REG64_FLD( EX_CME_SCOM_LFIR_SMALL_DROOP_ERR , 18 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SMALL_DROOP_ERR ); REG64_FLD( EX_CME_SCOM_LFIR_UNEXPECTED_DROOP_ENCODE , 19 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_UNEXPECTED_DROOP_ENCODE ); REG64_FLD( EX_CME_SCOM_LFIR_FIR_PARITY_ERR_DUP , 20 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR_DUP ); REG64_FLD( EX_CME_SCOM_LFIR_FIR_PARITY_ERR , 21 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR ); REG64_FLD( EQ_CME_SCOM_LFIRACT0_FIR_ACTION0 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION0 ); REG64_FLD( EQ_CME_SCOM_LFIRACT0_FIR_ACTION0_LEN , 22 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION0_LEN ); REG64_FLD( EX_CME_SCOM_LFIRACT0_FIR_ACTION0 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION0 ); REG64_FLD( EX_CME_SCOM_LFIRACT0_FIR_ACTION0_LEN , 22 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION0_LEN ); REG64_FLD( EQ_CME_SCOM_LFIRACT1_FIR_ACTION1 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION1 ); REG64_FLD( EQ_CME_SCOM_LFIRACT1_FIR_ACTION1_LEN , 22 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION1_LEN ); REG64_FLD( EX_CME_SCOM_LFIRACT1_FIR_ACTION1 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION1 ); REG64_FLD( EX_CME_SCOM_LFIRACT1_FIR_ACTION1_LEN , 22 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION1_LEN ); REG64_FLD( EQ_CME_SCOM_LFIRMASK_FIR_MASK , 0 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_FIR_MASK ); REG64_FLD( EQ_CME_SCOM_LFIRMASK_FIR_MASK_LEN , 22 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_FIR_MASK_LEN ); REG64_FLD( EX_CME_SCOM_LFIRMASK_FIR_MASK , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_FIR_MASK ); REG64_FLD( EX_CME_SCOM_LFIRMASK_FIR_MASK_LEN , 22 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_FIR_MASK_LEN ); REG64_FLD( EQ_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PMCR_OVERRIDE_EN ); REG64_FLD( EQ_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PSCR_OVERRIDE_EN ); REG64_FLD( EQ_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PMSR_OVERRIDE_EN ); REG64_FLD( EQ_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_BCECSR_OVERRIDE_EN ); REG64_FLD( EQ_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_IDR_LCL_SAMPLE_EN ); REG64_FLD( EQ_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VDM_LCL_SAMPLE_EN ); REG64_FLD( EQ_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_FREQ_LCL_SAMPLE_EN ); REG64_FLD( EQ_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_LOCK_PCB_ON_ERR ); REG64_FLD( EQ_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_QUEUED_WR_EN ); REG64_FLD( EQ_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_QUEUED_RD_EN ); REG64_FLD( EQ_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_MASK_PURGE_INTERFACE ); REG64_FLD( EQ_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_SPARE_11 ); REG64_FLD( EQ_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); REG64_FLD( EQ_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); REG64_FLD( EQ_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( EQ_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( EQ_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_STOP_OVERRIDE_MODE ); REG64_FLD( EQ_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_STOP_ACTIVE_MASK ); REG64_FLD( EQ_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_AUTO_STOP1_DISABLE ); REG64_FLD( EQ_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_STOP1_ACTIVE_ENABLE ); REG64_FLD( EQ_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_FENCE_EISR ); REG64_FLD( EQ_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( EQ_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_SPARE_22_23 ); REG64_FLD( EQ_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_SPARE_22_23_LEN ); REG64_FLD( EQ_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_AVG_FREQ_TSEL ); REG64_FLD( EQ_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_AVG_FREQ_TSEL_LEN ); REG64_FLD( EQ_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_SPARE_28_31 ); REG64_FLD( EQ_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_SPARE_28_31_LEN ); REG64_FLD( EQ_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_RESET_IMPRECISE_QERR ); REG64_FLD( EQ_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_SET_ECC_INJECT_ERR ); REG64_FLD( EX_CME_SCOM_LMCR_PMCR_OVERRIDE_EN , 0 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_PMCR_OVERRIDE_EN ); REG64_FLD( EX_CME_SCOM_LMCR_PSCR_OVERRIDE_EN , 1 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_PSCR_OVERRIDE_EN ); REG64_FLD( EX_CME_SCOM_LMCR_PMSR_OVERRIDE_EN , 2 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_PMSR_OVERRIDE_EN ); REG64_FLD( EX_CME_SCOM_LMCR_BCECSR_OVERRIDE_EN , 3 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_BCECSR_OVERRIDE_EN ); REG64_FLD( EX_CME_SCOM_LMCR_IDR_LCL_SAMPLE_EN , 4 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_IDR_LCL_SAMPLE_EN ); REG64_FLD( EX_CME_SCOM_LMCR_VDM_LCL_SAMPLE_EN , 5 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VDM_LCL_SAMPLE_EN ); REG64_FLD( EX_CME_SCOM_LMCR_FREQ_LCL_SAMPLE_EN , 6 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_FREQ_LCL_SAMPLE_EN ); REG64_FLD( EX_CME_SCOM_LMCR_LOCK_PCB_ON_ERR , 7 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_LOCK_PCB_ON_ERR ); REG64_FLD( EX_CME_SCOM_LMCR_QUEUED_WR_EN , 8 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_QUEUED_WR_EN ); REG64_FLD( EX_CME_SCOM_LMCR_QUEUED_RD_EN , 9 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_QUEUED_RD_EN ); REG64_FLD( EX_CME_SCOM_LMCR_MASK_PURGE_INTERFACE , 10 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_MASK_PURGE_INTERFACE ); REG64_FLD( EX_CME_SCOM_LMCR_SPARE_11 , 11 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_SPARE_11 ); REG64_FLD( EX_CME_SCOM_LMCR_C0_AUTO_SPECIAL_WAKEUP_DISABLE , 12 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_C0_AUTO_SPECIAL_WAKEUP_DISABLE ); REG64_FLD( EX_CME_SCOM_LMCR_C1_AUTO_SPECIAL_WAKEUP_DISABLE , 13 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_C1_AUTO_SPECIAL_WAKEUP_DISABLE ); REG64_FLD( EX_CME_SCOM_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 14 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( EX_CME_SCOM_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 15 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( EX_CME_SCOM_LMCR_STOP_OVERRIDE_MODE , 16 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_STOP_OVERRIDE_MODE ); REG64_FLD( EX_CME_SCOM_LMCR_STOP_ACTIVE_MASK , 17 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_STOP_ACTIVE_MASK ); REG64_FLD( EX_CME_SCOM_LMCR_AUTO_STOP1_DISABLE , 18 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_AUTO_STOP1_DISABLE ); REG64_FLD( EX_CME_SCOM_LMCR_STOP1_ACTIVE_ENABLE , 19 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_STOP1_ACTIVE_ENABLE ); REG64_FLD( EX_CME_SCOM_LMCR_FENCE_EISR , 20 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_FENCE_EISR ); REG64_FLD( EX_CME_SCOM_LMCR_PC_DISABLE_DROOP , 21 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( EX_CME_SCOM_LMCR_SPARE_22_23 , 22 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_SPARE_22_23 ); REG64_FLD( EX_CME_SCOM_LMCR_SPARE_22_23_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_SPARE_22_23_LEN ); REG64_FLD( EX_CME_SCOM_LMCR_AVG_FREQ_TSEL , 24 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_AVG_FREQ_TSEL ); REG64_FLD( EX_CME_SCOM_LMCR_AVG_FREQ_TSEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_AVG_FREQ_TSEL_LEN ); REG64_FLD( EX_CME_SCOM_LMCR_SPARE_28_31 , 28 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_SPARE_28_31 ); REG64_FLD( EX_CME_SCOM_LMCR_SPARE_28_31_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_SPARE_28_31_LEN ); REG64_FLD( EX_CME_SCOM_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_RESET_IMPRECISE_QERR ); REG64_FLD( EX_CME_SCOM_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_SET_ECC_INJECT_ERR ); REG64_FLD( EQ_CME_SCOM_PMCRS0_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( EQ_CME_SCOM_PMCRS0_DATA_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( EX_CME_SCOM_PMCRS0_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( EX_CME_SCOM_PMCRS0_DATA_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( EQ_CME_SCOM_PMCRS1_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( EQ_CME_SCOM_PMCRS1_DATA_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( EX_CME_SCOM_PMCRS1_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( EX_CME_SCOM_PMCRS1_DATA_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( EQ_CME_SCOM_PMSRS0_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( EQ_CME_SCOM_PMSRS0_DATA_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( EX_CME_SCOM_PMSRS0_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( EX_CME_SCOM_PMSRS0_DATA_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( EQ_CME_SCOM_PMSRS1_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( EQ_CME_SCOM_PMSRS1_DATA_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( EX_CME_SCOM_PMSRS1_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( EX_CME_SCOM_PMSRS1_DATA_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS00_SPARE0 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SPARE0 ); REG64_FLD( EQ_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N , 3 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE , 11 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE , 12 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE , 13 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS00_SPARE0 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SPARE0 ); REG64_FLD( EX_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE , 11 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE , 12 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE , 13 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS01_SPARE0 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SPARE0 ); REG64_FLD( EQ_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N , 3 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE , 11 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE , 12 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE , 13 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS01_SPARE0 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SPARE0 ); REG64_FLD( EX_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE , 11 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE , 12 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE , 13 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS02_SPARE0 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SPARE0 ); REG64_FLD( EQ_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N , 3 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE , 11 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE , 12 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE , 13 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS02_SPARE0 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SPARE0 ); REG64_FLD( EX_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE , 11 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE , 12 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE , 13 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS03_SPARE0 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SPARE0 ); REG64_FLD( EQ_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N , 3 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE , 11 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE , 12 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE , 13 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS03_SPARE0 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SPARE0 ); REG64_FLD( EX_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE , 11 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE , 12 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE , 13 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS10_SPARE0 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SPARE0 ); REG64_FLD( EQ_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N , 3 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE , 11 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE , 12 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE , 13 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS10_SPARE0 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SPARE0 ); REG64_FLD( EX_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE , 11 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE , 12 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE , 13 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS11_SPARE0 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SPARE0 ); REG64_FLD( EQ_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N , 3 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE , 11 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE , 12 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE , 13 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS11_SPARE0 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SPARE0 ); REG64_FLD( EX_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE , 11 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE , 12 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE , 13 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS12_SPARE0 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SPARE0 ); REG64_FLD( EQ_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N , 3 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE , 11 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE , 12 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE , 13 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS12_SPARE0 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SPARE0 ); REG64_FLD( EX_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE , 11 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE , 12 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE , 13 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS13_SPARE0 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SPARE0 ); REG64_FLD( EQ_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N , 3 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE , 11 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE , 12 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE , 13 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( EQ_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( EQ_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS13_SPARE0 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SPARE0 ); REG64_FLD( EX_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE , 11 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE , 12 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE , 13 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( EX_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( EX_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( EX_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( EQ_CME_SCOM_QFMR_TIMEBASE , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_TIMEBASE ); REG64_FLD( EQ_CME_SCOM_QFMR_TIMEBASE_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_TIMEBASE_LEN ); REG64_FLD( EQ_CME_SCOM_QFMR_CYCLES , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_CYCLES ); REG64_FLD( EQ_CME_SCOM_QFMR_CYCLES_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_CYCLES_LEN ); REG64_FLD( EX_CME_SCOM_QFMR_TIMEBASE , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_TIMEBASE ); REG64_FLD( EX_CME_SCOM_QFMR_TIMEBASE_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_TIMEBASE_LEN ); REG64_FLD( EX_CME_SCOM_QFMR_CYCLES , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_CYCLES ); REG64_FLD( EX_CME_SCOM_QFMR_CYCLES_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_CYCLES_LEN ); REG64_FLD( EQ_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); REG64_FLD( EQ_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( EQ_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); REG64_FLD( EQ_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( EQ_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DROPOUT_SAMPLE ); REG64_FLD( EQ_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DROPOUT_SAMPLE_LEN ); REG64_FLD( EX_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); REG64_FLD( EX_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( EX_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); REG64_FLD( EX_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( EX_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DROPOUT_SAMPLE ); REG64_FLD( EX_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DROPOUT_SAMPLE_LEN ); REG64_FLD( EQ_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PM_ENTRY_ACK_C0 ); REG64_FLD( EQ_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PM_ENTRY_ACK_C1 ); REG64_FLD( EQ_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); REG64_FLD( EQ_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); REG64_FLD( EQ_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PM_EXIT_C0 ); REG64_FLD( EQ_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PM_EXIT_C1 ); REG64_FLD( EQ_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); REG64_FLD( EQ_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); REG64_FLD( EQ_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); REG64_FLD( EQ_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); REG64_FLD( EQ_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PCBMUX_REQ_C0 ); REG64_FLD( EQ_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PCBMUX_REQ_C1 ); REG64_FLD( EQ_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_RESERVED_12_15 ); REG64_FLD( EQ_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( EQ_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_SPECIAL_WKUP_DONE_C0 ); REG64_FLD( EQ_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_SPECIAL_WKUP_DONE_C1 ); REG64_FLD( EQ_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_L2_PURGE ); REG64_FLD( EQ_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_L2_PURGE_ABORT ); REG64_FLD( EQ_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( EQ_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( EQ_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_NCU_PURGE ); REG64_FLD( EQ_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_NCU_PURGE_ABORT ); REG64_FLD( EQ_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_CHTM_PURGE_C0 ); REG64_FLD( EQ_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_CHTM_PURGE_C1 ); REG64_FLD( EQ_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_HMI_REQUEST_C0 ); REG64_FLD( EQ_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_HMI_REQUEST_C1 ); REG64_FLD( EQ_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PPM_SPARE_OUT_C0 ); REG64_FLD( EQ_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PPM_SPARE_OUT_C1 ); REG64_FLD( EQ_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_RESERVED_30_31 ); REG64_FLD( EQ_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_RESERVED_30_31_LEN ); REG64_FLD( EX_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_PM_ENTRY_ACK_C0 ); REG64_FLD( EX_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_PM_ENTRY_ACK_C1 ); REG64_FLD( EX_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); REG64_FLD( EX_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); REG64_FLD( EX_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_PM_EXIT_C0 ); REG64_FLD( EX_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_PM_EXIT_C1 ); REG64_FLD( EX_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); REG64_FLD( EX_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); REG64_FLD( EX_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); REG64_FLD( EX_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); REG64_FLD( EX_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_PCBMUX_REQ_C0 ); REG64_FLD( EX_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_PCBMUX_REQ_C1 ); REG64_FLD( EX_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_RESERVED_12_15 ); REG64_FLD( EX_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( EX_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_SPECIAL_WKUP_DONE_C0 ); REG64_FLD( EX_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_SPECIAL_WKUP_DONE_C1 ); REG64_FLD( EX_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_L2_PURGE ); REG64_FLD( EX_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_L2_PURGE_ABORT ); REG64_FLD( EX_CME_SCOM_SICR_PC_THROTTLE_REQ , 20 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_PC_THROTTLE_REQ ); REG64_FLD( EX_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( EX_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_NCU_PURGE ); REG64_FLD( EX_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_NCU_PURGE_ABORT ); REG64_FLD( EX_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_CHTM_PURGE_C0 ); REG64_FLD( EX_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_CHTM_PURGE_C1 ); REG64_FLD( EX_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_HMI_REQUEST_C0 ); REG64_FLD( EX_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_HMI_REQUEST_C1 ); REG64_FLD( EX_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_PPM_SPARE_OUT_C0 ); REG64_FLD( EX_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_PPM_SPARE_OUT_C1 ); REG64_FLD( EX_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_RESERVED_30_31 ); REG64_FLD( EX_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_RESERVED_30_31_LEN ); REG64_FLD( EQ_CME_SCOM_SRTCH0_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( EQ_CME_SCOM_SRTCH0_DATA_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( EX_CME_SCOM_SRTCH0_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( EX_CME_SCOM_SRTCH0_DATA_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( EQ_CME_SCOM_SRTCH1_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( EQ_CME_SCOM_SRTCH1_DATA_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( EX_CME_SCOM_SRTCH1_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( EX_CME_SCOM_SRTCH1_DATA_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( EQ_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SMALL_EVENT_THRESHOLD ); REG64_FLD( EQ_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); REG64_FLD( EQ_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_LARGE_EVENT_THRESHOLD ); REG64_FLD( EQ_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); REG64_FLD( EQ_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXTREME_EVENT_THRESHOLD ); REG64_FLD( EQ_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); REG64_FLD( EQ_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DROOP_PROFILE_TYPE ); REG64_FLD( EQ_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DROOP_PROFILE_TYPE_LEN ); REG64_FLD( EQ_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DROOP_TIMER_MODE ); REG64_FLD( EQ_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DROOP_CHAR_MODE ); REG64_FLD( EQ_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DROOP_NOTIFY_ENABLE ); REG64_FLD( EQ_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SPARE41_43 ); REG64_FLD( EQ_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SPARE41_43_LEN ); REG64_FLD( EQ_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DROOP_SAMPLE_RATE ); REG64_FLD( EQ_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DROOP_SAMPLE_RATE_LEN ); REG64_FLD( EX_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SMALL_EVENT_THRESHOLD ); REG64_FLD( EX_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); REG64_FLD( EX_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_LARGE_EVENT_THRESHOLD ); REG64_FLD( EX_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); REG64_FLD( EX_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXTREME_EVENT_THRESHOLD ); REG64_FLD( EX_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); REG64_FLD( EX_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DROOP_PROFILE_TYPE ); REG64_FLD( EX_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DROOP_PROFILE_TYPE_LEN ); REG64_FLD( EX_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DROOP_TIMER_MODE ); REG64_FLD( EX_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DROOP_CHAR_MODE ); REG64_FLD( EX_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DROOP_NOTIFY_ENABLE ); REG64_FLD( EX_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SPARE41_43 ); REG64_FLD( EX_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SPARE41_43_LEN ); REG64_FLD( EX_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DROOP_SAMPLE_RATE ); REG64_FLD( EX_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DROOP_SAMPLE_RATE_LEN ); REG64_FLD( EQ_CME_SCOM_VCTR_VDM_EXTREME_DROOP_THRESHOLD , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VDM_EXTREME_DROOP_THRESHOLD ); REG64_FLD( EQ_CME_SCOM_VCTR_VDM_EXTREME_DROOP_THRESHOLD_LEN , 16 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VDM_EXTREME_DROOP_THRESHOLD_LEN ); REG64_FLD( EQ_CME_SCOM_VCTR_VDM_LARGE_DROOP_THRESHOLD , 16 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VDM_LARGE_DROOP_THRESHOLD ); REG64_FLD( EQ_CME_SCOM_VCTR_VDM_LARGE_DROOP_THRESHOLD_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VDM_LARGE_DROOP_THRESHOLD_LEN ); REG64_FLD( EQ_CME_SCOM_VCTR_VDM_SMALL_DROOP_THRESHOLD , 40 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VDM_SMALL_DROOP_THRESHOLD ); REG64_FLD( EQ_CME_SCOM_VCTR_VDM_SMALL_DROOP_THRESHOLD_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VDM_SMALL_DROOP_THRESHOLD_LEN ); REG64_FLD( EX_CME_SCOM_VCTR_VDM_EXTREME_DROOP_THRESHOLD , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_VDM_EXTREME_DROOP_THRESHOLD ); REG64_FLD( EX_CME_SCOM_VCTR_VDM_EXTREME_DROOP_THRESHOLD_LEN , 16 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_VDM_EXTREME_DROOP_THRESHOLD_LEN ); REG64_FLD( EX_CME_SCOM_VCTR_VDM_LARGE_DROOP_THRESHOLD , 16 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_VDM_LARGE_DROOP_THRESHOLD ); REG64_FLD( EX_CME_SCOM_VCTR_VDM_LARGE_DROOP_THRESHOLD_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_VDM_LARGE_DROOP_THRESHOLD_LEN ); REG64_FLD( EX_CME_SCOM_VCTR_VDM_SMALL_DROOP_THRESHOLD , 40 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_VDM_SMALL_DROOP_THRESHOLD ); REG64_FLD( EX_CME_SCOM_VCTR_VDM_SMALL_DROOP_THRESHOLD_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_VDM_SMALL_DROOP_THRESHOLD_LEN ); REG64_FLD( EQ_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VDM_EXTREME_DROOP_CTR ); REG64_FLD( EQ_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); REG64_FLD( EQ_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VDM_LARGE_DROOP_CTR ); REG64_FLD( EQ_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); REG64_FLD( EQ_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VDM_SMALL_DROOP_CTR ); REG64_FLD( EQ_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); REG64_FLD( EX_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VDM_EXTREME_DROOP_CTR ); REG64_FLD( EX_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); REG64_FLD( EX_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VDM_LARGE_DROOP_CTR ); REG64_FLD( EX_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); REG64_FLD( EX_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VDM_SMALL_DROOP_CTR ); REG64_FLD( EX_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY ); REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INSTANT_CACHE_VDM_DATA ); REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN ); REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INSTANT_CORE0_VDM_DATA ); REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN ); REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA , 12 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INSTANT_CORE1_VDM_DATA ); REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN ); REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INSTANT_CORE2_VDM_DATA ); REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN ); REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA , 20 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INSTANT_CORE3_VDM_DATA ); REG64_FLD( EQ_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN ); REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_STICKY_VDM_CONTROL_SUMMARY ); REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA , 36 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_STICKY_CACHE_VDM_DATA ); REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_STICKY_CACHE_VDM_DATA_LEN ); REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA , 40 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_STICKY_CORE0_VDM_DATA ); REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_STICKY_CORE0_VDM_DATA_LEN ); REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA , 44 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_STICKY_CORE1_VDM_DATA ); REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_STICKY_CORE1_VDM_DATA_LEN ); REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA , 48 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_STICKY_CORE2_VDM_DATA ); REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_STICKY_CORE2_VDM_DATA_LEN ); REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA , 52 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_STICKY_CORE3_VDM_DATA ); REG64_FLD( EQ_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_STICKY_CORE3_VDM_DATA_LEN ); REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY ); REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INSTANT_CACHE_VDM_DATA ); REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN ); REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INSTANT_CORE0_VDM_DATA ); REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN ); REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA , 12 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INSTANT_CORE1_VDM_DATA ); REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN ); REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INSTANT_CORE2_VDM_DATA ); REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN ); REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA , 20 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INSTANT_CORE3_VDM_DATA ); REG64_FLD( EX_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN ); REG64_FLD( EX_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_STICKY_VDM_CONTROL_SUMMARY ); REG64_FLD( EX_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( EX_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA , 36 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_STICKY_CACHE_VDM_DATA ); REG64_FLD( EX_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_STICKY_CACHE_VDM_DATA_LEN ); REG64_FLD( EX_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA , 40 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_STICKY_CORE0_VDM_DATA ); REG64_FLD( EX_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_STICKY_CORE0_VDM_DATA_LEN ); REG64_FLD( EX_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA , 44 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_STICKY_CORE1_VDM_DATA ); REG64_FLD( EX_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_STICKY_CORE1_VDM_DATA_LEN ); REG64_FLD( EX_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA , 48 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_STICKY_CORE2_VDM_DATA ); REG64_FLD( EX_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_STICKY_CORE2_VDM_DATA_LEN ); REG64_FLD( EX_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA , 52 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_STICKY_CORE3_VDM_DATA ); REG64_FLD( EX_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_STICKY_CORE3_VDM_DATA_LEN ); REG64_FLD( EQ_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_TOTAL_DROOP_EVENT_CTR ); REG64_FLD( EQ_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); REG64_FLD( EQ_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SMALL_EVENT_PROFILE_CTR ); REG64_FLD( EQ_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); REG64_FLD( EQ_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LARGER_DROOP_EVENT_CTR ); REG64_FLD( EQ_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); REG64_FLD( EQ_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LARGE_EVENT_PROFILE_CTR ); REG64_FLD( EQ_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); REG64_FLD( EQ_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_EXTREME_DROOP_EVENT_CTR ); REG64_FLD( EQ_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); REG64_FLD( EX_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_TOTAL_DROOP_EVENT_CTR ); REG64_FLD( EX_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); REG64_FLD( EX_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SMALL_EVENT_PROFILE_CTR ); REG64_FLD( EX_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); REG64_FLD( EX_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_LARGER_DROOP_EVENT_CTR ); REG64_FLD( EX_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); REG64_FLD( EX_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_LARGE_EVENT_PROFILE_CTR ); REG64_FLD( EX_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); REG64_FLD( EX_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_EXTREME_DROOP_EVENT_CTR ); REG64_FLD( EX_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); REG64_FLD( EQ_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VDM_NO_DROOP_CTR ); REG64_FLD( EQ_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VDM_NO_DROOP_CTR_LEN ); REG64_FLD( EQ_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VDM_OVERVOLT_CTR ); REG64_FLD( EQ_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VDM_OVERVOLT_CTR_LEN ); REG64_FLD( EX_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VDM_NO_DROOP_CTR ); REG64_FLD( EX_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VDM_NO_DROOP_CTR_LEN ); REG64_FLD( EX_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VDM_OVERVOLT_CTR ); REG64_FLD( EX_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VDM_OVERVOLT_CTR_LEN ); REG64_FLD( EQ_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PCBM_DATA ); REG64_FLD( EQ_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PCBM_DATA_LEN ); REG64_FLD( EX_CME_SCOM_XIPCBMD0_PCBM_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PCBM_DATA ); REG64_FLD( EX_CME_SCOM_XIPCBMD0_PCBM_DATA_LEN , 27 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PCBM_DATA_LEN ); REG64_FLD( EQ_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PCBM_DATA ); REG64_FLD( EQ_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PCBM_DATA_LEN ); REG64_FLD( EX_CME_SCOM_XIPCBMD1_PCBM_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PCBM_DATA ); REG64_FLD( EX_CME_SCOM_XIPCBMD1_PCBM_DATA_LEN , 27 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PCBM_DATA_LEN ); REG64_FLD( EQ_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PCBM_INFO ); REG64_FLD( EQ_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PCBM_INFO_LEN ); REG64_FLD( EX_CME_SCOM_XIPCBMI0_PCBM_INFO , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PCBM_INFO ); REG64_FLD( EX_CME_SCOM_XIPCBMI0_PCBM_INFO_LEN , 7 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PCBM_INFO_LEN ); REG64_FLD( EQ_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PCBM_INFO ); REG64_FLD( EQ_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PCBM_INFO_LEN ); REG64_FLD( EX_CME_SCOM_XIPCBMI1_PCBM_INFO , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PCBM_INFO ); REG64_FLD( EX_CME_SCOM_XIPCBMI1_PCBM_INFO_LEN , 7 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PCBM_INFO_LEN ); REG64_FLD( EQ_CME_SCOM_XIPCBQ0_PCBQ_N_INFO , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PCBQ_N_INFO ); REG64_FLD( EQ_CME_SCOM_XIPCBQ0_PCBQ_N_INFO_LEN , 26 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PCBQ_N_INFO_LEN ); REG64_FLD( EX_CME_SCOM_XIPCBQ0_PCBQ_N_INFO , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PCBQ_N_INFO ); REG64_FLD( EX_CME_SCOM_XIPCBQ0_PCBQ_N_INFO_LEN , 26 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PCBQ_N_INFO_LEN ); REG64_FLD( EQ_CME_SCOM_XIPCBQ1_PCBQ_N_INFO , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PCBQ_N_INFO ); REG64_FLD( EQ_CME_SCOM_XIPCBQ1_PCBQ_N_INFO_LEN , 26 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PCBQ_N_INFO_LEN ); REG64_FLD( EX_CME_SCOM_XIPCBQ1_PCBQ_N_INFO , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PCBQ_N_INFO ); REG64_FLD( EX_CME_SCOM_XIPCBQ1_PCBQ_N_INFO_LEN , 26 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PCBQ_N_INFO_LEN ); REG64_FLD( EQ_CME_SCOM_XISIB_PIB_ADDR , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PIB_ADDR ); REG64_FLD( EQ_CME_SCOM_XISIB_PIB_ADDR_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PIB_ADDR_LEN ); REG64_FLD( EQ_CME_SCOM_XISIB_PIB_R_NW , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PIB_R_NW ); REG64_FLD( EQ_CME_SCOM_XISIB_PIB_BUSY , 33 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PIB_BUSY ); REG64_FLD( EQ_CME_SCOM_XISIB_PIB_IMPRECISE_ERROR_PENDING , 34 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PIB_IMPRECISE_ERROR_PENDING ); REG64_FLD( EQ_CME_SCOM_XISIB_PIB_RSP_INFO , 49 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PIB_RSP_INFO ); REG64_FLD( EQ_CME_SCOM_XISIB_PIB_RSP_INFO_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PIB_RSP_INFO_LEN ); REG64_FLD( EQ_CME_SCOM_XISIB_PIB_IFETCH_PENDING , 62 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PIB_IFETCH_PENDING ); REG64_FLD( EQ_CME_SCOM_XISIB_PIB_DATAOP_PENDING , 63 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PIB_DATAOP_PENDING ); REG64_FLD( EX_CME_SCOM_XISIB_PIB_ADDR , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PIB_ADDR ); REG64_FLD( EX_CME_SCOM_XISIB_PIB_ADDR_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PIB_ADDR_LEN ); REG64_FLD( EX_CME_SCOM_XISIB_PIB_R_NW , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PIB_R_NW ); REG64_FLD( EX_CME_SCOM_XISIB_PIB_BUSY , 33 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PIB_BUSY ); REG64_FLD( EX_CME_SCOM_XISIB_PIB_IMPRECISE_ERROR_PENDING , 34 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PIB_IMPRECISE_ERROR_PENDING ); REG64_FLD( EX_CME_SCOM_XISIB_PIB_RSP_INFO , 49 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PIB_RSP_INFO ); REG64_FLD( EX_CME_SCOM_XISIB_PIB_RSP_INFO_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PIB_RSP_INFO_LEN ); REG64_FLD( EX_CME_SCOM_XISIB_PIB_IFETCH_PENDING , 62 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PIB_IFETCH_PENDING ); REG64_FLD( EX_CME_SCOM_XISIB_PIB_DATAOP_PENDING , 63 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PIB_DATAOP_PENDING ); REG64_FLD( EQ_CONTROL_REG_RESET_TRIP_HISTORY , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RESET_TRIP_HISTORY ); REG64_FLD( EQ_CONTROL_REG_RESET_SAMPLE_PULSE_CNT , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RESET_SAMPLE_PULSE_CNT ); REG64_FLD( EQ_CONTROL_REG_F_RESET_CPM_RD , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_F_RESET_CPM_RD ); REG64_FLD( EQ_CONTROL_REG_F_RESET_CPM_WR , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_F_RESET_CPM_WR ); REG64_FLD( EQ_CONTROL_REG_RESET_SAMPLE_DTS , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RESET_SAMPLE_DTS ); REG64_FLD( EQ_CONTROL_REG_FORCE_SAMPLE_DTS , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FORCE_SAMPLE_DTS ); REG64_FLD( EQ_CONTROL_REG_FORCE_SAMPLE_DTS_INTERRUPTIBLE , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FORCE_SAMPLE_DTS_INTERRUPTIBLE ); REG64_FLD( EQ_CONTROL_REG_FORCE_RESET_THRES_L1RESULTS , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FORCE_RESET_THRES_L1RESULTS ); REG64_FLD( EQ_CONTROL_REG_FORCE_RESET_THRES_L2RESULTS , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FORCE_RESET_THRES_L2RESULTS ); REG64_FLD( EQ_CONTROL_REG_FORCE_RESET_THRES_L3RESULTS , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FORCE_RESET_THRES_L3RESULTS ); REG64_FLD( EQ_CONTROL_REG_FORCE_MEASURE_VOLT_INTERRUPTIBLE , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FORCE_MEASURE_VOLT_INTERRUPTIBLE ); REG64_FLD( EQ_CONTROL_REG_FORCE_RESET_MEASURE_VOLT , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FORCE_RESET_MEASURE_VOLT ); REG64_FLD( EQ_CONTROL_REG_FORCE_SHIFT_SENSOR , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FORCE_SHIFT_SENSOR ); REG64_FLD( EX_CONTROL_REG_RESET_TRIP_HISTORY , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESET_TRIP_HISTORY ); REG64_FLD( EX_CONTROL_REG_RESET_SAMPLE_PULSE_CNT , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESET_SAMPLE_PULSE_CNT ); REG64_FLD( EX_CONTROL_REG_F_RESET_CPM_RD , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_F_RESET_CPM_RD ); REG64_FLD( EX_CONTROL_REG_F_RESET_CPM_WR , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_F_RESET_CPM_WR ); REG64_FLD( EX_CONTROL_REG_RESET_SAMPLE_DTS , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESET_SAMPLE_DTS ); REG64_FLD( EX_CONTROL_REG_FORCE_SAMPLE_DTS , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FORCE_SAMPLE_DTS ); REG64_FLD( EX_CONTROL_REG_FORCE_SAMPLE_DTS_INTERRUPTIBLE , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FORCE_SAMPLE_DTS_INTERRUPTIBLE ); REG64_FLD( EX_CONTROL_REG_FORCE_RESET_THRES_L1RESULTS , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FORCE_RESET_THRES_L1RESULTS ); REG64_FLD( EX_CONTROL_REG_FORCE_RESET_THRES_L2RESULTS , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FORCE_RESET_THRES_L2RESULTS ); REG64_FLD( EX_CONTROL_REG_FORCE_RESET_THRES_L3RESULTS , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FORCE_RESET_THRES_L3RESULTS ); REG64_FLD( EX_CONTROL_REG_FORCE_MEASURE_VOLT_INTERRUPTIBLE , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FORCE_MEASURE_VOLT_INTERRUPTIBLE ); REG64_FLD( EX_CONTROL_REG_FORCE_RESET_MEASURE_VOLT , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FORCE_RESET_MEASURE_VOLT ); REG64_FLD( EX_CONTROL_REG_FORCE_SHIFT_SENSOR , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FORCE_SHIFT_SENSOR ); REG64_FLD( C_CONTROL_REG_RESET_TRIP_HISTORY , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESET_TRIP_HISTORY ); REG64_FLD( C_CONTROL_REG_RESET_SAMPLE_PULSE_CNT , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESET_SAMPLE_PULSE_CNT ); REG64_FLD( C_CONTROL_REG_F_RESET_CPM_RD , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_F_RESET_CPM_RD ); REG64_FLD( C_CONTROL_REG_F_RESET_CPM_WR , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_F_RESET_CPM_WR ); REG64_FLD( C_CONTROL_REG_RESET_SAMPLE_DTS , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESET_SAMPLE_DTS ); REG64_FLD( C_CONTROL_REG_FORCE_SAMPLE_DTS , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FORCE_SAMPLE_DTS ); REG64_FLD( C_CONTROL_REG_FORCE_SAMPLE_DTS_INTERRUPTIBLE , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FORCE_SAMPLE_DTS_INTERRUPTIBLE ); REG64_FLD( C_CONTROL_REG_FORCE_RESET_THRES_L1RESULTS , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FORCE_RESET_THRES_L1RESULTS ); REG64_FLD( C_CONTROL_REG_FORCE_RESET_THRES_L2RESULTS , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FORCE_RESET_THRES_L2RESULTS ); REG64_FLD( C_CONTROL_REG_FORCE_RESET_THRES_L3RESULTS , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FORCE_RESET_THRES_L3RESULTS ); REG64_FLD( C_CONTROL_REG_FORCE_MEASURE_VOLT_INTERRUPTIBLE , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FORCE_MEASURE_VOLT_INTERRUPTIBLE ); REG64_FLD( C_CONTROL_REG_FORCE_RESET_MEASURE_VOLT , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FORCE_RESET_MEASURE_VOLT ); REG64_FLD( C_CONTROL_REG_FORCE_SHIFT_SENSOR , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FORCE_SHIFT_SENSOR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_IF_SRAM_REC_ERROR , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_IF_SRAM_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_TC_FIR_XSTOP_ERROR , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_TC_FIR_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_IF_RFILE_REC_ERROR , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_IF_RFILE_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_IF_RFILE_XSTOP_ERROR , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_IF_RFILE_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_IF_LOG_REC_ERROR , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_IF_LOG_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_IF_LOG_XSTOP_ERROR , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_IF_LOG_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_6 , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_6 ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_7 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_7 ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_RECOV_XSTOP_ERROR , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_RECOV_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_SD_RFILE_REC_ERROR , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_RFILE_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_SD_RFILE_XSTOP_ERROR , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_RFILE_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_SD_LOG_REC_ERROR , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_LOG_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_SD_LOG_XSTOP_ERROR , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_LOG_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_SD_NOT_MT_CI_REC_ERROR , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_NOT_MT_CI_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_SD_MCHK_AND_ME_EQ_0_ERROR , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_MCHK_AND_ME_EQ_0_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_SD_L2_UE_ERROR , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_L2_UE_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_SD_L2_UE_OVER_THRES_ERROR , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_L2_UE_OVER_THRES_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_SD_CI_UE_ERROR , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_CI_UE_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_18 , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_18 ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_19 , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_19 ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_SD_SYS_XSTOP_ERROR , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_SYS_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_21 , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_21 ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_22 , 22 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_22 ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_23 , 23 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_23 ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_VS_LOG_REC_ERROR , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_VS_LOG_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_VS_LOG_XSTOP_ERROR , 25 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_VS_LOG_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_RECOV_IN_MAINT_ERROR , 26 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_RECOV_IN_MAINT_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_VS_DU_LOG_REC_ERROR , 27 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_VS_DU_LOG_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_SYS_XSTOP_ERROR , 28 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_SYS_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_SRAM_PARITY_ERROR , 29 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_SRAM_PARITY_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_SETDELETE_ERROR , 30 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_SETDELETE_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_RFILE_REC_ERROR , 31 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_RFILE_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_RFILE_XSTOP_ERROR , 32 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_RFILE_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_TLB_MULTIHIT_ERROR , 33 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_TLB_MULTIHIT_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_SLB_MULTIHIT_ERROR , 34 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_SLB_MULTIHIT_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_DERAT_MULTIHIT_ERROR , 35 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_DERAT_MULTIHIT_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_FWD_PROGRESS_ERROR , 36 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_FWD_PROGRESS_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_LOG_REC_ERROR , 37 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_LOG_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_LOG_XSTOP_ERROR , 38 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_LOG_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_NOT_MT_REC_ERROR , 39 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_NOT_MT_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_40 , 40 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_40 ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_LS_SYS_XSTOP_ERROR , 41 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_SYS_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_42 , 42 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_42 ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_THREAD_HANG_REC_ERROR , 43 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_THREAD_HANG_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_44 , 44 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_44 ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_LOG_XSTOP_ERROR , 45 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_LOG_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_46 , 46 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_46 ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_TFAC_XSTOP_ERROR , 47 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_TFAC_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_HYP_RES_ERROR , 48 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_HYP_RES_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_49 , 49 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_49 ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_50 , 50 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_50 ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_51 , 51 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_51 ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_HANG_RECOVERY_FAILED , 52 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_HANG_RECOVERY_FAILED ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_HANG_DETECT_ERROR , 53 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_HANG_DETECT_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_UNUSED_54 , 54 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_54 ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_NEST_HANG_DETECT_ERROR , 55 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_NEST_HANG_DETECT_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_OTHER_CHIPLET_REC_ERROR , 56 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_OTHER_CHIPLET_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_OTHER_CHIPLET_XSTOP_ERROR , 57 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_OTHER_CHIPLET_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR , 58 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_SCOM_ERROR , 59 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_SCOM_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_XSTOP_ON_DBG_TRIGGER_ERROR , 60 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_XSTOP_ON_DBG_TRIGGER_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_FW_INJ_REC_ERROR , 61 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_FW_INJ_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_FW_INJ_XSTOP_ERROR , 62 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_FW_INJ_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION0_ACTION_PC_PHYP_XSTOP_ERROR , 63 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_PHYP_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_IF_SRAM_REC_ERROR , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_IF_SRAM_REC_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_TC_FIR_XSTOP_ERROR , 1 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_TC_FIR_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_IF_RFILE_REC_ERROR , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_IF_RFILE_REC_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_IF_RFILE_XSTOP_ERROR , 3 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_IF_RFILE_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_IF_LOG_REC_ERROR , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_IF_LOG_REC_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_IF_LOG_XSTOP_ERROR , 5 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_IF_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_6 , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_6 ); REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_7 , 7 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_7 ); REG64_FLD( C_CORE_ACTION0_ACTION_PC_RECOV_XSTOP_ERROR , 8 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_RECOV_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_SD_RFILE_REC_ERROR , 9 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_RFILE_REC_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_SD_RFILE_XSTOP_ERROR , 10 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_RFILE_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_SD_LOG_REC_ERROR , 11 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_LOG_REC_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_SD_LOG_XSTOP_ERROR , 12 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_SD_NOT_MT_CI_REC_ERROR , 13 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_NOT_MT_CI_REC_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_SD_MCHK_AND_ME_EQ_0_ERROR , 14 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_MCHK_AND_ME_EQ_0_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_SD_L2_UE_ERROR , 15 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_L2_UE_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_SD_L2_UE_OVER_THRES_ERROR , 16 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_L2_UE_OVER_THRES_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_SD_CI_UE_ERROR , 17 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_CI_UE_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_18 , 18 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_18 ); REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_19 , 19 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_19 ); REG64_FLD( C_CORE_ACTION0_ACTION_SD_SYS_XSTOP_ERROR , 20 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_SYS_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_21 , 21 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_21 ); REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_22 , 22 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_22 ); REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_23 , 23 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_23 ); REG64_FLD( C_CORE_ACTION0_ACTION_VS_LOG_REC_ERROR , 24 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_VS_LOG_REC_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_VS_LOG_XSTOP_ERROR , 25 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_VS_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_PC_RECOV_IN_MAINT_ERROR , 26 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_RECOV_IN_MAINT_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_VS_DU_LOG_REC_ERROR , 27 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_VS_DU_LOG_REC_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_PC_SYS_XSTOP_ERROR , 28 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_SYS_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_LS_SRAM_PARITY_ERROR , 29 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_SRAM_PARITY_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_LS_SETDELETE_ERROR , 30 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_SETDELETE_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_LS_RFILE_REC_ERROR , 31 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_RFILE_REC_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_LS_RFILE_XSTOP_ERROR , 32 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_RFILE_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_LS_TLB_MULTIHIT_ERROR , 33 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_TLB_MULTIHIT_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_LS_SLB_MULTIHIT_ERROR , 34 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_SLB_MULTIHIT_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_LS_DERAT_MULTIHIT_ERROR , 35 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_DERAT_MULTIHIT_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_PC_FWD_PROGRESS_ERROR , 36 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_FWD_PROGRESS_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_LS_LOG_REC_ERROR , 37 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_LOG_REC_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_LS_LOG_XSTOP_ERROR , 38 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_LS_NOT_MT_REC_ERROR , 39 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_NOT_MT_REC_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_40 , 40 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_40 ); REG64_FLD( C_CORE_ACTION0_ACTION_LS_SYS_XSTOP_ERROR , 41 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_SYS_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_42 , 42 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_42 ); REG64_FLD( C_CORE_ACTION0_ACTION_PC_THREAD_HANG_REC_ERROR , 43 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_THREAD_HANG_REC_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_44 , 44 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_44 ); REG64_FLD( C_CORE_ACTION0_ACTION_PC_LOG_XSTOP_ERROR , 45 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_46 , 46 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_46 ); REG64_FLD( C_CORE_ACTION0_ACTION_PC_TFAC_XSTOP_ERROR , 47 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_TFAC_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_PC_HYP_RES_ERROR , 48 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_HYP_RES_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_49 , 49 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_49 ); REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_50 , 50 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_50 ); REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_51 , 51 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_51 ); REG64_FLD( C_CORE_ACTION0_ACTION_PC_HANG_RECOVERY_FAILED , 52 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_HANG_RECOVERY_FAILED ); REG64_FLD( C_CORE_ACTION0_ACTION_PC_HANG_DETECT_ERROR , 53 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_HANG_DETECT_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_UNUSED_54 , 54 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_54 ); REG64_FLD( C_CORE_ACTION0_ACTION_PC_NEST_HANG_DETECT_ERROR , 55 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_NEST_HANG_DETECT_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_PC_OTHER_CHIPLET_REC_ERROR , 56 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_OTHER_CHIPLET_REC_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_PC_OTHER_CHIPLET_XSTOP_ERROR , 57 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_OTHER_CHIPLET_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR , 58 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_PC_SCOM_ERROR , 59 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_SCOM_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_PC_XSTOP_ON_DBG_TRIGGER_ERROR , 60 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_XSTOP_ON_DBG_TRIGGER_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_PC_FW_INJ_REC_ERROR , 61 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_FW_INJ_REC_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_PC_FW_INJ_XSTOP_ERROR , 62 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_FW_INJ_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION0_ACTION_PC_PHYP_XSTOP_ERROR , 63 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_PHYP_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_IF_SRAM_REC_ERROR , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_IF_SRAM_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_TC_FIR_XSTOP_ERROR , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_TC_FIR_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_IF_RFILE_REC_ERROR , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_IF_RFILE_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_IF_RFILE_XSTOP_ERROR , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_IF_RFILE_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_IF_LOG_REC_ERROR , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_IF_LOG_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_IF_LOG_XSTOP_ERROR , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_IF_LOG_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_6 , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_6 ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_7 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_7 ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_RECOV_XSTOP_ERROR , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_RECOV_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_SD_RFILE_REC_ERROR , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_RFILE_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_SD_RFILE_XSTOP_ERROR , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_RFILE_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_SD_LOG_REC_ERROR , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_LOG_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_SD_LOG_XSTOP_ERROR , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_LOG_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_SD_NOT_MT_CI_REC_ERROR , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_NOT_MT_CI_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_SD_MCHK_AND_ME_EQ_0_ERROR , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_MCHK_AND_ME_EQ_0_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_SD_L2_UE_ERROR , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_L2_UE_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_SD_L2_UE_OVER_THRES_ERROR , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_L2_UE_OVER_THRES_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_SD_CI_UE_ERROR , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_CI_UE_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_18 , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_18 ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_19 , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_19 ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_SD_SYS_XSTOP_ERROR , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_SYS_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_21 , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_21 ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_22 , 22 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_22 ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_23 , 23 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_23 ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_VS_LOG_REC_ERROR , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_VS_LOG_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_VS_LOG_XSTOP_ERROR , 25 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_VS_LOG_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_RECOV_IN_MAINT_ERROR , 26 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_RECOV_IN_MAINT_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_VS_DU_LOG_REC_ERROR , 27 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_VS_DU_LOG_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_SYS_XSTOP_ERROR , 28 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_SYS_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_SRAM_PARITY_ERROR , 29 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_SRAM_PARITY_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_SETDELETE_ERROR , 30 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_SETDELETE_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_RFILE_REC_ERROR , 31 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_RFILE_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_RFILE_XSTOP_ERROR , 32 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_RFILE_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_TLB_MULTIHIT_ERROR , 33 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_TLB_MULTIHIT_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_SLB_MULTIHIT_ERROR , 34 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_SLB_MULTIHIT_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_DERAT_MULTIHIT_ERROR , 35 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_DERAT_MULTIHIT_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_FWD_PROGRESS_ERROR , 36 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_FWD_PROGRESS_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_LOG_REC_ERROR , 37 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_LOG_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_LOG_XSTOP_ERROR , 38 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_LOG_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_NOT_MT_REC_ERROR , 39 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_NOT_MT_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_40 , 40 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_40 ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_LS_SYS_XSTOP_ERROR , 41 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_SYS_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_42 , 42 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_42 ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_THREAD_HANG_REC_ERROR , 43 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_THREAD_HANG_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_44 , 44 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_44 ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_LOG_XSTOP_ERROR , 45 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_LOG_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_46 , 46 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_46 ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_TFAC_XSTOP_ERROR , 47 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_TFAC_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_HYP_RES_ERROR , 48 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_HYP_RES_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_49 , 49 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_49 ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_50 , 50 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_50 ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_51 , 51 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_51 ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_HANG_RECOVERY_FAILED , 52 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_HANG_RECOVERY_FAILED ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_HANG_DETECT_ERROR , 53 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_HANG_DETECT_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_UNUSED_54 , 54 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_54 ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_NEST_HANG_DETECT_ERROR , 55 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_NEST_HANG_DETECT_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_OTHER_CHIPLET_REC_ERROR , 56 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_OTHER_CHIPLET_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_OTHER_CHIPLET_XSTOP_ERROR , 57 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_OTHER_CHIPLET_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR , 58 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_SCOM_ERROR , 59 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_SCOM_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_XSTOP_ON_DBG_TRIGGER_ERROR , 60 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_XSTOP_ON_DBG_TRIGGER_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_FW_INJ_REC_ERROR , 61 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_FW_INJ_REC_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_FW_INJ_XSTOP_ERROR , 62 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_FW_INJ_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_ACTION1_ACTION_PC_PHYP_XSTOP_ERROR , 63 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_PHYP_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_IF_SRAM_REC_ERROR , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_IF_SRAM_REC_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_TC_FIR_XSTOP_ERROR , 1 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_TC_FIR_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_IF_RFILE_REC_ERROR , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_IF_RFILE_REC_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_IF_RFILE_XSTOP_ERROR , 3 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_IF_RFILE_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_IF_LOG_REC_ERROR , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_IF_LOG_REC_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_IF_LOG_XSTOP_ERROR , 5 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_IF_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_6 , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_6 ); REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_7 , 7 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_7 ); REG64_FLD( C_CORE_ACTION1_ACTION_PC_RECOV_XSTOP_ERROR , 8 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_RECOV_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_SD_RFILE_REC_ERROR , 9 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_RFILE_REC_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_SD_RFILE_XSTOP_ERROR , 10 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_RFILE_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_SD_LOG_REC_ERROR , 11 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_LOG_REC_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_SD_LOG_XSTOP_ERROR , 12 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_SD_NOT_MT_CI_REC_ERROR , 13 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_NOT_MT_CI_REC_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_SD_MCHK_AND_ME_EQ_0_ERROR , 14 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_MCHK_AND_ME_EQ_0_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_SD_L2_UE_ERROR , 15 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_L2_UE_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_SD_L2_UE_OVER_THRES_ERROR , 16 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_L2_UE_OVER_THRES_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_SD_CI_UE_ERROR , 17 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_CI_UE_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_18 , 18 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_18 ); REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_19 , 19 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_19 ); REG64_FLD( C_CORE_ACTION1_ACTION_SD_SYS_XSTOP_ERROR , 20 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_SD_SYS_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_21 , 21 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_21 ); REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_22 , 22 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_22 ); REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_23 , 23 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_23 ); REG64_FLD( C_CORE_ACTION1_ACTION_VS_LOG_REC_ERROR , 24 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_VS_LOG_REC_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_VS_LOG_XSTOP_ERROR , 25 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_VS_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_PC_RECOV_IN_MAINT_ERROR , 26 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_RECOV_IN_MAINT_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_VS_DU_LOG_REC_ERROR , 27 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_VS_DU_LOG_REC_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_PC_SYS_XSTOP_ERROR , 28 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_SYS_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_LS_SRAM_PARITY_ERROR , 29 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_SRAM_PARITY_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_LS_SETDELETE_ERROR , 30 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_SETDELETE_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_LS_RFILE_REC_ERROR , 31 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_RFILE_REC_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_LS_RFILE_XSTOP_ERROR , 32 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_RFILE_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_LS_TLB_MULTIHIT_ERROR , 33 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_TLB_MULTIHIT_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_LS_SLB_MULTIHIT_ERROR , 34 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_SLB_MULTIHIT_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_LS_DERAT_MULTIHIT_ERROR , 35 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_DERAT_MULTIHIT_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_PC_FWD_PROGRESS_ERROR , 36 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_FWD_PROGRESS_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_LS_LOG_REC_ERROR , 37 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_LOG_REC_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_LS_LOG_XSTOP_ERROR , 38 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_LS_NOT_MT_REC_ERROR , 39 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_NOT_MT_REC_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_40 , 40 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_40 ); REG64_FLD( C_CORE_ACTION1_ACTION_LS_SYS_XSTOP_ERROR , 41 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_LS_SYS_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_42 , 42 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_42 ); REG64_FLD( C_CORE_ACTION1_ACTION_PC_THREAD_HANG_REC_ERROR , 43 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_THREAD_HANG_REC_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_44 , 44 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_44 ); REG64_FLD( C_CORE_ACTION1_ACTION_PC_LOG_XSTOP_ERROR , 45 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_46 , 46 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_46 ); REG64_FLD( C_CORE_ACTION1_ACTION_PC_TFAC_XSTOP_ERROR , 47 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_TFAC_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_PC_HYP_RES_ERROR , 48 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_HYP_RES_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_49 , 49 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_49 ); REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_50 , 50 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_50 ); REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_51 , 51 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_51 ); REG64_FLD( C_CORE_ACTION1_ACTION_PC_HANG_RECOVERY_FAILED , 52 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_HANG_RECOVERY_FAILED ); REG64_FLD( C_CORE_ACTION1_ACTION_PC_HANG_DETECT_ERROR , 53 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_HANG_DETECT_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_UNUSED_54 , 54 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_UNUSED_54 ); REG64_FLD( C_CORE_ACTION1_ACTION_PC_NEST_HANG_DETECT_ERROR , 55 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_NEST_HANG_DETECT_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_PC_OTHER_CHIPLET_REC_ERROR , 56 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_OTHER_CHIPLET_REC_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_PC_OTHER_CHIPLET_XSTOP_ERROR , 57 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_OTHER_CHIPLET_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR , 58 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_PC_SCOM_ERROR , 59 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_SCOM_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_PC_XSTOP_ON_DBG_TRIGGER_ERROR , 60 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_XSTOP_ON_DBG_TRIGGER_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_PC_FW_INJ_REC_ERROR , 61 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_FW_INJ_REC_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_PC_FW_INJ_XSTOP_ERROR , 62 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_FW_INJ_XSTOP_ERROR ); REG64_FLD( C_CORE_ACTION1_ACTION_PC_PHYP_XSTOP_ERROR , 63 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTION_PC_PHYP_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIR_IF_SRAM_REC_ERROR , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_IF_SRAM_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIR_TC_FIR_XSTOP_ERROR , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_TC_FIR_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIR_IF_RFILE_REC_ERROR , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_IF_RFILE_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIR_IF_RFILE_XSTOP_ERROR , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_IF_RFILE_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIR_IF_LOG_REC_ERROR , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_IF_LOG_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIR_IF_LOG_XSTOP_ERROR , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_IF_LOG_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIR_UNUSED_6 , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_6 ); REG64_FLD( EX_L2_CORE_FIR_UNUSED_7 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_7 ); REG64_FLD( EX_L2_CORE_FIR_PC_RECOV_XSTOP_ERROR , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PC_RECOV_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIR_SD_RFILE_REC_ERROR , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SD_RFILE_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIR_SD_RFILE_XSTOP_ERROR , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SD_RFILE_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIR_SD_LOG_REC_ERROR , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SD_LOG_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIR_SD_LOG_XSTOP_ERROR , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SD_LOG_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIR_SD_NOT_MT_CI_REC_ERROR , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SD_NOT_MT_CI_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIR_SD_MCHK_AND_ME_EQ_0_ERROR , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SD_MCHK_AND_ME_EQ_0_ERROR ); REG64_FLD( EX_L2_CORE_FIR_SD_L2_UE_ERROR , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SD_L2_UE_ERROR ); REG64_FLD( EX_L2_CORE_FIR_SD_L2_UE_OVER_THRES_ERROR , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SD_L2_UE_OVER_THRES_ERROR ); REG64_FLD( EX_L2_CORE_FIR_SD_CI_UE_ERROR , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SD_CI_UE_ERROR ); REG64_FLD( EX_L2_CORE_FIR_UNUSED_18 , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_18 ); REG64_FLD( EX_L2_CORE_FIR_UNUSED_19 , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_19 ); REG64_FLD( EX_L2_CORE_FIR_SD_SYS_XSTOP_ERROR , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SD_SYS_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIR_UNUSED_21 , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_21 ); REG64_FLD( EX_L2_CORE_FIR_UNUSED_22 , 22 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_22 ); REG64_FLD( EX_L2_CORE_FIR_UNUSED_23 , 23 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_23 ); REG64_FLD( EX_L2_CORE_FIR_VS_LOG_REC_ERROR , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_VS_LOG_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIR_VS_LOG_XSTOP_ERROR , 25 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_VS_LOG_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIR_PC_RECOV_IN_MAINT_ERROR , 26 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PC_RECOV_IN_MAINT_ERROR ); REG64_FLD( EX_L2_CORE_FIR_VS_DU_LOG_REC_ERROR , 27 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_VS_DU_LOG_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIR_PC_SYS_XSTOP_ERROR , 28 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PC_SYS_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIR_LS_SRAM_PARITY_ERROR , 29 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LS_SRAM_PARITY_ERROR ); REG64_FLD( EX_L2_CORE_FIR_LS_SETDELETE_ERROR , 30 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LS_SETDELETE_ERROR ); REG64_FLD( EX_L2_CORE_FIR_LS_RFILE_REC_ERROR , 31 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LS_RFILE_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIR_LS_RFILE_XSTOP_ERROR , 32 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LS_RFILE_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIR_LS_TLB_MULTIHIT_ERROR , 33 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LS_TLB_MULTIHIT_ERROR ); REG64_FLD( EX_L2_CORE_FIR_LS_SLB_MULTIHIT_ERROR , 34 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LS_SLB_MULTIHIT_ERROR ); REG64_FLD( EX_L2_CORE_FIR_LS_DERAT_MULTIHIT_ERROR , 35 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LS_DERAT_MULTIHIT_ERROR ); REG64_FLD( EX_L2_CORE_FIR_PC_FWD_PROGRESS_ERROR , 36 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PC_FWD_PROGRESS_ERROR ); REG64_FLD( EX_L2_CORE_FIR_LS_LOG_REC_ERROR , 37 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LS_LOG_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIR_LS_LOG_XSTOP_ERROR , 38 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LS_LOG_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIR_LS_NOT_MT_REC_ERROR , 39 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LS_NOT_MT_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIR_UNUSED_40 , 40 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_40 ); REG64_FLD( EX_L2_CORE_FIR_LS_SYS_XSTOP_ERROR , 41 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LS_SYS_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIR_UNUSED_42 , 42 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_42 ); REG64_FLD( EX_L2_CORE_FIR_PC_THREAD_HANG_REC_ERROR , 43 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PC_THREAD_HANG_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIR_UNUSED_44 , 44 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_44 ); REG64_FLD( EX_L2_CORE_FIR_PC_LOG_XSTOP_ERROR , 45 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PC_LOG_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIR_UNUSED_46 , 46 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_46 ); REG64_FLD( EX_L2_CORE_FIR_PC_TFAC_XSTOP_ERROR , 47 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PC_TFAC_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIR_PC_HYP_RES_ERROR , 48 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PC_HYP_RES_ERROR ); REG64_FLD( EX_L2_CORE_FIR_UNUSED_49 , 49 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_49 ); REG64_FLD( EX_L2_CORE_FIR_UNUSED_50 , 50 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_50 ); REG64_FLD( EX_L2_CORE_FIR_UNUSED_51 , 51 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_51 ); REG64_FLD( EX_L2_CORE_FIR_PC_HANG_RECOVERY_FAILED , 52 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PC_HANG_RECOVERY_FAILED ); REG64_FLD( EX_L2_CORE_FIR_PC_CORE_HANG_DETECT_ERROR , 53 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PC_CORE_HANG_DETECT_ERROR ); REG64_FLD( EX_L2_CORE_FIR_UNUSED_54 , 54 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_54 ); REG64_FLD( EX_L2_CORE_FIR_PC_NEST_HANG_DETECT_ERROR , 55 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PC_NEST_HANG_DETECT_ERROR ); REG64_FLD( EX_L2_CORE_FIR_PC_OTHER_CORE_CHIPLET_REC_ERROR , 56 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PC_OTHER_CORE_CHIPLET_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIR_PC_OTHER_CORE_CHIPLET_XSTOP_ERROR , 57 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PC_OTHER_CORE_CHIPLET_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIR_PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR , 58 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIR_PC_SCOM_ERROR , 59 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PC_SCOM_ERROR ); REG64_FLD( EX_L2_CORE_FIR_PC_XSTOP_ON_DBG_TRIGGER_ERROR , 60 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PC_XSTOP_ON_DBG_TRIGGER_ERROR ); REG64_FLD( EX_L2_CORE_FIR_PC_FW_INJ_REC_ERROR , 61 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PC_FW_INJ_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIR_PC_FW_INJ_XSTOP_ERROR , 62 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PC_FW_INJ_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIR_PC_PHYP_XSTOP_ERROR , 63 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PC_PHYP_XSTOP_ERROR ); REG64_FLD( C_CORE_FIR_IF_SRAM_REC_ERROR , 0 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IF_SRAM_REC_ERROR ); REG64_FLD( C_CORE_FIR_TC_FIR_XSTOP_ERROR , 1 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TC_FIR_XSTOP_ERROR ); REG64_FLD( C_CORE_FIR_IF_RFILE_REC_ERROR , 2 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IF_RFILE_REC_ERROR ); REG64_FLD( C_CORE_FIR_IF_RFILE_XSTOP_ERROR , 3 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IF_RFILE_XSTOP_ERROR ); REG64_FLD( C_CORE_FIR_IF_LOG_REC_ERROR , 4 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IF_LOG_REC_ERROR ); REG64_FLD( C_CORE_FIR_IF_LOG_XSTOP_ERROR , 5 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IF_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_FIR_UNUSED_6 , 6 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_6 ); REG64_FLD( C_CORE_FIR_UNUSED_7 , 7 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_7 ); REG64_FLD( C_CORE_FIR_PC_RECOV_XSTOP_ERROR , 8 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PC_RECOV_XSTOP_ERROR ); REG64_FLD( C_CORE_FIR_SD_RFILE_REC_ERROR , 9 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SD_RFILE_REC_ERROR ); REG64_FLD( C_CORE_FIR_SD_RFILE_XSTOP_ERROR , 10 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SD_RFILE_XSTOP_ERROR ); REG64_FLD( C_CORE_FIR_SD_LOG_REC_ERROR , 11 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SD_LOG_REC_ERROR ); REG64_FLD( C_CORE_FIR_SD_LOG_XSTOP_ERROR , 12 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SD_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_FIR_SD_NOT_MT_CI_REC_ERROR , 13 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SD_NOT_MT_CI_REC_ERROR ); REG64_FLD( C_CORE_FIR_SD_MCHK_AND_ME_EQ_0_ERROR , 14 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SD_MCHK_AND_ME_EQ_0_ERROR ); REG64_FLD( C_CORE_FIR_SD_L2_UE_ERROR , 15 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SD_L2_UE_ERROR ); REG64_FLD( C_CORE_FIR_SD_L2_UE_OVER_THRES_ERROR , 16 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SD_L2_UE_OVER_THRES_ERROR ); REG64_FLD( C_CORE_FIR_SD_CI_UE_ERROR , 17 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SD_CI_UE_ERROR ); REG64_FLD( C_CORE_FIR_UNUSED_18 , 18 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_18 ); REG64_FLD( C_CORE_FIR_UNUSED_19 , 19 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_19 ); REG64_FLD( C_CORE_FIR_SD_SYS_XSTOP_ERROR , 20 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SD_SYS_XSTOP_ERROR ); REG64_FLD( C_CORE_FIR_UNUSED_21 , 21 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_21 ); REG64_FLD( C_CORE_FIR_UNUSED_22 , 22 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_22 ); REG64_FLD( C_CORE_FIR_UNUSED_23 , 23 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_23 ); REG64_FLD( C_CORE_FIR_VS_LOG_REC_ERROR , 24 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_VS_LOG_REC_ERROR ); REG64_FLD( C_CORE_FIR_VS_LOG_XSTOP_ERROR , 25 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_VS_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_FIR_PC_RECOV_IN_MAINT_ERROR , 26 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PC_RECOV_IN_MAINT_ERROR ); REG64_FLD( C_CORE_FIR_VS_DU_LOG_REC_ERROR , 27 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_VS_DU_LOG_REC_ERROR ); REG64_FLD( C_CORE_FIR_PC_SYS_XSTOP_ERROR , 28 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PC_SYS_XSTOP_ERROR ); REG64_FLD( C_CORE_FIR_LS_SRAM_PARITY_ERROR , 29 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_LS_SRAM_PARITY_ERROR ); REG64_FLD( C_CORE_FIR_LS_SETDELETE_ERROR , 30 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_LS_SETDELETE_ERROR ); REG64_FLD( C_CORE_FIR_LS_RFILE_REC_ERROR , 31 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_LS_RFILE_REC_ERROR ); REG64_FLD( C_CORE_FIR_LS_RFILE_XSTOP_ERROR , 32 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_LS_RFILE_XSTOP_ERROR ); REG64_FLD( C_CORE_FIR_LS_TLB_MULTIHIT_ERROR , 33 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_LS_TLB_MULTIHIT_ERROR ); REG64_FLD( C_CORE_FIR_LS_SLB_MULTIHIT_ERROR , 34 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_LS_SLB_MULTIHIT_ERROR ); REG64_FLD( C_CORE_FIR_LS_DERAT_MULTIHIT_ERROR , 35 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_LS_DERAT_MULTIHIT_ERROR ); REG64_FLD( C_CORE_FIR_PC_FWD_PROGRESS_ERROR , 36 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PC_FWD_PROGRESS_ERROR ); REG64_FLD( C_CORE_FIR_LS_LOG_REC_ERROR , 37 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_LS_LOG_REC_ERROR ); REG64_FLD( C_CORE_FIR_LS_LOG_XSTOP_ERROR , 38 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_LS_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_FIR_LS_NOT_MT_REC_ERROR , 39 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_LS_NOT_MT_REC_ERROR ); REG64_FLD( C_CORE_FIR_UNUSED_40 , 40 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_40 ); REG64_FLD( C_CORE_FIR_LS_SYS_XSTOP_ERROR , 41 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_LS_SYS_XSTOP_ERROR ); REG64_FLD( C_CORE_FIR_UNUSED_42 , 42 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_42 ); REG64_FLD( C_CORE_FIR_PC_THREAD_HANG_REC_ERROR , 43 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PC_THREAD_HANG_REC_ERROR ); REG64_FLD( C_CORE_FIR_UNUSED_44 , 44 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_44 ); REG64_FLD( C_CORE_FIR_PC_LOG_XSTOP_ERROR , 45 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PC_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_FIR_UNUSED_46 , 46 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_46 ); REG64_FLD( C_CORE_FIR_PC_TFAC_XSTOP_ERROR , 47 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PC_TFAC_XSTOP_ERROR ); REG64_FLD( C_CORE_FIR_PC_HYP_RES_ERROR , 48 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PC_HYP_RES_ERROR ); REG64_FLD( C_CORE_FIR_UNUSED_49 , 49 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_49 ); REG64_FLD( C_CORE_FIR_UNUSED_50 , 50 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_50 ); REG64_FLD( C_CORE_FIR_UNUSED_51 , 51 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_51 ); REG64_FLD( C_CORE_FIR_PC_HANG_RECOVERY_FAILED , 52 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PC_HANG_RECOVERY_FAILED ); REG64_FLD( C_CORE_FIR_PC_CORE_HANG_DETECT_ERROR , 53 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PC_CORE_HANG_DETECT_ERROR ); REG64_FLD( C_CORE_FIR_UNUSED_54 , 54 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_UNUSED_54 ); REG64_FLD( C_CORE_FIR_PC_NEST_HANG_DETECT_ERROR , 55 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PC_NEST_HANG_DETECT_ERROR ); REG64_FLD( C_CORE_FIR_PC_OTHER_CORE_CHIPLET_REC_ERROR , 56 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PC_OTHER_CORE_CHIPLET_REC_ERROR ); REG64_FLD( C_CORE_FIR_PC_OTHER_CORE_CHIPLET_XSTOP_ERROR , 57 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PC_OTHER_CORE_CHIPLET_XSTOP_ERROR ); REG64_FLD( C_CORE_FIR_PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR , 58 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR ); REG64_FLD( C_CORE_FIR_PC_SCOM_ERROR , 59 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PC_SCOM_ERROR ); REG64_FLD( C_CORE_FIR_PC_XSTOP_ON_DBG_TRIGGER_ERROR , 60 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PC_XSTOP_ON_DBG_TRIGGER_ERROR ); REG64_FLD( C_CORE_FIR_PC_FW_INJ_REC_ERROR , 61 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PC_FW_INJ_REC_ERROR ); REG64_FLD( C_CORE_FIR_PC_FW_INJ_XSTOP_ERROR , 62 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PC_FW_INJ_XSTOP_ERROR ); REG64_FLD( C_CORE_FIR_PC_PHYP_XSTOP_ERROR , 63 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PC_PHYP_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_IF_SRAM_REC_ERROR , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_IF_SRAM_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_TC_FIR_XSTOP_ERROR , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_TC_FIR_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_IF_RFILE_REC_ERROR , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_IF_RFILE_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_IF_RFILE_XSTOP_ERROR , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_IF_RFILE_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_IF_LOG_REC_ERROR , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_IF_LOG_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_IF_LOG_XSTOP_ERROR , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_IF_LOG_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_6 , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_6 ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_7 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_7 ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_RECOV_XSTOP_ERROR , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_RECOV_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_SD_RFILE_REC_ERROR , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_SD_RFILE_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_SD_RFILE_XSTOP_ERROR , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_SD_RFILE_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_SD_LOG_REC_ERROR , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_SD_LOG_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_SD_LOG_XSTOP_ERROR , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_SD_LOG_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_SD_NOT_MT_CI_REC_ERROR , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_SD_NOT_MT_CI_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_SD_MCHK_AND_ME_EQ_0_ERROR , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_SD_MCHK_AND_ME_EQ_0_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_SD_L2_UE_ERROR , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_SD_L2_UE_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_SD_L2_UE_OVER_THRES_ERROR , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_SD_L2_UE_OVER_THRES_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_SD_CI_UE_ERROR , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_SD_CI_UE_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_18 , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_18 ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_19 , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_19 ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_SD_SYS_XSTOP_ERROR , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_SD_SYS_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_21 , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_21 ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_22 , 22 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_22 ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_23 , 23 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_23 ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_VS_LOG_REC_ERROR , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_VS_LOG_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_VS_LOG_XSTOP_ERROR , 25 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_VS_LOG_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_RECOV_IN_MAINT_ERROR , 26 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_RECOV_IN_MAINT_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_VS_DU_LOG_REC_ERROR , 27 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_VS_DU_LOG_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_SYS_XSTOP_ERROR , 28 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_SYS_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_SRAM_PARITY_ERROR , 29 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_SRAM_PARITY_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_SETDELETE_ERROR , 30 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_SETDELETE_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_RFILE_REC_ERROR , 31 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_RFILE_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_RFILE_XSTOP_ERROR , 32 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_RFILE_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_TLB_MULTIHIT_ERROR , 33 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_TLB_MULTIHIT_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_SLB_MULTIHIT_ERROR , 34 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_SLB_MULTIHIT_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_DERAT_MULTIHIT_ERROR , 35 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_DERAT_MULTIHIT_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_FWD_PROGRESS_ERROR , 36 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_FWD_PROGRESS_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_LOG_REC_ERROR , 37 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_LOG_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_LOG_XSTOP_ERROR , 38 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_LOG_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_NOT_MT_REC_ERROR , 39 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_NOT_MT_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_40 , 40 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_40 ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_LS_SYS_XSTOP_ERROR , 41 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_SYS_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_42 , 42 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_42 ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_THREAD_HANG_REC_ERROR , 43 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_THREAD_HANG_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_44 , 44 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_44 ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_LOG_XSTOP_ERROR , 45 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_LOG_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_46 , 46 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_46 ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_TFAC_XSTOP_ERROR , 47 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_TFAC_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_HYP_RES_ERROR , 48 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_HYP_RES_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_49 , 49 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_49 ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_50 , 50 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_50 ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_51 , 51 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_51 ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_HANG_RECOVERY_FAILED , 52 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_HANG_RECOVERY_FAILED ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_HANG_DETECT_ERROR , 53 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_HANG_DETECT_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_UNUSED_54 , 54 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_54 ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_NEST_HANG_DETECT_ERROR , 55 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_NEST_HANG_DETECT_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_OTHER_CHIPLET_REC_ERROR , 56 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_OTHER_CHIPLET_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_OTHER_CHIPLET_XSTOP_ERROR , 57 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_OTHER_CHIPLET_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR , 58 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_SCOM_ERROR , 59 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_SCOM_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_XSTOP_ON_DBG_TRIGGER_ERROR , 60 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_XSTOP_ON_DBG_TRIGGER_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_FW_INJ_REC_ERROR , 61 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_FW_INJ_REC_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_FW_INJ_XSTOP_ERROR , 62 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_FW_INJ_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FIRMASK_MASK_PC_PHYP_XSTOP_ERROR , 63 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_PHYP_XSTOP_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_IF_SRAM_REC_ERROR , 0 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_IF_SRAM_REC_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_TC_FIR_XSTOP_ERROR , 1 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_TC_FIR_XSTOP_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_IF_RFILE_REC_ERROR , 2 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_IF_RFILE_REC_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_IF_RFILE_XSTOP_ERROR , 3 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_IF_RFILE_XSTOP_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_IF_LOG_REC_ERROR , 4 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_IF_LOG_REC_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_IF_LOG_XSTOP_ERROR , 5 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_IF_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_6 , 6 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_6 ); REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_7 , 7 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_7 ); REG64_FLD( C_CORE_FIRMASK_MASK_PC_RECOV_XSTOP_ERROR , 8 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_RECOV_XSTOP_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_SD_RFILE_REC_ERROR , 9 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_SD_RFILE_REC_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_SD_RFILE_XSTOP_ERROR , 10 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_SD_RFILE_XSTOP_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_SD_LOG_REC_ERROR , 11 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_SD_LOG_REC_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_SD_LOG_XSTOP_ERROR , 12 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_SD_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_SD_NOT_MT_CI_REC_ERROR , 13 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_SD_NOT_MT_CI_REC_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_SD_MCHK_AND_ME_EQ_0_ERROR , 14 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_SD_MCHK_AND_ME_EQ_0_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_SD_L2_UE_ERROR , 15 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_SD_L2_UE_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_SD_L2_UE_OVER_THRES_ERROR , 16 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_SD_L2_UE_OVER_THRES_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_SD_CI_UE_ERROR , 17 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_SD_CI_UE_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_18 , 18 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_18 ); REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_19 , 19 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_19 ); REG64_FLD( C_CORE_FIRMASK_MASK_SD_SYS_XSTOP_ERROR , 20 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_SD_SYS_XSTOP_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_21 , 21 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_21 ); REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_22 , 22 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_22 ); REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_23 , 23 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_23 ); REG64_FLD( C_CORE_FIRMASK_MASK_VS_LOG_REC_ERROR , 24 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_VS_LOG_REC_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_VS_LOG_XSTOP_ERROR , 25 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_VS_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_PC_RECOV_IN_MAINT_ERROR , 26 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_RECOV_IN_MAINT_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_VS_DU_LOG_REC_ERROR , 27 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_VS_DU_LOG_REC_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_PC_SYS_XSTOP_ERROR , 28 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_SYS_XSTOP_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_LS_SRAM_PARITY_ERROR , 29 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_SRAM_PARITY_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_LS_SETDELETE_ERROR , 30 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_SETDELETE_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_LS_RFILE_REC_ERROR , 31 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_RFILE_REC_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_LS_RFILE_XSTOP_ERROR , 32 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_RFILE_XSTOP_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_LS_TLB_MULTIHIT_ERROR , 33 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_TLB_MULTIHIT_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_LS_SLB_MULTIHIT_ERROR , 34 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_SLB_MULTIHIT_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_LS_DERAT_MULTIHIT_ERROR , 35 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_DERAT_MULTIHIT_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_PC_FWD_PROGRESS_ERROR , 36 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_FWD_PROGRESS_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_LS_LOG_REC_ERROR , 37 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_LOG_REC_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_LS_LOG_XSTOP_ERROR , 38 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_LS_NOT_MT_REC_ERROR , 39 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_NOT_MT_REC_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_40 , 40 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_40 ); REG64_FLD( C_CORE_FIRMASK_MASK_LS_SYS_XSTOP_ERROR , 41 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_LS_SYS_XSTOP_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_42 , 42 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_42 ); REG64_FLD( C_CORE_FIRMASK_MASK_PC_THREAD_HANG_REC_ERROR , 43 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_THREAD_HANG_REC_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_44 , 44 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_44 ); REG64_FLD( C_CORE_FIRMASK_MASK_PC_LOG_XSTOP_ERROR , 45 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_46 , 46 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_46 ); REG64_FLD( C_CORE_FIRMASK_MASK_PC_TFAC_XSTOP_ERROR , 47 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_TFAC_XSTOP_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_PC_HYP_RES_ERROR , 48 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_HYP_RES_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_49 , 49 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_49 ); REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_50 , 50 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_50 ); REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_51 , 51 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_51 ); REG64_FLD( C_CORE_FIRMASK_MASK_PC_HANG_RECOVERY_FAILED , 52 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_HANG_RECOVERY_FAILED ); REG64_FLD( C_CORE_FIRMASK_MASK_PC_HANG_DETECT_ERROR , 53 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_HANG_DETECT_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_UNUSED_54 , 54 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_UNUSED_54 ); REG64_FLD( C_CORE_FIRMASK_MASK_PC_NEST_HANG_DETECT_ERROR , 55 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_NEST_HANG_DETECT_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_PC_OTHER_CHIPLET_REC_ERROR , 56 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_OTHER_CHIPLET_REC_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_PC_OTHER_CHIPLET_XSTOP_ERROR , 57 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_OTHER_CHIPLET_XSTOP_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR , 58 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_OTHER_CHIPLET_SYS_XSTOP_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_PC_SCOM_ERROR , 59 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_SCOM_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_PC_XSTOP_ON_DBG_TRIGGER_ERROR , 60 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_XSTOP_ON_DBG_TRIGGER_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_PC_FW_INJ_REC_ERROR , 61 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_FW_INJ_REC_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_PC_FW_INJ_XSTOP_ERROR , 62 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_FW_INJ_XSTOP_ERROR ); REG64_FLD( C_CORE_FIRMASK_MASK_PC_PHYP_XSTOP_ERROR , 63 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MASK_PC_PHYP_XSTOP_ERROR ); REG64_FLD( EX_L2_CORE_FUSES_FP_THROTTLE_EN , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_FP_THROTTLE_EN ); REG64_FLD( EX_L2_CORE_FUSES_VMX_CRYPTO_DIS , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VMX_CRYPTO_DIS ); REG64_FLD( C_CORE_FUSES_FP_THROTTLE_EN , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_FP_THROTTLE_EN ); REG64_FLD( C_CORE_FUSES_VMX_CRYPTO_DIS , 1 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VMX_CRYPTO_DIS ); REG64_FLD( EX_L2_CORE_THREAD_STATE_VT0_PSSCR_RL , 32 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT0_PSSCR_RL ); REG64_FLD( EX_L2_CORE_THREAD_STATE_VT0_PSSCR_RL_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT0_PSSCR_RL_LEN ); REG64_FLD( EX_L2_CORE_THREAD_STATE_VT1_PSSCR_RL , 36 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT1_PSSCR_RL ); REG64_FLD( EX_L2_CORE_THREAD_STATE_VT1_PSSCR_RL_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT1_PSSCR_RL_LEN ); REG64_FLD( EX_L2_CORE_THREAD_STATE_VT2_PSSCR_RL , 40 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT2_PSSCR_RL ); REG64_FLD( EX_L2_CORE_THREAD_STATE_VT2_PSSCR_RL_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT2_PSSCR_RL_LEN ); REG64_FLD( EX_L2_CORE_THREAD_STATE_VT3_PSSCR_RL , 44 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT3_PSSCR_RL ); REG64_FLD( EX_L2_CORE_THREAD_STATE_VT3_PSSCR_RL_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT3_PSSCR_RL_LEN ); REG64_FLD( EX_L2_CORE_THREAD_STATE_VT0_STOP_STATE , 56 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT0_STOP_STATE ); REG64_FLD( EX_L2_CORE_THREAD_STATE_VT1_STOP_STATE , 57 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT1_STOP_STATE ); REG64_FLD( EX_L2_CORE_THREAD_STATE_VT2_STOP_STATE , 58 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT2_STOP_STATE ); REG64_FLD( EX_L2_CORE_THREAD_STATE_VT3_STOP_STATE , 59 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT3_STOP_STATE ); REG64_FLD( EX_L2_CORE_THREAD_STATE_LPAR_FUSED_CORE_MODE , 63 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LPAR_FUSED_CORE_MODE ); REG64_FLD( C_CORE_THREAD_STATE_VT0_PSSCR_RL , 32 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT0_PSSCR_RL ); REG64_FLD( C_CORE_THREAD_STATE_VT0_PSSCR_RL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT0_PSSCR_RL_LEN ); REG64_FLD( C_CORE_THREAD_STATE_VT1_PSSCR_RL , 36 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT1_PSSCR_RL ); REG64_FLD( C_CORE_THREAD_STATE_VT1_PSSCR_RL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT1_PSSCR_RL_LEN ); REG64_FLD( C_CORE_THREAD_STATE_VT2_PSSCR_RL , 40 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT2_PSSCR_RL ); REG64_FLD( C_CORE_THREAD_STATE_VT2_PSSCR_RL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT2_PSSCR_RL_LEN ); REG64_FLD( C_CORE_THREAD_STATE_VT3_PSSCR_RL , 44 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT3_PSSCR_RL ); REG64_FLD( C_CORE_THREAD_STATE_VT3_PSSCR_RL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT3_PSSCR_RL_LEN ); REG64_FLD( C_CORE_THREAD_STATE_VT0_STOP_STATE , 56 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT0_STOP_STATE ); REG64_FLD( C_CORE_THREAD_STATE_VT1_STOP_STATE , 57 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT1_STOP_STATE ); REG64_FLD( C_CORE_THREAD_STATE_VT2_STOP_STATE , 58 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT2_STOP_STATE ); REG64_FLD( C_CORE_THREAD_STATE_VT3_STOP_STATE , 59 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT3_STOP_STATE ); REG64_FLD( C_CORE_THREAD_STATE_LPAR_FUSED_CORE_MODE , 63 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LPAR_FUSED_CORE_MODE ); REG64_FLD( EX_CORE_WOF_WOF_IF_SRAM_REC_ERROR , 0 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_IF_SRAM_REC_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_TC_FIR_XSTOP_ERROR , 1 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_TC_FIR_XSTOP_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_IF_RFILE_REC_ERROR , 2 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_IF_RFILE_REC_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_IF_RFILE_XSTOP_ERROR , 3 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_IF_RFILE_XSTOP_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_IF_LOG_REC_ERROR , 4 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_IF_LOG_REC_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_IF_LOG_XSTOP_ERROR , 5 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_IF_LOG_XSTOP_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_UNUSED_6 , 6 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_6 ); REG64_FLD( EX_CORE_WOF_WOF_UNUSED_7 , 7 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_7 ); REG64_FLD( EX_CORE_WOF_WOF_PC_RECOV_XSTOP_ERROR , 8 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_RECOV_XSTOP_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_SD_RFILE_REC_ERROR , 9 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_SD_RFILE_REC_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_SD_RFILE_XSTOP_ERROR , 10 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_SD_RFILE_XSTOP_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_SD_LOG_REC_ERROR , 11 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_SD_LOG_REC_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_SD_LOG_XSTOP_ERROR , 12 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_SD_LOG_XSTOP_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_SD_NOT_MT_CI_REC_ERROR , 13 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_SD_NOT_MT_CI_REC_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_SD_MCHK_AND_ME_EQ_0_ERROR , 14 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_SD_MCHK_AND_ME_EQ_0_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_SD_L2_UE_ERROR , 15 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_SD_L2_UE_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_SD_L2_UE_OVER_THRES_ERROR , 16 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_SD_L2_UE_OVER_THRES_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_SD_CI_UE_ERROR , 17 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_SD_CI_UE_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_UNUSED_18 , 18 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_18 ); REG64_FLD( EX_CORE_WOF_WOF_UNUSED_19 , 19 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_19 ); REG64_FLD( EX_CORE_WOF_WOF_SD_SYS_XSTOP_ERROR , 20 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_SD_SYS_XSTOP_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_UNUSED_21 , 21 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_21 ); REG64_FLD( EX_CORE_WOF_WOF_UNUSED_22 , 22 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_22 ); REG64_FLD( EX_CORE_WOF_WOF_UNUSED_23 , 23 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_23 ); REG64_FLD( EX_CORE_WOF_WOF_VS_LOG_REC_ERROR , 24 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_VS_LOG_REC_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_VS_LOG_XSTOP_ERROR , 25 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_VS_LOG_XSTOP_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_PC_RECOV_IN_MAINT_ERROR , 26 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_RECOV_IN_MAINT_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_VS_DU_LOG_REC_ERROR , 27 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_VS_DU_LOG_REC_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_PC_SYS_XSTOP_ERROR , 28 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_SYS_XSTOP_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_LS_SRAM_PARITY_ERROR , 29 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_SRAM_PARITY_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_LS_SETDELETE_ERROR , 30 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_SETDELETE_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_LS_RFILE_REC_ERROR , 31 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_RFILE_REC_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_LS_RFILE_XSTOP_ERROR , 32 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_RFILE_XSTOP_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_LS_TLB_MULTIHIT_ERROR , 33 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_TLB_MULTIHIT_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_LS_SLB_MULTIHIT_ERROR , 34 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_SLB_MULTIHIT_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_LS_DERAT_MULTIHIT_ERROR , 35 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_DERAT_MULTIHIT_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_PC_FWD_PROGRESS_ERROR , 36 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_FWD_PROGRESS_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_LS_LOG_REC_ERROR , 37 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_LOG_REC_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_LS_LOG_XSTOP_ERROR , 38 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_LOG_XSTOP_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_LS_NOT_MT_REC_ERROR , 39 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_NOT_MT_REC_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_UNUSED_40 , 40 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_40 ); REG64_FLD( EX_CORE_WOF_WOF_LS_SYS_XSTOP_ERROR , 41 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_SYS_XSTOP_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_UNUSED_42 , 42 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_42 ); REG64_FLD( EX_CORE_WOF_WOF_PC_THREAD_HANG_REC_ERROR , 43 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_THREAD_HANG_REC_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_UNUSED_44 , 44 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_44 ); REG64_FLD( EX_CORE_WOF_WOF_PC_LOG_XSTOP_ERROR , 45 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_LOG_XSTOP_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_UNUSED_46 , 46 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_46 ); REG64_FLD( EX_CORE_WOF_WOF_PC_TFAC_XSTOP_ERROR , 47 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_TFAC_XSTOP_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_PC_HYP_RES_ERROR , 48 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_HYP_RES_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_UNUSED_49 , 49 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_49 ); REG64_FLD( EX_CORE_WOF_WOF_UNUSED_50 , 50 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_50 ); REG64_FLD( EX_CORE_WOF_WOF_UNUSED_51 , 51 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_51 ); REG64_FLD( EX_CORE_WOF_WOF_PC_HANG_RECOVERY_FAILED , 52 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_HANG_RECOVERY_FAILED ); REG64_FLD( EX_CORE_WOF_WOF_PC_CORE_HANG_DETECT_ERROR , 53 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_CORE_HANG_DETECT_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_UNUSED_54 , 54 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_54 ); REG64_FLD( EX_CORE_WOF_WOF_PC_NEST_HANG_DETECT_ERROR , 55 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_NEST_HANG_DETECT_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_PC_OTHER_CORE_CHIPLET_REC_ERROR , 56 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_OTHER_CORE_CHIPLET_REC_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_PC_OTHER_CORE_CHIPLET_XSTOP_ERROR , 57 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_OTHER_CORE_CHIPLET_XSTOP_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR , 58 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_PC_SCOM_ERROR , 59 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_SCOM_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_PC_XSTOP_ON_DBG_TRIGGER_ERROR , 60 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_XSTOP_ON_DBG_TRIGGER_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_PC_FW_INJ_REC_ERROR , 61 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_FW_INJ_REC_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_PC_FW_INJ_XSTOP_ERROR , 62 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_FW_INJ_XSTOP_ERROR ); REG64_FLD( EX_CORE_WOF_WOF_PC_PHYP_XSTOP_ERROR , 63 , SH_UNT_EX , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_PHYP_XSTOP_ERROR ); REG64_FLD( C_CORE_WOF_WOF_IF_SRAM_REC_ERROR , 0 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_IF_SRAM_REC_ERROR ); REG64_FLD( C_CORE_WOF_WOF_TC_FIR_XSTOP_ERROR , 1 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_TC_FIR_XSTOP_ERROR ); REG64_FLD( C_CORE_WOF_WOF_IF_RFILE_REC_ERROR , 2 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_IF_RFILE_REC_ERROR ); REG64_FLD( C_CORE_WOF_WOF_IF_RFILE_XSTOP_ERROR , 3 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_IF_RFILE_XSTOP_ERROR ); REG64_FLD( C_CORE_WOF_WOF_IF_LOG_REC_ERROR , 4 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_IF_LOG_REC_ERROR ); REG64_FLD( C_CORE_WOF_WOF_IF_LOG_XSTOP_ERROR , 5 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_IF_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_WOF_WOF_UNUSED_6 , 6 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_6 ); REG64_FLD( C_CORE_WOF_WOF_UNUSED_7 , 7 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_7 ); REG64_FLD( C_CORE_WOF_WOF_PC_RECOV_XSTOP_ERROR , 8 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_RECOV_XSTOP_ERROR ); REG64_FLD( C_CORE_WOF_WOF_SD_RFILE_REC_ERROR , 9 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_SD_RFILE_REC_ERROR ); REG64_FLD( C_CORE_WOF_WOF_SD_RFILE_XSTOP_ERROR , 10 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_SD_RFILE_XSTOP_ERROR ); REG64_FLD( C_CORE_WOF_WOF_SD_LOG_REC_ERROR , 11 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_SD_LOG_REC_ERROR ); REG64_FLD( C_CORE_WOF_WOF_SD_LOG_XSTOP_ERROR , 12 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_SD_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_WOF_WOF_SD_NOT_MT_CI_REC_ERROR , 13 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_SD_NOT_MT_CI_REC_ERROR ); REG64_FLD( C_CORE_WOF_WOF_SD_MCHK_AND_ME_EQ_0_ERROR , 14 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_SD_MCHK_AND_ME_EQ_0_ERROR ); REG64_FLD( C_CORE_WOF_WOF_SD_L2_UE_ERROR , 15 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_SD_L2_UE_ERROR ); REG64_FLD( C_CORE_WOF_WOF_SD_L2_UE_OVER_THRES_ERROR , 16 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_SD_L2_UE_OVER_THRES_ERROR ); REG64_FLD( C_CORE_WOF_WOF_SD_CI_UE_ERROR , 17 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_SD_CI_UE_ERROR ); REG64_FLD( C_CORE_WOF_WOF_UNUSED_18 , 18 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_18 ); REG64_FLD( C_CORE_WOF_WOF_UNUSED_19 , 19 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_19 ); REG64_FLD( C_CORE_WOF_WOF_SD_SYS_XSTOP_ERROR , 20 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_SD_SYS_XSTOP_ERROR ); REG64_FLD( C_CORE_WOF_WOF_UNUSED_21 , 21 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_21 ); REG64_FLD( C_CORE_WOF_WOF_UNUSED_22 , 22 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_22 ); REG64_FLD( C_CORE_WOF_WOF_UNUSED_23 , 23 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_23 ); REG64_FLD( C_CORE_WOF_WOF_VS_LOG_REC_ERROR , 24 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_VS_LOG_REC_ERROR ); REG64_FLD( C_CORE_WOF_WOF_VS_LOG_XSTOP_ERROR , 25 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_VS_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_WOF_WOF_PC_RECOV_IN_MAINT_ERROR , 26 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_RECOV_IN_MAINT_ERROR ); REG64_FLD( C_CORE_WOF_WOF_VS_DU_LOG_REC_ERROR , 27 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_VS_DU_LOG_REC_ERROR ); REG64_FLD( C_CORE_WOF_WOF_PC_SYS_XSTOP_ERROR , 28 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_SYS_XSTOP_ERROR ); REG64_FLD( C_CORE_WOF_WOF_LS_SRAM_PARITY_ERROR , 29 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_SRAM_PARITY_ERROR ); REG64_FLD( C_CORE_WOF_WOF_LS_SETDELETE_ERROR , 30 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_SETDELETE_ERROR ); REG64_FLD( C_CORE_WOF_WOF_LS_RFILE_REC_ERROR , 31 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_RFILE_REC_ERROR ); REG64_FLD( C_CORE_WOF_WOF_LS_RFILE_XSTOP_ERROR , 32 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_RFILE_XSTOP_ERROR ); REG64_FLD( C_CORE_WOF_WOF_LS_TLB_MULTIHIT_ERROR , 33 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_TLB_MULTIHIT_ERROR ); REG64_FLD( C_CORE_WOF_WOF_LS_SLB_MULTIHIT_ERROR , 34 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_SLB_MULTIHIT_ERROR ); REG64_FLD( C_CORE_WOF_WOF_LS_DERAT_MULTIHIT_ERROR , 35 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_DERAT_MULTIHIT_ERROR ); REG64_FLD( C_CORE_WOF_WOF_PC_FWD_PROGRESS_ERROR , 36 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_FWD_PROGRESS_ERROR ); REG64_FLD( C_CORE_WOF_WOF_LS_LOG_REC_ERROR , 37 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_LOG_REC_ERROR ); REG64_FLD( C_CORE_WOF_WOF_LS_LOG_XSTOP_ERROR , 38 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_WOF_WOF_LS_NOT_MT_REC_ERROR , 39 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_NOT_MT_REC_ERROR ); REG64_FLD( C_CORE_WOF_WOF_UNUSED_40 , 40 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_40 ); REG64_FLD( C_CORE_WOF_WOF_LS_SYS_XSTOP_ERROR , 41 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LS_SYS_XSTOP_ERROR ); REG64_FLD( C_CORE_WOF_WOF_UNUSED_42 , 42 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_42 ); REG64_FLD( C_CORE_WOF_WOF_PC_THREAD_HANG_REC_ERROR , 43 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_THREAD_HANG_REC_ERROR ); REG64_FLD( C_CORE_WOF_WOF_UNUSED_44 , 44 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_44 ); REG64_FLD( C_CORE_WOF_WOF_PC_LOG_XSTOP_ERROR , 45 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_LOG_XSTOP_ERROR ); REG64_FLD( C_CORE_WOF_WOF_UNUSED_46 , 46 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_46 ); REG64_FLD( C_CORE_WOF_WOF_PC_TFAC_XSTOP_ERROR , 47 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_TFAC_XSTOP_ERROR ); REG64_FLD( C_CORE_WOF_WOF_PC_HYP_RES_ERROR , 48 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_HYP_RES_ERROR ); REG64_FLD( C_CORE_WOF_WOF_UNUSED_49 , 49 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_49 ); REG64_FLD( C_CORE_WOF_WOF_UNUSED_50 , 50 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_50 ); REG64_FLD( C_CORE_WOF_WOF_UNUSED_51 , 51 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_51 ); REG64_FLD( C_CORE_WOF_WOF_PC_HANG_RECOVERY_FAILED , 52 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_HANG_RECOVERY_FAILED ); REG64_FLD( C_CORE_WOF_WOF_PC_CORE_HANG_DETECT_ERROR , 53 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_CORE_HANG_DETECT_ERROR ); REG64_FLD( C_CORE_WOF_WOF_UNUSED_54 , 54 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_UNUSED_54 ); REG64_FLD( C_CORE_WOF_WOF_PC_NEST_HANG_DETECT_ERROR , 55 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_NEST_HANG_DETECT_ERROR ); REG64_FLD( C_CORE_WOF_WOF_PC_OTHER_CORE_CHIPLET_REC_ERROR , 56 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_OTHER_CORE_CHIPLET_REC_ERROR ); REG64_FLD( C_CORE_WOF_WOF_PC_OTHER_CORE_CHIPLET_XSTOP_ERROR , 57 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_OTHER_CORE_CHIPLET_XSTOP_ERROR ); REG64_FLD( C_CORE_WOF_WOF_PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR , 58 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_OTHER_CORE_CHIPLET_SYS_XSTOP_ERROR ); REG64_FLD( C_CORE_WOF_WOF_PC_SCOM_ERROR , 59 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_SCOM_ERROR ); REG64_FLD( C_CORE_WOF_WOF_PC_XSTOP_ON_DBG_TRIGGER_ERROR , 60 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_XSTOP_ON_DBG_TRIGGER_ERROR ); REG64_FLD( C_CORE_WOF_WOF_PC_FW_INJ_REC_ERROR , 61 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_FW_INJ_REC_ERROR ); REG64_FLD( C_CORE_WOF_WOF_PC_FW_INJ_XSTOP_ERROR , 62 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_FW_INJ_XSTOP_ERROR ); REG64_FLD( C_CORE_WOF_WOF_PC_PHYP_XSTOP_ERROR , 63 , SH_UNT_C , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_PC_PHYP_XSTOP_ERROR ); REG64_FLD( EQ_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC , 0 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE0_SEL_DC ); REG64_FLD( EQ_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC_LEN , 6 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE0_SEL_DC_LEN ); REG64_FLD( EQ_CPLT_CONF0_RESERVED_6C , 6 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_6C ); REG64_FLD( EQ_CPLT_CONF0_RESERVED_7C , 7 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_7C ); REG64_FLD( EQ_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC , 8 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE1_SEL_DC ); REG64_FLD( EQ_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC_LEN , 6 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE1_SEL_DC_LEN ); REG64_FLD( EQ_CPLT_CONF0_RESERVED_14C , 14 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_14C ); REG64_FLD( EQ_CPLT_CONF0_RESERVED_15C , 15 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_15C ); REG64_FLD( EQ_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC , 16 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE2_SEL_DC ); REG64_FLD( EQ_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC_LEN , 6 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE2_SEL_DC_LEN ); REG64_FLD( EQ_CPLT_CONF0_RESERVED_22C , 22 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_22C ); REG64_FLD( EQ_CPLT_CONF0_RESERVED_23C , 23 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_23C ); REG64_FLD( EQ_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC , 24 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE3_SEL_DC ); REG64_FLD( EQ_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC_LEN , 6 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE3_SEL_DC_LEN ); REG64_FLD( EQ_CPLT_CONF0_RESERVED_30C , 30 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_30C ); REG64_FLD( EQ_CPLT_CONF0_RESERVED_31C , 31 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_31C ); REG64_FLD( EQ_CPLT_CONF0_CTRL_CC_OFLOW_FEH_SEL_DC , 32 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_OFLOW_FEH_SEL_DC ); REG64_FLD( EQ_CPLT_CONF0_CTRL_CC_SCAN_PROTECT_DC , 33 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_SCAN_PROTECT_DC ); REG64_FLD( EQ_CPLT_CONF0_CTRL_CC_SDIS_DC_N , 34 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_SDIS_DC_N ); REG64_FLD( EQ_CPLT_CONF0_RESERVED_TEST_CONTROL_35C , 35 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_35C ); REG64_FLD( EQ_CPLT_CONF0_RESERVED_TEST_CONTROL_36C , 36 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_36C ); REG64_FLD( EQ_CPLT_CONF0_RESERVED_TEST_CONTROL_37C , 37 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_37C ); REG64_FLD( EQ_CPLT_CONF0_RESERVED_TEST_CONTROL_38C , 38 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_38C ); REG64_FLD( EQ_CPLT_CONF0_RESERVED_TEST_CONTROL_39C , 39 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_39C ); REG64_FLD( EQ_CPLT_CONF0_CTRL_EPS_MASK_VITL_PCB_ERR_DC , 40 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_EPS_MASK_VITL_PCB_ERR_DC ); REG64_FLD( EQ_CPLT_CONF0_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC , 41 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC ); REG64_FLD( EQ_CPLT_CONF0_RESERVED_42C , 42 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_42C ); REG64_FLD( EQ_CPLT_CONF0_RESERVED_43C , 43 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_43C ); REG64_FLD( EQ_CPLT_CONF0_FREE_USAGE_44C , 44 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_44C ); REG64_FLD( EQ_CPLT_CONF0_FREE_USAGE_45C , 45 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_45C ); REG64_FLD( EQ_CPLT_CONF0_FREE_USAGE_46C , 46 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_46C ); REG64_FLD( EQ_CPLT_CONF0_FREE_USAGE_47C , 47 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_47C ); REG64_FLD( EQ_CPLT_CONF0_TC_UNIT_GROUP_ID_DC , 48 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_GROUP_ID_DC ); REG64_FLD( EQ_CPLT_CONF0_TC_UNIT_GROUP_ID_DC_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_GROUP_ID_DC_LEN ); REG64_FLD( EQ_CPLT_CONF0_TC_UNIT_CHIP_ID_DC , 52 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_CHIP_ID_DC ); REG64_FLD( EQ_CPLT_CONF0_TC_UNIT_CHIP_ID_DC_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_CHIP_ID_DC_LEN ); REG64_FLD( EQ_CPLT_CONF0_RESERVED_ID_55C , 55 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_55C ); REG64_FLD( EQ_CPLT_CONF0_TC_UNIT_SYS_ID_DC , 56 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_SYS_ID_DC ); REG64_FLD( EQ_CPLT_CONF0_TC_UNIT_SYS_ID_DC_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_SYS_ID_DC_LEN ); REG64_FLD( EQ_CPLT_CONF0_RESERVED_ID_61C , 61 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_61C ); REG64_FLD( EQ_CPLT_CONF0_RESERVED_ID_62C , 62 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_62C ); REG64_FLD( EQ_CPLT_CONF0_RESERVED_ID_63C , 63 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_63C ); REG64_FLD( EX_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC , 0 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE0_SEL_DC ); REG64_FLD( EX_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE0_SEL_DC_LEN ); REG64_FLD( EX_CPLT_CONF0_RESERVED_6C , 6 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_6C ); REG64_FLD( EX_CPLT_CONF0_RESERVED_7C , 7 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_7C ); REG64_FLD( EX_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC , 8 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE1_SEL_DC ); REG64_FLD( EX_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE1_SEL_DC_LEN ); REG64_FLD( EX_CPLT_CONF0_RESERVED_14C , 14 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_14C ); REG64_FLD( EX_CPLT_CONF0_RESERVED_15C , 15 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_15C ); REG64_FLD( EX_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC , 16 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE2_SEL_DC ); REG64_FLD( EX_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE2_SEL_DC_LEN ); REG64_FLD( EX_CPLT_CONF0_RESERVED_22C , 22 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_22C ); REG64_FLD( EX_CPLT_CONF0_RESERVED_23C , 23 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_23C ); REG64_FLD( EX_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC , 24 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE3_SEL_DC ); REG64_FLD( EX_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE3_SEL_DC_LEN ); REG64_FLD( EX_CPLT_CONF0_RESERVED_30C , 30 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_30C ); REG64_FLD( EX_CPLT_CONF0_RESERVED_31C , 31 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_31C ); REG64_FLD( EX_CPLT_CONF0_CTRL_CC_OFLOW_FEH_SEL_DC , 32 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_OFLOW_FEH_SEL_DC ); REG64_FLD( EX_CPLT_CONF0_CTRL_CC_SCAN_PROTECT_DC , 33 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_SCAN_PROTECT_DC ); REG64_FLD( EX_CPLT_CONF0_CTRL_CC_SDIS_DC_N , 34 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_SDIS_DC_N ); REG64_FLD( EX_CPLT_CONF0_RESERVED_TEST_CONTROL_35C , 35 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_35C ); REG64_FLD( EX_CPLT_CONF0_RESERVED_TEST_CONTROL_36C , 36 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_36C ); REG64_FLD( EX_CPLT_CONF0_RESERVED_TEST_CONTROL_37C , 37 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_37C ); REG64_FLD( EX_CPLT_CONF0_RESERVED_TEST_CONTROL_38C , 38 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_38C ); REG64_FLD( EX_CPLT_CONF0_RESERVED_TEST_CONTROL_39C , 39 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_39C ); REG64_FLD( EX_CPLT_CONF0_CTRL_EPS_MASK_VITL_PCB_ERR_DC , 40 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_EPS_MASK_VITL_PCB_ERR_DC ); REG64_FLD( EX_CPLT_CONF0_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC , 41 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC ); REG64_FLD( EX_CPLT_CONF0_RESERVED_42C , 42 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_42C ); REG64_FLD( EX_CPLT_CONF0_RESERVED_43C , 43 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_43C ); REG64_FLD( EX_CPLT_CONF0_FREE_USAGE_44C , 44 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_44C ); REG64_FLD( EX_CPLT_CONF0_FREE_USAGE_45C , 45 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_45C ); REG64_FLD( EX_CPLT_CONF0_FREE_USAGE_46C , 46 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_46C ); REG64_FLD( EX_CPLT_CONF0_FREE_USAGE_47C , 47 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_47C ); REG64_FLD( EX_CPLT_CONF0_TC_UNIT_GROUP_ID_DC , 48 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_GROUP_ID_DC ); REG64_FLD( EX_CPLT_CONF0_TC_UNIT_GROUP_ID_DC_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_GROUP_ID_DC_LEN ); REG64_FLD( EX_CPLT_CONF0_TC_UNIT_CHIP_ID_DC , 52 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_CHIP_ID_DC ); REG64_FLD( EX_CPLT_CONF0_TC_UNIT_CHIP_ID_DC_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_CHIP_ID_DC_LEN ); REG64_FLD( EX_CPLT_CONF0_RESERVED_ID_55C , 55 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_55C ); REG64_FLD( EX_CPLT_CONF0_TC_UNIT_SYS_ID_DC , 56 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_SYS_ID_DC ); REG64_FLD( EX_CPLT_CONF0_TC_UNIT_SYS_ID_DC_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_SYS_ID_DC_LEN ); REG64_FLD( EX_CPLT_CONF0_RESERVED_ID_61C , 61 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_61C ); REG64_FLD( EX_CPLT_CONF0_RESERVED_ID_62C , 62 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_62C ); REG64_FLD( EX_CPLT_CONF0_RESERVED_ID_63C , 63 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_63C ); REG64_FLD( C_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC , 0 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE0_SEL_DC ); REG64_FLD( C_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC_LEN , 6 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE0_SEL_DC_LEN ); REG64_FLD( C_CPLT_CONF0_RESERVED_6C , 6 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_6C ); REG64_FLD( C_CPLT_CONF0_RESERVED_7C , 7 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_7C ); REG64_FLD( C_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC , 8 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE1_SEL_DC ); REG64_FLD( C_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC_LEN , 6 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE1_SEL_DC_LEN ); REG64_FLD( C_CPLT_CONF0_RESERVED_14C , 14 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_14C ); REG64_FLD( C_CPLT_CONF0_RESERVED_15C , 15 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_15C ); REG64_FLD( C_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC , 16 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE2_SEL_DC ); REG64_FLD( C_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC_LEN , 6 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE2_SEL_DC_LEN ); REG64_FLD( C_CPLT_CONF0_RESERVED_22C , 22 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_22C ); REG64_FLD( C_CPLT_CONF0_RESERVED_23C , 23 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_23C ); REG64_FLD( C_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC , 24 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE3_SEL_DC ); REG64_FLD( C_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC_LEN , 6 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE3_SEL_DC_LEN ); REG64_FLD( C_CPLT_CONF0_RESERVED_30C , 30 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_30C ); REG64_FLD( C_CPLT_CONF0_RESERVED_31C , 31 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_31C ); REG64_FLD( C_CPLT_CONF0_CTRL_CC_OFLOW_FEH_SEL_DC , 32 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_OFLOW_FEH_SEL_DC ); REG64_FLD( C_CPLT_CONF0_CTRL_CC_SCAN_PROTECT_DC , 33 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_SCAN_PROTECT_DC ); REG64_FLD( C_CPLT_CONF0_CTRL_CC_SDIS_DC_N , 34 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_SDIS_DC_N ); REG64_FLD( C_CPLT_CONF0_RESERVED_TEST_CONTROL_35C , 35 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_35C ); REG64_FLD( C_CPLT_CONF0_RESERVED_TEST_CONTROL_36C , 36 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_36C ); REG64_FLD( C_CPLT_CONF0_RESERVED_TEST_CONTROL_37C , 37 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_37C ); REG64_FLD( C_CPLT_CONF0_RESERVED_TEST_CONTROL_38C , 38 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_38C ); REG64_FLD( C_CPLT_CONF0_RESERVED_TEST_CONTROL_39C , 39 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_39C ); REG64_FLD( C_CPLT_CONF0_CTRL_EPS_MASK_VITL_PCB_ERR_DC , 40 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_EPS_MASK_VITL_PCB_ERR_DC ); REG64_FLD( C_CPLT_CONF0_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC , 41 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC ); REG64_FLD( C_CPLT_CONF0_RESERVED_42C , 42 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_42C ); REG64_FLD( C_CPLT_CONF0_RESERVED_43C , 43 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_43C ); REG64_FLD( C_CPLT_CONF0_FREE_USAGE_44C , 44 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_44C ); REG64_FLD( C_CPLT_CONF0_FREE_USAGE_45C , 45 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_45C ); REG64_FLD( C_CPLT_CONF0_FREE_USAGE_46C , 46 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_46C ); REG64_FLD( C_CPLT_CONF0_FREE_USAGE_47C , 47 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_47C ); REG64_FLD( C_CPLT_CONF0_TC_UNIT_GROUP_ID_DC , 48 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_GROUP_ID_DC ); REG64_FLD( C_CPLT_CONF0_TC_UNIT_GROUP_ID_DC_LEN , 4 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_GROUP_ID_DC_LEN ); REG64_FLD( C_CPLT_CONF0_TC_UNIT_CHIP_ID_DC , 52 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_CHIP_ID_DC ); REG64_FLD( C_CPLT_CONF0_TC_UNIT_CHIP_ID_DC_LEN , 3 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_CHIP_ID_DC_LEN ); REG64_FLD( C_CPLT_CONF0_RESERVED_ID_55C , 55 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_55C ); REG64_FLD( C_CPLT_CONF0_TC_UNIT_SYS_ID_DC , 56 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_SYS_ID_DC ); REG64_FLD( C_CPLT_CONF0_TC_UNIT_SYS_ID_DC_LEN , 5 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_SYS_ID_DC_LEN ); REG64_FLD( C_CPLT_CONF0_RESERVED_ID_61C , 61 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_61C ); REG64_FLD( C_CPLT_CONF0_RESERVED_ID_62C , 62 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_62C ); REG64_FLD( C_CPLT_CONF0_RESERVED_ID_63C , 63 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_63C ); REG64_FLD( EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_EQ , 0 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TCEP_AMUX_VSELECT_EQ ); REG64_FLD( EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_EQ_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TCEP_AMUX_VSELECT_EQ_LEN ); REG64_FLD( EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_UP , 3 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TCEP_AMUX_VSELECT_PWR_UP ); REG64_FLD( EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_UP_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TCEP_AMUX_VSELECT_PWR_UP_LEN ); REG64_FLD( EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_DN , 5 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TCEP_AMUX_VSELECT_PWR_DN ); REG64_FLD( EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_PWR_DN_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TCEP_AMUX_VSELECT_PWR_DN_LEN ); REG64_FLD( EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_UP , 7 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TCEP_AMUX_VSELECT_L3_UP ); REG64_FLD( EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_UP_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TCEP_AMUX_VSELECT_L3_UP_LEN ); REG64_FLD( EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_DN , 10 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TCEP_AMUX_VSELECT_L3_DN ); REG64_FLD( EQ_CPLT_CONF1_TCEP_AMUX_VSELECT_L3_DN_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TCEP_AMUX_VSELECT_L3_DN_LEN ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_13D , 13 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_13D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_14D , 14 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_14D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_15D , 15 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_15D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_16D , 16 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_16D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_17D , 17 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_17D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_18D , 18 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_18D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_19D , 19 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_19D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_20D , 20 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_20D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_21D , 21 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_21D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_22D , 22 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_22D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_23D , 23 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_23D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_24D , 24 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_24D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_25D , 25 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_25D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_26D , 26 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_26D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_27D , 27 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_27D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_28D , 28 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_28D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_29D , 29 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_29D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_30D , 30 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_30D ); REG64_FLD( EQ_CPLT_CONF1_FREE_USAGE_31D , 31 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_31D ); REG64_FLD( EX_CPLT_CONF1_UNUSED_0D , 0 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_0D ); REG64_FLD( EX_CPLT_CONF1_UNUSED_1D , 1 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_1D ); REG64_FLD( EX_CPLT_CONF1_UNUSED_2D , 2 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_2D ); REG64_FLD( EX_CPLT_CONF1_UNUSED_3D , 3 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_3D ); REG64_FLD( EX_CPLT_CONF1_IOVALID_4D , 4 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_4D ); REG64_FLD( EX_CPLT_CONF1_IOVALID_5D , 5 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_5D ); REG64_FLD( EX_CPLT_CONF1_IOVALID_6D , 6 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_6D ); REG64_FLD( EX_CPLT_CONF1_IOVALID_7D , 7 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_7D ); REG64_FLD( EX_CPLT_CONF1_IOVALID_8D , 8 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_8D ); REG64_FLD( EX_CPLT_CONF1_IOVALID_9D , 9 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_9D ); REG64_FLD( EX_CPLT_CONF1_IOVALID_10D , 10 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_10D ); REG64_FLD( EX_CPLT_CONF1_IOVALID_11D , 11 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_11D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_12D , 12 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_12D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_13D , 13 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_13D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_14D , 14 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_14D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_15D , 15 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_15D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_16D , 16 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_16D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_17D , 17 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_17D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_18D , 18 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_18D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_19D , 19 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_19D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_20D , 20 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_20D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_21D , 21 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_21D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_22D , 22 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_22D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_23D , 23 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_23D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_24D , 24 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_24D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_25D , 25 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_25D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_26D , 26 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_26D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_27D , 27 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_27D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_28D , 28 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_28D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_29D , 29 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_29D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_30D , 30 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_30D ); REG64_FLD( EX_CPLT_CONF1_FREE_USAGE_31D , 31 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_31D ); REG64_FLD( C_CPLT_CONF1_UNUSED_0D , 0 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_0D ); REG64_FLD( C_CPLT_CONF1_UNUSED_1D , 1 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_1D ); REG64_FLD( C_CPLT_CONF1_UNUSED_2D , 2 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_2D ); REG64_FLD( C_CPLT_CONF1_UNUSED_3D , 3 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_3D ); REG64_FLD( C_CPLT_CONF1_IOVALID_4D , 4 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_4D ); REG64_FLD( C_CPLT_CONF1_IOVALID_5D , 5 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_5D ); REG64_FLD( C_CPLT_CONF1_IOVALID_6D , 6 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_6D ); REG64_FLD( C_CPLT_CONF1_IOVALID_7D , 7 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_7D ); REG64_FLD( C_CPLT_CONF1_IOVALID_8D , 8 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_8D ); REG64_FLD( C_CPLT_CONF1_IOVALID_9D , 9 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_9D ); REG64_FLD( C_CPLT_CONF1_IOVALID_10D , 10 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_10D ); REG64_FLD( C_CPLT_CONF1_IOVALID_11D , 11 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID_11D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_12D , 12 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_12D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_13D , 13 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_13D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_14D , 14 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_14D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_15D , 15 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_15D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_16D , 16 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_16D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_17D , 17 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_17D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_18D , 18 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_18D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_19D , 19 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_19D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_20D , 20 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_20D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_21D , 21 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_21D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_22D , 22 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_22D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_23D , 23 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_23D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_24D , 24 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_24D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_25D , 25 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_25D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_26D , 26 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_26D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_27D , 27 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_27D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_28D , 28 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_28D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_29D , 29 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_29D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_30D , 30 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_30D ); REG64_FLD( C_CPLT_CONF1_FREE_USAGE_31D , 31 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_31D ); REG64_FLD( EQ_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC , 0 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_ABSTCLK_MUXSEL_DC ); REG64_FLD( EQ_CPLT_CTRL0_TC_UNIT_SYNCCLK_MUXSEL_DC , 1 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_SYNCCLK_MUXSEL_DC ); REG64_FLD( EQ_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC , 2 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_FLUSHMODE_INH_DC ); REG64_FLD( EQ_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC , 3 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_FORCE_ALIGN_DC ); REG64_FLD( EQ_CPLT_CTRL0_TC_UNIT_ARY_WRT_THRU_DC , 4 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_ARY_WRT_THRU_DC ); REG64_FLD( EQ_CPLT_CTRL0_TC_UNIT_AVP_MODE , 5 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_AVP_MODE ); REG64_FLD( EQ_CPLT_CTRL0_TC_BIT6_CHIPLET_ID_DC , 6 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_BIT6_CHIPLET_ID_DC ); REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_7A , 7 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_7A ); REG64_FLD( EQ_CPLT_CTRL0_CTRL_CC_ABIST_RECOV_DISABLE_DC , 8 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_ABIST_RECOV_DISABLE_DC ); REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_9A , 9 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_9A ); REG64_FLD( EQ_CPLT_CTRL0_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC , 10 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC ); REG64_FLD( EQ_CPLT_CTRL0_RESERVED_11A , 11 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_11A ); REG64_FLD( EQ_CPLT_CTRL0_TC_SKIT_MODE_BIST_DC , 12 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_SKIT_MODE_BIST_DC ); REG64_FLD( EQ_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC , 13 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC ); REG64_FLD( EQ_CPLT_CTRL0_TC_UNIT_CONSTRAIN_SAFESCAN_DC , 14 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_CONSTRAIN_SAFESCAN_DC ); REG64_FLD( EQ_CPLT_CTRL0_TC_UNIT_RRFA_TEST_ENABLE_DC , 15 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_RRFA_TEST_ENABLE_DC ); REG64_FLD( EQ_CPLT_CTRL0_TC_NBTI_HDR_ENABLE_OVR_DC , 16 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_NBTI_HDR_ENABLE_OVR_DC ); REG64_FLD( EQ_CPLT_CTRL0_TC_NBTI_PROBE_GATE_DC , 17 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_NBTI_PROBE_GATE_DC ); REG64_FLD( EQ_CPLT_CTRL0_RESERVED_18A , 18 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_18A ); REG64_FLD( EQ_CPLT_CTRL0_RESERVED_19A , 19 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_19A ); REG64_FLD( EQ_CPLT_CTRL0_TC_PSRO_SEL_DC , 20 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PSRO_SEL_DC ); REG64_FLD( EQ_CPLT_CTRL0_TC_PSRO_SEL_DC_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PSRO_SEL_DC_LEN ); REG64_FLD( EQ_CPLT_CTRL0_TC_BSC_WRAPSEL_DC , 28 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_BSC_WRAPSEL_DC ); REG64_FLD( EQ_CPLT_CTRL0_TC_BSC_INTMODE_DC , 29 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_BSC_INTMODE_DC ); REG64_FLD( EQ_CPLT_CTRL0_TC_BSC_INV_DC , 30 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_BSC_INV_DC ); REG64_FLD( EQ_CPLT_CTRL0_TC_BSC_EXTMODE_DC , 31 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_BSC_EXTMODE_DC ); REG64_FLD( EQ_CPLT_CTRL0_TC_REFCLK_DRVR_EN_DC , 32 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REFCLK_DRVR_EN_DC ); REG64_FLD( EQ_CPLT_CTRL0_RESERVED_33A , 33 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_33A ); REG64_FLD( EQ_CPLT_CTRL0_RESERVED_34A , 34 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_34A ); REG64_FLD( EQ_CPLT_CTRL0_RESERVED_35A , 35 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_35A ); REG64_FLD( EQ_CPLT_CTRL0_TC_OELCC_EDGE_DELAYED_DC , 36 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_OELCC_EDGE_DELAYED_DC ); REG64_FLD( EQ_CPLT_CTRL0_TC_OELCC_ALIGN_FLUSH_DC , 37 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_OELCC_ALIGN_FLUSH_DC ); REG64_FLD( EQ_CPLT_CTRL0_RESERVED_38A , 38 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_38A ); REG64_FLD( EQ_CPLT_CTRL0_RESERVED_39A , 39 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_39A ); REG64_FLD( EQ_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC , 40 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_CLKDIV_SEL_DC ); REG64_FLD( EQ_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_CLKDIV_SEL_DC_LEN ); REG64_FLD( EQ_CPLT_CTRL0_RESERVED_42A , 42 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_42A ); REG64_FLD( EQ_CPLT_CTRL0_RESERVED_43A , 43 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_43A ); REG64_FLD( EQ_CPLT_CTRL0_CTRL_CC_DCTEST_DC , 44 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_DCTEST_DC ); REG64_FLD( EQ_CPLT_CTRL0_CTRL_CC_OTP_PRGMODE_DC , 45 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_OTP_PRGMODE_DC ); REG64_FLD( EQ_CPLT_CTRL0_CTRL_CC_SSS_CALIBRATE_DC , 46 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_SSS_CALIBRATE_DC ); REG64_FLD( EQ_CPLT_CTRL0_CTRL_CC_PIN_LBIST_DC , 47 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_PIN_LBIST_DC ); REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_48A , 48 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_48A ); REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_49A , 49 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_49A ); REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_50A , 50 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_50A ); REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_51A , 51 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_51A ); REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_52A , 52 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_52A ); REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_53A , 53 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_53A ); REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_54A , 54 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_54A ); REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_55A , 55 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_55A ); REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_56A , 56 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_56A ); REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_57A , 57 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_57A ); REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_58A , 58 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_58A ); REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_59A , 59 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_59A ); REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_60A , 60 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_60A ); REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_61A , 61 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_61A ); REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_62A , 62 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_62A ); REG64_FLD( EQ_CPLT_CTRL0_FREE_USAGE_63A , 63 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_63A ); REG64_FLD( EX_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC , 0 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_ABSTCLK_MUXSEL_DC ); REG64_FLD( EX_CPLT_CTRL0_TC_UNIT_SYNCCLK_MUXSEL_DC , 1 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_SYNCCLK_MUXSEL_DC ); REG64_FLD( EX_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC , 2 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_FLUSHMODE_INH_DC ); REG64_FLD( EX_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC , 3 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_FORCE_ALIGN_DC ); REG64_FLD( EX_CPLT_CTRL0_TC_UNIT_ARY_WRT_THRU_DC , 4 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_ARY_WRT_THRU_DC ); REG64_FLD( EX_CPLT_CTRL0_TC_UNIT_AVP_MODE , 5 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_AVP_MODE ); REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_6A , 6 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_6A ); REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_7A , 7 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_7A ); REG64_FLD( EX_CPLT_CTRL0_CTRL_CC_ABIST_RECOV_DISABLE_DC , 8 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_ABIST_RECOV_DISABLE_DC ); REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_9A , 9 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_9A ); REG64_FLD( EX_CPLT_CTRL0_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC , 10 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC ); REG64_FLD( EX_CPLT_CTRL0_RESERVED_11A , 11 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_11A ); REG64_FLD( EX_CPLT_CTRL0_TC_SKIT_MODE_BIST_DC , 12 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_SKIT_MODE_BIST_DC ); REG64_FLD( EX_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC , 13 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC ); REG64_FLD( EX_CPLT_CTRL0_TC_UNIT_CONSTRAIN_SAFESCAN_DC , 14 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_CONSTRAIN_SAFESCAN_DC ); REG64_FLD( EX_CPLT_CTRL0_TC_UNIT_RRFA_TEST_ENABLE_DC , 15 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_RRFA_TEST_ENABLE_DC ); REG64_FLD( EX_CPLT_CTRL0_TC_NBTI_HDR_ENABLE_OVR_DC , 16 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_NBTI_HDR_ENABLE_OVR_DC ); REG64_FLD( EX_CPLT_CTRL0_TC_NBTI_PROBE_GATE_DC , 17 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_NBTI_PROBE_GATE_DC ); REG64_FLD( EX_CPLT_CTRL0_RESERVED_18A , 18 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_18A ); REG64_FLD( EX_CPLT_CTRL0_RESERVED_19A , 19 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_19A ); REG64_FLD( EX_CPLT_CTRL0_TC_PSRO_SEL_DC , 20 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PSRO_SEL_DC ); REG64_FLD( EX_CPLT_CTRL0_TC_PSRO_SEL_DC_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PSRO_SEL_DC_LEN ); REG64_FLD( EX_CPLT_CTRL0_TC_BSC_WRAPSEL_DC , 28 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_BSC_WRAPSEL_DC ); REG64_FLD( EX_CPLT_CTRL0_TC_BSC_INTMODE_DC , 29 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_BSC_INTMODE_DC ); REG64_FLD( EX_CPLT_CTRL0_TC_BSC_INV_DC , 30 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_BSC_INV_DC ); REG64_FLD( EX_CPLT_CTRL0_TC_BSC_EXTMODE_DC , 31 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_BSC_EXTMODE_DC ); REG64_FLD( EX_CPLT_CTRL0_TC_REFCLK_DRVR_EN_DC , 32 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REFCLK_DRVR_EN_DC ); REG64_FLD( EX_CPLT_CTRL0_RESERVED_33A , 33 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_33A ); REG64_FLD( EX_CPLT_CTRL0_RESERVED_34A , 34 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_34A ); REG64_FLD( EX_CPLT_CTRL0_RESERVED_35A , 35 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_35A ); REG64_FLD( EX_CPLT_CTRL0_TC_OELCC_EDGE_DELAYED_DC , 36 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_OELCC_EDGE_DELAYED_DC ); REG64_FLD( EX_CPLT_CTRL0_TC_OELCC_ALIGN_FLUSH_DC , 37 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_OELCC_ALIGN_FLUSH_DC ); REG64_FLD( EX_CPLT_CTRL0_RESERVED_38A , 38 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_38A ); REG64_FLD( EX_CPLT_CTRL0_RESERVED_39A , 39 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_39A ); REG64_FLD( EX_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC , 40 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_CLKDIV_SEL_DC ); REG64_FLD( EX_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_CLKDIV_SEL_DC_LEN ); REG64_FLD( EX_CPLT_CTRL0_RESERVED_42A , 42 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_42A ); REG64_FLD( EX_CPLT_CTRL0_RESERVED_43A , 43 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_43A ); REG64_FLD( EX_CPLT_CTRL0_CTRL_CC_DCTEST_DC , 44 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_DCTEST_DC ); REG64_FLD( EX_CPLT_CTRL0_CTRL_CC_OTP_PRGMODE_DC , 45 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_OTP_PRGMODE_DC ); REG64_FLD( EX_CPLT_CTRL0_CTRL_CC_SSS_CALIBRATE_DC , 46 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_SSS_CALIBRATE_DC ); REG64_FLD( EX_CPLT_CTRL0_CTRL_CC_PIN_LBIST_DC , 47 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_PIN_LBIST_DC ); REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_48A , 48 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_48A ); REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_49A , 49 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_49A ); REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_50A , 50 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_50A ); REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_51A , 51 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_51A ); REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_52A , 52 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_52A ); REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_53A , 53 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_53A ); REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_54A , 54 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_54A ); REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_55A , 55 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_55A ); REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_56A , 56 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_56A ); REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_57A , 57 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_57A ); REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_58A , 58 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_58A ); REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_59A , 59 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_59A ); REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_60A , 60 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_60A ); REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_61A , 61 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_61A ); REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_62A , 62 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_62A ); REG64_FLD( EX_CPLT_CTRL0_FREE_USAGE_63A , 63 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_63A ); REG64_FLD( C_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC , 0 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_ABSTCLK_MUXSEL_DC ); REG64_FLD( C_CPLT_CTRL0_TC_UNIT_SYNCCLK_MUXSEL_DC , 1 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_SYNCCLK_MUXSEL_DC ); REG64_FLD( C_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC , 2 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_FLUSHMODE_INH_DC ); REG64_FLD( C_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC , 3 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_FORCE_ALIGN_DC ); REG64_FLD( C_CPLT_CTRL0_TC_UNIT_ARY_WRT_THRU_DC , 4 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_ARY_WRT_THRU_DC ); REG64_FLD( C_CPLT_CTRL0_TC_UNIT_AVP_MODE , 5 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_AVP_MODE ); REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_6A , 6 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_6A ); REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_7A , 7 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_7A ); REG64_FLD( C_CPLT_CTRL0_CTRL_CC_ABIST_RECOV_DISABLE_DC , 8 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_ABIST_RECOV_DISABLE_DC ); REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_9A , 9 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_9A ); REG64_FLD( C_CPLT_CTRL0_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC , 10 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC ); REG64_FLD( C_CPLT_CTRL0_RESERVED_11A , 11 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_11A ); REG64_FLD( C_CPLT_CTRL0_TC_SKIT_MODE_BIST_DC , 12 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_SKIT_MODE_BIST_DC ); REG64_FLD( C_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC , 13 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC ); REG64_FLD( C_CPLT_CTRL0_TC_UNIT_CONSTRAIN_SAFESCAN_DC , 14 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_CONSTRAIN_SAFESCAN_DC ); REG64_FLD( C_CPLT_CTRL0_TC_UNIT_RRFA_TEST_ENABLE_DC , 15 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_RRFA_TEST_ENABLE_DC ); REG64_FLD( C_CPLT_CTRL0_TC_NBTI_HDR_ENABLE_OVR_DC , 16 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_NBTI_HDR_ENABLE_OVR_DC ); REG64_FLD( C_CPLT_CTRL0_TC_NBTI_PROBE_GATE_DC , 17 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_NBTI_PROBE_GATE_DC ); REG64_FLD( C_CPLT_CTRL0_RESERVED_18A , 18 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_18A ); REG64_FLD( C_CPLT_CTRL0_RESERVED_19A , 19 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_19A ); REG64_FLD( C_CPLT_CTRL0_TC_PSRO_SEL_DC , 20 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PSRO_SEL_DC ); REG64_FLD( C_CPLT_CTRL0_TC_PSRO_SEL_DC_LEN , 8 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PSRO_SEL_DC_LEN ); REG64_FLD( C_CPLT_CTRL0_TC_BSC_WRAPSEL_DC , 28 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_BSC_WRAPSEL_DC ); REG64_FLD( C_CPLT_CTRL0_TC_BSC_INTMODE_DC , 29 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_BSC_INTMODE_DC ); REG64_FLD( C_CPLT_CTRL0_TC_BSC_INV_DC , 30 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_BSC_INV_DC ); REG64_FLD( C_CPLT_CTRL0_TC_BSC_EXTMODE_DC , 31 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_BSC_EXTMODE_DC ); REG64_FLD( C_CPLT_CTRL0_TC_REFCLK_DRVR_EN_DC , 32 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REFCLK_DRVR_EN_DC ); REG64_FLD( C_CPLT_CTRL0_RESERVED_33A , 33 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_33A ); REG64_FLD( C_CPLT_CTRL0_RESERVED_34A , 34 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_34A ); REG64_FLD( C_CPLT_CTRL0_RESERVED_35A , 35 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_35A ); REG64_FLD( C_CPLT_CTRL0_TC_OELCC_EDGE_DELAYED_DC , 36 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_OELCC_EDGE_DELAYED_DC ); REG64_FLD( C_CPLT_CTRL0_TC_OELCC_ALIGN_FLUSH_DC , 37 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_OELCC_ALIGN_FLUSH_DC ); REG64_FLD( C_CPLT_CTRL0_RESERVED_38A , 38 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_38A ); REG64_FLD( C_CPLT_CTRL0_RESERVED_39A , 39 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_39A ); REG64_FLD( C_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC , 40 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_CLKDIV_SEL_DC ); REG64_FLD( C_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC_LEN , 2 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_CLKDIV_SEL_DC_LEN ); REG64_FLD( C_CPLT_CTRL0_RESERVED_42A , 42 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_42A ); REG64_FLD( C_CPLT_CTRL0_RESERVED_43A , 43 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_43A ); REG64_FLD( C_CPLT_CTRL0_CTRL_CC_DCTEST_DC , 44 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_DCTEST_DC ); REG64_FLD( C_CPLT_CTRL0_CTRL_CC_OTP_PRGMODE_DC , 45 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_OTP_PRGMODE_DC ); REG64_FLD( C_CPLT_CTRL0_CTRL_CC_SSS_CALIBRATE_DC , 46 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_SSS_CALIBRATE_DC ); REG64_FLD( C_CPLT_CTRL0_CTRL_CC_PIN_LBIST_DC , 47 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_PIN_LBIST_DC ); REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_48A , 48 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_48A ); REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_49A , 49 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_49A ); REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_50A , 50 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_50A ); REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_51A , 51 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_51A ); REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_52A , 52 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_52A ); REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_53A , 53 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_53A ); REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_54A , 54 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_54A ); REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_55A , 55 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_55A ); REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_56A , 56 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_56A ); REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_57A , 57 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_57A ); REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_58A , 58 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_58A ); REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_59A , 59 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_59A ); REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_60A , 60 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_60A ); REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_61A , 61 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_61A ); REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_62A , 62 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_62A ); REG64_FLD( C_CPLT_CTRL0_FREE_USAGE_63A , 63 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_63A ); REG64_FLD( EQ_CPLT_CTRL1_UNUSED_0B , 0 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_0B ); REG64_FLD( EQ_CPLT_CTRL1_UNUSED_1B , 1 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_1B ); REG64_FLD( EQ_CPLT_CTRL1_UNUSED_2B , 2 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_2B ); REG64_FLD( EQ_CPLT_CTRL1_TC_VITL_REGION_FENCE , 3 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_VITL_REGION_FENCE ); REG64_FLD( EQ_CPLT_CTRL1_TC_PERV_REGION_FENCE , 4 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PERV_REGION_FENCE ); REG64_FLD( EQ_CPLT_CTRL1_TC_REGION1_FENCE , 5 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION1_FENCE ); REG64_FLD( EQ_CPLT_CTRL1_TC_REGION2_FENCE , 6 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION2_FENCE ); REG64_FLD( EQ_CPLT_CTRL1_TC_REGION3_FENCE , 7 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION3_FENCE ); REG64_FLD( EQ_CPLT_CTRL1_TC_REGION4_FENCE , 8 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION4_FENCE ); REG64_FLD( EQ_CPLT_CTRL1_TC_REGION5_FENCE , 9 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION5_FENCE ); REG64_FLD( EQ_CPLT_CTRL1_TC_REGION6_FENCE , 10 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION6_FENCE ); REG64_FLD( EQ_CPLT_CTRL1_TC_REGION7_FENCE , 11 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION7_FENCE ); REG64_FLD( EQ_CPLT_CTRL1_TC_REGION8_FENCE , 12 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION8_FENCE ); REG64_FLD( EQ_CPLT_CTRL1_TC_REGION9_FENCE , 13 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION9_FENCE ); REG64_FLD( EQ_CPLT_CTRL1_UNUSED_14B , 14 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_14B ); REG64_FLD( EQ_CPLT_CTRL1_RESERVED , 15 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED ); REG64_FLD( EQ_CPLT_CTRL1_TC_UNIT_MULTICYCLE_TEST_FENCE , 16 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_MULTICYCLE_TEST_FENCE ); REG64_FLD( EQ_CPLT_CTRL1_UNUSED_17B , 17 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_17B ); REG64_FLD( EQ_CPLT_CTRL1_UNUSED_18B , 18 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_18B ); REG64_FLD( EQ_CPLT_CTRL1_UNUSED_19B , 19 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_19B ); REG64_FLD( EQ_CPLT_CTRL1_UNUSED_20B , 20 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_20B ); REG64_FLD( EQ_CPLT_CTRL1_UNUSED_21B , 21 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_21B ); REG64_FLD( EQ_CPLT_CTRL1_UNUSED_22B , 22 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_22B ); REG64_FLD( EQ_CPLT_CTRL1_UNUSED_23B , 23 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_23B ); REG64_FLD( EQ_CPLT_CTRL1_UNUSED_24B , 24 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_24B ); REG64_FLD( EQ_CPLT_CTRL1_UNUSED_25B , 25 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_25B ); REG64_FLD( EQ_CPLT_CTRL1_UNUSED_26B , 26 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_26B ); REG64_FLD( EQ_CPLT_CTRL1_UNUSED_27B , 27 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_27B ); REG64_FLD( EQ_CPLT_CTRL1_UNUSED_28B , 28 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_28B ); REG64_FLD( EQ_CPLT_CTRL1_UNUSED_29B , 29 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_29B ); REG64_FLD( EQ_CPLT_CTRL1_UNUSED_30B , 30 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_30B ); REG64_FLD( EQ_CPLT_CTRL1_UNUSED_31B , 31 , SH_UNT_EQ , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_31B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_0B , 0 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_0B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_1B , 1 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_1B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_2B , 2 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_2B ); REG64_FLD( EX_CPLT_CTRL1_TC_VITL_REGION_FENCE , 3 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_VITL_REGION_FENCE ); REG64_FLD( EX_CPLT_CTRL1_TC_PERV_REGION_FENCE , 4 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PERV_REGION_FENCE ); REG64_FLD( EX_CPLT_CTRL1_TC_REGION1_FENCE , 5 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION1_FENCE ); REG64_FLD( EX_CPLT_CTRL1_TC_REGION2_FENCE , 6 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION2_FENCE ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_7B , 7 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_7B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_8B , 8 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_8B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_9B , 9 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_9B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_10B , 10 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_10B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_11B , 11 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_11B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_12B , 12 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_12B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_13B , 13 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_13B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_14B , 14 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_14B ); REG64_FLD( EX_CPLT_CTRL1_RESERVED , 15 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED ); REG64_FLD( EX_CPLT_CTRL1_TC_UNIT_MULTICYCLE_TEST_FENCE , 16 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_MULTICYCLE_TEST_FENCE ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_17B , 17 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_17B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_18B , 18 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_18B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_19B , 19 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_19B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_20B , 20 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_20B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_21B , 21 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_21B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_22B , 22 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_22B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_23B , 23 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_23B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_24B , 24 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_24B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_25B , 25 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_25B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_26B , 26 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_26B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_27B , 27 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_27B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_28B , 28 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_28B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_29B , 29 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_29B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_30B , 30 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_30B ); REG64_FLD( EX_CPLT_CTRL1_UNUSED_31B , 31 , SH_UNT_EX , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_31B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_0B , 0 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_0B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_1B , 1 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_1B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_2B , 2 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_2B ); REG64_FLD( C_CPLT_CTRL1_TC_VITL_REGION_FENCE , 3 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_VITL_REGION_FENCE ); REG64_FLD( C_CPLT_CTRL1_TC_PERV_REGION_FENCE , 4 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PERV_REGION_FENCE ); REG64_FLD( C_CPLT_CTRL1_TC_REGION1_FENCE , 5 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION1_FENCE ); REG64_FLD( C_CPLT_CTRL1_TC_REGION2_FENCE , 6 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION2_FENCE ); REG64_FLD( C_CPLT_CTRL1_UNUSED_7B , 7 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_7B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_8B , 8 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_8B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_9B , 9 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_9B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_10B , 10 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_10B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_11B , 11 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_11B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_12B , 12 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_12B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_13B , 13 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_13B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_14B , 14 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_14B ); REG64_FLD( C_CPLT_CTRL1_RESERVED , 15 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED ); REG64_FLD( C_CPLT_CTRL1_TC_UNIT_MULTICYCLE_TEST_FENCE , 16 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_MULTICYCLE_TEST_FENCE ); REG64_FLD( C_CPLT_CTRL1_UNUSED_17B , 17 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_17B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_18B , 18 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_18B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_19B , 19 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_19B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_20B , 20 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_20B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_21B , 21 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_21B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_22B , 22 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_22B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_23B , 23 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_23B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_24B , 24 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_24B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_25B , 25 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_25B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_26B , 26 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_26B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_27B , 27 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_27B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_28B , 28 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_28B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_29B , 29 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_29B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_30B , 30 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_30B ); REG64_FLD( C_CPLT_CTRL1_UNUSED_31B , 31 , SH_UNT_C , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_31B ); REG64_FLD( EQ_CPLT_MASK0_CPLTMASK0 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CPLTMASK0 ); REG64_FLD( EQ_CPLT_MASK0_CPLTMASK0_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CPLTMASK0_LEN ); REG64_FLD( EX_CPLT_MASK0_CPLTMASK0 , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CPLTMASK0 ); REG64_FLD( EX_CPLT_MASK0_CPLTMASK0_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CPLTMASK0_LEN ); REG64_FLD( C_CPLT_MASK0_CPLTMASK0 , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CPLTMASK0 ); REG64_FLD( C_CPLT_MASK0_CPLTMASK0_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CPLTMASK0_LEN ); REG64_FLD( EQ_CPLT_STAT0_SRAM_ABIST_DONE_DC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SRAM_ABIST_DONE_DC ); REG64_FLD( EQ_CPLT_STAT0_DRAM_ABIST_DONE_DC , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DRAM_ABIST_DONE_DC ); REG64_FLD( EQ_CPLT_STAT0_RESERVED_2E , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RESERVED_2E ); REG64_FLD( EQ_CPLT_STAT0_RESERVED_3E , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RESERVED_3E ); REG64_FLD( EQ_CPLT_STAT0_TC_DIAG_PORT0_OUT , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TC_DIAG_PORT0_OUT ); REG64_FLD( EQ_CPLT_STAT0_TC_DIAG_PORT1_OUT , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TC_DIAG_PORT1_OUT ); REG64_FLD( EQ_CPLT_STAT0_RESERVED_6E , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RESERVED_6E ); REG64_FLD( EQ_CPLT_STAT0_PLL_DESTOUT , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PLL_DESTOUT ); REG64_FLD( EQ_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CC_CTRL_OPCG_DONE_DC ); REG64_FLD( EQ_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CC_CTRL_CHIPLET_IS_ALIGNED_DC ); REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_10E , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FREE_USAGE_10E ); REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_11E , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FREE_USAGE_11E ); REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_12E , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FREE_USAGE_12E ); REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_13E , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FREE_USAGE_13E ); REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_14E , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FREE_USAGE_14E ); REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_15E , 15 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FREE_USAGE_15E ); REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_16E , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FREE_USAGE_16E ); REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_17E , 17 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FREE_USAGE_17E ); REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_18E , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FREE_USAGE_18E ); REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_19E , 19 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FREE_USAGE_19E ); REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_20E , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FREE_USAGE_20E ); REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_21E , 21 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FREE_USAGE_21E ); REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_22E , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FREE_USAGE_22E ); REG64_FLD( EQ_CPLT_STAT0_FREE_USAGE_23E , 23 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FREE_USAGE_23E ); REG64_FLD( EX_CPLT_STAT0_SRAM_ABIST_DONE_DC , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SRAM_ABIST_DONE_DC ); REG64_FLD( EX_CPLT_STAT0_DRAM_ABIST_DONE_DC , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DRAM_ABIST_DONE_DC ); REG64_FLD( EX_CPLT_STAT0_RESERVED_2E , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESERVED_2E ); REG64_FLD( EX_CPLT_STAT0_RESERVED_3E , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESERVED_3E ); REG64_FLD( EX_CPLT_STAT0_TC_DIAG_PORT0_OUT , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TC_DIAG_PORT0_OUT ); REG64_FLD( EX_CPLT_STAT0_TC_DIAG_PORT1_OUT , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TC_DIAG_PORT1_OUT ); REG64_FLD( EX_CPLT_STAT0_RESERVED_6E , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESERVED_6E ); REG64_FLD( EX_CPLT_STAT0_PLL_DESTOUT , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PLL_DESTOUT ); REG64_FLD( EX_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CC_CTRL_OPCG_DONE_DC ); REG64_FLD( EX_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CC_CTRL_CHIPLET_IS_ALIGNED_DC ); REG64_FLD( EX_CPLT_STAT0_PC_TC_VALID_NOT_HV_MODE , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PC_TC_VALID_NOT_HV_MODE ); REG64_FLD( EX_CPLT_STAT0_PC_TC_AVP_OUT , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PC_TC_AVP_OUT ); REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_12E , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FREE_USAGE_12E ); REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_13E , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FREE_USAGE_13E ); REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_14E , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FREE_USAGE_14E ); REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_15E , 15 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FREE_USAGE_15E ); REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_16E , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FREE_USAGE_16E ); REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_17E , 17 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FREE_USAGE_17E ); REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_18E , 18 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FREE_USAGE_18E ); REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_19E , 19 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FREE_USAGE_19E ); REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_20E , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FREE_USAGE_20E ); REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_21E , 21 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FREE_USAGE_21E ); REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_22E , 22 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FREE_USAGE_22E ); REG64_FLD( EX_CPLT_STAT0_FREE_USAGE_23E , 23 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FREE_USAGE_23E ); REG64_FLD( C_CPLT_STAT0_SRAM_ABIST_DONE_DC , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SRAM_ABIST_DONE_DC ); REG64_FLD( C_CPLT_STAT0_DRAM_ABIST_DONE_DC , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DRAM_ABIST_DONE_DC ); REG64_FLD( C_CPLT_STAT0_RESERVED_2E , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESERVED_2E ); REG64_FLD( C_CPLT_STAT0_RESERVED_3E , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESERVED_3E ); REG64_FLD( C_CPLT_STAT0_TC_DIAG_PORT0_OUT , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TC_DIAG_PORT0_OUT ); REG64_FLD( C_CPLT_STAT0_TC_DIAG_PORT1_OUT , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TC_DIAG_PORT1_OUT ); REG64_FLD( C_CPLT_STAT0_RESERVED_6E , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESERVED_6E ); REG64_FLD( C_CPLT_STAT0_PLL_DESTOUT , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PLL_DESTOUT ); REG64_FLD( C_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CC_CTRL_OPCG_DONE_DC ); REG64_FLD( C_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CC_CTRL_CHIPLET_IS_ALIGNED_DC ); REG64_FLD( C_CPLT_STAT0_PC_TC_VALID_NOT_HV_MODE , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PC_TC_VALID_NOT_HV_MODE ); REG64_FLD( C_CPLT_STAT0_PC_TC_AVP_OUT , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PC_TC_AVP_OUT ); REG64_FLD( C_CPLT_STAT0_FREE_USAGE_12E , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FREE_USAGE_12E ); REG64_FLD( C_CPLT_STAT0_FREE_USAGE_13E , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FREE_USAGE_13E ); REG64_FLD( C_CPLT_STAT0_FREE_USAGE_14E , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FREE_USAGE_14E ); REG64_FLD( C_CPLT_STAT0_FREE_USAGE_15E , 15 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FREE_USAGE_15E ); REG64_FLD( C_CPLT_STAT0_FREE_USAGE_16E , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FREE_USAGE_16E ); REG64_FLD( C_CPLT_STAT0_FREE_USAGE_17E , 17 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FREE_USAGE_17E ); REG64_FLD( C_CPLT_STAT0_FREE_USAGE_18E , 18 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FREE_USAGE_18E ); REG64_FLD( C_CPLT_STAT0_FREE_USAGE_19E , 19 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FREE_USAGE_19E ); REG64_FLD( C_CPLT_STAT0_FREE_USAGE_20E , 20 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FREE_USAGE_20E ); REG64_FLD( C_CPLT_STAT0_FREE_USAGE_21E , 21 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FREE_USAGE_21E ); REG64_FLD( C_CPLT_STAT0_FREE_USAGE_22E , 22 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FREE_USAGE_22E ); REG64_FLD( C_CPLT_STAT0_FREE_USAGE_23E , 23 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FREE_USAGE_23E ); REG64_FLD( EX_CPPM_CACCR_CLK_SB_STRENGTH , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CLK_SB_STRENGTH ); REG64_FLD( EX_CPPM_CACCR_CLK_SB_STRENGTH_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CLK_SB_STRENGTH_LEN ); REG64_FLD( EX_CPPM_CACCR_CLK_SB_SPARE , 4 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CLK_SB_SPARE ); REG64_FLD( EX_CPPM_CACCR_CLK_SB_PULSE_MODE_EN , 5 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CLK_SB_PULSE_MODE_EN ); REG64_FLD( EX_CPPM_CACCR_CLK_SB_PULSE_MODE , 6 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CLK_SB_PULSE_MODE ); REG64_FLD( EX_CPPM_CACCR_CLK_SB_PULSE_MODE_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CLK_SB_PULSE_MODE_LEN ); REG64_FLD( EX_CPPM_CACCR_CLK_SW_RESCLK , 8 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CLK_SW_RESCLK ); REG64_FLD( EX_CPPM_CACCR_CLK_SW_RESCLK_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CLK_SW_RESCLK_LEN ); REG64_FLD( EX_CPPM_CACCR_CLK_SW_SPARE , 12 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CLK_SW_SPARE ); REG64_FLD( EX_CPPM_CACCR_QUAD_CLK_SB_OVERRIDE , 13 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_QUAD_CLK_SB_OVERRIDE ); REG64_FLD( EX_CPPM_CACCR_QUAD_CLK_SW_OVERRIDE , 14 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_QUAD_CLK_SW_OVERRIDE ); REG64_FLD( EX_CPPM_CACCR_CLK_SYNC_ENABLE , 15 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CLK_SYNC_ENABLE ); REG64_FLD( C_CPPM_CACCR_CLK_SB_STRENGTH , 0 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CLK_SB_STRENGTH ); REG64_FLD( C_CPPM_CACCR_CLK_SB_STRENGTH_LEN , 4 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CLK_SB_STRENGTH_LEN ); REG64_FLD( C_CPPM_CACCR_CLK_SB_SPARE , 4 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CLK_SB_SPARE ); REG64_FLD( C_CPPM_CACCR_CLK_SB_PULSE_MODE_EN , 5 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CLK_SB_PULSE_MODE_EN ); REG64_FLD( C_CPPM_CACCR_CLK_SB_PULSE_MODE , 6 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CLK_SB_PULSE_MODE ); REG64_FLD( C_CPPM_CACCR_CLK_SB_PULSE_MODE_LEN , 2 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CLK_SB_PULSE_MODE_LEN ); REG64_FLD( C_CPPM_CACCR_CLK_SW_RESCLK , 8 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CLK_SW_RESCLK ); REG64_FLD( C_CPPM_CACCR_CLK_SW_RESCLK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CLK_SW_RESCLK_LEN ); REG64_FLD( C_CPPM_CACCR_CLK_SW_SPARE , 12 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CLK_SW_SPARE ); REG64_FLD( C_CPPM_CACCR_QUAD_CLK_SB_OVERRIDE , 13 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_QUAD_CLK_SB_OVERRIDE ); REG64_FLD( C_CPPM_CACCR_QUAD_CLK_SW_OVERRIDE , 14 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_QUAD_CLK_SW_OVERRIDE ); REG64_FLD( C_CPPM_CACCR_CLK_SYNC_ENABLE , 15 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CLK_SYNC_ENABLE ); REG64_FLD( EX_CPPM_CACSR_ACTUAL_CLK_SB_STRENGTH , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_CLK_SB_STRENGTH ); REG64_FLD( EX_CPPM_CACSR_ACTUAL_CLK_SB_STRENGTH_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_CLK_SB_STRENGTH_LEN ); REG64_FLD( EX_CPPM_CACSR_ACTUAL_CLK_SB_SPARE , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_CLK_SB_SPARE ); REG64_FLD( EX_CPPM_CACSR_ACTUAL_CLK_SB_PULSE_MODE_EN , 5 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_CLK_SB_PULSE_MODE_EN ); REG64_FLD( EX_CPPM_CACSR_ACTUAL_CLK_SB_PULSE_MODE , 6 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_CLK_SB_PULSE_MODE ); REG64_FLD( EX_CPPM_CACSR_ACTUAL_CLK_SB_PULSE_MODE_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_CLK_SB_PULSE_MODE_LEN ); REG64_FLD( EX_CPPM_CACSR_ACTUAL_CLK_SW_RESCLK , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_CLK_SW_RESCLK ); REG64_FLD( EX_CPPM_CACSR_ACTUAL_CLK_SW_RESCLK_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_CLK_SW_RESCLK_LEN ); REG64_FLD( EX_CPPM_CACSR_ACTUAL_CLK_SW_SPARE , 12 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_CLK_SW_SPARE ); REG64_FLD( EX_CPPM_CACSR_CLK_SYNC_DONE , 13 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_CLK_SYNC_DONE ); REG64_FLD( C_CPPM_CACSR_ACTUAL_CLK_SB_STRENGTH , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_CLK_SB_STRENGTH ); REG64_FLD( C_CPPM_CACSR_ACTUAL_CLK_SB_STRENGTH_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_CLK_SB_STRENGTH_LEN ); REG64_FLD( C_CPPM_CACSR_ACTUAL_CLK_SB_SPARE , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_CLK_SB_SPARE ); REG64_FLD( C_CPPM_CACSR_ACTUAL_CLK_SB_PULSE_MODE_EN , 5 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_CLK_SB_PULSE_MODE_EN ); REG64_FLD( C_CPPM_CACSR_ACTUAL_CLK_SB_PULSE_MODE , 6 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_CLK_SB_PULSE_MODE ); REG64_FLD( C_CPPM_CACSR_ACTUAL_CLK_SB_PULSE_MODE_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_CLK_SB_PULSE_MODE_LEN ); REG64_FLD( C_CPPM_CACSR_ACTUAL_CLK_SW_RESCLK , 8 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_CLK_SW_RESCLK ); REG64_FLD( C_CPPM_CACSR_ACTUAL_CLK_SW_RESCLK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_CLK_SW_RESCLK_LEN ); REG64_FLD( C_CPPM_CACSR_ACTUAL_CLK_SW_SPARE , 12 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_CLK_SW_SPARE ); REG64_FLD( C_CPPM_CACSR_CLK_SYNC_DONE , 13 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_CLK_SYNC_DONE ); REG64_FLD( EX_CPPM_CIIR_MSGSND_INTR_INJECT , 28 , SH_UNT_EX , SH_ACS_SCOM_4P , SH_FLD_MSGSND_INTR_INJECT ); REG64_FLD( EX_CPPM_CIIR_MSGSND_INTR_INJECT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_4P , SH_FLD_MSGSND_INTR_INJECT_LEN ); REG64_FLD( C_CPPM_CIIR_MSGSND_INTR_INJECT , 28 , SH_UNT_C , SH_ACS_SCOM_4P , SH_FLD_MSGSND_INTR_INJECT ); REG64_FLD( C_CPPM_CIIR_MSGSND_INTR_INJECT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_4P , SH_FLD_MSGSND_INTR_INJECT_LEN ); REG64_FLD( EX_CPPM_CISR_HYP_INTR_PRESENT , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HYP_INTR_PRESENT ); REG64_FLD( EX_CPPM_CISR_HYP_INTR_PRESENT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HYP_INTR_PRESENT_LEN ); REG64_FLD( EX_CPPM_CISR_OS_INTR_PRESENT , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_OS_INTR_PRESENT ); REG64_FLD( EX_CPPM_CISR_OS_INTR_PRESENT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_OS_INTR_PRESENT_LEN ); REG64_FLD( EX_CPPM_CISR_MSGSND_INTR_PRESENT , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MSGSND_INTR_PRESENT ); REG64_FLD( EX_CPPM_CISR_MSGSND_INTR_PRESENT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MSGSND_INTR_PRESENT_LEN ); REG64_FLD( EX_CPPM_CISR_EBB_INTR_PRESENT , 12 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_EBB_INTR_PRESENT ); REG64_FLD( EX_CPPM_CISR_EBB_INTR_PRESENT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_EBB_INTR_PRESENT_LEN ); REG64_FLD( EX_CPPM_CISR_HYP_INTR_REQUESTED , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HYP_INTR_REQUESTED ); REG64_FLD( EX_CPPM_CISR_HYP_INTR_REQUESTED_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HYP_INTR_REQUESTED_LEN ); REG64_FLD( EX_CPPM_CISR_OS_INTR_REQUESTED , 20 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_OS_INTR_REQUESTED ); REG64_FLD( EX_CPPM_CISR_OS_INTR_REQUESTED_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_OS_INTR_REQUESTED_LEN ); REG64_FLD( EX_CPPM_CISR_MSGSND_INTR_REQUESTED , 24 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MSGSND_INTR_REQUESTED ); REG64_FLD( EX_CPPM_CISR_MSGSND_INTR_REQUESTED_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MSGSND_INTR_REQUESTED_LEN ); REG64_FLD( EX_CPPM_CISR_MSGSND_INTR_SAMPLE , 28 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MSGSND_INTR_SAMPLE ); REG64_FLD( EX_CPPM_CISR_MSGSND_INTR_SAMPLE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MSGSND_INTR_SAMPLE_LEN ); REG64_FLD( EX_CPPM_CISR_MSGSND_ACK , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MSGSND_ACK ); REG64_FLD( EX_CPPM_CISR_MALF_ALERT_PRESENT , 33 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MALF_ALERT_PRESENT ); REG64_FLD( EX_CPPM_CISR_MALF_ALERT_REQUESTED , 34 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MALF_ALERT_REQUESTED ); REG64_FLD( EX_CPPM_CISR_CME_SPECIAL_WKUP_DONE , 35 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_CME_SPECIAL_WKUP_DONE ); REG64_FLD( C_CPPM_CISR_HYP_INTR_PRESENT , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_HYP_INTR_PRESENT ); REG64_FLD( C_CPPM_CISR_HYP_INTR_PRESENT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_HYP_INTR_PRESENT_LEN ); REG64_FLD( C_CPPM_CISR_OS_INTR_PRESENT , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_OS_INTR_PRESENT ); REG64_FLD( C_CPPM_CISR_OS_INTR_PRESENT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_OS_INTR_PRESENT_LEN ); REG64_FLD( C_CPPM_CISR_MSGSND_INTR_PRESENT , 8 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_MSGSND_INTR_PRESENT ); REG64_FLD( C_CPPM_CISR_MSGSND_INTR_PRESENT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_MSGSND_INTR_PRESENT_LEN ); REG64_FLD( C_CPPM_CISR_EBB_INTR_PRESENT , 12 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_EBB_INTR_PRESENT ); REG64_FLD( C_CPPM_CISR_EBB_INTR_PRESENT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_EBB_INTR_PRESENT_LEN ); REG64_FLD( C_CPPM_CISR_HYP_INTR_REQUESTED , 16 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_HYP_INTR_REQUESTED ); REG64_FLD( C_CPPM_CISR_HYP_INTR_REQUESTED_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_HYP_INTR_REQUESTED_LEN ); REG64_FLD( C_CPPM_CISR_OS_INTR_REQUESTED , 20 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_OS_INTR_REQUESTED ); REG64_FLD( C_CPPM_CISR_OS_INTR_REQUESTED_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_OS_INTR_REQUESTED_LEN ); REG64_FLD( C_CPPM_CISR_MSGSND_INTR_REQUESTED , 24 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_MSGSND_INTR_REQUESTED ); REG64_FLD( C_CPPM_CISR_MSGSND_INTR_REQUESTED_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_MSGSND_INTR_REQUESTED_LEN ); REG64_FLD( C_CPPM_CISR_MSGSND_INTR_SAMPLE , 28 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_MSGSND_INTR_SAMPLE ); REG64_FLD( C_CPPM_CISR_MSGSND_INTR_SAMPLE_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_MSGSND_INTR_SAMPLE_LEN ); REG64_FLD( C_CPPM_CISR_MSGSND_ACK , 32 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_MSGSND_ACK ); REG64_FLD( C_CPPM_CISR_MALF_ALERT_PRESENT , 33 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_MALF_ALERT_PRESENT ); REG64_FLD( C_CPPM_CISR_MALF_ALERT_REQUESTED , 34 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_MALF_ALERT_REQUESTED ); REG64_FLD( C_CPPM_CISR_CME_SPECIAL_WKUP_DONE , 35 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_CME_SPECIAL_WKUP_DONE ); REG64_FLD( EX_CPPM_CIVRMLCR_IVRM_LOCAL_CONTROL , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_IVRM_LOCAL_CONTROL ); REG64_FLD( EX_CPPM_CIVRMLCR_RESERVED_1_2 , 1 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_RESERVED_1_2 ); REG64_FLD( EX_CPPM_CIVRMLCR_RESERVED_1_2_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_RESERVED_1_2_LEN ); REG64_FLD( EX_CPPM_CIVRMLCR_IVRM_UREG_TEST_EN , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_IVRM_UREG_TEST_EN ); REG64_FLD( EX_CPPM_CIVRMLCR_IVRM_UREG_TEST_ID , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_IVRM_UREG_TEST_ID ); REG64_FLD( EX_CPPM_CIVRMLCR_IVRM_UREG_TEST_ID_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_IVRM_UREG_TEST_ID_LEN ); REG64_FLD( C_CPPM_CIVRMLCR_IVRM_LOCAL_CONTROL , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_IVRM_LOCAL_CONTROL ); REG64_FLD( C_CPPM_CIVRMLCR_RESERVED_1_2 , 1 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RESERVED_1_2 ); REG64_FLD( C_CPPM_CIVRMLCR_RESERVED_1_2_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RESERVED_1_2_LEN ); REG64_FLD( C_CPPM_CIVRMLCR_IVRM_UREG_TEST_EN , 3 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_IVRM_UREG_TEST_EN ); REG64_FLD( C_CPPM_CIVRMLCR_IVRM_UREG_TEST_ID , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_IVRM_UREG_TEST_ID ); REG64_FLD( C_CPPM_CIVRMLCR_IVRM_UREG_TEST_ID_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_IVRM_UREG_TEST_ID_LEN ); REG64_FLD( EX_CPPM_CMEDATA_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_DATA ); REG64_FLD( EX_CPPM_CMEDATA_DATA_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_DATA_LEN ); REG64_FLD( C_CPPM_CMEDATA_DATA , 0 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_DATA ); REG64_FLD( C_CPPM_CMEDATA_DATA_LEN , 32 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_DATA_LEN ); REG64_FLD( EX_CPPM_CMEDB0_CME_MESSAGE_NUMBER0 , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_NUMBER0 ); REG64_FLD( EX_CPPM_CMEDB0_CME_MESSAGE_NUMBER0_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_NUMBER0_LEN ); REG64_FLD( EX_CPPM_CMEDB0_CME_MESSAGE_HI , 8 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_HI ); REG64_FLD( EX_CPPM_CMEDB0_CME_MESSAGE_HI_LEN , 56 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_HI_LEN ); REG64_FLD( C_CPPM_CMEDB0_CME_MESSAGE_NUMBER0 , 0 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_NUMBER0 ); REG64_FLD( C_CPPM_CMEDB0_CME_MESSAGE_NUMBER0_LEN , 8 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_NUMBER0_LEN ); REG64_FLD( C_CPPM_CMEDB0_CME_MESSAGE_HI , 8 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_HI ); REG64_FLD( C_CPPM_CMEDB0_CME_MESSAGE_HI_LEN , 56 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_HI_LEN ); REG64_FLD( EX_CPPM_CMEDB1_CME_MESSAGE_NUMBER_N , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_NUMBER_N ); REG64_FLD( EX_CPPM_CMEDB1_CME_MESSAGE_NUMBER_N_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_NUMBER_N_LEN ); REG64_FLD( C_CPPM_CMEDB1_CME_MESSAGE_NUMBER_N , 0 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_NUMBER_N ); REG64_FLD( C_CPPM_CMEDB1_CME_MESSAGE_NUMBER_N_LEN , 8 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_NUMBER_N_LEN ); REG64_FLD( EX_CPPM_CMEDB2_CME_MESSAGE_NUMBER_N , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_NUMBER_N ); REG64_FLD( EX_CPPM_CMEDB2_CME_MESSAGE_NUMBER_N_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_NUMBER_N_LEN ); REG64_FLD( C_CPPM_CMEDB2_CME_MESSAGE_NUMBER_N , 0 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_NUMBER_N ); REG64_FLD( C_CPPM_CMEDB2_CME_MESSAGE_NUMBER_N_LEN , 8 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_NUMBER_N_LEN ); REG64_FLD( EX_CPPM_CMEDB3_CME_MESSAGE_NUMBER_N , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_NUMBER_N ); REG64_FLD( EX_CPPM_CMEDB3_CME_MESSAGE_NUMBER_N_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_NUMBER_N_LEN ); REG64_FLD( EX_CPPM_CMEDB3_CME_MESSAGE_HI , 8 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_HI ); REG64_FLD( EX_CPPM_CMEDB3_CME_MESSAGE_HI_LEN , 56 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_HI_LEN ); REG64_FLD( C_CPPM_CMEDB3_CME_MESSAGE_NUMBER_N , 0 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_NUMBER_N ); REG64_FLD( C_CPPM_CMEDB3_CME_MESSAGE_NUMBER_N_LEN , 8 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_NUMBER_N_LEN ); REG64_FLD( C_CPPM_CMEDB3_CME_MESSAGE_HI , 8 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_HI ); REG64_FLD( C_CPPM_CMEDB3_CME_MESSAGE_HI_LEN , 56 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CME_MESSAGE_HI_LEN ); REG64_FLD( EX_CPPM_CMEMSG_CME_MESSAGE , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_CME_MESSAGE ); REG64_FLD( EX_CPPM_CMEMSG_CME_MESSAGE_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_CME_MESSAGE_LEN ); REG64_FLD( C_CPPM_CMEMSG_CME_MESSAGE , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_CME_MESSAGE ); REG64_FLD( C_CPPM_CMEMSG_CME_MESSAGE_LEN , 64 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_CME_MESSAGE_LEN ); REG64_FLD( EX_CPPM_CPMMR_PPM_WRITE_DISABLE , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PPM_WRITE_DISABLE ); REG64_FLD( EX_CPPM_CPMMR_PPM_WRITE_OVERRIDE , 1 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PPM_WRITE_OVERRIDE ); REG64_FLD( EX_CPPM_CPMMR_RESERVED_2_9 , 2 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_2_9 ); REG64_FLD( EX_CPPM_CPMMR_RESERVED_2_9_LEN , 7 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_2_9_LEN ); REG64_FLD( EX_CPPM_CPMMR_FUSED_CORE_MODE , 9 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_FUSED_CORE_MODE ); REG64_FLD( EX_CPPM_CPMMR_STOP_EXIT_TYPE_SEL , 10 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_STOP_EXIT_TYPE_SEL ); REG64_FLD( EX_CPPM_CPMMR_BLOCK_INTR_INPUTS , 11 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_BLOCK_INTR_INPUTS ); REG64_FLD( EX_CPPM_CPMMR_CME_ERR_NOTIFY_DIS , 12 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CME_ERR_NOTIFY_DIS ); REG64_FLD( EX_CPPM_CPMMR_WKUP_NOTIFY_SELECT , 13 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_WKUP_NOTIFY_SELECT ); REG64_FLD( EX_CPPM_CPMMR_ENABLE_PECE , 14 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_ENABLE_PECE ); REG64_FLD( EX_CPPM_CPMMR_CME_SPECIAL_WKUP_DONE_DIS , 15 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CME_SPECIAL_WKUP_DONE_DIS ); REG64_FLD( C_CPPM_CPMMR_PPM_WRITE_DISABLE , 0 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PPM_WRITE_DISABLE ); REG64_FLD( C_CPPM_CPMMR_PPM_WRITE_OVERRIDE , 1 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PPM_WRITE_OVERRIDE ); REG64_FLD( C_CPPM_CPMMR_RESERVED_2_9 , 2 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_2_9 ); REG64_FLD( C_CPPM_CPMMR_RESERVED_2_9_LEN , 7 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_2_9_LEN ); REG64_FLD( C_CPPM_CPMMR_FUSED_CORE_MODE , 9 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_FUSED_CORE_MODE ); REG64_FLD( C_CPPM_CPMMR_STOP_EXIT_TYPE_SEL , 10 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_STOP_EXIT_TYPE_SEL ); REG64_FLD( C_CPPM_CPMMR_BLOCK_INTR_INPUTS , 11 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_BLOCK_INTR_INPUTS ); REG64_FLD( C_CPPM_CPMMR_CME_ERR_NOTIFY_DIS , 12 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CME_ERR_NOTIFY_DIS ); REG64_FLD( C_CPPM_CPMMR_WKUP_NOTIFY_SELECT , 13 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_WKUP_NOTIFY_SELECT ); REG64_FLD( C_CPPM_CPMMR_ENABLE_PECE , 14 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_ENABLE_PECE ); REG64_FLD( C_CPPM_CPMMR_CME_SPECIAL_WKUP_DONE_DIS , 15 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CME_SPECIAL_WKUP_DONE_DIS ); REG64_FLD( EX_CPPM_CSAR_SCRATCH_ATOMIC_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SCRATCH_ATOMIC_DATA ); REG64_FLD( EX_CPPM_CSAR_SCRATCH_ATOMIC_DATA_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SCRATCH_ATOMIC_DATA_LEN ); REG64_FLD( C_CPPM_CSAR_SCRATCH_ATOMIC_DATA , 0 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SCRATCH_ATOMIC_DATA ); REG64_FLD( C_CPPM_CSAR_SCRATCH_ATOMIC_DATA_LEN , 32 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SCRATCH_ATOMIC_DATA_LEN ); REG64_FLD( EX_CPPM_ERR_PCB_INTERRUPT_PROTOCOL , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PCB_INTERRUPT_PROTOCOL ); REG64_FLD( EX_CPPM_ERR_SPECIAL_WKUP_PROTOCOL , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SPECIAL_WKUP_PROTOCOL ); REG64_FLD( EX_CPPM_ERR_SPECIAL_WKUP_DONE_PROTOCOL , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SPECIAL_WKUP_DONE_PROTOCOL ); REG64_FLD( EX_CPPM_ERR_PFET_SEQ_PROGRAM , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PFET_SEQ_PROGRAM ); REG64_FLD( EX_CPPM_ERR_CLK_SYNC , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CLK_SYNC ); REG64_FLD( EX_CPPM_ERR_PECE_INTR_DISABLED , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PECE_INTR_DISABLED ); REG64_FLD( EX_CPPM_ERR_DECONFIGURED_INTR , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DECONFIGURED_INTR ); REG64_FLD( EX_CPPM_ERR_RESERVED_7 , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESERVED_7 ); REG64_FLD( EX_CPPM_ERR_RESERVED_8_11 , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESERVED_8_11 ); REG64_FLD( EX_CPPM_ERR_RESERVED_8_11_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESERVED_8_11_LEN ); REG64_FLD( C_CPPM_ERR_PCB_INTERRUPT_PROTOCOL , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_INTERRUPT_PROTOCOL ); REG64_FLD( C_CPPM_ERR_SPECIAL_WKUP_PROTOCOL , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SPECIAL_WKUP_PROTOCOL ); REG64_FLD( C_CPPM_ERR_SPECIAL_WKUP_DONE_PROTOCOL , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SPECIAL_WKUP_DONE_PROTOCOL ); REG64_FLD( C_CPPM_ERR_PFET_SEQ_PROGRAM , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PFET_SEQ_PROGRAM ); REG64_FLD( C_CPPM_ERR_CLK_SYNC , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CLK_SYNC ); REG64_FLD( C_CPPM_ERR_PECE_INTR_DISABLED , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PECE_INTR_DISABLED ); REG64_FLD( C_CPPM_ERR_DECONFIGURED_INTR , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DECONFIGURED_INTR ); REG64_FLD( C_CPPM_ERR_RESERVED_7 , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESERVED_7 ); REG64_FLD( C_CPPM_ERR_RESERVED_8_11 , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESERVED_8_11 ); REG64_FLD( C_CPPM_ERR_RESERVED_8_11_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESERVED_8_11_LEN ); REG64_FLD( EX_CPPM_ERRMSK_RESERVED_0_11 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_11 ); REG64_FLD( EX_CPPM_ERRMSK_RESERVED_0_11_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_11_LEN ); REG64_FLD( C_CPPM_ERRMSK_RESERVED_0_11 , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_11 ); REG64_FLD( C_CPPM_ERRMSK_RESERVED_0_11_LEN , 12 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_11_LEN ); REG64_FLD( EX_CPPM_IPPMCMD_QPPM_REG , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_QPPM_REG ); REG64_FLD( EX_CPPM_IPPMCMD_QPPM_REG_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_QPPM_REG_LEN ); REG64_FLD( EX_CPPM_IPPMCMD_QPPM_RNW , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_QPPM_RNW ); REG64_FLD( EX_CPPM_IPPMCMD_RESERVED_9 , 9 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_RESERVED_9 ); REG64_FLD( C_CPPM_IPPMCMD_QPPM_REG , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_QPPM_REG ); REG64_FLD( C_CPPM_IPPMCMD_QPPM_REG_LEN , 8 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_QPPM_REG_LEN ); REG64_FLD( C_CPPM_IPPMCMD_QPPM_RNW , 8 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_QPPM_RNW ); REG64_FLD( C_CPPM_IPPMCMD_RESERVED_9 , 9 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RESERVED_9 ); REG64_FLD( EX_CPPM_IPPMRDATA_QPPM_RDATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_QPPM_RDATA ); REG64_FLD( EX_CPPM_IPPMRDATA_QPPM_RDATA_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_QPPM_RDATA_LEN ); REG64_FLD( C_CPPM_IPPMRDATA_QPPM_RDATA , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_QPPM_RDATA ); REG64_FLD( C_CPPM_IPPMRDATA_QPPM_RDATA_LEN , 64 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_QPPM_RDATA_LEN ); REG64_FLD( EX_CPPM_IPPMSTAT_QPPM_ONGOING , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_QPPM_ONGOING ); REG64_FLD( EX_CPPM_IPPMSTAT_QPPM_STATUS , 1 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_QPPM_STATUS ); REG64_FLD( EX_CPPM_IPPMSTAT_QPPM_STATUS_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_QPPM_STATUS_LEN ); REG64_FLD( C_CPPM_IPPMSTAT_QPPM_ONGOING , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_QPPM_ONGOING ); REG64_FLD( C_CPPM_IPPMSTAT_QPPM_STATUS , 1 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_QPPM_STATUS ); REG64_FLD( C_CPPM_IPPMSTAT_QPPM_STATUS_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_QPPM_STATUS_LEN ); REG64_FLD( EX_CPPM_IPPMWDATA_QPPM_WDATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_QPPM_WDATA ); REG64_FLD( EX_CPPM_IPPMWDATA_QPPM_WDATA_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_QPPM_WDATA_LEN ); REG64_FLD( C_CPPM_IPPMWDATA_QPPM_WDATA , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_QPPM_WDATA ); REG64_FLD( C_CPPM_IPPMWDATA_QPPM_WDATA_LEN , 64 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_QPPM_WDATA_LEN ); REG64_FLD( EX_CPPM_NC0INDIR_NC_N_INDIRECT , 0 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_NC_N_INDIRECT ); REG64_FLD( EX_CPPM_NC0INDIR_NC_N_INDIRECT_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_NC_N_INDIRECT_LEN ); REG64_FLD( C_CPPM_NC0INDIR_NC_N_INDIRECT , 0 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_NC_N_INDIRECT ); REG64_FLD( C_CPPM_NC0INDIR_NC_N_INDIRECT_LEN , 32 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_NC_N_INDIRECT_LEN ); REG64_FLD( EX_CPPM_NC1INDIR_NC_N_INDIRECT , 0 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_NC_N_INDIRECT ); REG64_FLD( EX_CPPM_NC1INDIR_NC_N_INDIRECT_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_NC_N_INDIRECT_LEN ); REG64_FLD( C_CPPM_NC1INDIR_NC_N_INDIRECT , 0 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_NC_N_INDIRECT ); REG64_FLD( C_CPPM_NC1INDIR_NC_N_INDIRECT_LEN , 32 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_NC_N_INDIRECT_LEN ); REG64_FLD( EX_CPPM_PECES_PECE_T0 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_PECE_T0 ); REG64_FLD( EX_CPPM_PECES_PECE_T0_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_PECE_T0_LEN ); REG64_FLD( EX_CPPM_PECES_PECE_T1 , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_PECE_T1 ); REG64_FLD( EX_CPPM_PECES_PECE_T1_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_PECE_T1_LEN ); REG64_FLD( EX_CPPM_PECES_PECE_T2 , 16 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_PECE_T2 ); REG64_FLD( EX_CPPM_PECES_PECE_T2_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_PECE_T2_LEN ); REG64_FLD( EX_CPPM_PECES_PECE_T3 , 24 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_PECE_T3 ); REG64_FLD( EX_CPPM_PECES_PECE_T3_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_PECE_T3_LEN ); REG64_FLD( EX_CPPM_PECES_USE_PECE , 32 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_USE_PECE ); REG64_FLD( EX_CPPM_PECES_USE_PECE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_USE_PECE_LEN ); REG64_FLD( C_CPPM_PECES_PECE_T0 , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PECE_T0 ); REG64_FLD( C_CPPM_PECES_PECE_T0_LEN , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PECE_T0_LEN ); REG64_FLD( C_CPPM_PECES_PECE_T1 , 8 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PECE_T1 ); REG64_FLD( C_CPPM_PECES_PECE_T1_LEN , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PECE_T1_LEN ); REG64_FLD( C_CPPM_PECES_PECE_T2 , 16 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PECE_T2 ); REG64_FLD( C_CPPM_PECES_PECE_T2_LEN , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PECE_T2_LEN ); REG64_FLD( C_CPPM_PECES_PECE_T3 , 24 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PECE_T3 ); REG64_FLD( C_CPPM_PECES_PECE_T3_LEN , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PECE_T3_LEN ); REG64_FLD( C_CPPM_PECES_USE_PECE , 32 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_USE_PECE ); REG64_FLD( C_CPPM_PECES_USE_PECE_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_USE_PECE_LEN ); REG64_FLD( EX_CPPM_PERRSUM_ERROR , 0 , SH_UNT_EX , SH_ACS_SCOM_WCLEAR, SH_FLD_ERROR ); REG64_FLD( C_CPPM_PERRSUM_ERROR , 0 , SH_UNT_C , SH_ACS_SCOM_WCLEAR, SH_FLD_ERROR ); REG64_FLD( EQ_CSAR_SRAM_ADDRESS , 16 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SRAM_ADDRESS ); REG64_FLD( EQ_CSAR_SRAM_ADDRESS_LEN , 13 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SRAM_ADDRESS_LEN ); REG64_FLD( EX_CSAR_SRAM_ADDRESS , 16 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SRAM_ADDRESS ); REG64_FLD( EX_CSAR_SRAM_ADDRESS_LEN , 13 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SRAM_ADDRESS_LEN ); REG64_FLD( EQ_CSCR_SRAM_ACCESS_MODE , 0 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_SRAM_ACCESS_MODE ); REG64_FLD( EQ_CSCR_SRAM_SCRUB_ENABLE , 1 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_SRAM_SCRUB_ENABLE ); REG64_FLD( EQ_CSCR_ECC_CORRECT_DIS , 2 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_ECC_CORRECT_DIS ); REG64_FLD( EQ_CSCR_ECC_DETECT_DIS , 3 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_ECC_DETECT_DIS ); REG64_FLD( EQ_CSCR_ECC_INJECT_TYPE , 4 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_ECC_INJECT_TYPE ); REG64_FLD( EQ_CSCR_ECC_INJECT_ERR , 5 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_ECC_INJECT_ERR ); REG64_FLD( EQ_CSCR_SPARE_6_7 , 6 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_SPARE_6_7 ); REG64_FLD( EQ_CSCR_SPARE_6_7_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_SPARE_6_7_LEN ); REG64_FLD( EQ_CSCR_SRAM_SCRUB_INDEX , 47 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_SRAM_SCRUB_INDEX ); REG64_FLD( EQ_CSCR_SRAM_SCRUB_INDEX_LEN , 13 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_SRAM_SCRUB_INDEX_LEN ); REG64_FLD( EX_CSCR_SRAM_ACCESS_MODE , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SRAM_ACCESS_MODE ); REG64_FLD( EX_CSCR_SRAM_SCRUB_ENABLE , 1 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SRAM_SCRUB_ENABLE ); REG64_FLD( EX_CSCR_ECC_CORRECT_DIS , 2 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_ECC_CORRECT_DIS ); REG64_FLD( EX_CSCR_ECC_DETECT_DIS , 3 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_ECC_DETECT_DIS ); REG64_FLD( EX_CSCR_ECC_INJECT_TYPE , 4 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_ECC_INJECT_TYPE ); REG64_FLD( EX_CSCR_ECC_INJECT_ERR , 5 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_ECC_INJECT_ERR ); REG64_FLD( EX_CSCR_SPARE_6_7 , 6 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_6_7 ); REG64_FLD( EX_CSCR_SPARE_6_7_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_6_7_LEN ); REG64_FLD( EX_CSCR_SRAM_SCRUB_INDEX , 47 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SRAM_SCRUB_INDEX ); REG64_FLD( EX_CSCR_SRAM_SCRUB_INDEX_LEN , 13 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SRAM_SCRUB_INDEX_LEN ); REG64_FLD( EQ_CSDR_SRAM_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SRAM_DATA ); REG64_FLD( EQ_CSDR_SRAM_DATA_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SRAM_DATA_LEN ); REG64_FLD( EX_CSDR_SRAM_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SRAM_DATA ); REG64_FLD( EX_CSDR_SRAM_DATA_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SRAM_DATA_LEN ); REG64_FLD( EX_L2_CTRL_T0_RUN_Q , 48 , SH_UNT_EX_L2 , SH_ACS_SCOM_NC , SH_FLD_T0_RUN_Q ); REG64_FLD( EX_L2_CTRL_T1_RUN_Q , 49 , SH_UNT_EX_L2 , SH_ACS_SCOM_NC , SH_FLD_T1_RUN_Q ); REG64_FLD( EX_L2_CTRL_T2_RUN_Q , 50 , SH_UNT_EX_L2 , SH_ACS_SCOM_NC , SH_FLD_T2_RUN_Q ); REG64_FLD( EX_L2_CTRL_T3_RUN_Q , 51 , SH_UNT_EX_L2 , SH_ACS_SCOM_NC , SH_FLD_T3_RUN_Q ); REG64_FLD( EX_L2_CTRL_T4_RUN_Q , 52 , SH_UNT_EX_L2 , SH_ACS_SCOM_NC , SH_FLD_T4_RUN_Q ); REG64_FLD( EX_L2_CTRL_T5_RUN_Q , 53 , SH_UNT_EX_L2 , SH_ACS_SCOM_NC , SH_FLD_T5_RUN_Q ); REG64_FLD( EX_L2_CTRL_T6_RUN_Q , 54 , SH_UNT_EX_L2 , SH_ACS_SCOM_NC , SH_FLD_T6_RUN_Q ); REG64_FLD( EX_L2_CTRL_T7_RUN_Q , 55 , SH_UNT_EX_L2 , SH_ACS_SCOM_NC , SH_FLD_T7_RUN_Q ); REG64_FLD( EX_L2_CTRL_RUN_LATCH , 63 , SH_UNT_EX_L2 , SH_ACS_SCOM_NC , SH_FLD_RUN_LATCH ); REG64_FLD( C_CTRL_T0_RUN_Q , 48 , SH_UNT_C , SH_ACS_SCOM_NC , SH_FLD_T0_RUN_Q ); REG64_FLD( C_CTRL_T1_RUN_Q , 49 , SH_UNT_C , SH_ACS_SCOM_NC , SH_FLD_T1_RUN_Q ); REG64_FLD( C_CTRL_T2_RUN_Q , 50 , SH_UNT_C , SH_ACS_SCOM_NC , SH_FLD_T2_RUN_Q ); REG64_FLD( C_CTRL_T3_RUN_Q , 51 , SH_UNT_C , SH_ACS_SCOM_NC , SH_FLD_T3_RUN_Q ); REG64_FLD( C_CTRL_T4_RUN_Q , 52 , SH_UNT_C , SH_ACS_SCOM_NC , SH_FLD_T4_RUN_Q ); REG64_FLD( C_CTRL_T5_RUN_Q , 53 , SH_UNT_C , SH_ACS_SCOM_NC , SH_FLD_T5_RUN_Q ); REG64_FLD( C_CTRL_T6_RUN_Q , 54 , SH_UNT_C , SH_ACS_SCOM_NC , SH_FLD_T6_RUN_Q ); REG64_FLD( C_CTRL_T7_RUN_Q , 55 , SH_UNT_C , SH_ACS_SCOM_NC , SH_FLD_T7_RUN_Q ); REG64_FLD( C_CTRL_RUN_LATCH , 63 , SH_UNT_C , SH_ACS_SCOM_NC , SH_FLD_RUN_LATCH ); REG64_FLD( EQ_CTRL_ATOMIC_LOCK_REG_ENABLE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( EQ_CTRL_ATOMIC_LOCK_REG_ID , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ID ); REG64_FLD( EQ_CTRL_ATOMIC_LOCK_REG_ID_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ID_LEN ); REG64_FLD( EQ_CTRL_ATOMIC_LOCK_REG_ACTIVITY , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACTIVITY ); REG64_FLD( EQ_CTRL_ATOMIC_LOCK_REG_ACTIVITY_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACTIVITY_LEN ); REG64_FLD( EX_CTRL_ATOMIC_LOCK_REG_ENABLE , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( EX_CTRL_ATOMIC_LOCK_REG_ID , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ID ); REG64_FLD( EX_CTRL_ATOMIC_LOCK_REG_ID_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ID_LEN ); REG64_FLD( EX_CTRL_ATOMIC_LOCK_REG_ACTIVITY , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACTIVITY ); REG64_FLD( EX_CTRL_ATOMIC_LOCK_REG_ACTIVITY_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACTIVITY_LEN ); REG64_FLD( C_CTRL_ATOMIC_LOCK_REG_ENABLE , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( C_CTRL_ATOMIC_LOCK_REG_ID , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ID ); REG64_FLD( C_CTRL_ATOMIC_LOCK_REG_ID_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ID_LEN ); REG64_FLD( C_CTRL_ATOMIC_LOCK_REG_ACTIVITY , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACTIVITY ); REG64_FLD( C_CTRL_ATOMIC_LOCK_REG_ACTIVITY_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACTIVITY_LEN ); REG64_FLD( EQ_CTRL_PROTECT_MODE_REG_READ_ENABLE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_READ_ENABLE ); REG64_FLD( EQ_CTRL_PROTECT_MODE_REG_WRITE_ENABLE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WRITE_ENABLE ); REG64_FLD( EX_CTRL_PROTECT_MODE_REG_READ_ENABLE , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_READ_ENABLE ); REG64_FLD( EX_CTRL_PROTECT_MODE_REG_WRITE_ENABLE , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WRITE_ENABLE ); REG64_FLD( C_CTRL_PROTECT_MODE_REG_READ_ENABLE , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_READ_ENABLE ); REG64_FLD( C_CTRL_PROTECT_MODE_REG_WRITE_ENABLE , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WRITE_ENABLE ); REG64_FLD( EQ_DBG_CBS_CC_RESET_EP , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RESET_EP ); REG64_FLD( EQ_DBG_CBS_CC_OPCG_IP , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_OPCG_IP ); REG64_FLD( EQ_DBG_CBS_CC_VITL_CLKOFF , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_VITL_CLKOFF ); REG64_FLD( EQ_DBG_CBS_CC_TEST_ENABLE , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TEST_ENABLE ); REG64_FLD( EQ_DBG_CBS_CC_REQ , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_REQ ); REG64_FLD( EQ_DBG_CBS_CC_CMD , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMD ); REG64_FLD( EQ_DBG_CBS_CC_CMD_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMD_LEN ); REG64_FLD( EQ_DBG_CBS_CC_STATE , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATE ); REG64_FLD( EQ_DBG_CBS_CC_STATE_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STATE_LEN ); REG64_FLD( EQ_DBG_CBS_CC_SECURITY_DEBUG_MODE , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SECURITY_DEBUG_MODE ); REG64_FLD( EQ_DBG_CBS_CC_PROTOCOL_ERROR , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PROTOCOL_ERROR ); REG64_FLD( EQ_DBG_CBS_CC_PCB_IDLE , 15 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PCB_IDLE ); REG64_FLD( EQ_DBG_CBS_CC_CURRENT_OPCG_MODE , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CURRENT_OPCG_MODE ); REG64_FLD( EQ_DBG_CBS_CC_CURRENT_OPCG_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CURRENT_OPCG_MODE_LEN ); REG64_FLD( EQ_DBG_CBS_CC_LAST_OPCG_MODE , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LAST_OPCG_MODE ); REG64_FLD( EQ_DBG_CBS_CC_LAST_OPCG_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LAST_OPCG_MODE_LEN ); REG64_FLD( EQ_DBG_CBS_CC_PCB_ERROR , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PCB_ERROR ); REG64_FLD( EQ_DBG_CBS_CC_PARITY_ERROR , 25 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PARITY_ERROR ); REG64_FLD( EQ_DBG_CBS_CC_ERROR , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR ); REG64_FLD( EQ_DBG_CBS_CC_CHIPLET_IS_ALIGNED , 27 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CHIPLET_IS_ALIGNED ); REG64_FLD( EQ_DBG_CBS_CC_PCB_REQUEST_SINCE_RESET , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PCB_REQUEST_SINCE_RESET ); REG64_FLD( EQ_DBG_CBS_CC_PARANOIA_TEST_ENABLE_CHANGE , 29 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PARANOIA_TEST_ENABLE_CHANGE ); REG64_FLD( EQ_DBG_CBS_CC_PARANOIA_VITL_CLKOFF_CHANGE , 30 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PARANOIA_VITL_CLKOFF_CHANGE ); REG64_FLD( EQ_DBG_CBS_CC_TP_TPFSI_ACK , 31 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TP_TPFSI_ACK ); REG64_FLD( EX_DBG_CBS_CC_RESET_EP , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESET_EP ); REG64_FLD( EX_DBG_CBS_CC_OPCG_IP , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_OPCG_IP ); REG64_FLD( EX_DBG_CBS_CC_VITL_CLKOFF , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_VITL_CLKOFF ); REG64_FLD( EX_DBG_CBS_CC_TEST_ENABLE , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TEST_ENABLE ); REG64_FLD( EX_DBG_CBS_CC_REQ , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_REQ ); REG64_FLD( EX_DBG_CBS_CC_CMD , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CMD ); REG64_FLD( EX_DBG_CBS_CC_CMD_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CMD_LEN ); REG64_FLD( EX_DBG_CBS_CC_STATE , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATE ); REG64_FLD( EX_DBG_CBS_CC_STATE_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STATE_LEN ); REG64_FLD( EX_DBG_CBS_CC_SECURITY_DEBUG_MODE , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SECURITY_DEBUG_MODE ); REG64_FLD( EX_DBG_CBS_CC_PROTOCOL_ERROR , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PROTOCOL_ERROR ); REG64_FLD( EX_DBG_CBS_CC_PCB_IDLE , 15 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PCB_IDLE ); REG64_FLD( EX_DBG_CBS_CC_CURRENT_OPCG_MODE , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CURRENT_OPCG_MODE ); REG64_FLD( EX_DBG_CBS_CC_CURRENT_OPCG_MODE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CURRENT_OPCG_MODE_LEN ); REG64_FLD( EX_DBG_CBS_CC_LAST_OPCG_MODE , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_LAST_OPCG_MODE ); REG64_FLD( EX_DBG_CBS_CC_LAST_OPCG_MODE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_LAST_OPCG_MODE_LEN ); REG64_FLD( EX_DBG_CBS_CC_PCB_ERROR , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PCB_ERROR ); REG64_FLD( EX_DBG_CBS_CC_PARITY_ERROR , 25 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PARITY_ERROR ); REG64_FLD( EX_DBG_CBS_CC_ERROR , 26 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ERROR ); REG64_FLD( EX_DBG_CBS_CC_CHIPLET_IS_ALIGNED , 27 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CHIPLET_IS_ALIGNED ); REG64_FLD( EX_DBG_CBS_CC_PCB_REQUEST_SINCE_RESET , 28 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PCB_REQUEST_SINCE_RESET ); REG64_FLD( EX_DBG_CBS_CC_PARANOIA_TEST_ENABLE_CHANGE , 29 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PARANOIA_TEST_ENABLE_CHANGE ); REG64_FLD( EX_DBG_CBS_CC_PARANOIA_VITL_CLKOFF_CHANGE , 30 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PARANOIA_VITL_CLKOFF_CHANGE ); REG64_FLD( EX_DBG_CBS_CC_TP_TPFSI_ACK , 31 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TP_TPFSI_ACK ); REG64_FLD( C_DBG_CBS_CC_RESET_EP , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESET_EP ); REG64_FLD( C_DBG_CBS_CC_OPCG_IP , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_OPCG_IP ); REG64_FLD( C_DBG_CBS_CC_VITL_CLKOFF , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_VITL_CLKOFF ); REG64_FLD( C_DBG_CBS_CC_TEST_ENABLE , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TEST_ENABLE ); REG64_FLD( C_DBG_CBS_CC_REQ , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_REQ ); REG64_FLD( C_DBG_CBS_CC_CMD , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CMD ); REG64_FLD( C_DBG_CBS_CC_CMD_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CMD_LEN ); REG64_FLD( C_DBG_CBS_CC_STATE , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATE ); REG64_FLD( C_DBG_CBS_CC_STATE_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STATE_LEN ); REG64_FLD( C_DBG_CBS_CC_SECURITY_DEBUG_MODE , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SECURITY_DEBUG_MODE ); REG64_FLD( C_DBG_CBS_CC_PROTOCOL_ERROR , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PROTOCOL_ERROR ); REG64_FLD( C_DBG_CBS_CC_PCB_IDLE , 15 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_IDLE ); REG64_FLD( C_DBG_CBS_CC_CURRENT_OPCG_MODE , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CURRENT_OPCG_MODE ); REG64_FLD( C_DBG_CBS_CC_CURRENT_OPCG_MODE_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CURRENT_OPCG_MODE_LEN ); REG64_FLD( C_DBG_CBS_CC_LAST_OPCG_MODE , 20 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LAST_OPCG_MODE ); REG64_FLD( C_DBG_CBS_CC_LAST_OPCG_MODE_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LAST_OPCG_MODE_LEN ); REG64_FLD( C_DBG_CBS_CC_PCB_ERROR , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_ERROR ); REG64_FLD( C_DBG_CBS_CC_PARITY_ERROR , 25 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PARITY_ERROR ); REG64_FLD( C_DBG_CBS_CC_ERROR , 26 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ERROR ); REG64_FLD( C_DBG_CBS_CC_CHIPLET_IS_ALIGNED , 27 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CHIPLET_IS_ALIGNED ); REG64_FLD( C_DBG_CBS_CC_PCB_REQUEST_SINCE_RESET , 28 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_REQUEST_SINCE_RESET ); REG64_FLD( C_DBG_CBS_CC_PARANOIA_TEST_ENABLE_CHANGE , 29 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PARANOIA_TEST_ENABLE_CHANGE ); REG64_FLD( C_DBG_CBS_CC_PARANOIA_VITL_CLKOFF_CHANGE , 30 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PARANOIA_VITL_CLKOFF_CHANGE ); REG64_FLD( C_DBG_CBS_CC_TP_TPFSI_ACK , 31 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TP_TPFSI_ACK ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_UNUSED , 36 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_UNUSED_2 , 43 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED_2 ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED_2_LEN ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( EQ_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); REG64_FLD( EX_DBG_INST1_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); REG64_FLD( EX_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); REG64_FLD( EX_DBG_INST1_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); REG64_FLD( EX_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); REG64_FLD( EX_DBG_INST1_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); REG64_FLD( EX_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); REG64_FLD( EX_DBG_INST1_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); REG64_FLD( EX_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); REG64_FLD( EX_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); REG64_FLD( EX_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); REG64_FLD( EX_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); REG64_FLD( EX_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); REG64_FLD( EX_DBG_INST1_COND_REG_1_UNUSED , 36 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( EX_DBG_INST1_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( EX_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); REG64_FLD( EX_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); REG64_FLD( EX_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); REG64_FLD( EX_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); REG64_FLD( EX_DBG_INST1_COND_REG_1_UNUSED_2 , 43 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED_2 ); REG64_FLD( EX_DBG_INST1_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED_2_LEN ); REG64_FLD( EX_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); REG64_FLD( EX_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); REG64_FLD( EX_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); REG64_FLD( EX_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); REG64_FLD( EX_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); REG64_FLD( EX_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); REG64_FLD( EX_DBG_INST1_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( EX_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); REG64_FLD( EX_DBG_INST1_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( EX_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); REG64_FLD( EX_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( EX_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); REG64_FLD( C_DBG_INST1_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); REG64_FLD( C_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); REG64_FLD( C_DBG_INST1_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); REG64_FLD( C_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); REG64_FLD( C_DBG_INST1_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); REG64_FLD( C_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); REG64_FLD( C_DBG_INST1_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); REG64_FLD( C_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); REG64_FLD( C_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); REG64_FLD( C_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); REG64_FLD( C_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); REG64_FLD( C_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); REG64_FLD( C_DBG_INST1_COND_REG_1_UNUSED , 36 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( C_DBG_INST1_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( C_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); REG64_FLD( C_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); REG64_FLD( C_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); REG64_FLD( C_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); REG64_FLD( C_DBG_INST1_COND_REG_1_UNUSED_2 , 43 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED_2 ); REG64_FLD( C_DBG_INST1_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED_2_LEN ); REG64_FLD( C_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); REG64_FLD( C_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); REG64_FLD( C_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); REG64_FLD( C_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); REG64_FLD( C_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); REG64_FLD( C_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); REG64_FLD( C_DBG_INST1_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( C_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); REG64_FLD( C_DBG_INST1_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( C_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); REG64_FLD( C_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( C_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); REG64_FLD( EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A ); REG64_FLD( EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); REG64_FLD( EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); REG64_FLD( EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( EQ_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); REG64_FLD( EQ_DBG_INST1_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TO_CMP_LT ); REG64_FLD( EQ_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TO_CMP_LT_LEN ); REG64_FLD( EQ_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); REG64_FLD( EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A ); REG64_FLD( EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); REG64_FLD( EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); REG64_FLD( EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( EX_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); REG64_FLD( EX_DBG_INST1_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TO_CMP_LT ); REG64_FLD( EX_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TO_CMP_LT_LEN ); REG64_FLD( EX_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); REG64_FLD( C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A ); REG64_FLD( C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); REG64_FLD( C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); REG64_FLD( C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( C_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); REG64_FLD( C_DBG_INST1_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TO_CMP_LT ); REG64_FLD( C_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TO_CMP_LT_LEN ); REG64_FLD( C_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); REG64_FLD( EQ_DBG_INST1_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT ); REG64_FLD( EQ_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT_LEN ); REG64_FLD( EX_DBG_INST1_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT ); REG64_FLD( EX_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT_LEN ); REG64_FLD( C_DBG_INST1_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT ); REG64_FLD( C_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT_LEN ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_UNUSED , 36 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_UNUSED_2 , 43 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED_2 ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED_2_LEN ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( EQ_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); REG64_FLD( EX_DBG_INST2_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); REG64_FLD( EX_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); REG64_FLD( EX_DBG_INST2_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); REG64_FLD( EX_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); REG64_FLD( EX_DBG_INST2_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); REG64_FLD( EX_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); REG64_FLD( EX_DBG_INST2_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); REG64_FLD( EX_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); REG64_FLD( EX_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); REG64_FLD( EX_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); REG64_FLD( EX_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); REG64_FLD( EX_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); REG64_FLD( EX_DBG_INST2_COND_REG_1_UNUSED , 36 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( EX_DBG_INST2_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( EX_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); REG64_FLD( EX_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); REG64_FLD( EX_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); REG64_FLD( EX_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); REG64_FLD( EX_DBG_INST2_COND_REG_1_UNUSED_2 , 43 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED_2 ); REG64_FLD( EX_DBG_INST2_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED_2_LEN ); REG64_FLD( EX_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); REG64_FLD( EX_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); REG64_FLD( EX_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); REG64_FLD( EX_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); REG64_FLD( EX_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); REG64_FLD( EX_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); REG64_FLD( EX_DBG_INST2_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( EX_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); REG64_FLD( EX_DBG_INST2_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( EX_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); REG64_FLD( EX_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( EX_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); REG64_FLD( C_DBG_INST2_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); REG64_FLD( C_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); REG64_FLD( C_DBG_INST2_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); REG64_FLD( C_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); REG64_FLD( C_DBG_INST2_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); REG64_FLD( C_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); REG64_FLD( C_DBG_INST2_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); REG64_FLD( C_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); REG64_FLD( C_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); REG64_FLD( C_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); REG64_FLD( C_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); REG64_FLD( C_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); REG64_FLD( C_DBG_INST2_COND_REG_1_UNUSED , 36 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( C_DBG_INST2_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( C_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); REG64_FLD( C_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); REG64_FLD( C_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); REG64_FLD( C_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); REG64_FLD( C_DBG_INST2_COND_REG_1_UNUSED_2 , 43 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED_2 ); REG64_FLD( C_DBG_INST2_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED_2_LEN ); REG64_FLD( C_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); REG64_FLD( C_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); REG64_FLD( C_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); REG64_FLD( C_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); REG64_FLD( C_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); REG64_FLD( C_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); REG64_FLD( C_DBG_INST2_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( C_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); REG64_FLD( C_DBG_INST2_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( C_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); REG64_FLD( C_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( C_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); REG64_FLD( EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A ); REG64_FLD( EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); REG64_FLD( EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); REG64_FLD( EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( EQ_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); REG64_FLD( EQ_DBG_INST2_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TO_CMP_LT ); REG64_FLD( EQ_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TO_CMP_LT_LEN ); REG64_FLD( EQ_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); REG64_FLD( EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A ); REG64_FLD( EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); REG64_FLD( EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); REG64_FLD( EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( EX_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); REG64_FLD( EX_DBG_INST2_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TO_CMP_LT ); REG64_FLD( EX_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TO_CMP_LT_LEN ); REG64_FLD( EX_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); REG64_FLD( C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A ); REG64_FLD( C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); REG64_FLD( C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); REG64_FLD( C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( C_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); REG64_FLD( C_DBG_INST2_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TO_CMP_LT ); REG64_FLD( C_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TO_CMP_LT_LEN ); REG64_FLD( C_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); REG64_FLD( EQ_DBG_INST2_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT ); REG64_FLD( EQ_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT_LEN ); REG64_FLD( EX_DBG_INST2_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT ); REG64_FLD( EX_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT_LEN ); REG64_FLD( C_DBG_INST2_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT ); REG64_FLD( C_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT_LEN ); REG64_FLD( EQ_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( EQ_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); REG64_FLD( EQ_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); REG64_FLD( EQ_DBG_MODE_REG_TRACE_SEL_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRACE_SEL_LEN ); REG64_FLD( EQ_DBG_MODE_REG_TRIG_SEL , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); REG64_FLD( EQ_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG_SEL_LEN ); REG64_FLD( EQ_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( EQ_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STOP_ON_RECOV_ERR_SELECTION ); REG64_FLD( EQ_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( EQ_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); REG64_FLD( EQ_DBG_MODE_REG_SYNC_BRCST , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SYNC_BRCST ); REG64_FLD( EQ_DBG_MODE_REG_SYNC_BRCST_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SYNC_BRCST_LEN ); REG64_FLD( EX_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( EX_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); REG64_FLD( EX_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); REG64_FLD( EX_DBG_MODE_REG_TRACE_SEL_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRACE_SEL_LEN ); REG64_FLD( EX_DBG_MODE_REG_TRIG_SEL , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); REG64_FLD( EX_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG_SEL_LEN ); REG64_FLD( EX_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( EX_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STOP_ON_RECOV_ERR_SELECTION ); REG64_FLD( EX_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( EX_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); REG64_FLD( EX_DBG_MODE_REG_SYNC_BRCST , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SYNC_BRCST ); REG64_FLD( EX_DBG_MODE_REG_SYNC_BRCST_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SYNC_BRCST_LEN ); REG64_FLD( C_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( C_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); REG64_FLD( C_DBG_MODE_REG_TRACE_SEL , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); REG64_FLD( C_DBG_MODE_REG_TRACE_SEL_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRACE_SEL_LEN ); REG64_FLD( C_DBG_MODE_REG_TRIG_SEL , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); REG64_FLD( C_DBG_MODE_REG_TRIG_SEL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIG_SEL_LEN ); REG64_FLD( C_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( C_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STOP_ON_RECOV_ERR_SELECTION ); REG64_FLD( C_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( C_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); REG64_FLD( C_DBG_MODE_REG_SYNC_BRCST , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SYNC_BRCST ); REG64_FLD( C_DBG_MODE_REG_SYNC_BRCST_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SYNC_BRCST_LEN ); REG64_FLD( EQ_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE ); REG64_FLD( EQ_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN ); REG64_FLD( EQ_DBG_TRACE_MODE_REG_2_IMM_FREEZE , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IMM_FREEZE ); REG64_FLD( EQ_DBG_TRACE_MODE_REG_2_STOP_ON_ERR , 17 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STOP_ON_ERR ); REG64_FLD( EQ_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_BANK_ON_RUNN_MATCH ); REG64_FLD( EQ_DBG_TRACE_MODE_REG_2_FORCE_TEST , 19 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FORCE_TEST ); REG64_FLD( EQ_DBG_TRACE_MODE_REG_2_ACCUM_HIST , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACCUM_HIST ); REG64_FLD( EQ_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ , 21 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FRZ_COUNT_ON_FRZ ); REG64_FLD( EX_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE ); REG64_FLD( EX_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN ); REG64_FLD( EX_DBG_TRACE_MODE_REG_2_IMM_FREEZE , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IMM_FREEZE ); REG64_FLD( EX_DBG_TRACE_MODE_REG_2_STOP_ON_ERR , 17 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STOP_ON_ERR ); REG64_FLD( EX_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH , 18 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_BANK_ON_RUNN_MATCH ); REG64_FLD( EX_DBG_TRACE_MODE_REG_2_FORCE_TEST , 19 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FORCE_TEST ); REG64_FLD( EX_DBG_TRACE_MODE_REG_2_ACCUM_HIST , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACCUM_HIST ); REG64_FLD( EX_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ , 21 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FRZ_COUNT_ON_FRZ ); REG64_FLD( C_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE ); REG64_FLD( C_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN ); REG64_FLD( C_DBG_TRACE_MODE_REG_2_IMM_FREEZE , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IMM_FREEZE ); REG64_FLD( C_DBG_TRACE_MODE_REG_2_STOP_ON_ERR , 17 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STOP_ON_ERR ); REG64_FLD( C_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH , 18 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_BANK_ON_RUNN_MATCH ); REG64_FLD( C_DBG_TRACE_MODE_REG_2_FORCE_TEST , 19 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FORCE_TEST ); REG64_FLD( C_DBG_TRACE_MODE_REG_2_ACCUM_HIST , 20 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACCUM_HIST ); REG64_FLD( C_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ , 21 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FRZ_COUNT_ON_FRZ ); REG64_FLD( EQ_DBG_TRACE_REG_0_INST1_COND3_ENABLE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_COND3_ENABLE ); REG64_FLD( EQ_DBG_TRACE_REG_0_INST2_COND3_ENABLE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_COND3_ENABLE ); REG64_FLD( EQ_DBG_TRACE_REG_0_INST3_COND3_ENABLE , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST3_COND3_ENABLE ); REG64_FLD( EQ_DBG_TRACE_REG_0_INST4_COND3_ENABLE , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST4_COND3_ENABLE ); REG64_FLD( EQ_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_SLOW_LFSR_MODE ); REG64_FLD( EQ_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_SLOW_LFSR_MODE ); REG64_FLD( EQ_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST3_SLOW_LFSR_MODE ); REG64_FLD( EQ_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST4_SLOW_LFSR_MODE ); REG64_FLD( EQ_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_TRIG_SEL ); REG64_FLD( EQ_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN ); REG64_FLD( EQ_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_TRIG_SEL ); REG64_FLD( EQ_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN ); REG64_FLD( EQ_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL ); REG64_FLD( EQ_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN ); REG64_FLD( EQ_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_TRIG_SEL ); REG64_FLD( EQ_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN ); REG64_FLD( EQ_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_TRIG_SEL ); REG64_FLD( EQ_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN ); REG64_FLD( EQ_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL ); REG64_FLD( EQ_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN ); REG64_FLD( EQ_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXT_TRIG_ON_STOP ); REG64_FLD( EQ_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE , 33 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXT_TRIG_ON_FREEZE ); REG64_FLD( EQ_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL , 34 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CORE_RAS0_TRIG_SEL ); REG64_FLD( EQ_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CORE_RAS0_TRIG_SEL_LEN ); REG64_FLD( EQ_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL , 39 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CORE_RAS1_TRIG_SEL ); REG64_FLD( EQ_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CORE_RAS1_TRIG_SEL_LEN ); REG64_FLD( EQ_DBG_TRACE_REG_0_PC_TP_TRIG_SEL , 44 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PC_TP_TRIG_SEL ); REG64_FLD( EQ_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PC_TP_TRIG_SEL_LEN ); REG64_FLD( EQ_DBG_TRACE_REG_0_ARM_SEL , 46 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ARM_SEL ); REG64_FLD( EQ_DBG_TRACE_REG_0_ARM_SEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ARM_SEL_LEN ); REG64_FLD( EQ_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL , 50 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_LEVEL_SEL ); REG64_FLD( EQ_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_LEVEL_SEL_LEN ); REG64_FLD( EQ_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL , 54 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_LEVEL_SEL ); REG64_FLD( EQ_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_LEVEL_SEL_LEN ); REG64_FLD( EX_DBG_TRACE_REG_0_INST1_COND3_ENABLE , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_COND3_ENABLE ); REG64_FLD( EX_DBG_TRACE_REG_0_INST2_COND3_ENABLE , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_COND3_ENABLE ); REG64_FLD( EX_DBG_TRACE_REG_0_INST3_COND3_ENABLE , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST3_COND3_ENABLE ); REG64_FLD( EX_DBG_TRACE_REG_0_INST4_COND3_ENABLE , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST4_COND3_ENABLE ); REG64_FLD( EX_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_SLOW_LFSR_MODE ); REG64_FLD( EX_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_SLOW_LFSR_MODE ); REG64_FLD( EX_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST3_SLOW_LFSR_MODE ); REG64_FLD( EX_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST4_SLOW_LFSR_MODE ); REG64_FLD( EX_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_TRIG_SEL ); REG64_FLD( EX_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN ); REG64_FLD( EX_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_TRIG_SEL ); REG64_FLD( EX_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN ); REG64_FLD( EX_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL ); REG64_FLD( EX_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN ); REG64_FLD( EX_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_TRIG_SEL ); REG64_FLD( EX_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN ); REG64_FLD( EX_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_TRIG_SEL ); REG64_FLD( EX_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN ); REG64_FLD( EX_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL , 18 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL ); REG64_FLD( EX_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN ); REG64_FLD( EX_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP , 32 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EXT_TRIG_ON_STOP ); REG64_FLD( EX_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE , 33 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EXT_TRIG_ON_FREEZE ); REG64_FLD( EX_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL , 34 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CORE_RAS0_TRIG_SEL ); REG64_FLD( EX_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CORE_RAS0_TRIG_SEL_LEN ); REG64_FLD( EX_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL , 39 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CORE_RAS1_TRIG_SEL ); REG64_FLD( EX_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CORE_RAS1_TRIG_SEL_LEN ); REG64_FLD( EX_DBG_TRACE_REG_0_PC_TP_TRIG_SEL , 44 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PC_TP_TRIG_SEL ); REG64_FLD( EX_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PC_TP_TRIG_SEL_LEN ); REG64_FLD( EX_DBG_TRACE_REG_0_ARM_SEL , 46 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ARM_SEL ); REG64_FLD( EX_DBG_TRACE_REG_0_ARM_SEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ARM_SEL_LEN ); REG64_FLD( EX_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL , 50 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG0_LEVEL_SEL ); REG64_FLD( EX_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG0_LEVEL_SEL_LEN ); REG64_FLD( EX_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL , 54 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG1_LEVEL_SEL ); REG64_FLD( EX_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG1_LEVEL_SEL_LEN ); REG64_FLD( C_DBG_TRACE_REG_0_INST1_COND3_ENABLE , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_COND3_ENABLE ); REG64_FLD( C_DBG_TRACE_REG_0_INST2_COND3_ENABLE , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_COND3_ENABLE ); REG64_FLD( C_DBG_TRACE_REG_0_INST3_COND3_ENABLE , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST3_COND3_ENABLE ); REG64_FLD( C_DBG_TRACE_REG_0_INST4_COND3_ENABLE , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST4_COND3_ENABLE ); REG64_FLD( C_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_SLOW_LFSR_MODE ); REG64_FLD( C_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_SLOW_LFSR_MODE ); REG64_FLD( C_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST3_SLOW_LFSR_MODE ); REG64_FLD( C_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST4_SLOW_LFSR_MODE ); REG64_FLD( C_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_TRIG_SEL ); REG64_FLD( C_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN ); REG64_FLD( C_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_TRIG_SEL ); REG64_FLD( C_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN ); REG64_FLD( C_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL ); REG64_FLD( C_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN ); REG64_FLD( C_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_TRIG_SEL ); REG64_FLD( C_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN ); REG64_FLD( C_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_TRIG_SEL ); REG64_FLD( C_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN ); REG64_FLD( C_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL , 18 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL ); REG64_FLD( C_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN ); REG64_FLD( C_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP , 32 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_EXT_TRIG_ON_STOP ); REG64_FLD( C_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE , 33 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_EXT_TRIG_ON_FREEZE ); REG64_FLD( C_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL , 34 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CORE_RAS0_TRIG_SEL ); REG64_FLD( C_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CORE_RAS0_TRIG_SEL_LEN ); REG64_FLD( C_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL , 39 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CORE_RAS1_TRIG_SEL ); REG64_FLD( C_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CORE_RAS1_TRIG_SEL_LEN ); REG64_FLD( C_DBG_TRACE_REG_0_PC_TP_TRIG_SEL , 44 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PC_TP_TRIG_SEL ); REG64_FLD( C_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PC_TP_TRIG_SEL_LEN ); REG64_FLD( C_DBG_TRACE_REG_0_ARM_SEL , 46 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ARM_SEL ); REG64_FLD( C_DBG_TRACE_REG_0_ARM_SEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ARM_SEL_LEN ); REG64_FLD( C_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL , 50 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIG0_LEVEL_SEL ); REG64_FLD( C_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIG0_LEVEL_SEL_LEN ); REG64_FLD( C_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL , 54 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIG1_LEVEL_SEL ); REG64_FLD( C_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIG1_LEVEL_SEL_LEN ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_DO ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_DO_LEN ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_DO ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_DO_LEN ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_DO ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_DO ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_DO_LEN ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_DO ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_DO_LEN ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_DO ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_WAITN ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN , 25 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_WAITN ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN , 27 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_WAITN ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_WAITN ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN , 29 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK , 36 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_BANK ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK , 37 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_BANK ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK , 38 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK , 39 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_BANK ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK , 40 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_BANK ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK , 41 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT , 48 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_LT ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR , 51 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT , 52 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_LT ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN ); REG64_FLD( EQ_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR ); REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_DO ); REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_DO_LEN ); REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_DO ); REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_DO_LEN ); REG64_FLD( EX_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_DO ); REG64_FLD( EX_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN ); REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_DO ); REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_DO_LEN ); REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_DO ); REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_DO_LEN ); REG64_FLD( EX_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_DO ); REG64_FLD( EX_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN ); REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_WAITN ); REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN , 25 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_WAITN ); REG64_FLD( EX_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN , 26 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN ); REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN , 27 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_WAITN ); REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN , 28 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_WAITN ); REG64_FLD( EX_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN , 29 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN ); REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK , 36 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_BANK ); REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK , 37 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_BANK ); REG64_FLD( EX_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK , 38 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK ); REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK , 39 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_BANK ); REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK , 40 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_BANK ); REG64_FLD( EX_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK , 41 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK ); REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT , 48 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_LT ); REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN ); REG64_FLD( EX_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR , 51 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR ); REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT , 52 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_LT ); REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN ); REG64_FLD( EX_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR ); REG64_FLD( C_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_DO ); REG64_FLD( C_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_DO_LEN ); REG64_FLD( C_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_DO ); REG64_FLD( C_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_DO_LEN ); REG64_FLD( C_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_DO ); REG64_FLD( C_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN ); REG64_FLD( C_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_DO ); REG64_FLD( C_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_DO_LEN ); REG64_FLD( C_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_DO ); REG64_FLD( C_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_DO_LEN ); REG64_FLD( C_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_DO ); REG64_FLD( C_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN ); REG64_FLD( C_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_WAITN ); REG64_FLD( C_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN , 25 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_WAITN ); REG64_FLD( C_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN , 26 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN ); REG64_FLD( C_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN , 27 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_WAITN ); REG64_FLD( C_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN , 28 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_WAITN ); REG64_FLD( C_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN , 29 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN ); REG64_FLD( C_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK , 36 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_BANK ); REG64_FLD( C_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK , 37 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_BANK ); REG64_FLD( C_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK , 38 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK ); REG64_FLD( C_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK , 39 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_BANK ); REG64_FLD( C_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK , 40 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_BANK ); REG64_FLD( C_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK , 41 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK ); REG64_FLD( C_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT , 48 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_LT ); REG64_FLD( C_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN ); REG64_FLD( C_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR , 51 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR ); REG64_FLD( C_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT , 52 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_LT ); REG64_FLD( C_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN ); REG64_FLD( C_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR ); REG64_FLD( EQ_DEBUG_TRACE_CONTROL_SCOM_TRACE_START , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SCOM_TRACE_START ); REG64_FLD( EQ_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SCOM_TRACE_STOP ); REG64_FLD( EQ_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SCOM_TRACE_RESET ); REG64_FLD( EX_DEBUG_TRACE_CONTROL_SCOM_TRACE_START , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SCOM_TRACE_START ); REG64_FLD( EX_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SCOM_TRACE_STOP ); REG64_FLD( EX_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SCOM_TRACE_RESET ); REG64_FLD( C_DEBUG_TRACE_CONTROL_SCOM_TRACE_START , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SCOM_TRACE_START ); REG64_FLD( C_DEBUG_TRACE_CONTROL_SCOM_TRACE_STOP , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SCOM_TRACE_STOP ); REG64_FLD( C_DEBUG_TRACE_CONTROL_SCOM_TRACE_RESET , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SCOM_TRACE_RESET ); REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T0_CLEAR_MAINT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DC_T0_CLEAR_MAINT ); REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T0_SRESET_REQUEST , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DC_T0_SRESET_REQUEST ); REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T0_CORE_STEP , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DC_T0_CORE_STEP ); REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T0_CORE_START , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DC_T0_CORE_START ); REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T0_CORE_STOP , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DC_T0_CORE_STOP ); REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T1_CLEAR_MAINT , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DC_T1_CLEAR_MAINT ); REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T1_SRESET_REQUEST , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DC_T1_SRESET_REQUEST ); REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T1_CORE_STEP , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DC_T1_CORE_STEP ); REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T1_CORE_START , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DC_T1_CORE_START ); REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T1_CORE_STOP , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DC_T1_CORE_STOP ); REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T2_CLEAR_MAINT , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DC_T2_CLEAR_MAINT ); REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T2_SRESET_REQUEST , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DC_T2_SRESET_REQUEST ); REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T2_CORE_STEP , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DC_T2_CORE_STEP ); REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T2_CORE_START , 22 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DC_T2_CORE_START ); REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T2_CORE_STOP , 23 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DC_T2_CORE_STOP ); REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T3_CLEAR_MAINT , 27 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DC_T3_CLEAR_MAINT ); REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T3_SRESET_REQUEST , 28 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DC_T3_SRESET_REQUEST ); REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T3_CORE_STEP , 29 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DC_T3_CORE_STEP ); REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T3_CORE_START , 30 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DC_T3_CORE_START ); REG64_FLD( EX_L2_DIRECT_CONTROLS_DC_T3_CORE_STOP , 31 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DC_T3_CORE_STOP ); REG64_FLD( EX_L2_DIRECT_CONTROLS_WRITE_T0_PM_STATE , 32 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_WRITE_T0_PM_STATE ); REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T0_PLS , 33 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PSSCR_T0_PLS ); REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T0_PLS_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PSSCR_T0_PLS_LEN ); REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T0_SRR1 , 37 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PSSCR_T0_SRR1 ); REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T0_SRR1_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PSSCR_T0_SRR1_LEN ); REG64_FLD( EX_L2_DIRECT_CONTROLS_WRITE_T1_PM_STATE , 40 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_WRITE_T1_PM_STATE ); REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T1_PLS , 41 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PSSCR_T1_PLS ); REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T1_PLS_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PSSCR_T1_PLS_LEN ); REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T1_SRR1 , 45 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PSSCR_T1_SRR1 ); REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T1_SRR1_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PSSCR_T1_SRR1_LEN ); REG64_FLD( EX_L2_DIRECT_CONTROLS_WRITE_T2_PM_STATE , 48 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_WRITE_T2_PM_STATE ); REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T2_PLS , 49 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PSSCR_T2_PLS ); REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T2_PLS_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PSSCR_T2_PLS_LEN ); REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T2_SRR1 , 53 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PSSCR_T2_SRR1 ); REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T2_SRR1_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PSSCR_T2_SRR1_LEN ); REG64_FLD( EX_L2_DIRECT_CONTROLS_WRITE_T3_PM_STATE , 56 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_WRITE_T3_PM_STATE ); REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T3_PLS , 57 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PSSCR_T3_PLS ); REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T3_PLS_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PSSCR_T3_PLS_LEN ); REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T3_SRR1 , 61 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PSSCR_T3_SRR1 ); REG64_FLD( EX_L2_DIRECT_CONTROLS_PSSCR_T3_SRR1_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PSSCR_T3_SRR1_LEN ); REG64_FLD( C_DIRECT_CONTROLS_DC_T0_CLEAR_MAINT , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DC_T0_CLEAR_MAINT ); REG64_FLD( C_DIRECT_CONTROLS_DC_T0_SRESET_REQUEST , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DC_T0_SRESET_REQUEST ); REG64_FLD( C_DIRECT_CONTROLS_DC_T0_CORE_STEP , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DC_T0_CORE_STEP ); REG64_FLD( C_DIRECT_CONTROLS_DC_T0_CORE_START , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DC_T0_CORE_START ); REG64_FLD( C_DIRECT_CONTROLS_DC_T0_CORE_STOP , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DC_T0_CORE_STOP ); REG64_FLD( C_DIRECT_CONTROLS_DC_T1_CLEAR_MAINT , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DC_T1_CLEAR_MAINT ); REG64_FLD( C_DIRECT_CONTROLS_DC_T1_SRESET_REQUEST , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DC_T1_SRESET_REQUEST ); REG64_FLD( C_DIRECT_CONTROLS_DC_T1_CORE_STEP , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DC_T1_CORE_STEP ); REG64_FLD( C_DIRECT_CONTROLS_DC_T1_CORE_START , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DC_T1_CORE_START ); REG64_FLD( C_DIRECT_CONTROLS_DC_T1_CORE_STOP , 15 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DC_T1_CORE_STOP ); REG64_FLD( C_DIRECT_CONTROLS_DC_T2_CLEAR_MAINT , 19 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DC_T2_CLEAR_MAINT ); REG64_FLD( C_DIRECT_CONTROLS_DC_T2_SRESET_REQUEST , 20 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DC_T2_SRESET_REQUEST ); REG64_FLD( C_DIRECT_CONTROLS_DC_T2_CORE_STEP , 21 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DC_T2_CORE_STEP ); REG64_FLD( C_DIRECT_CONTROLS_DC_T2_CORE_START , 22 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DC_T2_CORE_START ); REG64_FLD( C_DIRECT_CONTROLS_DC_T2_CORE_STOP , 23 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DC_T2_CORE_STOP ); REG64_FLD( C_DIRECT_CONTROLS_DC_T3_CLEAR_MAINT , 27 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DC_T3_CLEAR_MAINT ); REG64_FLD( C_DIRECT_CONTROLS_DC_T3_SRESET_REQUEST , 28 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DC_T3_SRESET_REQUEST ); REG64_FLD( C_DIRECT_CONTROLS_DC_T3_CORE_STEP , 29 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DC_T3_CORE_STEP ); REG64_FLD( C_DIRECT_CONTROLS_DC_T3_CORE_START , 30 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DC_T3_CORE_START ); REG64_FLD( C_DIRECT_CONTROLS_DC_T3_CORE_STOP , 31 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DC_T3_CORE_STOP ); REG64_FLD( C_DIRECT_CONTROLS_WRITE_T0_PM_STATE , 32 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WRITE_T0_PM_STATE ); REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T0_PLS , 33 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PSSCR_T0_PLS ); REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T0_PLS_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PSSCR_T0_PLS_LEN ); REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T0_SRR1 , 37 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PSSCR_T0_SRR1 ); REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T0_SRR1_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PSSCR_T0_SRR1_LEN ); REG64_FLD( C_DIRECT_CONTROLS_WRITE_T1_PM_STATE , 40 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WRITE_T1_PM_STATE ); REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T1_PLS , 41 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PSSCR_T1_PLS ); REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T1_PLS_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PSSCR_T1_PLS_LEN ); REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T1_SRR1 , 45 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PSSCR_T1_SRR1 ); REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T1_SRR1_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PSSCR_T1_SRR1_LEN ); REG64_FLD( C_DIRECT_CONTROLS_WRITE_T2_PM_STATE , 48 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WRITE_T2_PM_STATE ); REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T2_PLS , 49 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PSSCR_T2_PLS ); REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T2_PLS_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PSSCR_T2_PLS_LEN ); REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T2_SRR1 , 53 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PSSCR_T2_SRR1 ); REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T2_SRR1_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PSSCR_T2_SRR1_LEN ); REG64_FLD( C_DIRECT_CONTROLS_WRITE_T3_PM_STATE , 56 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WRITE_T3_PM_STATE ); REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T3_PLS , 57 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PSSCR_T3_PLS ); REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T3_PLS_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PSSCR_T3_PLS_LEN ); REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T3_SRR1 , 61 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PSSCR_T3_SRR1 ); REG64_FLD( C_DIRECT_CONTROLS_PSSCR_T3_SRR1_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PSSCR_T3_SRR1_LEN ); REG64_FLD( EQ_DRAM_REF_REG_L3_TIMER_DIVIDE_MAJOR , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_TIMER_DIVIDE_MAJOR ); REG64_FLD( EQ_DRAM_REF_REG_L3_TIMER_DIVIDE_MAJOR_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_TIMER_DIVIDE_MAJOR_LEN ); REG64_FLD( EQ_DRAM_REF_REG_L3_SCOM_INIT , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_SCOM_INIT ); REG64_FLD( EQ_DRAM_REF_REG_L3_SCOM_QUIESCE_CACHE , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_SCOM_QUIESCE_CACHE ); REG64_FLD( EQ_DRAM_REF_REG_L3_SCOM_QUIESCE_CACHE_LFSR , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_SCOM_QUIESCE_CACHE_LFSR ); REG64_FLD( EQ_DRAM_REF_REG_L3_SCOM_QUIESCE_REFRESH , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_SCOM_QUIESCE_REFRESH ); REG64_FLD( EQ_DRAM_REF_REG_L3_TIMER_DIVIDE_MINOR , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_TIMER_DIVIDE_MINOR ); REG64_FLD( EQ_DRAM_REF_REG_L3_TIMER_DIVIDE_MINOR_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_TIMER_DIVIDE_MINOR_LEN ); REG64_FLD( EX_DRAM_REF_REG_L3_TIMER_DIVIDE_MAJOR , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_TIMER_DIVIDE_MAJOR ); REG64_FLD( EX_DRAM_REF_REG_L3_TIMER_DIVIDE_MAJOR_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_TIMER_DIVIDE_MAJOR_LEN ); REG64_FLD( EX_DRAM_REF_REG_L3_SCOM_INIT , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_SCOM_INIT ); REG64_FLD( EX_DRAM_REF_REG_L3_SCOM_QUIESCE_CACHE , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_SCOM_QUIESCE_CACHE ); REG64_FLD( EX_DRAM_REF_REG_L3_SCOM_QUIESCE_CACHE_LFSR , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_SCOM_QUIESCE_CACHE_LFSR ); REG64_FLD( EX_DRAM_REF_REG_L3_SCOM_QUIESCE_REFRESH , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_SCOM_QUIESCE_REFRESH ); REG64_FLD( EX_DRAM_REF_REG_L3_TIMER_DIVIDE_MINOR , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_TIMER_DIVIDE_MINOR ); REG64_FLD( EX_DRAM_REF_REG_L3_TIMER_DIVIDE_MINOR_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_TIMER_DIVIDE_MINOR_LEN ); REG64_FLD( EQ_DTS_RESULT0_0_RESULT , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_0_RESULT ); REG64_FLD( EQ_DTS_RESULT0_0_RESULT_LEN , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_0_RESULT_LEN ); REG64_FLD( EQ_DTS_RESULT0_1_RESULT , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_1_RESULT ); REG64_FLD( EQ_DTS_RESULT0_1_RESULT_LEN , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_1_RESULT_LEN ); REG64_FLD( EX_DTS_RESULT0_0_RESULT , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_0_RESULT ); REG64_FLD( EX_DTS_RESULT0_0_RESULT_LEN , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_0_RESULT_LEN ); REG64_FLD( EX_DTS_RESULT0_1_RESULT , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_1_RESULT ); REG64_FLD( EX_DTS_RESULT0_1_RESULT_LEN , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_1_RESULT_LEN ); REG64_FLD( C_DTS_RESULT0_0_RESULT , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_0_RESULT ); REG64_FLD( C_DTS_RESULT0_0_RESULT_LEN , 16 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_0_RESULT_LEN ); REG64_FLD( C_DTS_RESULT0_1_RESULT , 16 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_1_RESULT ); REG64_FLD( C_DTS_RESULT0_1_RESULT_LEN , 16 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_1_RESULT_LEN ); REG64_FLD( EQ_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_TIMESTAMP_COUNTER_VALUE ); REG64_FLD( EQ_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE_LEN , 44 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_TIMESTAMP_COUNTER_VALUE_LEN ); REG64_FLD( EQ_DTS_TRC_RESULT_TIMESTAMP_COUNTER_OVERFLOW_ERR , 44 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_TIMESTAMP_COUNTER_OVERFLOW_ERR ); REG64_FLD( EQ_DTS_TRC_RESULT_1 , 48 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_1 ); REG64_FLD( EQ_DTS_TRC_RESULT_1_LEN , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_1_LEN ); REG64_FLD( EX_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_TIMESTAMP_COUNTER_VALUE ); REG64_FLD( EX_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE_LEN , 44 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_TIMESTAMP_COUNTER_VALUE_LEN ); REG64_FLD( EX_DTS_TRC_RESULT_TIMESTAMP_COUNTER_OVERFLOW_ERR , 44 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_TIMESTAMP_COUNTER_OVERFLOW_ERR ); REG64_FLD( EX_DTS_TRC_RESULT_1 , 48 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_1 ); REG64_FLD( EX_DTS_TRC_RESULT_1_LEN , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_1_LEN ); REG64_FLD( C_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_TIMESTAMP_COUNTER_VALUE ); REG64_FLD( C_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE_LEN , 44 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_TIMESTAMP_COUNTER_VALUE_LEN ); REG64_FLD( C_DTS_TRC_RESULT_TIMESTAMP_COUNTER_OVERFLOW_ERR , 44 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_TIMESTAMP_COUNTER_OVERFLOW_ERR ); REG64_FLD( C_DTS_TRC_RESULT_1 , 48 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_1 ); REG64_FLD( C_DTS_TRC_RESULT_1_LEN , 16 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_1_LEN ); REG64_FLD( EQ_EDRAM_BANK_FAIL_SCOM_RD_L3 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3 ); REG64_FLD( EQ_EDRAM_BANK_FAIL_SCOM_RD_L3_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_LEN ); REG64_FLD( EX_L3_EDRAM_BANK_FAIL_SCOM_RD_L3 , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3 ); REG64_FLD( EX_L3_EDRAM_BANK_FAIL_SCOM_RD_L3_LEN , 3 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_LEN ); REG64_FLD( EQ_EDRAM_BANK_SOFT_DIS_L3_CFG , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_CFG ); REG64_FLD( EQ_EDRAM_BANK_SOFT_DIS_L3_CFG_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_CFG_LEN ); REG64_FLD( EX_L3_EDRAM_BANK_SOFT_DIS_L3_CFG , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_CFG ); REG64_FLD( EX_L3_EDRAM_BANK_SOFT_DIS_L3_CFG_LEN , 10 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_CFG_LEN ); REG64_FLD( EQ_EDRAM_REG_L3_CP_UTIL_EN_DC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_CP_UTIL_EN_DC ); REG64_FLD( EQ_EDRAM_REG_L3_CP_UTIL_SEL_DC , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_CP_UTIL_SEL_DC ); REG64_FLD( EQ_EDRAM_REG_L3_CP_UTIL_SEL_DC_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_CP_UTIL_SEL_DC_LEN ); REG64_FLD( EQ_EDRAM_REG_L3_SPARE3 , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_SPARE3 ); REG64_FLD( EQ_EDRAM_REG_L3_CP_UTIL_EXT_SEL , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_CP_UTIL_EXT_SEL ); REG64_FLD( EQ_EDRAM_REG_L3_CP_UTIL_EXT_SEL_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_CP_UTIL_EXT_SEL_LEN ); REG64_FLD( EQ_EDRAM_REG_L3_UTIL_MON_BITS , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_UTIL_MON_BITS ); REG64_FLD( EQ_EDRAM_REG_L3_UTIL_MON_BITS_LEN , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_UTIL_MON_BITS_LEN ); REG64_FLD( EX_L3_EDRAM_REG_L3_CP_UTIL_EN_DC , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_CP_UTIL_EN_DC ); REG64_FLD( EX_L3_EDRAM_REG_L3_CP_UTIL_SEL_DC , 1 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_CP_UTIL_SEL_DC ); REG64_FLD( EX_L3_EDRAM_REG_L3_CP_UTIL_SEL_DC_LEN , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_CP_UTIL_SEL_DC_LEN ); REG64_FLD( EX_L3_EDRAM_REG_L3_SPARE3 , 3 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_SPARE3 ); REG64_FLD( EX_L3_EDRAM_REG_L3_CP_UTIL_EXT_SEL , 4 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_CP_UTIL_EXT_SEL ); REG64_FLD( EX_L3_EDRAM_REG_L3_CP_UTIL_EXT_SEL_LEN , 3 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_CP_UTIL_EXT_SEL_LEN ); REG64_FLD( EX_L3_EDRAM_REG_L3_UTIL_MON_BITS , 7 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_UTIL_MON_BITS ); REG64_FLD( EX_L3_EDRAM_REG_L3_UTIL_MON_BITS_LEN , 6 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_UTIL_MON_BITS_LEN ); REG64_FLD( EQ_EDRAM_STATUS_STAT , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STAT ); REG64_FLD( EQ_EDRAM_STATUS_STAT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STAT_LEN ); REG64_FLD( EX_EDRAM_STATUS_STAT , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STAT ); REG64_FLD( EX_EDRAM_STATUS_STAT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STAT_LEN ); REG64_FLD( C_EDRAM_STATUS_STAT , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STAT ); REG64_FLD( C_EDRAM_STATUS_STAT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STAT_LEN ); REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_VAL , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_VAL ); REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_1ST_BEAT_UE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_1ST_BEAT_UE ); REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_2ND_BEAT_UE , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_2ND_BEAT_UE ); REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_SPARE3 , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_SPARE3 ); REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_1ST_BEAT_SYNDROME , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_1ST_BEAT_SYNDROME ); REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_1ST_BEAT_SYNDROME_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_1ST_BEAT_SYNDROME_LEN ); REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_2ND_BEAT_SYNDROME , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_2ND_BEAT_SYNDROME ); REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_2ND_BEAT_SYNDROME_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_2ND_BEAT_SYNDROME_LEN ); REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_DW , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_DW ); REG64_FLD( EQ_ED_RD_ERR_STAT_REG0_L3_DW_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_DW_LEN ); REG64_FLD( EX_ED_RD_ERR_STAT_REG0_L3_VAL , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_VAL ); REG64_FLD( EX_ED_RD_ERR_STAT_REG0_L3_1ST_BEAT_UE , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_1ST_BEAT_UE ); REG64_FLD( EX_ED_RD_ERR_STAT_REG0_L3_2ND_BEAT_UE , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_2ND_BEAT_UE ); REG64_FLD( EX_ED_RD_ERR_STAT_REG0_L3_SPARE3 , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_SPARE3 ); REG64_FLD( EX_ED_RD_ERR_STAT_REG0_L3_1ST_BEAT_SYNDROME , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_1ST_BEAT_SYNDROME ); REG64_FLD( EX_ED_RD_ERR_STAT_REG0_L3_1ST_BEAT_SYNDROME_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_1ST_BEAT_SYNDROME_LEN ); REG64_FLD( EX_ED_RD_ERR_STAT_REG0_L3_2ND_BEAT_SYNDROME , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_2ND_BEAT_SYNDROME ); REG64_FLD( EX_ED_RD_ERR_STAT_REG0_L3_2ND_BEAT_SYNDROME_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_2ND_BEAT_SYNDROME_LEN ); REG64_FLD( EX_ED_RD_ERR_STAT_REG0_L3_DW , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_DW ); REG64_FLD( EX_ED_RD_ERR_STAT_REG0_L3_DW_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_DW_LEN ); REG64_FLD( EQ_ED_RD_ERR_STAT_REG1_L3_RA , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_RA ); REG64_FLD( EQ_ED_RD_ERR_STAT_REG1_L3_RA_LEN , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_RA_LEN ); REG64_FLD( EQ_ED_RD_ERR_STAT_REG1_L3_BANK , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_BANK ); REG64_FLD( EQ_ED_RD_ERR_STAT_REG1_L3_BANK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_BANK_LEN ); REG64_FLD( EX_L3_ED_RD_ERR_STAT_REG1_L3_RA , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_RA ); REG64_FLD( EX_L3_ED_RD_ERR_STAT_REG1_L3_RA_LEN , 14 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_RA_LEN ); REG64_FLD( EX_L3_ED_RD_ERR_STAT_REG1_L3_BANK , 14 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_BANK ); REG64_FLD( EX_L3_ED_RD_ERR_STAT_REG1_L3_BANK_LEN , 4 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_BANK_LEN ); REG64_FLD( EQ_ERROR_REG_CE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CE ); REG64_FLD( EQ_ERROR_REG_CHIPLET_ERRORS , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CHIPLET_ERRORS ); REG64_FLD( EQ_ERROR_REG_CHIPLET_ERRORS_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CHIPLET_ERRORS_LEN ); REG64_FLD( EQ_ERROR_REG_PARITY , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PARITY ); REG64_FLD( EQ_ERROR_REG_DATA_BUFFER , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DATA_BUFFER ); REG64_FLD( EQ_ERROR_REG_ADDR_BUFFER , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ADDR_BUFFER ); REG64_FLD( EQ_ERROR_REG_PCB_FSM , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PCB_FSM ); REG64_FLD( EQ_ERROR_REG_CL_FSM , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CL_FSM ); REG64_FLD( EQ_ERROR_REG_INT_RX_FSM , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INT_RX_FSM ); REG64_FLD( EQ_ERROR_REG_INT_TX_FSM , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INT_TX_FSM ); REG64_FLD( EQ_ERROR_REG_INT_TYPE , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INT_TYPE ); REG64_FLD( EQ_ERROR_REG_CL_DATA , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CL_DATA ); REG64_FLD( EQ_ERROR_REG_INFO , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INFO ); REG64_FLD( EQ_ERROR_REG_UNUSED_0 , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED_0 ); REG64_FLD( EQ_ERROR_REG_CHIPLET_ATOMIC_LOCK , 15 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CHIPLET_ATOMIC_LOCK ); REG64_FLD( EQ_ERROR_REG_PCB_INTERFACE , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PCB_INTERFACE ); REG64_FLD( EQ_ERROR_REG_CHIPLET_OFFLINE , 17 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CHIPLET_OFFLINE ); REG64_FLD( EQ_ERROR_REG_EDRAM_SEQUENCE_ERR , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EDRAM_SEQUENCE_ERR ); REG64_FLD( EQ_ERROR_REG_CTRL_PARITY , 19 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CTRL_PARITY ); REG64_FLD( EQ_ERROR_REG_ADDRESS_PARITY , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ADDRESS_PARITY ); REG64_FLD( EQ_ERROR_REG_TIMEOUT_PARITY , 21 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TIMEOUT_PARITY ); REG64_FLD( EQ_ERROR_REG_CONFIG_PARITY , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CONFIG_PARITY ); REG64_FLD( EQ_ERROR_REG_UNUSED_1 , 23 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED_1 ); REG64_FLD( EQ_ERROR_REG_DIV_PARITY , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DIV_PARITY ); REG64_FLD( EQ_ERROR_REG_PLL_UNLOCK , 25 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PLL_UNLOCK ); REG64_FLD( EQ_ERROR_REG_PLL_UNLOCK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PLL_UNLOCK_LEN ); REG64_FLD( EX_ERROR_REG_CE , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CE ); REG64_FLD( EX_ERROR_REG_CHIPLET_ERRORS , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CHIPLET_ERRORS ); REG64_FLD( EX_ERROR_REG_CHIPLET_ERRORS_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CHIPLET_ERRORS_LEN ); REG64_FLD( EX_ERROR_REG_PARITY , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PARITY ); REG64_FLD( EX_ERROR_REG_DATA_BUFFER , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DATA_BUFFER ); REG64_FLD( EX_ERROR_REG_ADDR_BUFFER , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ADDR_BUFFER ); REG64_FLD( EX_ERROR_REG_PCB_FSM , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PCB_FSM ); REG64_FLD( EX_ERROR_REG_CL_FSM , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CL_FSM ); REG64_FLD( EX_ERROR_REG_INT_RX_FSM , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INT_RX_FSM ); REG64_FLD( EX_ERROR_REG_INT_TX_FSM , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INT_TX_FSM ); REG64_FLD( EX_ERROR_REG_INT_TYPE , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INT_TYPE ); REG64_FLD( EX_ERROR_REG_CL_DATA , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CL_DATA ); REG64_FLD( EX_ERROR_REG_INFO , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INFO ); REG64_FLD( EX_ERROR_REG_UNUSED_0 , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED_0 ); REG64_FLD( EX_ERROR_REG_CHIPLET_ATOMIC_LOCK , 15 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CHIPLET_ATOMIC_LOCK ); REG64_FLD( EX_ERROR_REG_PCB_INTERFACE , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PCB_INTERFACE ); REG64_FLD( EX_ERROR_REG_CHIPLET_OFFLINE , 17 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CHIPLET_OFFLINE ); REG64_FLD( EX_ERROR_REG_EDRAM_SEQUENCE_ERR , 18 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EDRAM_SEQUENCE_ERR ); REG64_FLD( EX_ERROR_REG_CTRL_PARITY , 19 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CTRL_PARITY ); REG64_FLD( EX_ERROR_REG_ADDRESS_PARITY , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ADDRESS_PARITY ); REG64_FLD( EX_ERROR_REG_TIMEOUT_PARITY , 21 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TIMEOUT_PARITY ); REG64_FLD( EX_ERROR_REG_CONFIG_PARITY , 22 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CONFIG_PARITY ); REG64_FLD( EX_ERROR_REG_UNUSED_1 , 23 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED_1 ); REG64_FLD( EX_ERROR_REG_DIV_PARITY , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DIV_PARITY ); REG64_FLD( EX_ERROR_REG_PLL_UNLOCK , 25 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PLL_UNLOCK ); REG64_FLD( EX_ERROR_REG_PLL_UNLOCK_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PLL_UNLOCK_LEN ); REG64_FLD( C_ERROR_REG_CE , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CE ); REG64_FLD( C_ERROR_REG_CHIPLET_ERRORS , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CHIPLET_ERRORS ); REG64_FLD( C_ERROR_REG_CHIPLET_ERRORS_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CHIPLET_ERRORS_LEN ); REG64_FLD( C_ERROR_REG_PARITY , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PARITY ); REG64_FLD( C_ERROR_REG_DATA_BUFFER , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DATA_BUFFER ); REG64_FLD( C_ERROR_REG_ADDR_BUFFER , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ADDR_BUFFER ); REG64_FLD( C_ERROR_REG_PCB_FSM , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_FSM ); REG64_FLD( C_ERROR_REG_CL_FSM , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CL_FSM ); REG64_FLD( C_ERROR_REG_INT_RX_FSM , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INT_RX_FSM ); REG64_FLD( C_ERROR_REG_INT_TX_FSM , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INT_TX_FSM ); REG64_FLD( C_ERROR_REG_INT_TYPE , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INT_TYPE ); REG64_FLD( C_ERROR_REG_CL_DATA , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CL_DATA ); REG64_FLD( C_ERROR_REG_INFO , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INFO ); REG64_FLD( C_ERROR_REG_UNUSED_0 , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED_0 ); REG64_FLD( C_ERROR_REG_CHIPLET_ATOMIC_LOCK , 15 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CHIPLET_ATOMIC_LOCK ); REG64_FLD( C_ERROR_REG_PCB_INTERFACE , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_INTERFACE ); REG64_FLD( C_ERROR_REG_CHIPLET_OFFLINE , 17 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CHIPLET_OFFLINE ); REG64_FLD( C_ERROR_REG_EDRAM_SEQUENCE_ERR , 18 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_EDRAM_SEQUENCE_ERR ); REG64_FLD( C_ERROR_REG_CTRL_PARITY , 19 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CTRL_PARITY ); REG64_FLD( C_ERROR_REG_ADDRESS_PARITY , 20 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ADDRESS_PARITY ); REG64_FLD( C_ERROR_REG_TIMEOUT_PARITY , 21 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TIMEOUT_PARITY ); REG64_FLD( C_ERROR_REG_CONFIG_PARITY , 22 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CONFIG_PARITY ); REG64_FLD( C_ERROR_REG_UNUSED_1 , 23 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED_1 ); REG64_FLD( C_ERROR_REG_DIV_PARITY , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DIV_PARITY ); REG64_FLD( C_ERROR_REG_PLL_UNLOCK , 25 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PLL_UNLOCK ); REG64_FLD( C_ERROR_REG_PLL_UNLOCK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PLL_UNLOCK_LEN ); REG64_FLD( EQ_ERROR_STATUS_PCB_WRITE_NOT_ALLOWED_ERR , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PCB_WRITE_NOT_ALLOWED_ERR ); REG64_FLD( EQ_ERROR_STATUS_PCB_READ_NOT_ALLOWED_ERR , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PCB_READ_NOT_ALLOWED_ERR ); REG64_FLD( EQ_ERROR_STATUS_PCB_PARITY_ON_CMD_ERR , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PCB_PARITY_ON_CMD_ERR ); REG64_FLD( EQ_ERROR_STATUS_PCB_ADDRESS_NOT_VALID_ERR , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_NOT_VALID_ERR ); REG64_FLD( EQ_ERROR_STATUS_PCB_PARITY_ON_ADDR_ERR , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PCB_PARITY_ON_ADDR_ERR ); REG64_FLD( EQ_ERROR_STATUS_PCB_PARITY_ON_DATA_ERR , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PCB_PARITY_ON_DATA_ERR ); REG64_FLD( EQ_ERROR_STATUS_PCB_PROTECTED_ACCESS_INVALID_ERR , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PCB_PROTECTED_ACCESS_INVALID_ERR ); REG64_FLD( EQ_ERROR_STATUS_PCB_PARITY_ON_SPCIF_ERR , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PCB_PARITY_ON_SPCIF_ERR ); REG64_FLD( EQ_ERROR_STATUS_PCB_WRITE_AND_OPCG_IP_ERR , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PCB_WRITE_AND_OPCG_IP_ERR ); REG64_FLD( EQ_ERROR_STATUS_SCAN_READ_AND_OPCG_IP_ERR , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SCAN_READ_AND_OPCG_IP_ERR ); REG64_FLD( EQ_ERROR_STATUS_CLOCK_CMD_CONFLICT_ERR , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CLOCK_CMD_CONFLICT_ERR ); REG64_FLD( EQ_ERROR_STATUS_SCAN_COLLISION_ERR , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SCAN_COLLISION_ERR ); REG64_FLD( EQ_ERROR_STATUS_PREVENTED_SCAN_COLLISION_ERR , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PREVENTED_SCAN_COLLISION_ERR ); REG64_FLD( EQ_ERROR_STATUS_OPCG_TRIGGER_ERR , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_OPCG_TRIGGER_ERR ); REG64_FLD( EQ_ERROR_STATUS_PHASE_CNT_CORRUPTION_ERR , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PHASE_CNT_CORRUPTION_ERR ); REG64_FLD( EQ_ERROR_STATUS_CLOCK_CMD_PREVENTED_ERR , 15 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CLOCK_CMD_PREVENTED_ERR ); REG64_FLD( EQ_ERROR_STATUS_PARITY_ON_OPCG_SM_ERR , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PARITY_ON_OPCG_SM_ERR ); REG64_FLD( EQ_ERROR_STATUS_PARITY_ON_CLOCK_MUX_REG_ERR , 17 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PARITY_ON_CLOCK_MUX_REG_ERR ); REG64_FLD( EQ_ERROR_STATUS_PARITY_ON_OPCG_REG_ERR , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PARITY_ON_OPCG_REG_ERR ); REG64_FLD( EQ_ERROR_STATUS_PARITY_ON_SYNC_CONFIG_REG_ERR , 19 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PARITY_ON_SYNC_CONFIG_REG_ERR ); REG64_FLD( EQ_ERROR_STATUS_PARITY_ON_XSTOP_REG_ERR , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PARITY_ON_XSTOP_REG_ERR ); REG64_FLD( EQ_ERROR_STATUS_PARITY_ON_GPIO_REG_ERR , 21 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PARITY_ON_GPIO_REG_ERR ); REG64_FLD( EQ_ERROR_STATUS_CLKCMD_REQUEST_ERR , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CLKCMD_REQUEST_ERR ); REG64_FLD( EQ_ERROR_STATUS_CBS_PROTOCOL_ERR , 23 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CBS_PROTOCOL_ERR ); REG64_FLD( EQ_ERROR_STATUS_VITL_ALIGN_ERR , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_VITL_ALIGN_ERR ); REG64_FLD( EQ_ERROR_STATUS_UNIT_SYNC_LVL_ERR , 25 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT_SYNC_LVL_ERR ); REG64_FLD( EQ_ERROR_STATUS_PARITY_ON_SELFBOOT_CMD_STATE_ERR , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PARITY_ON_SELFBOOT_CMD_STATE_ERR ); REG64_FLD( EQ_ERROR_STATUS_UNUSED_ERROR27 , 27 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED_ERROR27 ); REG64_FLD( EQ_ERROR_STATUS_UNUSED_ERROR28 , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED_ERROR28 ); REG64_FLD( EQ_ERROR_STATUS_UNUSED_ERROR29 , 29 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED_ERROR29 ); REG64_FLD( EQ_ERROR_STATUS_UNUSED_ERROR30 , 30 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED_ERROR30 ); REG64_FLD( EQ_ERROR_STATUS_UNUSED_ERROR31 , 31 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED_ERROR31 ); REG64_FLD( EX_ERROR_STATUS_PCB_WRITE_NOT_ALLOWED_ERR , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PCB_WRITE_NOT_ALLOWED_ERR ); REG64_FLD( EX_ERROR_STATUS_PCB_READ_NOT_ALLOWED_ERR , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PCB_READ_NOT_ALLOWED_ERR ); REG64_FLD( EX_ERROR_STATUS_PCB_PARITY_ON_CMD_ERR , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PCB_PARITY_ON_CMD_ERR ); REG64_FLD( EX_ERROR_STATUS_PCB_ADDRESS_NOT_VALID_ERR , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_NOT_VALID_ERR ); REG64_FLD( EX_ERROR_STATUS_PCB_PARITY_ON_ADDR_ERR , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PCB_PARITY_ON_ADDR_ERR ); REG64_FLD( EX_ERROR_STATUS_PCB_PARITY_ON_DATA_ERR , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PCB_PARITY_ON_DATA_ERR ); REG64_FLD( EX_ERROR_STATUS_PCB_PROTECTED_ACCESS_INVALID_ERR , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PCB_PROTECTED_ACCESS_INVALID_ERR ); REG64_FLD( EX_ERROR_STATUS_PCB_PARITY_ON_SPCIF_ERR , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PCB_PARITY_ON_SPCIF_ERR ); REG64_FLD( EX_ERROR_STATUS_PCB_WRITE_AND_OPCG_IP_ERR , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PCB_WRITE_AND_OPCG_IP_ERR ); REG64_FLD( EX_ERROR_STATUS_SCAN_READ_AND_OPCG_IP_ERR , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SCAN_READ_AND_OPCG_IP_ERR ); REG64_FLD( EX_ERROR_STATUS_CLOCK_CMD_CONFLICT_ERR , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CLOCK_CMD_CONFLICT_ERR ); REG64_FLD( EX_ERROR_STATUS_SCAN_COLLISION_ERR , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SCAN_COLLISION_ERR ); REG64_FLD( EX_ERROR_STATUS_PREVENTED_SCAN_COLLISION_ERR , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PREVENTED_SCAN_COLLISION_ERR ); REG64_FLD( EX_ERROR_STATUS_OPCG_TRIGGER_ERR , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_OPCG_TRIGGER_ERR ); REG64_FLD( EX_ERROR_STATUS_PHASE_CNT_CORRUPTION_ERR , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PHASE_CNT_CORRUPTION_ERR ); REG64_FLD( EX_ERROR_STATUS_CLOCK_CMD_PREVENTED_ERR , 15 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CLOCK_CMD_PREVENTED_ERR ); REG64_FLD( EX_ERROR_STATUS_PARITY_ON_OPCG_SM_ERR , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PARITY_ON_OPCG_SM_ERR ); REG64_FLD( EX_ERROR_STATUS_PARITY_ON_CLOCK_MUX_REG_ERR , 17 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PARITY_ON_CLOCK_MUX_REG_ERR ); REG64_FLD( EX_ERROR_STATUS_PARITY_ON_OPCG_REG_ERR , 18 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PARITY_ON_OPCG_REG_ERR ); REG64_FLD( EX_ERROR_STATUS_PARITY_ON_SYNC_CONFIG_REG_ERR , 19 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PARITY_ON_SYNC_CONFIG_REG_ERR ); REG64_FLD( EX_ERROR_STATUS_PARITY_ON_XSTOP_REG_ERR , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PARITY_ON_XSTOP_REG_ERR ); REG64_FLD( EX_ERROR_STATUS_PARITY_ON_GPIO_REG_ERR , 21 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PARITY_ON_GPIO_REG_ERR ); REG64_FLD( EX_ERROR_STATUS_CLKCMD_REQUEST_ERR , 22 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CLKCMD_REQUEST_ERR ); REG64_FLD( EX_ERROR_STATUS_CBS_PROTOCOL_ERR , 23 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CBS_PROTOCOL_ERR ); REG64_FLD( EX_ERROR_STATUS_VITL_ALIGN_ERR , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_VITL_ALIGN_ERR ); REG64_FLD( EX_ERROR_STATUS_UNIT_SYNC_LVL_ERR , 25 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT_SYNC_LVL_ERR ); REG64_FLD( EX_ERROR_STATUS_PARITY_ON_SELFBOOT_CMD_STATE_ERR , 26 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PARITY_ON_SELFBOOT_CMD_STATE_ERR ); REG64_FLD( EX_ERROR_STATUS_UNUSED_ERROR27 , 27 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED_ERROR27 ); REG64_FLD( EX_ERROR_STATUS_UNUSED_ERROR28 , 28 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED_ERROR28 ); REG64_FLD( EX_ERROR_STATUS_UNUSED_ERROR29 , 29 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED_ERROR29 ); REG64_FLD( EX_ERROR_STATUS_UNUSED_ERROR30 , 30 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED_ERROR30 ); REG64_FLD( EX_ERROR_STATUS_UNUSED_ERROR31 , 31 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED_ERROR31 ); REG64_FLD( C_ERROR_STATUS_PCB_WRITE_NOT_ALLOWED_ERR , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_WRITE_NOT_ALLOWED_ERR ); REG64_FLD( C_ERROR_STATUS_PCB_READ_NOT_ALLOWED_ERR , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_READ_NOT_ALLOWED_ERR ); REG64_FLD( C_ERROR_STATUS_PCB_PARITY_ON_CMD_ERR , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_PARITY_ON_CMD_ERR ); REG64_FLD( C_ERROR_STATUS_PCB_ADDRESS_NOT_VALID_ERR , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_NOT_VALID_ERR ); REG64_FLD( C_ERROR_STATUS_PCB_PARITY_ON_ADDR_ERR , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_PARITY_ON_ADDR_ERR ); REG64_FLD( C_ERROR_STATUS_PCB_PARITY_ON_DATA_ERR , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_PARITY_ON_DATA_ERR ); REG64_FLD( C_ERROR_STATUS_PCB_PROTECTED_ACCESS_INVALID_ERR , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_PROTECTED_ACCESS_INVALID_ERR ); REG64_FLD( C_ERROR_STATUS_PCB_PARITY_ON_SPCIF_ERR , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_PARITY_ON_SPCIF_ERR ); REG64_FLD( C_ERROR_STATUS_PCB_WRITE_AND_OPCG_IP_ERR , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_WRITE_AND_OPCG_IP_ERR ); REG64_FLD( C_ERROR_STATUS_SCAN_READ_AND_OPCG_IP_ERR , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SCAN_READ_AND_OPCG_IP_ERR ); REG64_FLD( C_ERROR_STATUS_CLOCK_CMD_CONFLICT_ERR , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CLOCK_CMD_CONFLICT_ERR ); REG64_FLD( C_ERROR_STATUS_SCAN_COLLISION_ERR , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SCAN_COLLISION_ERR ); REG64_FLD( C_ERROR_STATUS_PREVENTED_SCAN_COLLISION_ERR , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PREVENTED_SCAN_COLLISION_ERR ); REG64_FLD( C_ERROR_STATUS_OPCG_TRIGGER_ERR , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_OPCG_TRIGGER_ERR ); REG64_FLD( C_ERROR_STATUS_PHASE_CNT_CORRUPTION_ERR , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PHASE_CNT_CORRUPTION_ERR ); REG64_FLD( C_ERROR_STATUS_CLOCK_CMD_PREVENTED_ERR , 15 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CLOCK_CMD_PREVENTED_ERR ); REG64_FLD( C_ERROR_STATUS_PARITY_ON_OPCG_SM_ERR , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PARITY_ON_OPCG_SM_ERR ); REG64_FLD( C_ERROR_STATUS_PARITY_ON_CLOCK_MUX_REG_ERR , 17 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PARITY_ON_CLOCK_MUX_REG_ERR ); REG64_FLD( C_ERROR_STATUS_PARITY_ON_OPCG_REG_ERR , 18 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PARITY_ON_OPCG_REG_ERR ); REG64_FLD( C_ERROR_STATUS_PARITY_ON_SYNC_CONFIG_REG_ERR , 19 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PARITY_ON_SYNC_CONFIG_REG_ERR ); REG64_FLD( C_ERROR_STATUS_PARITY_ON_XSTOP_REG_ERR , 20 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PARITY_ON_XSTOP_REG_ERR ); REG64_FLD( C_ERROR_STATUS_PARITY_ON_GPIO_REG_ERR , 21 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PARITY_ON_GPIO_REG_ERR ); REG64_FLD( C_ERROR_STATUS_CLKCMD_REQUEST_ERR , 22 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CLKCMD_REQUEST_ERR ); REG64_FLD( C_ERROR_STATUS_CBS_PROTOCOL_ERR , 23 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CBS_PROTOCOL_ERR ); REG64_FLD( C_ERROR_STATUS_VITL_ALIGN_ERR , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_VITL_ALIGN_ERR ); REG64_FLD( C_ERROR_STATUS_UNIT_SYNC_LVL_ERR , 25 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT_SYNC_LVL_ERR ); REG64_FLD( C_ERROR_STATUS_PARITY_ON_SELFBOOT_CMD_STATE_ERR , 26 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PARITY_ON_SELFBOOT_CMD_STATE_ERR ); REG64_FLD( C_ERROR_STATUS_UNUSED_ERROR27 , 27 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED_ERROR27 ); REG64_FLD( C_ERROR_STATUS_UNUSED_ERROR28 , 28 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED_ERROR28 ); REG64_FLD( C_ERROR_STATUS_UNUSED_ERROR29 , 29 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED_ERROR29 ); REG64_FLD( C_ERROR_STATUS_UNUSED_ERROR30 , 30 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED_ERROR30 ); REG64_FLD( C_ERROR_STATUS_UNUSED_ERROR31 , 31 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED_ERROR31 ); REG64_FLD( EQ_ERR_INJ_REG_L3_SINGLE_CAC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_SINGLE_CAC ); REG64_FLD( EQ_ERR_INJ_REG_L3_SOLID_CAC , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_SOLID_CAC ); REG64_FLD( EQ_ERR_INJ_REG_L3_CAC_TYPE , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_CAC_TYPE ); REG64_FLD( EQ_ERR_INJ_REG_L3_CAC_TYPE_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_CAC_TYPE_LEN ); REG64_FLD( EQ_ERR_INJ_REG_L3_SINGLE_DIR , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_SINGLE_DIR ); REG64_FLD( EQ_ERR_INJ_REG_L3_SOLID_DIR , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_SOLID_DIR ); REG64_FLD( EQ_ERR_INJ_REG_L3_DIR_TYPE , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_DIR_TYPE ); REG64_FLD( EQ_ERR_INJ_REG_L3_SINGLE_LRU , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_SINGLE_LRU ); REG64_FLD( EQ_ERR_INJ_REG_L3_SOLID_LRU , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_SOLID_LRU ); REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_DCSET0 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_DCSET0 ); REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_DCSET1 , 1 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_DCSET1 ); REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_DCSET2 , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_DCSET2 ); REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_SLICE_DCD0 , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_SLICE_DCD0 ); REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_SLICE_DCD1 , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_SLICE_DCD1 ); REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_SLICE_DCD2 , 5 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_SLICE_DCD2 ); REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_DCACHE , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_DCACHE ); REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_DDIR , 7 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_DDIR ); REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_SETP , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_SETP ); REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_DERAT , 9 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_DERAT ); REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_DERAT_MULTIHIT , 10 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_DERAT_MULTIHIT ); REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_SLB , 11 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_SLB ); REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_SLB_MULTIHIT , 12 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_SLB_MULTIHIT ); REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_ITLB , 13 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_ITLB ); REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_DTLB , 14 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_DTLB ); REG64_FLD( EX_ERR_INJ_REG_ERROR_INJ_DTLB_MULTIHIT , 15 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_DTLB_MULTIHIT ); REG64_FLD( EX_L2_ERR_INJ_REG_DW_TYPE , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_DW_TYPE ); REG64_FLD( EX_L2_ERR_INJ_REG_DW_TYPE_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_DW_TYPE_LEN ); REG64_FLD( EX_L2_ERR_INJ_REG_CW_TYPE , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_CW_TYPE ); REG64_FLD( EX_L2_ERR_INJ_REG_CW_TYPE_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_CW_TYPE_LEN ); REG64_FLD( EX_L2_ERR_INJ_REG_STQ_TYPE , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_STQ_TYPE ); REG64_FLD( EX_L2_ERR_INJ_REG_STQ_TYPE_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_STQ_TYPE_LEN ); REG64_FLD( EX_L2_ERR_INJ_REG_CPI_TYPE , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_CPI_TYPE ); REG64_FLD( EX_L2_ERR_INJ_REG_CPI_TYPE_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_CPI_TYPE_LEN ); REG64_FLD( EX_L2_ERR_INJ_REG_LVDIR_EN , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_LVDIR_EN ); REG64_FLD( EX_L2_ERR_INJ_REG_LRU_EN , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_LRU_EN ); REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_DCSET0 , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_DCSET0 ); REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_DCSET1 , 1 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_DCSET1 ); REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_DCSET2 , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_DCSET2 ); REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_SLICE_DCD0 , 3 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_SLICE_DCD0 ); REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_SLICE_DCD1 , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_SLICE_DCD1 ); REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_SLICE_DCD2 , 5 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_SLICE_DCD2 ); REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_DCACHE , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_DCACHE ); REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_DDIR , 7 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_DDIR ); REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_SETP , 8 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_SETP ); REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_DERAT , 9 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_DERAT ); REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_DERAT_MULTIHIT , 10 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_DERAT_MULTIHIT ); REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_SLB , 11 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_SLB ); REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_SLB_MULTIHIT , 12 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_SLB_MULTIHIT ); REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_ITLB , 13 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_ITLB ); REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_DTLB , 14 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_DTLB ); REG64_FLD( C_ERR_INJ_REG_ERROR_INJ_DTLB_MULTIHIT , 15 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJ_DTLB_MULTIHIT ); REG64_FLD( EX_L3_ERR_INJ_REG_L3_SINGLE_CAC , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_SINGLE_CAC ); REG64_FLD( EX_L3_ERR_INJ_REG_L3_SOLID_CAC , 1 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_SOLID_CAC ); REG64_FLD( EX_L3_ERR_INJ_REG_L3_CAC_TYPE , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_CAC_TYPE ); REG64_FLD( EX_L3_ERR_INJ_REG_L3_CAC_TYPE_LEN , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_CAC_TYPE_LEN ); REG64_FLD( EX_L3_ERR_INJ_REG_L3_SINGLE_DIR , 4 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_SINGLE_DIR ); REG64_FLD( EX_L3_ERR_INJ_REG_L3_SOLID_DIR , 5 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_SOLID_DIR ); REG64_FLD( EX_L3_ERR_INJ_REG_L3_DIR_TYPE , 6 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_DIR_TYPE ); REG64_FLD( EX_L3_ERR_INJ_REG_L3_SINGLE_LRU , 7 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_SINGLE_LRU ); REG64_FLD( EX_L3_ERR_INJ_REG_L3_SOLID_LRU , 8 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_SOLID_LRU ); REG64_FLD( EQ_ERR_RPT0_RSV , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RSV ); REG64_FLD( EQ_ERR_RPT0_FIR14_NCCTL_RLD_BARRIER , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_NCCTL_RLD_BARRIER ); REG64_FLD( EQ_ERR_RPT0_FIR14_NCCTL_SNP , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_NCCTL_SNP ); REG64_FLD( EQ_ERR_RPT0_FIR14_NCCTL_TLBIE_ACK , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_NCCTL_TLBIE_ACK ); REG64_FLD( EQ_ERR_RPT0_FIR14_NCCTL_SYNC , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_NCCTL_SYNC ); REG64_FLD( EQ_ERR_RPT0_FIR14_NCCTL_VSYNC , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_NCCTL_VSYNC ); REG64_FLD( EQ_ERR_RPT0_FIR14_TMCTL_TIDX_TEND_LDST_SEQ , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_TMCTL_TIDX_TEND_LDST_SEQ ); REG64_FLD( EQ_ERR_RPT0_FIR14_RVCTL , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_RVCTL ); REG64_FLD( EQ_ERR_RPT0_FIR14_SRCTL0_BAD_HPC , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_SRCTL0_BAD_HPC ); REG64_FLD( EQ_ERR_RPT0_FIR14_SRCTL1_BAD_HPC , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_SRCTL1_BAD_HPC ); REG64_FLD( EQ_ERR_RPT0_FIR14_SRCTL2_BAD_HPC , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_SRCTL2_BAD_HPC ); REG64_FLD( EQ_ERR_RPT0_FIR14_SRCTL3_BAD_HPC , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_SRCTL3_BAD_HPC ); REG64_FLD( EQ_ERR_RPT0_FIR14_PBARB_FSM_REQ_OVERFLOW , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_PBARB_FSM_REQ_OVERFLOW ); REG64_FLD( EQ_ERR_RPT0_FIR14_PBARB_TRASHMODE_PB_REQ , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_PBARB_TRASHMODE_PB_REQ ); REG64_FLD( EQ_ERR_RPT0_FIR14_L3PF_MACH_DONE , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_L3PF_MACH_DONE ); REG64_FLD( EQ_ERR_RPT0_FIR14_RCMD0_TTAG_PERR , 15 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_RCMD0_TTAG_PERR ); REG64_FLD( EQ_ERR_RPT0_FIR14_RCMD1_TTAG_PERR , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_RCMD1_TTAG_PERR ); REG64_FLD( EQ_ERR_RPT0_FIR14_RCMD2_TTAG_PERR , 17 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_RCMD2_TTAG_PERR ); REG64_FLD( EQ_ERR_RPT0_FIR14_RCMD3_TTAG_PERR , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_RCMD3_TTAG_PERR ); REG64_FLD( EQ_ERR_RPT0_FIR14_CR0_TTAG_PERR , 19 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_CR0_TTAG_PERR ); REG64_FLD( EQ_ERR_RPT0_FIR14_CR0_ATAG_PERR , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_CR0_ATAG_PERR ); REG64_FLD( EQ_ERR_RPT0_FIR14_CR1_TTAG_PERR , 21 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_CR1_TTAG_PERR ); REG64_FLD( EQ_ERR_RPT0_FIR14_CR1_ATAG_PERR , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_CR1_ATAG_PERR ); REG64_FLD( EQ_ERR_RPT0_FIR14_CR2_TTAG_PERR , 23 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_CR2_TTAG_PERR ); REG64_FLD( EQ_ERR_RPT0_FIR14_CR2_ATAG_PERR , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_CR2_ATAG_PERR ); REG64_FLD( EQ_ERR_RPT0_FIR14_CR3_TTAG_PERR , 25 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_CR3_TTAG_PERR ); REG64_FLD( EQ_ERR_RPT0_FIR14_CR3_ATAG_PERR , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_CR3_ATAG_PERR ); REG64_FLD( EQ_ERR_RPT0_FIR14_RCMD0_ADDR_PERR , 27 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_RCMD0_ADDR_PERR ); REG64_FLD( EQ_ERR_RPT0_FIR14_RCMD1_ADDR_PERR , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_RCMD1_ADDR_PERR ); REG64_FLD( EQ_ERR_RPT0_FIR14_RCMD2_ADDR_PERR , 29 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_RCMD2_ADDR_PERR ); REG64_FLD( EQ_ERR_RPT0_FIR14_RCMD3_ADDR_PERR , 30 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_RCMD3_ADDR_PERR ); REG64_FLD( EQ_ERR_RPT0_FIR9_PEC_PHASE3_TIMEOUT , 31 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR9_PEC_PHASE3_TIMEOUT ); REG64_FLD( EQ_ERR_RPT0_FIR9_PEC_PHASE4_SAME , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR9_PEC_PHASE4_SAME ); REG64_FLD( EQ_ERR_RPT0_FIR9_PEC_PHASE4_RCCO_DISP_FAIL , 33 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR9_PEC_PHASE4_RCCO_DISP_FAIL ); REG64_FLD( EQ_ERR_RPT0_FIR9_PEC_PHASE5_TIMEOUT , 34 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR9_PEC_PHASE5_TIMEOUT ); REG64_FLD( EQ_ERR_RPT0_FIR14_B01_BOTH_ACTIVE , 35 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_B01_BOTH_ACTIVE ); REG64_FLD( EQ_ERR_RPT0_FIR14_PHANTOM_B01_REQ , 36 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_PHANTOM_B01_REQ ); REG64_FLD( EQ_ERR_RPT0_FIR14_RC_UNEXP_F2_DATA , 37 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_RC_UNEXP_F2_DATA ); REG64_FLD( EQ_ERR_RPT0_FIR14_RC_UNEXP_PURG_HIT , 38 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_RC_UNEXP_PURG_HIT ); REG64_FLD( EQ_ERR_RPT0_FIR14_RCX_UNEXP_IDLE_PBL3_DATA , 39 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_RCX_UNEXP_IDLE_PBL3_DATA ); REG64_FLD( EQ_ERR_RPT0_FIR14_RCX_UNEXP_IDLE_PB_CRESP , 40 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_RCX_UNEXP_IDLE_PB_CRESP ); REG64_FLD( EQ_ERR_RPT0_FIR14_COX_UNEXP_IDLE_PB_CRESP , 41 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_COX_UNEXP_IDLE_PB_CRESP ); REG64_FLD( EX_L2_ERR_RPT0_RSV , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_RSV ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_NCCTL_RLD_BARRIER , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_NCCTL_RLD_BARRIER ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_NCCTL_SNP , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_NCCTL_SNP ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_NCCTL_TLBIE_ACK , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_NCCTL_TLBIE_ACK ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_NCCTL_SYNC , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_NCCTL_SYNC ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_NCCTL_VSYNC , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_NCCTL_VSYNC ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_TMCTL_TIDX_TEND_LDST_SEQ , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_TMCTL_TIDX_TEND_LDST_SEQ ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_RVCTL , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_RVCTL ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_SRCTL0_BAD_HPC , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_SRCTL0_BAD_HPC ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_SRCTL1_BAD_HPC , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_SRCTL1_BAD_HPC ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_SRCTL2_BAD_HPC , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_SRCTL2_BAD_HPC ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_SRCTL3_BAD_HPC , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_SRCTL3_BAD_HPC ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_PBARB_FSM_REQ_OVERFLOW , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_PBARB_FSM_REQ_OVERFLOW ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_PBARB_TRASHMODE_PB_REQ , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_PBARB_TRASHMODE_PB_REQ ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_L3PF_MACH_DONE , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_L3PF_MACH_DONE ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_RCMD0_TTAG_PERR , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_RCMD0_TTAG_PERR ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_RCMD1_TTAG_PERR , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_RCMD1_TTAG_PERR ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_RCMD2_TTAG_PERR , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_RCMD2_TTAG_PERR ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_RCMD3_TTAG_PERR , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_RCMD3_TTAG_PERR ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_CR0_TTAG_PERR , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_CR0_TTAG_PERR ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_CR0_ATAG_PERR , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_CR0_ATAG_PERR ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_CR1_TTAG_PERR , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_CR1_TTAG_PERR ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_CR1_ATAG_PERR , 22 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_CR1_ATAG_PERR ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_CR2_TTAG_PERR , 23 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_CR2_TTAG_PERR ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_CR2_ATAG_PERR , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_CR2_ATAG_PERR ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_CR3_TTAG_PERR , 25 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_CR3_TTAG_PERR ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_CR3_ATAG_PERR , 26 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_CR3_ATAG_PERR ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_RCMD0_ADDR_PERR , 27 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_RCMD0_ADDR_PERR ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_RCMD1_ADDR_PERR , 28 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_RCMD1_ADDR_PERR ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_RCMD2_ADDR_PERR , 29 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_RCMD2_ADDR_PERR ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_RCMD3_ADDR_PERR , 30 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_RCMD3_ADDR_PERR ); REG64_FLD( EX_L2_ERR_RPT0_FIR9_PEC_PHASE3_TIMEOUT , 31 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR9_PEC_PHASE3_TIMEOUT ); REG64_FLD( EX_L2_ERR_RPT0_FIR9_PEC_PHASE4_SAME , 32 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR9_PEC_PHASE4_SAME ); REG64_FLD( EX_L2_ERR_RPT0_FIR9_PEC_PHASE4_RCCO_DISP_FAIL , 33 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR9_PEC_PHASE4_RCCO_DISP_FAIL ); REG64_FLD( EX_L2_ERR_RPT0_FIR9_PEC_PHASE5_TIMEOUT , 34 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR9_PEC_PHASE5_TIMEOUT ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_B01_BOTH_ACTIVE , 35 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_B01_BOTH_ACTIVE ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_PHANTOM_B01_REQ , 36 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_PHANTOM_B01_REQ ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_RC_UNEXP_F2_DATA , 37 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_RC_UNEXP_F2_DATA ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_RC_UNEXP_PURG_HIT , 38 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_RC_UNEXP_PURG_HIT ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_RCX_UNEXP_IDLE_PBL3_DATA , 39 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_RCX_UNEXP_IDLE_PBL3_DATA ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_RCX_UNEXP_IDLE_PB_CRESP , 40 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_RCX_UNEXP_IDLE_PB_CRESP ); REG64_FLD( EX_L2_ERR_RPT0_FIR14_COX_UNEXP_IDLE_PB_CRESP , 41 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_COX_UNEXP_IDLE_PB_CRESP ); REG64_FLD( EQ_ERR_RPT1_FIR14_RCX_UNEXP_IDLE_L3_CRESP , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_RCX_UNEXP_IDLE_L3_CRESP ); REG64_FLD( EQ_ERR_RPT1_FIR14_RCX_UNEXP_IDLE_L3_DWDONE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_RCX_UNEXP_IDLE_L3_DWDONE ); REG64_FLD( EQ_ERR_RPT1_FIR14_RCX_UNEXP_PB_RC_DTAG_PCHK , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_RCX_UNEXP_PB_RC_DTAG_PCHK ); REG64_FLD( EQ_ERR_RPT1_FIR14_DW_SET_REF_WITH_FLAG_IDLE , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_DW_SET_REF_WITH_FLAG_IDLE ); REG64_FLD( EQ_ERR_RPT1_FIR14_KILL_REF_WITH_FLAG_IDLE , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_KILL_REF_WITH_FLAG_IDLE ); REG64_FLD( EQ_ERR_RPT1_FIR14_DW_SET_SI_BY_MACH , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_DW_SET_SI_BY_MACH ); REG64_FLD( EQ_ERR_RPT1_FIR14_PD_DIR_MULT_HIT , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_PD_DIR_MULT_HIT ); REG64_FLD( EQ_ERR_RPT1_FIR14_B0_SD_DIR_MULT_HIT , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_B0_SD_DIR_MULT_HIT ); REG64_FLD( EQ_ERR_RPT1_FIR14_B1_SD_DIR_MULT_HIT , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_B1_SD_DIR_MULT_HIT ); REG64_FLD( EQ_ERR_RPT1_FIR14_B2_SD_DIR_MULT_HIT , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_B2_SD_DIR_MULT_HIT ); REG64_FLD( EQ_ERR_RPT1_FIR14_B3_SD_DIR_MULT_HIT , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_B3_SD_DIR_MULT_HIT ); REG64_FLD( EQ_ERR_RPT1_FIR14_INVALID_SNP_CPS_STATU_RTN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_INVALID_SNP_CPS_STATU_RTN ); REG64_FLD( EQ_ERR_RPT1_FIR14_HANG_WAITING_FOR_FP_MATE , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_HANG_WAITING_FOR_FP_MATE ); REG64_FLD( EQ_ERR_RPT1_FIR14_BAD_FP_MATE , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_BAD_FP_MATE ); REG64_FLD( EQ_ERR_RPT1_FIR14_LSU_TAG_REUSE , 15 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_LSU_TAG_REUSE ); REG64_FLD( EQ_ERR_RPT1_FIR14_IFU_MULT_REQ , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_IFU_MULT_REQ ); REG64_FLD( EQ_ERR_RPT1_FIR14_XPF_MULT_REQ , 17 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_XPF_MULT_REQ ); REG64_FLD( EQ_ERR_RPT1_FIR14_XLT_QUEUE_OVRFLW , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_XLT_QUEUE_OVRFLW ); REG64_FLD( EQ_ERR_RPT1_FIR14_L3PF_REQ , 19 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_L3PF_REQ ); REG64_FLD( EQ_ERR_RPT1_FIR14_NCU_TID_DONE , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_NCU_TID_DONE ); REG64_FLD( EQ_ERR_RPT1_FIR11_LRU_MEM_INVALID_ABCD , 21 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR11_LRU_MEM_INVALID_ABCD ); REG64_FLD( EQ_ERR_RPT1_FIR11_LRU_MEM_INVALID_EFGH , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR11_LRU_MEM_INVALID_EFGH ); REG64_FLD( EQ_ERR_RPT1_FIR14_STQ_COMING , 23 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_STQ_COMING ); REG64_FLD( EQ_ERR_RPT1_FIR14_STQ_OVERFLOW , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_STQ_OVERFLOW ); REG64_FLD( EQ_ERR_RPT1_FIR14_RC_PBBUS_SFSTAT , 25 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_RC_PBBUS_SFSTAT ); REG64_FLD( EQ_ERR_RPT1_FIR14_TMA_LARXA_VS_FRCMISS_SV , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_TMA_LARXA_VS_FRCMISS_SV ); REG64_FLD( EQ_ERR_RPT1_FIR37_RC_TGT_NODAL_REQ_CRESP_DINC , 27 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR37_RC_TGT_NODAL_REQ_CRESP_DINC ); REG64_FLD( EQ_ERR_RPT1_FIR37_SN_TGT_NODAL_REQ_CRESP_DINC , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR37_SN_TGT_NODAL_REQ_CRESP_DINC ); REG64_FLD( EQ_ERR_RPT1_FIR14_RC_UNEXP_DIRSTAT_VS_DSECT_CHK , 29 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR14_RC_UNEXP_DIRSTAT_VS_DSECT_CHK ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_RCX_UNEXP_IDLE_L3_CRESP , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_RCX_UNEXP_IDLE_L3_CRESP ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_RCX_UNEXP_IDLE_L3_DWDONE , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_RCX_UNEXP_IDLE_L3_DWDONE ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_RCX_UNEXP_PB_RC_DTAG_PCHK , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_RCX_UNEXP_PB_RC_DTAG_PCHK ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_DW_SET_REF_WITH_FLAG_IDLE , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_DW_SET_REF_WITH_FLAG_IDLE ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_KILL_REF_WITH_FLAG_IDLE , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_KILL_REF_WITH_FLAG_IDLE ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_DW_SET_SI_BY_MACH , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_DW_SET_SI_BY_MACH ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_PD_DIR_MULT_HIT , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_PD_DIR_MULT_HIT ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_B0_SD_DIR_MULT_HIT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_B0_SD_DIR_MULT_HIT ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_B1_SD_DIR_MULT_HIT , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_B1_SD_DIR_MULT_HIT ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_B2_SD_DIR_MULT_HIT , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_B2_SD_DIR_MULT_HIT ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_B3_SD_DIR_MULT_HIT , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_B3_SD_DIR_MULT_HIT ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_INVALID_SNP_CPS_STATU_RTN , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_INVALID_SNP_CPS_STATU_RTN ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_HANG_WAITING_FOR_FP_MATE , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_HANG_WAITING_FOR_FP_MATE ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_BAD_FP_MATE , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_BAD_FP_MATE ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_LSU_TAG_REUSE , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_LSU_TAG_REUSE ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_IFU_MULT_REQ , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_IFU_MULT_REQ ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_XPF_MULT_REQ , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_XPF_MULT_REQ ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_XLT_QUEUE_OVRFLW , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_XLT_QUEUE_OVRFLW ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_L3PF_REQ , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_L3PF_REQ ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_NCU_TID_DONE , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_NCU_TID_DONE ); REG64_FLD( EX_L2_ERR_RPT1_FIR11_LRU_MEM_INVALID_ABCD , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR11_LRU_MEM_INVALID_ABCD ); REG64_FLD( EX_L2_ERR_RPT1_FIR11_LRU_MEM_INVALID_EFGH , 22 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR11_LRU_MEM_INVALID_EFGH ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_STQ_COMING , 23 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_STQ_COMING ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_STQ_OVERFLOW , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_STQ_OVERFLOW ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_RC_PBBUS_SFSTAT , 25 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_RC_PBBUS_SFSTAT ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_TMA_LARXA_VS_FRCMISS_SV , 26 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_TMA_LARXA_VS_FRCMISS_SV ); REG64_FLD( EX_L2_ERR_RPT1_FIR37_RC_TGT_NODAL_REQ_CRESP_DINC , 27 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR37_RC_TGT_NODAL_REQ_CRESP_DINC ); REG64_FLD( EX_L2_ERR_RPT1_FIR37_SN_TGT_NODAL_REQ_CRESP_DINC , 28 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR37_SN_TGT_NODAL_REQ_CRESP_DINC ); REG64_FLD( EX_L2_ERR_RPT1_FIR14_RC_UNEXP_DIRSTAT_VS_DSECT_CHK , 29 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FIR14_RC_UNEXP_DIRSTAT_VS_DSECT_CHK ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_OVERFLOW , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_OVERFLOW ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_ILLEGAL_STORE_SIZE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_ILLEGAL_STORE_SIZE ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_LD_AMO_SEQ , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_LD_AMO_SEQ ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_CR0_TTAG_PERR , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_CR0_TTAG_PERR ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_CR0_ATAG_PERR , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_CR0_ATAG_PERR ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_CR1_TTAG_PERR , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_CR1_TTAG_PERR ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_CR1_ATAG_PERR , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_CR1_ATAG_PERR ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_CR2_TTAG_PERR , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_CR2_TTAG_PERR ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_CR2_ATAG_PERR , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_CR2_ATAG_PERR ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_CR3_TTAG_PERR , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_CR3_TTAG_PERR ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_CR3_ATAG_PERR , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_CR3_ATAG_PERR ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_SNP0_ADDR_PERR , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_SNP0_ADDR_PERR ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_SNP0_TTAG_PERR , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_SNP0_TTAG_PERR ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_SNP1_ADDR_PERR , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_SNP1_ADDR_PERR ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_SNP1_TTAG_PERR , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_SNP1_TTAG_PERR ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_PBARB_TRASHMODE , 15 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_PBARB_TRASHMODE ); REG64_FLD( EQ_ERR_RPT_REG_FIR1_TLBIE_BAD_OP , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR1_TLBIE_BAD_OP ); REG64_FLD( EQ_ERR_RPT_REG_FIR1_MASTER_SEQ_ID_PAR , 17 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR1_MASTER_SEQ_ID_PAR ); REG64_FLD( EQ_ERR_RPT_REG_FIR1_SNOOP_TLBIE_SEQ_PARITY , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR1_SNOOP_TLBIE_SEQ_PARITY ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_PURGE_LVL_ERR1 , 19 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_PURGE_LVL_ERR1 ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_PURGE_LVL_ERR2 , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_PURGE_LVL_ERR2 ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_PURGE_ABORT_LVL_ERR1 , 21 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_PURGE_ABORT_LVL_ERR1 ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_PURGE_ABORT_LVL_ERR2 , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_PURGE_ABORT_LVL_ERR2 ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_PURGE_DONE_LVL_ERR1 , 23 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_PURGE_DONE_LVL_ERR1 ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_IMA_FSM_TIMEOUT , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_IMA_FSM_TIMEOUT ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_PPE_WR_FSM_TIMEOUT , 25 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_PPE_WR_FSM_TIMEOUT ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_PPE_RD_FSM_TIMEOUT , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_PPE_RD_FSM_TIMEOUT ); REG64_FLD( EQ_ERR_RPT_REG_FIR0_TLB_DATA_PAR , 27 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR0_TLB_DATA_PAR ); REG64_FLD( EQ_ERR_RPT_REG_FIR19_LD_TGT_NODAL_DINC , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR19_LD_TGT_NODAL_DINC ); REG64_FLD( EQ_ERR_RPT_REG_FIR19_ST_TGT_NODAL_DINC , 29 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FIR19_ST_TGT_NODAL_DINC ); REG64_FLD( EX_ERR_RPT_REG_FIR0_OVERFLOW , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_OVERFLOW ); REG64_FLD( EX_ERR_RPT_REG_FIR0_ILLEGAL_STORE_SIZE , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_ILLEGAL_STORE_SIZE ); REG64_FLD( EX_ERR_RPT_REG_FIR0_LD_AMO_SEQ , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_LD_AMO_SEQ ); REG64_FLD( EX_ERR_RPT_REG_FIR0_CR0_TTAG_PERR , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_CR0_TTAG_PERR ); REG64_FLD( EX_ERR_RPT_REG_FIR0_CR0_ATAG_PERR , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_CR0_ATAG_PERR ); REG64_FLD( EX_ERR_RPT_REG_FIR0_CR1_TTAG_PERR , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_CR1_TTAG_PERR ); REG64_FLD( EX_ERR_RPT_REG_FIR0_CR1_ATAG_PERR , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_CR1_ATAG_PERR ); REG64_FLD( EX_ERR_RPT_REG_FIR0_CR2_TTAG_PERR , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_CR2_TTAG_PERR ); REG64_FLD( EX_ERR_RPT_REG_FIR0_CR2_ATAG_PERR , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_CR2_ATAG_PERR ); REG64_FLD( EX_ERR_RPT_REG_FIR0_CR3_TTAG_PERR , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_CR3_TTAG_PERR ); REG64_FLD( EX_ERR_RPT_REG_FIR0_CR3_ATAG_PERR , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_CR3_ATAG_PERR ); REG64_FLD( EX_ERR_RPT_REG_FIR0_SNP0_ADDR_PERR , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_SNP0_ADDR_PERR ); REG64_FLD( EX_ERR_RPT_REG_FIR0_SNP0_TTAG_PERR , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_SNP0_TTAG_PERR ); REG64_FLD( EX_ERR_RPT_REG_FIR0_SNP1_ADDR_PERR , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_SNP1_ADDR_PERR ); REG64_FLD( EX_ERR_RPT_REG_FIR0_SNP1_TTAG_PERR , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_SNP1_TTAG_PERR ); REG64_FLD( EX_ERR_RPT_REG_FIR0_PBARB_TRASHMODE , 15 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_PBARB_TRASHMODE ); REG64_FLD( EX_ERR_RPT_REG_FIR1_TLBIE_BAD_OP , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR1_TLBIE_BAD_OP ); REG64_FLD( EX_ERR_RPT_REG_FIR1_MASTER_SEQ_ID_PAR , 17 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR1_MASTER_SEQ_ID_PAR ); REG64_FLD( EX_ERR_RPT_REG_FIR1_SNOOP_TLBIE_SEQ_PARITY , 18 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR1_SNOOP_TLBIE_SEQ_PARITY ); REG64_FLD( EX_ERR_RPT_REG_FIR0_PURGE_LVL_ERR1 , 19 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_PURGE_LVL_ERR1 ); REG64_FLD( EX_ERR_RPT_REG_FIR0_PURGE_LVL_ERR2 , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_PURGE_LVL_ERR2 ); REG64_FLD( EX_ERR_RPT_REG_FIR0_PURGE_ABORT_LVL_ERR1 , 21 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_PURGE_ABORT_LVL_ERR1 ); REG64_FLD( EX_ERR_RPT_REG_FIR0_PURGE_ABORT_LVL_ERR2 , 22 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_PURGE_ABORT_LVL_ERR2 ); REG64_FLD( EX_ERR_RPT_REG_FIR0_PURGE_DONE_LVL_ERR1 , 23 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_PURGE_DONE_LVL_ERR1 ); REG64_FLD( EX_ERR_RPT_REG_FIR0_IMA_FSM_TIMEOUT , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_IMA_FSM_TIMEOUT ); REG64_FLD( EX_ERR_RPT_REG_FIR0_PPE_WR_FSM_TIMEOUT , 25 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_PPE_WR_FSM_TIMEOUT ); REG64_FLD( EX_ERR_RPT_REG_FIR0_PPE_RD_FSM_TIMEOUT , 26 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_PPE_RD_FSM_TIMEOUT ); REG64_FLD( EX_ERR_RPT_REG_FIR0_TLB_DATA_PAR , 27 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR0_TLB_DATA_PAR ); REG64_FLD( EX_ERR_RPT_REG_FIR19_LD_TGT_NODAL_DINC , 28 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR19_LD_TGT_NODAL_DINC ); REG64_FLD( EX_ERR_RPT_REG_FIR19_ST_TGT_NODAL_DINC , 29 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FIR19_ST_TGT_NODAL_DINC ); REG64_FLD( EQ_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD ); REG64_FLD( EQ_ERR_STATUS_REG_THERM_MODEREG_PARITY_ERR_HOLD , 1 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_THERM_MODEREG_PARITY_ERR_HOLD ); REG64_FLD( EQ_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_ERR_HOLD , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SKITTER_MODEREG_PARITY_ERR_HOLD ); REG64_FLD( EQ_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_ERR_HOLD , 3 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SKITTER_FORCEREG_PARITY_ERR_HOLD ); REG64_FLD( EQ_ERR_STATUS_REG_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD ); REG64_FLD( EQ_ERR_STATUS_REG_VOLT_MODEREG_PARITY_ERR_HOLD , 5 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VOLT_MODEREG_PARITY_ERR_HOLD ); REG64_FLD( EQ_ERR_STATUS_REG_SKITTER_CLKSRCREG_PARITY_ERR_HOLD , 6 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SKITTER_CLKSRCREG_PARITY_ERR_HOLD ); REG64_FLD( EQ_ERR_STATUS_REG_COUNT_STATE_ERR_HOLD , 7 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_COUNT_STATE_ERR_HOLD ); REG64_FLD( EQ_ERR_STATUS_REG_RUN_STATE_ERR_HOLD , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RUN_STATE_ERR_HOLD ); REG64_FLD( EQ_ERR_STATUS_REG_THRES_THERM_STATE_ERR_HOLD , 9 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_THRES_THERM_STATE_ERR_HOLD ); REG64_FLD( EQ_ERR_STATUS_REG_THRES_THERM_OVERFLOW_ERR_HOLD , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_THRES_THERM_OVERFLOW_ERR_HOLD ); REG64_FLD( EQ_ERR_STATUS_REG_SHIFTER_PARITY_ERR_HOLD , 11 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SHIFTER_PARITY_ERR_HOLD ); REG64_FLD( EQ_ERR_STATUS_REG_SHIFTER_VALID_ERR_HOLD , 12 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SHIFTER_VALID_ERR_HOLD ); REG64_FLD( EQ_ERR_STATUS_REG_TIMEOUT_ERR_HOLD , 13 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_TIMEOUT_ERR_HOLD ); REG64_FLD( EQ_ERR_STATUS_REG_F_SKITTER_ERR_HOLD , 14 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_F_SKITTER_ERR_HOLD ); REG64_FLD( EQ_ERR_STATUS_REG_PCB_ERR_HOLD_OUT , 15 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PCB_ERR_HOLD_OUT ); REG64_FLD( EQ_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK ); REG64_FLD( EQ_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK , 17 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_THERM_MODEREG_PARITY_MASK ); REG64_FLD( EQ_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_MASK , 18 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SKITTER_MODEREG_PARITY_MASK ); REG64_FLD( EQ_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_MASK , 19 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SKITTER_FORCEREG_PARITY_MASK ); REG64_FLD( EQ_ERR_STATUS_REG_SCAN_INIT_VERSION_PARITY_MASK , 20 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SCAN_INIT_VERSION_PARITY_MASK ); REG64_FLD( EQ_ERR_STATUS_REG_VOLT_MODEREG_PARITY_MASK , 21 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VOLT_MODEREG_PARITY_MASK ); REG64_FLD( EQ_ERR_STATUS_REG_COUNT_STATE_MASK , 23 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_COUNT_STATE_MASK ); REG64_FLD( EQ_ERR_STATUS_REG_RUN_STATE_MASK , 24 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RUN_STATE_MASK ); REG64_FLD( EQ_ERR_STATUS_REG_THRES_STATE_MASK , 25 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_THRES_STATE_MASK ); REG64_FLD( EQ_ERR_STATUS_REG_OVERFLOW_MASK , 26 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_OVERFLOW_MASK ); REG64_FLD( EQ_ERR_STATUS_REG_SHIFTER_PARITY_MASK , 27 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SHIFTER_PARITY_MASK ); REG64_FLD( EQ_ERR_STATUS_REG_SHIFTER_VALID_MASK , 28 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SHIFTER_VALID_MASK ); REG64_FLD( EQ_ERR_STATUS_REG_TIMEOUT_MASK , 29 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_TIMEOUT_MASK ); REG64_FLD( EQ_ERR_STATUS_REG_F_SKITTER_READ_MASK , 30 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_F_SKITTER_READ_MASK ); REG64_FLD( EQ_ERR_STATUS_REG_PCB_MASK , 31 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_PCB_MASK ); REG64_FLD( EQ_ERR_STATUS_REG_COUNT_STATE_LT , 40 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_COUNT_STATE_LT ); REG64_FLD( EQ_ERR_STATUS_REG_COUNT_STATE_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_COUNT_STATE_LT_LEN ); REG64_FLD( EQ_ERR_STATUS_REG_RUN_STATE_LT , 44 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RUN_STATE_LT ); REG64_FLD( EQ_ERR_STATUS_REG_RUN_STATE_LT_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RUN_STATE_LT_LEN ); REG64_FLD( EQ_ERR_STATUS_REG_SHIFT_DTS_LT , 47 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SHIFT_DTS_LT ); REG64_FLD( EQ_ERR_STATUS_REG_SHIFT_VOLT_LT , 48 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SHIFT_VOLT_LT ); REG64_FLD( EQ_ERR_STATUS_REG_READ_STATE_LT , 49 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_READ_STATE_LT ); REG64_FLD( EQ_ERR_STATUS_REG_READ_STATE_LT_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_READ_STATE_LT_LEN ); REG64_FLD( EQ_ERR_STATUS_REG_WRITE_STATE_LT , 51 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_WRITE_STATE_LT ); REG64_FLD( EQ_ERR_STATUS_REG_WRITE_STATE_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_WRITE_STATE_LT_LEN ); REG64_FLD( EQ_ERR_STATUS_REG_SAMPLE_DTS_LT , 55 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SAMPLE_DTS_LT ); REG64_FLD( EQ_ERR_STATUS_REG_MEASURE_VOLT_LT , 56 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_MEASURE_VOLT_LT ); REG64_FLD( EQ_ERR_STATUS_REG_READ_CPM_LT , 57 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_READ_CPM_LT ); REG64_FLD( EQ_ERR_STATUS_REG_WRITE_CPM_LT , 58 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_WRITE_CPM_LT ); REG64_FLD( EQ_ERR_STATUS_REG_UNUSED , 59 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_UNUSED ); REG64_FLD( EX_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD ); REG64_FLD( EX_ERR_STATUS_REG_THERM_MODEREG_PARITY_ERR_HOLD , 1 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_THERM_MODEREG_PARITY_ERR_HOLD ); REG64_FLD( EX_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_ERR_HOLD , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SKITTER_MODEREG_PARITY_ERR_HOLD ); REG64_FLD( EX_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_ERR_HOLD , 3 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SKITTER_FORCEREG_PARITY_ERR_HOLD ); REG64_FLD( EX_ERR_STATUS_REG_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD ); REG64_FLD( EX_ERR_STATUS_REG_VOLT_MODEREG_PARITY_ERR_HOLD , 5 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VOLT_MODEREG_PARITY_ERR_HOLD ); REG64_FLD( EX_ERR_STATUS_REG_SKITTER_CLKSRCREG_PARITY_ERR_HOLD , 6 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SKITTER_CLKSRCREG_PARITY_ERR_HOLD ); REG64_FLD( EX_ERR_STATUS_REG_COUNT_STATE_ERR_HOLD , 7 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_COUNT_STATE_ERR_HOLD ); REG64_FLD( EX_ERR_STATUS_REG_RUN_STATE_ERR_HOLD , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_RUN_STATE_ERR_HOLD ); REG64_FLD( EX_ERR_STATUS_REG_THRES_THERM_STATE_ERR_HOLD , 9 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_THRES_THERM_STATE_ERR_HOLD ); REG64_FLD( EX_ERR_STATUS_REG_THRES_THERM_OVERFLOW_ERR_HOLD , 10 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_THRES_THERM_OVERFLOW_ERR_HOLD ); REG64_FLD( EX_ERR_STATUS_REG_SHIFTER_PARITY_ERR_HOLD , 11 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SHIFTER_PARITY_ERR_HOLD ); REG64_FLD( EX_ERR_STATUS_REG_SHIFTER_VALID_ERR_HOLD , 12 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SHIFTER_VALID_ERR_HOLD ); REG64_FLD( EX_ERR_STATUS_REG_TIMEOUT_ERR_HOLD , 13 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_TIMEOUT_ERR_HOLD ); REG64_FLD( EX_ERR_STATUS_REG_F_SKITTER_ERR_HOLD , 14 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_F_SKITTER_ERR_HOLD ); REG64_FLD( EX_ERR_STATUS_REG_PCB_ERR_HOLD_OUT , 15 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PCB_ERR_HOLD_OUT ); REG64_FLD( EX_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK ); REG64_FLD( EX_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK , 17 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_THERM_MODEREG_PARITY_MASK ); REG64_FLD( EX_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_MASK , 18 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SKITTER_MODEREG_PARITY_MASK ); REG64_FLD( EX_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_MASK , 19 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SKITTER_FORCEREG_PARITY_MASK ); REG64_FLD( EX_ERR_STATUS_REG_SCAN_INIT_VERSION_PARITY_MASK , 20 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SCAN_INIT_VERSION_PARITY_MASK ); REG64_FLD( EX_ERR_STATUS_REG_VOLT_MODEREG_PARITY_MASK , 21 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VOLT_MODEREG_PARITY_MASK ); REG64_FLD( EX_ERR_STATUS_REG_COUNT_STATE_MASK , 23 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_COUNT_STATE_MASK ); REG64_FLD( EX_ERR_STATUS_REG_RUN_STATE_MASK , 24 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_RUN_STATE_MASK ); REG64_FLD( EX_ERR_STATUS_REG_THRES_STATE_MASK , 25 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_THRES_STATE_MASK ); REG64_FLD( EX_ERR_STATUS_REG_OVERFLOW_MASK , 26 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_OVERFLOW_MASK ); REG64_FLD( EX_ERR_STATUS_REG_SHIFTER_PARITY_MASK , 27 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SHIFTER_PARITY_MASK ); REG64_FLD( EX_ERR_STATUS_REG_SHIFTER_VALID_MASK , 28 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SHIFTER_VALID_MASK ); REG64_FLD( EX_ERR_STATUS_REG_TIMEOUT_MASK , 29 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_TIMEOUT_MASK ); REG64_FLD( EX_ERR_STATUS_REG_F_SKITTER_READ_MASK , 30 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_F_SKITTER_READ_MASK ); REG64_FLD( EX_ERR_STATUS_REG_PCB_MASK , 31 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_PCB_MASK ); REG64_FLD( EX_ERR_STATUS_REG_COUNT_STATE_LT , 40 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_COUNT_STATE_LT ); REG64_FLD( EX_ERR_STATUS_REG_COUNT_STATE_LT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_COUNT_STATE_LT_LEN ); REG64_FLD( EX_ERR_STATUS_REG_RUN_STATE_LT , 44 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_RUN_STATE_LT ); REG64_FLD( EX_ERR_STATUS_REG_RUN_STATE_LT_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_RUN_STATE_LT_LEN ); REG64_FLD( EX_ERR_STATUS_REG_SHIFT_DTS_LT , 47 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SHIFT_DTS_LT ); REG64_FLD( EX_ERR_STATUS_REG_SHIFT_VOLT_LT , 48 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SHIFT_VOLT_LT ); REG64_FLD( EX_ERR_STATUS_REG_READ_STATE_LT , 49 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_READ_STATE_LT ); REG64_FLD( EX_ERR_STATUS_REG_READ_STATE_LT_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_READ_STATE_LT_LEN ); REG64_FLD( EX_ERR_STATUS_REG_WRITE_STATE_LT , 51 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_WRITE_STATE_LT ); REG64_FLD( EX_ERR_STATUS_REG_WRITE_STATE_LT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_WRITE_STATE_LT_LEN ); REG64_FLD( EX_ERR_STATUS_REG_SAMPLE_DTS_LT , 55 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SAMPLE_DTS_LT ); REG64_FLD( EX_ERR_STATUS_REG_MEASURE_VOLT_LT , 56 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MEASURE_VOLT_LT ); REG64_FLD( EX_ERR_STATUS_REG_READ_CPM_LT , 57 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_READ_CPM_LT ); REG64_FLD( EX_ERR_STATUS_REG_WRITE_CPM_LT , 58 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_WRITE_CPM_LT ); REG64_FLD( EX_ERR_STATUS_REG_UNUSED , 59 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_UNUSED ); REG64_FLD( C_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_ERR_HOLD ); REG64_FLD( C_ERR_STATUS_REG_THERM_MODEREG_PARITY_ERR_HOLD , 1 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_THERM_MODEREG_PARITY_ERR_HOLD ); REG64_FLD( C_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_ERR_HOLD , 2 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_SKITTER_MODEREG_PARITY_ERR_HOLD ); REG64_FLD( C_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_ERR_HOLD , 3 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_SKITTER_FORCEREG_PARITY_ERR_HOLD ); REG64_FLD( C_ERR_STATUS_REG_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_SCAN_INIT_VERSION_REG_PARITY_ERR_HOLD ); REG64_FLD( C_ERR_STATUS_REG_VOLT_MODEREG_PARITY_ERR_HOLD , 5 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VOLT_MODEREG_PARITY_ERR_HOLD ); REG64_FLD( C_ERR_STATUS_REG_SKITTER_CLKSRCREG_PARITY_ERR_HOLD , 6 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_SKITTER_CLKSRCREG_PARITY_ERR_HOLD ); REG64_FLD( C_ERR_STATUS_REG_COUNT_STATE_ERR_HOLD , 7 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_COUNT_STATE_ERR_HOLD ); REG64_FLD( C_ERR_STATUS_REG_RUN_STATE_ERR_HOLD , 8 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_RUN_STATE_ERR_HOLD ); REG64_FLD( C_ERR_STATUS_REG_THRES_THERM_STATE_ERR_HOLD , 9 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_THRES_THERM_STATE_ERR_HOLD ); REG64_FLD( C_ERR_STATUS_REG_THRES_THERM_OVERFLOW_ERR_HOLD , 10 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_THRES_THERM_OVERFLOW_ERR_HOLD ); REG64_FLD( C_ERR_STATUS_REG_SHIFTER_PARITY_ERR_HOLD , 11 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_SHIFTER_PARITY_ERR_HOLD ); REG64_FLD( C_ERR_STATUS_REG_SHIFTER_VALID_ERR_HOLD , 12 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_SHIFTER_VALID_ERR_HOLD ); REG64_FLD( C_ERR_STATUS_REG_TIMEOUT_ERR_HOLD , 13 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_TIMEOUT_ERR_HOLD ); REG64_FLD( C_ERR_STATUS_REG_F_SKITTER_ERR_HOLD , 14 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_F_SKITTER_ERR_HOLD ); REG64_FLD( C_ERR_STATUS_REG_PCB_ERR_HOLD_OUT , 15 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_PCB_ERR_HOLD_OUT ); REG64_FLD( C_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK , 16 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK ); REG64_FLD( C_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK , 17 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_THERM_MODEREG_PARITY_MASK ); REG64_FLD( C_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_MASK , 18 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_SKITTER_MODEREG_PARITY_MASK ); REG64_FLD( C_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_MASK , 19 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_SKITTER_FORCEREG_PARITY_MASK ); REG64_FLD( C_ERR_STATUS_REG_SCAN_INIT_VERSION_PARITY_MASK , 20 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_SCAN_INIT_VERSION_PARITY_MASK ); REG64_FLD( C_ERR_STATUS_REG_VOLT_MODEREG_PARITY_MASK , 21 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VOLT_MODEREG_PARITY_MASK ); REG64_FLD( C_ERR_STATUS_REG_COUNT_STATE_MASK , 23 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_COUNT_STATE_MASK ); REG64_FLD( C_ERR_STATUS_REG_RUN_STATE_MASK , 24 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_RUN_STATE_MASK ); REG64_FLD( C_ERR_STATUS_REG_THRES_STATE_MASK , 25 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_THRES_STATE_MASK ); REG64_FLD( C_ERR_STATUS_REG_OVERFLOW_MASK , 26 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_OVERFLOW_MASK ); REG64_FLD( C_ERR_STATUS_REG_SHIFTER_PARITY_MASK , 27 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_SHIFTER_PARITY_MASK ); REG64_FLD( C_ERR_STATUS_REG_SHIFTER_VALID_MASK , 28 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_SHIFTER_VALID_MASK ); REG64_FLD( C_ERR_STATUS_REG_TIMEOUT_MASK , 29 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_TIMEOUT_MASK ); REG64_FLD( C_ERR_STATUS_REG_F_SKITTER_READ_MASK , 30 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_F_SKITTER_READ_MASK ); REG64_FLD( C_ERR_STATUS_REG_PCB_MASK , 31 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_PCB_MASK ); REG64_FLD( C_ERR_STATUS_REG_COUNT_STATE_LT , 40 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_COUNT_STATE_LT ); REG64_FLD( C_ERR_STATUS_REG_COUNT_STATE_LT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_COUNT_STATE_LT_LEN ); REG64_FLD( C_ERR_STATUS_REG_RUN_STATE_LT , 44 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_RUN_STATE_LT ); REG64_FLD( C_ERR_STATUS_REG_RUN_STATE_LT_LEN , 3 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_RUN_STATE_LT_LEN ); REG64_FLD( C_ERR_STATUS_REG_SHIFT_DTS_LT , 47 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_SHIFT_DTS_LT ); REG64_FLD( C_ERR_STATUS_REG_SHIFT_VOLT_LT , 48 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_SHIFT_VOLT_LT ); REG64_FLD( C_ERR_STATUS_REG_READ_STATE_LT , 49 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_READ_STATE_LT ); REG64_FLD( C_ERR_STATUS_REG_READ_STATE_LT_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_READ_STATE_LT_LEN ); REG64_FLD( C_ERR_STATUS_REG_WRITE_STATE_LT , 51 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_WRITE_STATE_LT ); REG64_FLD( C_ERR_STATUS_REG_WRITE_STATE_LT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_WRITE_STATE_LT_LEN ); REG64_FLD( C_ERR_STATUS_REG_SAMPLE_DTS_LT , 55 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_SAMPLE_DTS_LT ); REG64_FLD( C_ERR_STATUS_REG_MEASURE_VOLT_LT , 56 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_MEASURE_VOLT_LT ); REG64_FLD( C_ERR_STATUS_REG_READ_CPM_LT , 57 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_READ_CPM_LT ); REG64_FLD( C_ERR_STATUS_REG_WRITE_CPM_LT , 58 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_WRITE_CPM_LT ); REG64_FLD( C_ERR_STATUS_REG_UNUSED , 59 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_UNUSED ); REG64_FLD( EQ_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( EQ_FIR_ACTION0_REG_ACTION0_LEN , 31 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); REG64_FLD( EX_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( EX_FIR_ACTION0_REG_ACTION0_LEN , 31 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); REG64_FLD( EX_L2_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( EX_L2_FIR_ACTION0_REG_ACTION0_LEN , 42 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); REG64_FLD( EX_L3_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( EX_L3_FIR_ACTION0_REG_ACTION0_LEN , 31 , SH_UNT_EX_L3 , SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); REG64_FLD( EQ_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); REG64_FLD( EQ_FIR_ACTION1_REG_ACTION1_LEN , 31 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); REG64_FLD( EX_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); REG64_FLD( EX_FIR_ACTION1_REG_ACTION1_LEN , 31 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); REG64_FLD( EX_L2_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); REG64_FLD( EX_L2_FIR_ACTION1_REG_ACTION1_LEN , 42 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); REG64_FLD( EX_L3_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); REG64_FLD( EX_L3_FIR_ACTION1_REG_ACTION1_LEN , 31 , SH_UNT_EX_L3 , SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); REG64_FLD( EX_L2_FIR_ERR_INJ_TO_LSU , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_TO_LSU ); REG64_FLD( EX_L2_FIR_ERR_INJ_TO_IFU , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_TO_IFU ); REG64_FLD( EX_L2_FIR_ERR_INJ_TO_ISU , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_TO_ISU ); REG64_FLD( EX_L2_FIR_ERR_INJ_TO_VSU , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_TO_VSU ); REG64_FLD( EX_L2_FIR_ERR_INJ_TO_PC , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_TO_PC ); REG64_FLD( EX_L2_FIR_ERR_INJ_RESERVED , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_RESERVED ); REG64_FLD( EX_L2_FIR_ERR_INJ_ERROR_PULSE_OR_LEVEL , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ERROR_PULSE_OR_LEVEL ); REG64_FLD( EX_L2_FIR_ERR_INJ_CLEAR_STICKY_LEVEL , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_CLEAR_STICKY_LEVEL ); REG64_FLD( EX_L2_FIR_ERR_INJ_SCOM_WRITE , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_SCOM_WRITE ); REG64_FLD( EX_L2_FIR_ERR_INJ_TRIGGER , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_TRIGGER ); REG64_FLD( EX_L2_FIR_ERR_INJ_TRIGGER1 , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_TRIGGER1 ); REG64_FLD( EX_L2_FIR_ERR_INJ_TOD_TAP , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_TOD_TAP ); REG64_FLD( EX_L2_FIR_ERR_INJ_BLOCK , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_BLOCK ); REG64_FLD( EX_L2_FIR_ERR_INJ_BLOCK_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_BLOCK_LEN ); REG64_FLD( EX_L2_FIR_ERR_INJ_DELAY_AFTER_BLOCK , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_DELAY_AFTER_BLOCK ); REG64_FLD( EX_L2_FIR_ERR_INJ_RECOVERY_BLK , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_RECOVERY_BLK ); REG64_FLD( EX_L2_FIR_ERR_INJ_RECOVERY_BLK_EXTEND , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_RECOVERY_BLK_EXTEND ); REG64_FLD( EX_L2_FIR_ERR_INJ_TAP_SEL , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_TAP_SEL ); REG64_FLD( EX_L2_FIR_ERR_INJ_TAP_SEL_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_TAP_SEL_LEN ); REG64_FLD( EX_L2_FIR_ERR_INJ_HYP_BLOCK , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_HYP_BLOCK ); REG64_FLD( EX_L2_FIR_ERR_INJ_HYP_BLOCK_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_HYP_BLOCK_LEN ); REG64_FLD( C_FIR_ERR_INJ_TO_LSU , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_TO_LSU ); REG64_FLD( C_FIR_ERR_INJ_TO_IFU , 1 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_TO_IFU ); REG64_FLD( C_FIR_ERR_INJ_TO_ISU , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_TO_ISU ); REG64_FLD( C_FIR_ERR_INJ_TO_VSU , 3 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_TO_VSU ); REG64_FLD( C_FIR_ERR_INJ_TO_PC , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_TO_PC ); REG64_FLD( C_FIR_ERR_INJ_RESERVED , 5 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RESERVED ); REG64_FLD( C_FIR_ERR_INJ_ERROR_PULSE_OR_LEVEL , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ERROR_PULSE_OR_LEVEL ); REG64_FLD( C_FIR_ERR_INJ_CLEAR_STICKY_LEVEL , 7 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_CLEAR_STICKY_LEVEL ); REG64_FLD( C_FIR_ERR_INJ_SCOM_WRITE , 8 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SCOM_WRITE ); REG64_FLD( C_FIR_ERR_INJ_TRIGGER , 9 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_TRIGGER ); REG64_FLD( C_FIR_ERR_INJ_TRIGGER1 , 10 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_TRIGGER1 ); REG64_FLD( C_FIR_ERR_INJ_TOD_TAP , 11 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_TOD_TAP ); REG64_FLD( C_FIR_ERR_INJ_BLOCK , 12 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_BLOCK ); REG64_FLD( C_FIR_ERR_INJ_BLOCK_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_BLOCK_LEN ); REG64_FLD( C_FIR_ERR_INJ_DELAY_AFTER_BLOCK , 14 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_DELAY_AFTER_BLOCK ); REG64_FLD( C_FIR_ERR_INJ_RECOVERY_BLK , 15 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RECOVERY_BLK ); REG64_FLD( C_FIR_ERR_INJ_RECOVERY_BLK_EXTEND , 16 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RECOVERY_BLK_EXTEND ); REG64_FLD( C_FIR_ERR_INJ_TAP_SEL , 17 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_TAP_SEL ); REG64_FLD( C_FIR_ERR_INJ_TAP_SEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_TAP_SEL_LEN ); REG64_FLD( C_FIR_ERR_INJ_HYP_BLOCK , 21 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_HYP_BLOCK ); REG64_FLD( C_FIR_ERR_INJ_HYP_BLOCK_LEN , 3 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_HYP_BLOCK_LEN ); REG64_FLD( EQ_FIR_MASK_IN0 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN0 ); REG64_FLD( EQ_FIR_MASK_IN1 , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN1 ); REG64_FLD( EQ_FIR_MASK_IN2 , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN2 ); REG64_FLD( EQ_FIR_MASK_IN3 , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN3 ); REG64_FLD( EQ_FIR_MASK_IN4 , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN4 ); REG64_FLD( EQ_FIR_MASK_IN5 , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN5 ); REG64_FLD( EQ_FIR_MASK_IN5_LEN , 21 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN5_LEN ); REG64_FLD( EQ_FIR_MASK_IN26 , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN26 ); REG64_FLD( EX_FIR_MASK_IN0 , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN0 ); REG64_FLD( EX_FIR_MASK_IN1 , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN1 ); REG64_FLD( EX_FIR_MASK_IN2 , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN2 ); REG64_FLD( EX_FIR_MASK_IN3 , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN3 ); REG64_FLD( EX_FIR_MASK_IN4 , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN4 ); REG64_FLD( EX_FIR_MASK_IN5 , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN5 ); REG64_FLD( EX_FIR_MASK_IN5_LEN , 21 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN5_LEN ); REG64_FLD( EX_FIR_MASK_IN26 , 26 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN26 ); REG64_FLD( C_FIR_MASK_IN0 , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN0 ); REG64_FLD( C_FIR_MASK_IN1 , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN1 ); REG64_FLD( C_FIR_MASK_IN2 , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN2 ); REG64_FLD( C_FIR_MASK_IN3 , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN3 ); REG64_FLD( C_FIR_MASK_IN4 , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN4 ); REG64_FLD( C_FIR_MASK_IN5 , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN5 ); REG64_FLD( C_FIR_MASK_IN5_LEN , 21 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN5_LEN ); REG64_FLD( C_FIR_MASK_IN26 , 26 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN26 ); REG64_FLD( EQ_FIR_MASK_REG_MASK , 0 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_MASK ); REG64_FLD( EQ_FIR_MASK_REG_MASK_LEN , 31 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_MASK_LEN ); REG64_FLD( EX_FIR_MASK_REG_MASK , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_MASK ); REG64_FLD( EX_FIR_MASK_REG_MASK_LEN , 31 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_MASK_LEN ); REG64_FLD( EX_L2_FIR_MASK_REG_L2 , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_L2 ); REG64_FLD( EX_L2_FIR_MASK_REG_L2_LEN , 42 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_L2_LEN ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_RDDSP_SEGR_LCO_ALL_MEM_UNAVAIL_ERR_MASK , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_RDDSP_SEGR_LCO_ALL_MEM_UNAVAIL_ERR_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_FIR_SPARE1_MASK , 1 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_FIR_SPARE1_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_FIR_SPARE2_MASK , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_FIR_SPARE2_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_DRAM_POS_WORDLINE_FAIL_MASK , 3 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_DRAM_POS_WORDLINE_FAIL_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_CAC_RD_CE_DET_NOT_LINDEL_REQ_MASK , 4 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_CAC_RD_CE_DET_NOT_LINDEL_REQ_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_CAC_RD_UE_DET_MASK , 5 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_CAC_RD_UE_DET_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_CAC_RD_SUE_DET_MASK , 6 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_CAC_RD_SUE_DET_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_CAC_WR_DATA_CE_FROM_PB_MASK , 7 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_CAC_WR_DATA_CE_FROM_PB_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_CAC_WR_DATA_UE_FROM_PB_MASK , 8 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_CAC_WR_DATA_UE_FROM_PB_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_CAC_WR_DATA_SUE_FROM_PB_MASK , 9 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_CAC_WR_DATA_SUE_FROM_PB_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_CAC_WR_DATA_CE_FROM_L2_MASK , 10 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_CAC_WR_DATA_CE_FROM_L2_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_CAC_WR_DATA_UE_FROM_L2_MASK , 11 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_CAC_WR_DATA_UE_FROM_L2_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_CAC_WR_DATA_SUE_FROM_L2_OR_WIHPC_MASK , 12 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_CAC_WR_DATA_SUE_FROM_L2_OR_WIHPC_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_DIR_RD_CE_DET_MASK , 13 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_DIR_RD_CE_DET_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_DIR_RD_UE_DET_MASK , 14 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_DIR_RD_UE_DET_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_DIR_RD_PHANTOM_ERROR_MASK , 15 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_DIR_RD_PHANTOM_ERROR_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_PB_MAST_WR_ADDR_ERR_MASK , 16 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_PB_MAST_WR_ADDR_ERR_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_PB_MAST_RD_ADDR_ERR_MASK , 17 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_PB_MAST_RD_ADDR_ERR_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_ADDR_HANG_DETECTED_MASK , 18 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_ADDR_HANG_DETECTED_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_LRU_INVAL_CNT_MASK , 19 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_LRU_INVAL_CNT_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_PPE_RD_CE_DET_MASK , 20 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_PPE_RD_CE_DET_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_PPE_RD_UE_DET_MASK , 21 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_PPE_RD_UE_DET_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_PPE_RD_SUE_DET_MASK , 22 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_PPE_RD_SUE_DET_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_MACH_HANG_DETECTED_MASK , 23 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_MACH_HANG_DETECTED_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_HW_CONTROL_ERR_MASK , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_HW_CONTROL_ERR_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_SNP_CACHE_INHIBIT_ERR_MASK , 25 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_SNP_CACHE_INHIBIT_ERR_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_LINE_DEL_CE_DONE_MASK , 26 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_LINE_DEL_CE_DONE_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_DRAM_ERROR_MASK , 27 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_DRAM_ERROR_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_LRU_ERROR_MASK , 28 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_LRU_ERROR_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_ALL_MEMBERS_DELETED_ERROR_MASK , 29 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_ALL_MEMBERS_DELETED_ERROR_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_REFRESH_TIMER_ERROR_MASK , 30 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_REFRESH_TIMER_ERROR_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_PB_MAST_WR_ACK_DEAD_MASK , 31 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_PB_MAST_WR_ACK_DEAD_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_L3_PB_MAST_RD_ACK_DEAD_MASK , 32 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_PB_MAST_RD_ACK_DEAD_MASK ); REG64_FLD( EX_L3_FIR_MASK_REG_SCOM_ERR_MASK1 , 33 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_MASK1 ); REG64_FLD( EX_L3_FIR_MASK_REG_SCOM_ERR_MASK2 , 34 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_MASK2 ); REG64_FLD( EQ_FIR_REG_CONTROL_ERR , 0 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_CONTROL_ERR ); REG64_FLD( EQ_FIR_REG_TLBIE_CONTROL_ERR , 1 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_TLBIE_CONTROL_ERR ); REG64_FLD( EQ_FIR_REG_TLBIE_SLBIEG_SW_ERR , 2 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_TLBIE_SLBIEG_SW_ERR ); REG64_FLD( EQ_FIR_REG_ST_ADDR_ERR , 3 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_ST_ADDR_ERR ); REG64_FLD( EQ_FIR_REG_LD_ADDR_ERR , 4 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_LD_ADDR_ERR ); REG64_FLD( EQ_FIR_REG_ST_ACK_DEAD , 5 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_ST_ACK_DEAD ); REG64_FLD( EQ_FIR_REG_LD_ACK_DEAD , 6 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_LD_ACK_DEAD ); REG64_FLD( EQ_FIR_REG_MSG_ADDR_ERR , 7 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_MSG_ADDR_ERR ); REG64_FLD( EQ_FIR_REG_STQ_DATA_PARITY_ERR , 8 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_STQ_DATA_PARITY_ERR ); REG64_FLD( EQ_FIR_REG_STORE_TIMEOUT , 9 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_STORE_TIMEOUT ); REG64_FLD( EQ_FIR_REG_TLBIE_MASTER_TIMEOUT , 10 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_TLBIE_MASTER_TIMEOUT ); REG64_FLD( EQ_FIR_REG_TLBIE_SNOOP_TIMEOUT , 11 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_TLBIE_SNOOP_TIMEOUT ); REG64_FLD( EQ_FIR_REG_IMA_CRESP_ADDR_ERR , 12 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IMA_CRESP_ADDR_ERR ); REG64_FLD( EQ_FIR_REG_IMA_ACK_DEAD , 13 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IMA_ACK_DEAD ); REG64_FLD( EQ_FIR_REG_PMISC_CRESP_ADDR_ERR , 14 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_PMISC_CRESP_ADDR_ERR ); REG64_FLD( EQ_FIR_REG_PPE_RD_CRESP_ADDR_ERR , 15 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_PPE_RD_CRESP_ADDR_ERR ); REG64_FLD( EQ_FIR_REG_PPE_WR_CRESP_ADDR_ERR , 16 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_PPE_WR_CRESP_ADDR_ERR ); REG64_FLD( EQ_FIR_REG_PPE_RD_ACK_DEAD , 17 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_PPE_RD_ACK_DEAD ); REG64_FLD( EQ_FIR_REG_PPE_WR_ACK_DEAD , 18 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_PPE_WR_ACK_DEAD ); REG64_FLD( EQ_FIR_REG_TGT_NODAL_DINC_ERR , 19 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_TGT_NODAL_DINC_ERR ); REG64_FLD( EQ_FIR_REG_DARN_EN_ERR , 20 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_DARN_EN_ERR ); REG64_FLD( EQ_FIR_REG_DARN_ADDR_ERR , 21 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_DARN_ADDR_ERR ); REG64_FLD( EQ_FIR_REG_SPARE , 22 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_SPARE ); REG64_FLD( EQ_FIR_REG_SPARE_LEN , 7 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_SPARE_LEN ); REG64_FLD( EQ_FIR_REG_SCOM_ERR1 , 29 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR1 ); REG64_FLD( EQ_FIR_REG_SCOM_ERR2 , 30 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR2 ); REG64_FLD( EX_FIR_REG_CONTROL_ERR , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CONTROL_ERR ); REG64_FLD( EX_FIR_REG_TLBIE_CONTROL_ERR , 1 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_TLBIE_CONTROL_ERR ); REG64_FLD( EX_FIR_REG_TLBIE_SLBIEG_SW_ERR , 2 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_TLBIE_SLBIEG_SW_ERR ); REG64_FLD( EX_FIR_REG_ST_ADDR_ERR , 3 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_ST_ADDR_ERR ); REG64_FLD( EX_FIR_REG_LD_ADDR_ERR , 4 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_LD_ADDR_ERR ); REG64_FLD( EX_FIR_REG_ST_ACK_DEAD , 5 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_ST_ACK_DEAD ); REG64_FLD( EX_FIR_REG_LD_ACK_DEAD , 6 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_LD_ACK_DEAD ); REG64_FLD( EX_FIR_REG_MSG_ADDR_ERR , 7 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_MSG_ADDR_ERR ); REG64_FLD( EX_FIR_REG_STQ_DATA_PARITY_ERR , 8 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_STQ_DATA_PARITY_ERR ); REG64_FLD( EX_FIR_REG_STORE_TIMEOUT , 9 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_STORE_TIMEOUT ); REG64_FLD( EX_FIR_REG_TLBIE_MASTER_TIMEOUT , 10 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_TLBIE_MASTER_TIMEOUT ); REG64_FLD( EX_FIR_REG_TLBIE_SNOOP_TIMEOUT , 11 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_TLBIE_SNOOP_TIMEOUT ); REG64_FLD( EX_FIR_REG_IMA_CRESP_ADDR_ERR , 12 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IMA_CRESP_ADDR_ERR ); REG64_FLD( EX_FIR_REG_IMA_ACK_DEAD , 13 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IMA_ACK_DEAD ); REG64_FLD( EX_FIR_REG_PMISC_CRESP_ADDR_ERR , 14 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PMISC_CRESP_ADDR_ERR ); REG64_FLD( EX_FIR_REG_PPE_RD_CRESP_ADDR_ERR , 15 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PPE_RD_CRESP_ADDR_ERR ); REG64_FLD( EX_FIR_REG_PPE_WR_CRESP_ADDR_ERR , 16 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PPE_WR_CRESP_ADDR_ERR ); REG64_FLD( EX_FIR_REG_PPE_RD_ACK_DEAD , 17 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PPE_RD_ACK_DEAD ); REG64_FLD( EX_FIR_REG_PPE_WR_ACK_DEAD , 18 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PPE_WR_ACK_DEAD ); REG64_FLD( EX_FIR_REG_TGT_NODAL_DINC_ERR , 19 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_TGT_NODAL_DINC_ERR ); REG64_FLD( EX_FIR_REG_DARN_EN_ERR , 20 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_DARN_EN_ERR ); REG64_FLD( EX_FIR_REG_DARN_ADDR_ERR , 21 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_DARN_ADDR_ERR ); REG64_FLD( EX_FIR_REG_SPARE , 22 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE ); REG64_FLD( EX_FIR_REG_SPARE_LEN , 7 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_LEN ); REG64_FLD( EX_FIR_REG_SCOM_ERR1 , 29 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR1 ); REG64_FLD( EX_FIR_REG_SCOM_ERR2 , 30 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR2 ); REG64_FLD( EX_L2_FIR_REG_CACHE_RD_CE , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_CACHE_RD_CE ); REG64_FLD( EX_L2_FIR_REG_CACHE_RD_UE , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_CACHE_RD_UE ); REG64_FLD( EX_L2_FIR_REG_CACHE_RD_SUE , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_CACHE_RD_SUE ); REG64_FLD( EX_L2_FIR_REG_HW_DIR_INTIATED_LINE_DELETE_OCCURRED , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_HW_DIR_INTIATED_LINE_DELETE_OCCURRED ); REG64_FLD( EX_L2_FIR_REG_CACHE_UE_SUE_DETECTED_ON_MODIFIED_LINE_BY_CO , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_CACHE_UE_SUE_DETECTED_ON_MODIFIED_LINE_BY_CO ); REG64_FLD( EX_L2_FIR_REG_CACHE_UE_SUE_DETECTED_ON_NON_MODIFIED_LINE_BY_CO , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_CACHE_UE_SUE_DETECTED_ON_NON_MODIFIED_LINE_BY_CO ); REG64_FLD( EX_L2_FIR_REG_DIR_CE_DETECTED , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_DIR_CE_DETECTED ); REG64_FLD( EX_L2_FIR_REG_DIR_UE_DETECTED , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_DIR_UE_DETECTED ); REG64_FLD( EX_L2_FIR_REG_DIR_STUCK_BIT_CE , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_DIR_STUCK_BIT_CE ); REG64_FLD( EX_L2_FIR_REG_DIR_SBCE_REPAIR_FAILED , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_DIR_SBCE_REPAIR_FAILED ); REG64_FLD( EX_L2_FIR_REG_MULTIPLE_DIR_ERRORS_DETECTED , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MULTIPLE_DIR_ERRORS_DETECTED ); REG64_FLD( EX_L2_FIR_REG_LRU_READ_ERROR_DETECTED , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LRU_READ_ERROR_DETECTED ); REG64_FLD( EX_L2_FIR_REG_RC_POWERBUS_DATA_TIMEOUT , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_RC_POWERBUS_DATA_TIMEOUT ); REG64_FLD( EX_L2_FIR_REG_NCU_POWERBUS_DATA_TIMEOUT , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_NCU_POWERBUS_DATA_TIMEOUT ); REG64_FLD( EX_L2_FIR_REG_HW_CONTROL_ERROR , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_HW_CONTROL_ERROR ); REG64_FLD( EX_L2_FIR_REG_LRU_ALL_MEMBERS_IN_CGC_ARE_LINE_DELETED , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LRU_ALL_MEMBERS_IN_CGC_ARE_LINE_DELETED ); REG64_FLD( EX_L2_FIR_REG_CACHE_INHIBITED_HIT_CACHEABLE_ERROR , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_CACHE_INHIBITED_HIT_CACHEABLE_ERROR ); REG64_FLD( EX_L2_FIR_REG_RC_LOAD_RECEIVED_PB_CRESP_ADR_ERR , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_RC_LOAD_RECEIVED_PB_CRESP_ADR_ERR ); REG64_FLD( EX_L2_FIR_REG_RC_STORE_RECEIVED_PB_CRESP_ADR_ERR , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_RC_STORE_RECEIVED_PB_CRESP_ADR_ERR ); REG64_FLD( EX_L2_FIR_REG_RC_POWBUS_DATA_CE_ERR_FROM_F2CHK , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_RC_POWBUS_DATA_CE_ERR_FROM_F2CHK ); REG64_FLD( EX_L2_FIR_REG_RC_POWBUS_DATA_UE_ERR_FROM_F2CHK , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_RC_POWBUS_DATA_UE_ERR_FROM_F2CHK ); REG64_FLD( EX_L2_FIR_REG_RC_POWBUS_DATA_SUE_ERR_FROM_F2CHK , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_RC_POWBUS_DATA_SUE_ERR_FROM_F2CHK ); REG64_FLD( EX_L2_FIR_REG_TGT_NODAL_REQ_DINC_ERR , 22 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_TGT_NODAL_REQ_DINC_ERR ); REG64_FLD( EX_L2_FIR_REG_RC_LOAD_RECEIVED_PB_CRESP_ADR_ERR_FOR_HYP , 23 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_RC_LOAD_RECEIVED_PB_CRESP_ADR_ERR_FOR_HYP ); REG64_FLD( EX_L2_FIR_REG_RCDAT_RD_PARITY_ERR , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_RCDAT_RD_PARITY_ERR ); REG64_FLD( EX_L2_FIR_REG_CO_PSH_RECEIVED_PB_CRESP_ADR_ERR , 25 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_CO_PSH_RECEIVED_PB_CRESP_ADR_ERR ); REG64_FLD( EX_L2_FIR_REG_LVDIR_PERR , 26 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LVDIR_PERR ); REG64_FLD( EX_L2_FIR_REG_RC_LOAD_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV , 27 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_RC_LOAD_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV ); REG64_FLD( EX_L2_FIR_REG_DARN_DATA_TIMEOUT , 28 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_DARN_DATA_TIMEOUT ); REG64_FLD( EX_L2_FIR_REG_RC_STORE_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV , 29 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_RC_STORE_RECEIVED_PB_ACK_DEAD_FROM_ALINKRECOV ); REG64_FLD( EX_L2_FIR_REG_SPARE2TO1 , 30 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE2TO1 ); REG64_FLD( EX_L2_FIR_REG_SPARE2TO1_LEN , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE2TO1_LEN ); REG64_FLD( EX_L2_FIR_REG_CACHE_RD_CE_AND_UE , 36 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_CACHE_RD_CE_AND_UE ); REG64_FLD( EX_L2_FIR_REG_SPARE1TO1 , 37 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE1TO1 ); REG64_FLD( EX_L2_FIR_REG_SPARE1TO1_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE1TO1_LEN ); REG64_FLD( EX_L2_FIR_REG_SCOM_ERR1 , 40 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR1 ); REG64_FLD( EX_L2_FIR_REG_SCOM_ERR2 , 41 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR2 ); REG64_FLD( EX_L3_FIR_REG_L3_RDDSP_SEGR_LCO_ALL_MEM_UNAVAIL_ERR , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_RDDSP_SEGR_LCO_ALL_MEM_UNAVAIL_ERR ); REG64_FLD( EX_L3_FIR_REG_L3_SPARE1 , 1 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_SPARE1 ); REG64_FLD( EX_L3_FIR_REG_L3_SPARE2 , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_SPARE2 ); REG64_FLD( EX_L3_FIR_REG_L3_DRAM_POS_WORDLINE_FAIL , 3 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_DRAM_POS_WORDLINE_FAIL ); REG64_FLD( EX_L3_FIR_REG_L3_CAC_RD_CE_DET_NOT_LINDEL_REQ , 4 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_CAC_RD_CE_DET_NOT_LINDEL_REQ ); REG64_FLD( EX_L3_FIR_REG_L3_CAC_RD_UE_DET , 5 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_CAC_RD_UE_DET ); REG64_FLD( EX_L3_FIR_REG_L3_CAC_RD_SUE_DET , 6 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_CAC_RD_SUE_DET ); REG64_FLD( EX_L3_FIR_REG_L3_CAC_WR_DATA_CE_FROM_PB , 7 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_CAC_WR_DATA_CE_FROM_PB ); REG64_FLD( EX_L3_FIR_REG_L3_CAC_WR_DATA_UE_FROM_PB , 8 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_CAC_WR_DATA_UE_FROM_PB ); REG64_FLD( EX_L3_FIR_REG_L3_CAC_WR_DATA_SUE_FROM_PB , 9 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_CAC_WR_DATA_SUE_FROM_PB ); REG64_FLD( EX_L3_FIR_REG_L3_CAC_WR_DATA_CE_FROM_L2 , 10 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_CAC_WR_DATA_CE_FROM_L2 ); REG64_FLD( EX_L3_FIR_REG_L3_CAC_WR_DATA_UE_FROM_L2 , 11 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_CAC_WR_DATA_UE_FROM_L2 ); REG64_FLD( EX_L3_FIR_REG_L3_CAC_WR_DATA_SUE_FROM_L2_OR_WIHPC , 12 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_CAC_WR_DATA_SUE_FROM_L2_OR_WIHPC ); REG64_FLD( EX_L3_FIR_REG_L3_DIR_RD_CE_DET , 13 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_DIR_RD_CE_DET ); REG64_FLD( EX_L3_FIR_REG_L3_DIR_RD_UE_DET , 14 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_DIR_RD_UE_DET ); REG64_FLD( EX_L3_FIR_REG_L3_DIR_RD_PHANTOM_ERROR , 15 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_DIR_RD_PHANTOM_ERROR ); REG64_FLD( EX_L3_FIR_REG_L3_PB_MAST_WR_ADDR_ERR , 16 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_PB_MAST_WR_ADDR_ERR ); REG64_FLD( EX_L3_FIR_REG_L3_PB_MAST_RD_ADDR_ERR , 17 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_PB_MAST_RD_ADDR_ERR ); REG64_FLD( EX_L3_FIR_REG_L3_ADDR_HANG_DETECTED , 18 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_ADDR_HANG_DETECTED ); REG64_FLD( EX_L3_FIR_REG_L3_LRU_INVAL_CNT , 19 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_LRU_INVAL_CNT ); REG64_FLD( EX_L3_FIR_REG_L3_PPE_RD_CE_DET , 20 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_PPE_RD_CE_DET ); REG64_FLD( EX_L3_FIR_REG_L3_PPE_RD_UE_DET , 21 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_PPE_RD_UE_DET ); REG64_FLD( EX_L3_FIR_REG_L3_PPE_RD_SUE_DET , 22 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_PPE_RD_SUE_DET ); REG64_FLD( EX_L3_FIR_REG_L3_MACH_HANG_DETECTED , 23 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_MACH_HANG_DETECTED ); REG64_FLD( EX_L3_FIR_REG_L3_HW_CONTROL_ERR , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_HW_CONTROL_ERR ); REG64_FLD( EX_L3_FIR_REG_L3_SNP_CACHE_INHIBIT_ERR , 25 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_SNP_CACHE_INHIBIT_ERR ); REG64_FLD( EX_L3_FIR_REG_L3_LINE_DEL_CE_DONE , 26 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_LINE_DEL_CE_DONE ); REG64_FLD( EX_L3_FIR_REG_L3_DRAM_ERROR , 27 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_DRAM_ERROR ); REG64_FLD( EX_L3_FIR_REG_L3_LRU_ERROR , 28 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_LRU_ERROR ); REG64_FLD( EX_L3_FIR_REG_L3_ALL_MEMBERS_DELETED_ERROR , 29 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_ALL_MEMBERS_DELETED_ERROR ); REG64_FLD( EX_L3_FIR_REG_L3_REFRESH_TIMER_ERROR , 30 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_REFRESH_TIMER_ERROR ); REG64_FLD( EX_L3_FIR_REG_L3_PB_MAST_WR_ACK_DEAD , 31 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_PB_MAST_WR_ACK_DEAD ); REG64_FLD( EX_L3_FIR_REG_L3_PB_MAST_RD_ACK_DEAD , 32 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_L3_PB_MAST_RD_ACK_DEAD ); REG64_FLD( EX_L3_FIR_REG_SCOM_ERR1 , 33 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR1 ); REG64_FLD( EX_L3_FIR_REG_SCOM_ERR2 , 34 , SH_UNT_EX_L3 , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR2 ); REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN0 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN0 ); REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN1 , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN1 ); REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN2 , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN2 ); REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN3 , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN3 ); REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN4 , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN4 ); REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN5 , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN5 ); REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN6 , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN6 ); REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN7 , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN7 ); REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN8 , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN8 ); REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN9 , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN9 ); REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN10 , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN10 ); REG64_FLD( EQ_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN11 , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN11 ); REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN0 , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN0 ); REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN1 , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN1 ); REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN2 , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN2 ); REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN3 , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN3 ); REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN4 , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN4 ); REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN5 , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN5 ); REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN6 , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN6 ); REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN7 , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN7 ); REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN8 , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN8 ); REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN9 , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN9 ); REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN10 , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN10 ); REG64_FLD( EX_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN11 , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN11 ); REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN0 , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN0 ); REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN1 , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN1 ); REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN2 , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN2 ); REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN3 , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN3 ); REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN4 , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN4 ); REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN5 , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN5 ); REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN6 , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN6 ); REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN7 , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN7 ); REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN8 , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN8 ); REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN9 , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN9 ); REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN10 , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN10 ); REG64_FLD( C_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN11 , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN11 ); REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN0 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN0 ); REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN1 , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN1 ); REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN2 , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN2 ); REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN3 , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN3 ); REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN4 , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN4 ); REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN5 , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN5 ); REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN6 , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN6 ); REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN7 , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN7 ); REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN8 , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN8 ); REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN9 , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN9 ); REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN10 , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN10 ); REG64_FLD( EQ_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN11 , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN11 ); REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN0 , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN0 ); REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN1 , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN1 ); REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN2 , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN2 ); REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN3 , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN3 ); REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN4 , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN4 ); REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN5 , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN5 ); REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN6 , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN6 ); REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN7 , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN7 ); REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN8 , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN8 ); REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN9 , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN9 ); REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN10 , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN10 ); REG64_FLD( EX_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN11 , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN11 ); REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN0 , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN0 ); REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN1 , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN1 ); REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN2 , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN2 ); REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN3 , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN3 ); REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN4 , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN4 ); REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN5 , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN5 ); REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN6 , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN6 ); REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN7 , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN7 ); REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN8 , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN8 ); REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN9 , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN9 ); REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN10 , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN10 ); REG64_FLD( C_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN11 , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN11 ); REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN0 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN0 ); REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN1 , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN1 ); REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN2 , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN2 ); REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN3 , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN3 ); REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN4 , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN4 ); REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN5 , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN5 ); REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN6 , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN6 ); REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN7 , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN7 ); REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN8 , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN8 ); REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN9 , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN9 ); REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN10 , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN10 ); REG64_FLD( EQ_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN11 , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN11 ); REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN0 , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN0 ); REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN1 , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN1 ); REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN2 , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN2 ); REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN3 , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN3 ); REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN4 , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN4 ); REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN5 , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN5 ); REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN6 , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN6 ); REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN7 , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN7 ); REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN8 , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN8 ); REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN9 , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN9 ); REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN10 , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN10 ); REG64_FLD( EX_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN11 , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN11 ); REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN0 , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN0 ); REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN1 , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN1 ); REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN2 , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN2 ); REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN3 , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN3 ); REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN4 , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN4 ); REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN5 , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN5 ); REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN6 , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN6 ); REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN7 , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN7 ); REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN8 , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN8 ); REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN9 , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN9 ); REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN10 , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN10 ); REG64_FLD( C_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN11 , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN11 ); REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN0 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP_IN0 ); REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN1 , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP_IN1 ); REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN2 , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP_IN2 ); REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN3 , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP_IN3 ); REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN4 , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP_IN4 ); REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN5 , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP_IN5 ); REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN6 , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP_IN6 ); REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN7 , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP_IN7 ); REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN8 , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP_IN8 ); REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN9 , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP_IN9 ); REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN10 , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP_IN10 ); REG64_FLD( EQ_GXSTOP_TRIG_REG_GXSTP_IN11 , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GXSTP_IN11 ); REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN0 , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP_IN0 ); REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN1 , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP_IN1 ); REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN2 , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP_IN2 ); REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN3 , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP_IN3 ); REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN4 , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP_IN4 ); REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN5 , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP_IN5 ); REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN6 , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP_IN6 ); REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN7 , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP_IN7 ); REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN8 , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP_IN8 ); REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN9 , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP_IN9 ); REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN10 , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP_IN10 ); REG64_FLD( EX_GXSTOP_TRIG_REG_GXSTP_IN11 , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GXSTP_IN11 ); REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN0 , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP_IN0 ); REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN1 , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP_IN1 ); REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN2 , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP_IN2 ); REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN3 , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP_IN3 ); REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN4 , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP_IN4 ); REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN5 , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP_IN5 ); REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN6 , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP_IN6 ); REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN7 , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP_IN7 ); REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN8 , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP_IN8 ); REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN9 , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP_IN9 ); REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN10 , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP_IN10 ); REG64_FLD( C_GXSTOP_TRIG_REG_GXSTP_IN11 , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GXSTP_IN11 ); REG64_FLD( EX_L2_HANG_CONTROL_CORE_LIMIT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_CORE_LIMIT ); REG64_FLD( EX_L2_HANG_CONTROL_CORE_LIMIT_LEN , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_CORE_LIMIT_LEN ); REG64_FLD( EX_L2_HANG_CONTROL_NEST_LIMIT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_NEST_LIMIT ); REG64_FLD( EX_L2_HANG_CONTROL_NEST_LIMIT_LEN , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_NEST_LIMIT_LEN ); REG64_FLD( EX_L2_HANG_CONTROL_RETURN_GOOD_ON_COMP , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_RETURN_GOOD_ON_COMP ); REG64_FLD( EX_L2_HANG_CONTROL_COMP_CNT_LIMIT , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_COMP_CNT_LIMIT ); REG64_FLD( EX_L2_HANG_CONTROL_COMP_CNT_LIMIT_LEN , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_COMP_CNT_LIMIT_LEN ); REG64_FLD( EX_L2_HANG_CONTROL_REC_LIMIT , 25 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_REC_LIMIT ); REG64_FLD( EX_L2_HANG_CONTROL_REC_LIMIT_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_REC_LIMIT_LEN ); REG64_FLD( EX_L2_HANG_CONTROL_USE_REC_LIMIT , 28 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_USE_REC_LIMIT ); REG64_FLD( EX_L2_HANG_CONTROL_ACTIVE_MASK , 29 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTIVE_MASK ); REG64_FLD( EX_L2_HANG_CONTROL_ACTIVE_MASK_LEN , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ACTIVE_MASK_LEN ); REG64_FLD( EX_L2_HANG_CONTROL_TLBIE_STALL_LIMIT , 34 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_TLBIE_STALL_LIMIT ); REG64_FLD( EX_L2_HANG_CONTROL_TLBIE_STALL_LIMIT_LEN , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_TLBIE_STALL_LIMIT_LEN ); REG64_FLD( C_HANG_CONTROL_CORE_LIMIT , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_CORE_LIMIT ); REG64_FLD( C_HANG_CONTROL_CORE_LIMIT_LEN , 8 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_CORE_LIMIT_LEN ); REG64_FLD( C_HANG_CONTROL_NEST_LIMIT , 8 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_NEST_LIMIT ); REG64_FLD( C_HANG_CONTROL_NEST_LIMIT_LEN , 8 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_NEST_LIMIT_LEN ); REG64_FLD( C_HANG_CONTROL_RETURN_GOOD_ON_COMP , 16 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RETURN_GOOD_ON_COMP ); REG64_FLD( C_HANG_CONTROL_COMP_CNT_LIMIT , 17 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_COMP_CNT_LIMIT ); REG64_FLD( C_HANG_CONTROL_COMP_CNT_LIMIT_LEN , 8 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_COMP_CNT_LIMIT_LEN ); REG64_FLD( C_HANG_CONTROL_REC_LIMIT , 25 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_REC_LIMIT ); REG64_FLD( C_HANG_CONTROL_REC_LIMIT_LEN , 3 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_REC_LIMIT_LEN ); REG64_FLD( C_HANG_CONTROL_USE_REC_LIMIT , 28 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_USE_REC_LIMIT ); REG64_FLD( C_HANG_CONTROL_ACTIVE_MASK , 29 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTIVE_MASK ); REG64_FLD( C_HANG_CONTROL_ACTIVE_MASK_LEN , 5 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ACTIVE_MASK_LEN ); REG64_FLD( C_HANG_CONTROL_TLBIE_STALL_LIMIT , 34 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_TLBIE_STALL_LIMIT ); REG64_FLD( C_HANG_CONTROL_TLBIE_STALL_LIMIT_LEN , 8 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_TLBIE_STALL_LIMIT_LEN ); REG64_FLD( EQ_HANG_PULSE_0_REG_0 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_0 ); REG64_FLD( EQ_HANG_PULSE_0_REG_0_LEN , 6 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_0_LEN ); REG64_FLD( EQ_HANG_PULSE_0_REG_SUPPRESS , 6 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( EX_HANG_PULSE_0_REG_0 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_0 ); REG64_FLD( EX_HANG_PULSE_0_REG_0_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_0_LEN ); REG64_FLD( EX_HANG_PULSE_0_REG_SUPPRESS , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( C_HANG_PULSE_0_REG_0 , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_0 ); REG64_FLD( C_HANG_PULSE_0_REG_0_LEN , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_0_LEN ); REG64_FLD( C_HANG_PULSE_0_REG_SUPPRESS , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( EQ_HANG_PULSE_1_REG_1 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_1 ); REG64_FLD( EQ_HANG_PULSE_1_REG_1_LEN , 6 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_1_LEN ); REG64_FLD( EQ_HANG_PULSE_1_REG_SUPPRESS , 6 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( EX_HANG_PULSE_1_REG_1 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_1 ); REG64_FLD( EX_HANG_PULSE_1_REG_1_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_1_LEN ); REG64_FLD( EX_HANG_PULSE_1_REG_SUPPRESS , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( C_HANG_PULSE_1_REG_1 , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_1 ); REG64_FLD( C_HANG_PULSE_1_REG_1_LEN , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_1_LEN ); REG64_FLD( C_HANG_PULSE_1_REG_SUPPRESS , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( EQ_HANG_PULSE_2_REG_2 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_2 ); REG64_FLD( EQ_HANG_PULSE_2_REG_2_LEN , 6 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_2_LEN ); REG64_FLD( EQ_HANG_PULSE_2_REG_SUPPRESS , 6 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( EX_HANG_PULSE_2_REG_2 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_2 ); REG64_FLD( EX_HANG_PULSE_2_REG_2_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_2_LEN ); REG64_FLD( EX_HANG_PULSE_2_REG_SUPPRESS , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( C_HANG_PULSE_2_REG_2 , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_2 ); REG64_FLD( C_HANG_PULSE_2_REG_2_LEN , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_2_LEN ); REG64_FLD( C_HANG_PULSE_2_REG_SUPPRESS , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( EQ_HANG_PULSE_3_REG_3 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_3 ); REG64_FLD( EQ_HANG_PULSE_3_REG_3_LEN , 6 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_3_LEN ); REG64_FLD( EQ_HANG_PULSE_3_REG_SUPPRESS , 6 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( EX_HANG_PULSE_3_REG_3 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_3 ); REG64_FLD( EX_HANG_PULSE_3_REG_3_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_3_LEN ); REG64_FLD( EX_HANG_PULSE_3_REG_SUPPRESS , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( C_HANG_PULSE_3_REG_3 , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_3 ); REG64_FLD( C_HANG_PULSE_3_REG_3_LEN , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_3_LEN ); REG64_FLD( C_HANG_PULSE_3_REG_SUPPRESS , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( EQ_HANG_PULSE_4_REG_4 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_4 ); REG64_FLD( EQ_HANG_PULSE_4_REG_4_LEN , 6 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_4_LEN ); REG64_FLD( EQ_HANG_PULSE_4_REG_SUPPRESS , 6 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( EX_HANG_PULSE_4_REG_4 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_4 ); REG64_FLD( EX_HANG_PULSE_4_REG_4_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_4_LEN ); REG64_FLD( EX_HANG_PULSE_4_REG_SUPPRESS , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( C_HANG_PULSE_4_REG_4 , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_4 ); REG64_FLD( C_HANG_PULSE_4_REG_4_LEN , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_4_LEN ); REG64_FLD( C_HANG_PULSE_4_REG_SUPPRESS , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( EQ_HANG_PULSE_5_REG_5 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_5 ); REG64_FLD( EQ_HANG_PULSE_5_REG_5_LEN , 6 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_5_LEN ); REG64_FLD( EQ_HANG_PULSE_5_REG_SUPPRESS , 6 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( EX_HANG_PULSE_5_REG_5 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_5 ); REG64_FLD( EX_HANG_PULSE_5_REG_5_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_5_LEN ); REG64_FLD( EX_HANG_PULSE_5_REG_SUPPRESS , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( C_HANG_PULSE_5_REG_5 , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_5 ); REG64_FLD( C_HANG_PULSE_5_REG_5_LEN , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_5_LEN ); REG64_FLD( C_HANG_PULSE_5_REG_SUPPRESS , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( EQ_HANG_PULSE_6_REG_6 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_6 ); REG64_FLD( EQ_HANG_PULSE_6_REG_6_LEN , 6 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_6_LEN ); REG64_FLD( EQ_HANG_PULSE_6_REG_SUPPRESS , 6 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( EX_HANG_PULSE_6_REG_6 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_6 ); REG64_FLD( EX_HANG_PULSE_6_REG_6_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_6_LEN ); REG64_FLD( EX_HANG_PULSE_6_REG_SUPPRESS , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( C_HANG_PULSE_6_REG_6 , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_6 ); REG64_FLD( C_HANG_PULSE_6_REG_6_LEN , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_6_LEN ); REG64_FLD( C_HANG_PULSE_6_REG_SUPPRESS , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( EQ_HEARTBEAT_REG_DEAD , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DEAD ); REG64_FLD( EX_HEARTBEAT_REG_DEAD , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DEAD ); REG64_FLD( C_HEARTBEAT_REG_DEAD , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DEAD ); REG64_FLD( EX_L2_HID_ONE_PPC , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ONE_PPC ); REG64_FLD( EX_L2_HID_EN_INSTRUC_TRACE , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_EN_INSTRUC_TRACE ); REG64_FLD( EX_L2_HID_FLUSH_IC , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_FLUSH_IC ); REG64_FLD( EX_L2_HID_EN_ATTN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_EN_ATTN ); REG64_FLD( EX_L2_HID_HILE , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_HILE ); REG64_FLD( EX_L2_HID_DIS_RECOVERY , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_DIS_RECOVERY ); REG64_FLD( EX_L2_HID_MEGAMOUTH , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_MEGAMOUTH ); REG64_FLD( EX_L2_HID_PREFETCH_RESET , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_PREFETCH_RESET ); REG64_FLD( EX_L2_HID_LSU_SPARE , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_LSU_SPARE ); REG64_FLD( C_HID_ONE_PPC , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ONE_PPC ); REG64_FLD( C_HID_EN_INSTRUC_TRACE , 1 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_EN_INSTRUC_TRACE ); REG64_FLD( C_HID_FLUSH_IC , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_FLUSH_IC ); REG64_FLD( C_HID_EN_ATTN , 3 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_EN_ATTN ); REG64_FLD( C_HID_HILE , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_HILE ); REG64_FLD( C_HID_DIS_RECOVERY , 5 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_DIS_RECOVERY ); REG64_FLD( C_HID_MEGAMOUTH , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_MEGAMOUTH ); REG64_FLD( C_HID_PREFETCH_RESET , 7 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PREFETCH_RESET ); REG64_FLD( C_HID_LSU_SPARE , 8 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_LSU_SPARE ); REG64_FLD( EX_L2_HMEER_ENABLE , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ENABLE ); REG64_FLD( EX_L2_HMEER_ENABLE_LEN , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ENABLE_LEN ); REG64_FLD( C_HMEER_ENABLE , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ENABLE ); REG64_FLD( C_HMEER_ENABLE_LEN , 24 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ENABLE_LEN ); REG64_FLD( EQ_HOSTATTN_IN0 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN0 ); REG64_FLD( EQ_HOSTATTN_IN1 , 1 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN1 ); REG64_FLD( EQ_HOSTATTN_IN2 , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN2 ); REG64_FLD( EQ_HOSTATTN_IN3 , 3 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN3 ); REG64_FLD( EQ_HOSTATTN_IN4 , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN4 ); REG64_FLD( EQ_HOSTATTN_IN5 , 5 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN5 ); REG64_FLD( EQ_HOSTATTN_IN6 , 6 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN6 ); REG64_FLD( EQ_HOSTATTN_IN7 , 7 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN7 ); REG64_FLD( EQ_HOSTATTN_IN8 , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN8 ); REG64_FLD( EQ_HOSTATTN_IN9 , 9 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN9 ); REG64_FLD( EQ_HOSTATTN_IN10 , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN10 ); REG64_FLD( EQ_HOSTATTN_IN11 , 11 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN11 ); REG64_FLD( EQ_HOSTATTN_IN12 , 12 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN12 ); REG64_FLD( EQ_HOSTATTN_IN13 , 13 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN13 ); REG64_FLD( EQ_HOSTATTN_IN14 , 14 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN14 ); REG64_FLD( EQ_HOSTATTN_IN15 , 15 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN15 ); REG64_FLD( EQ_HOSTATTN_IN16 , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN16 ); REG64_FLD( EQ_HOSTATTN_IN17 , 17 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN17 ); REG64_FLD( EQ_HOSTATTN_IN18 , 18 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN18 ); REG64_FLD( EQ_HOSTATTN_IN19 , 19 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN19 ); REG64_FLD( EQ_HOSTATTN_IN20 , 20 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN20 ); REG64_FLD( EQ_HOSTATTN_IN21 , 21 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN21 ); REG64_FLD( EQ_HOSTATTN_IN22 , 22 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN22 ); REG64_FLD( EX_HOSTATTN_IN0 , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN0 ); REG64_FLD( EX_HOSTATTN_IN1 , 1 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN1 ); REG64_FLD( EX_HOSTATTN_IN2 , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN2 ); REG64_FLD( EX_HOSTATTN_IN3 , 3 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN3 ); REG64_FLD( EX_HOSTATTN_IN4 , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN4 ); REG64_FLD( EX_HOSTATTN_IN5 , 5 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN5 ); REG64_FLD( EX_HOSTATTN_IN6 , 6 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN6 ); REG64_FLD( EX_HOSTATTN_IN7 , 7 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN7 ); REG64_FLD( EX_HOSTATTN_IN8 , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN8 ); REG64_FLD( EX_HOSTATTN_IN9 , 9 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN9 ); REG64_FLD( EX_HOSTATTN_IN10 , 10 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN10 ); REG64_FLD( EX_HOSTATTN_IN11 , 11 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN11 ); REG64_FLD( EX_HOSTATTN_IN12 , 12 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN12 ); REG64_FLD( EX_HOSTATTN_IN13 , 13 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN13 ); REG64_FLD( EX_HOSTATTN_IN14 , 14 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN14 ); REG64_FLD( EX_HOSTATTN_IN15 , 15 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN15 ); REG64_FLD( EX_HOSTATTN_IN16 , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN16 ); REG64_FLD( EX_HOSTATTN_IN17 , 17 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN17 ); REG64_FLD( EX_HOSTATTN_IN18 , 18 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN18 ); REG64_FLD( EX_HOSTATTN_IN19 , 19 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN19 ); REG64_FLD( EX_HOSTATTN_IN20 , 20 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN20 ); REG64_FLD( EX_HOSTATTN_IN21 , 21 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN21 ); REG64_FLD( EX_HOSTATTN_IN22 , 22 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN22 ); REG64_FLD( C_HOSTATTN_IN0 , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN0 ); REG64_FLD( C_HOSTATTN_IN1 , 1 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN1 ); REG64_FLD( C_HOSTATTN_IN2 , 2 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN2 ); REG64_FLD( C_HOSTATTN_IN3 , 3 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN3 ); REG64_FLD( C_HOSTATTN_IN4 , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN4 ); REG64_FLD( C_HOSTATTN_IN5 , 5 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN5 ); REG64_FLD( C_HOSTATTN_IN6 , 6 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN6 ); REG64_FLD( C_HOSTATTN_IN7 , 7 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN7 ); REG64_FLD( C_HOSTATTN_IN8 , 8 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN8 ); REG64_FLD( C_HOSTATTN_IN9 , 9 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN9 ); REG64_FLD( C_HOSTATTN_IN10 , 10 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN10 ); REG64_FLD( C_HOSTATTN_IN11 , 11 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN11 ); REG64_FLD( C_HOSTATTN_IN12 , 12 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN12 ); REG64_FLD( C_HOSTATTN_IN13 , 13 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN13 ); REG64_FLD( C_HOSTATTN_IN14 , 14 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN14 ); REG64_FLD( C_HOSTATTN_IN15 , 15 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN15 ); REG64_FLD( C_HOSTATTN_IN16 , 16 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN16 ); REG64_FLD( C_HOSTATTN_IN17 , 17 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN17 ); REG64_FLD( C_HOSTATTN_IN18 , 18 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN18 ); REG64_FLD( C_HOSTATTN_IN19 , 19 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN19 ); REG64_FLD( C_HOSTATTN_IN20 , 20 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN20 ); REG64_FLD( C_HOSTATTN_IN21 , 21 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN21 ); REG64_FLD( C_HOSTATTN_IN22 , 22 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN22 ); REG64_FLD( EQ_HOSTATTN_MASK_IN , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( EQ_HOSTATTN_MASK_IN_LEN , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( EX_HOSTATTN_MASK_IN , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( EX_HOSTATTN_MASK_IN_LEN , 22 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( C_HOSTATTN_MASK_IN , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( C_HOSTATTN_MASK_IN_LEN , 22 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( EQ_HTM_CTRL_HTMSC_TRIG , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_TRIG ); REG64_FLD( EQ_HTM_CTRL_HTMSC_TRIG_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_TRIG_LEN ); REG64_FLD( EQ_HTM_CTRL_HTMSC_MTSPR_TRIG , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MTSPR_TRIG ); REG64_FLD( EQ_HTM_CTRL_HTMSC_MTSPR_MARK , 3 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MTSPR_MARK ); REG64_FLD( EQ_HTM_CTRL_HTMSC_MARK , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARK ); REG64_FLD( EQ_HTM_CTRL_HTMSC_MARK_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARK_LEN ); REG64_FLD( EQ_HTM_CTRL_HTMSC_DBG0_STOP , 6 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DBG0_STOP ); REG64_FLD( EQ_HTM_CTRL_HTMSC_DBG1_STOP , 7 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DBG1_STOP ); REG64_FLD( EQ_HTM_CTRL_HTMSC_RUN_STOP , 8 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_RUN_STOP ); REG64_FLD( EQ_HTM_CTRL_HTMSC_CHIP0_STOP , 9 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CHIP0_STOP ); REG64_FLD( EQ_HTM_CTRL_HTMSC_CHIP1_STOP , 10 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CHIP1_STOP ); REG64_FLD( EQ_HTM_CTRL_HTMSC_SPARE1112 , 11 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE1112 ); REG64_FLD( EQ_HTM_CTRL_HTMSC_SPARE1112_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE1112_LEN ); REG64_FLD( EQ_HTM_CTRL_HTMSC_XSTOP_STOP , 13 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_XSTOP_STOP ); REG64_FLD( EQ_HTM_CTRL_HTMSC_SPARE1415 , 14 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE1415 ); REG64_FLD( EQ_HTM_CTRL_HTMSC_SPARE1415_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE1415_LEN ); REG64_FLD( EX_HTM_CTRL_HTMSC_TRIG , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_TRIG ); REG64_FLD( EX_HTM_CTRL_HTMSC_TRIG_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_TRIG_LEN ); REG64_FLD( EX_HTM_CTRL_HTMSC_MTSPR_TRIG , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MTSPR_TRIG ); REG64_FLD( EX_HTM_CTRL_HTMSC_MTSPR_MARK , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MTSPR_MARK ); REG64_FLD( EX_HTM_CTRL_HTMSC_MARK , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARK ); REG64_FLD( EX_HTM_CTRL_HTMSC_MARK_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARK_LEN ); REG64_FLD( EX_HTM_CTRL_HTMSC_DBG0_STOP , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DBG0_STOP ); REG64_FLD( EX_HTM_CTRL_HTMSC_DBG1_STOP , 7 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DBG1_STOP ); REG64_FLD( EX_HTM_CTRL_HTMSC_RUN_STOP , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_RUN_STOP ); REG64_FLD( EX_HTM_CTRL_HTMSC_CHIP0_STOP , 9 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CHIP0_STOP ); REG64_FLD( EX_HTM_CTRL_HTMSC_CHIP1_STOP , 10 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CHIP1_STOP ); REG64_FLD( EX_HTM_CTRL_HTMSC_SPARE1112 , 11 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE1112 ); REG64_FLD( EX_HTM_CTRL_HTMSC_SPARE1112_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE1112_LEN ); REG64_FLD( EX_HTM_CTRL_HTMSC_XSTOP_STOP , 13 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_XSTOP_STOP ); REG64_FLD( EX_HTM_CTRL_HTMSC_SPARE1415 , 14 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE1415 ); REG64_FLD( EX_HTM_CTRL_HTMSC_SPARE1415_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE1415_LEN ); REG64_FLD( EQ_HTM_IMA_PDBAR_HTMSC_ENABLE_SPLIT_CORE , 1 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_ENABLE_SPLIT_CORE ); REG64_FLD( EQ_HTM_IMA_PDBAR_HTMSC_SPARE2TO4 , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE2TO4 ); REG64_FLD( EQ_HTM_IMA_PDBAR_HTMSC_SPARE2TO4_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE2TO4_LEN ); REG64_FLD( EQ_HTM_IMA_PDBAR_HTMSC_SCOPE , 5 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SCOPE ); REG64_FLD( EQ_HTM_IMA_PDBAR_HTMSC_SCOPE_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SCOPE_LEN ); REG64_FLD( EQ_HTM_IMA_PDBAR_HTMSC , 8 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC ); REG64_FLD( EQ_HTM_IMA_PDBAR_HTMSC_LEN , 43 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_LEN ); REG64_FLD( EX_HTM_IMA_PDBAR_HTMSC_ENABLE_SPLIT_CORE , 1 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_ENABLE_SPLIT_CORE ); REG64_FLD( EX_HTM_IMA_PDBAR_HTMSC_SPARE2TO4 , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE2TO4 ); REG64_FLD( EX_HTM_IMA_PDBAR_HTMSC_SPARE2TO4_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE2TO4_LEN ); REG64_FLD( EX_HTM_IMA_PDBAR_HTMSC_SCOPE , 5 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SCOPE ); REG64_FLD( EX_HTM_IMA_PDBAR_HTMSC_SCOPE_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SCOPE_LEN ); REG64_FLD( EX_HTM_IMA_PDBAR_HTMSC , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC ); REG64_FLD( EX_HTM_IMA_PDBAR_HTMSC_LEN , 43 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_LEN ); REG64_FLD( EQ_HTM_IMA_STATUS_HTMSC_ERROR , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMSC_ERROR ); REG64_FLD( EQ_HTM_IMA_STATUS_HTMSC_TRACE_ACTIVE , 1 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMSC_TRACE_ACTIVE ); REG64_FLD( EQ_HTM_IMA_STATUS_HTMSC_PDBAR_ERROR , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMSC_PDBAR_ERROR ); REG64_FLD( EQ_HTM_IMA_STATUS_HTMSC_RESERVED , 3 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMSC_RESERVED ); REG64_FLD( EQ_HTM_IMA_STATUS_HTMSC_RESERVED_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMSC_RESERVED_LEN ); REG64_FLD( EQ_HTM_IMA_STATUS_HTMSC_FSM , 5 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMSC_FSM ); REG64_FLD( EQ_HTM_IMA_STATUS_HTMSC_FSM_LEN , 7 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMSC_FSM_LEN ); REG64_FLD( EQ_HTM_IMA_STATUS_HTMSC_COUNT , 12 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMSC_COUNT ); REG64_FLD( EQ_HTM_IMA_STATUS_HTMSC_COUNT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMSC_COUNT_LEN ); REG64_FLD( EX_HTM_IMA_STATUS_HTMSC_ERROR , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMSC_ERROR ); REG64_FLD( EX_HTM_IMA_STATUS_HTMSC_TRACE_ACTIVE , 1 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMSC_TRACE_ACTIVE ); REG64_FLD( EX_HTM_IMA_STATUS_HTMSC_PDBAR_ERROR , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMSC_PDBAR_ERROR ); REG64_FLD( EX_HTM_IMA_STATUS_HTMSC_RESERVED , 3 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMSC_RESERVED ); REG64_FLD( EX_HTM_IMA_STATUS_HTMSC_RESERVED_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMSC_RESERVED_LEN ); REG64_FLD( EX_HTM_IMA_STATUS_HTMSC_FSM , 5 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMSC_FSM ); REG64_FLD( EX_HTM_IMA_STATUS_HTMSC_FSM_LEN , 7 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMSC_FSM_LEN ); REG64_FLD( EX_HTM_IMA_STATUS_HTMSC_COUNT , 12 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMSC_COUNT ); REG64_FLD( EX_HTM_IMA_STATUS_HTMSC_COUNT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMSC_COUNT_LEN ); REG64_FLD( EQ_HTM_LAST_ADDRESS , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( EQ_HTM_LAST_ADDRESS_LEN , 49 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( EX_HTM_LAST_ADDRESS , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( EX_HTM_LAST_ADDRESS_LEN , 49 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( EQ_HTM_MEM_HTMSC_ALLOC , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_ALLOC ); REG64_FLD( EQ_HTM_MEM_HTMSC_SCOPE , 1 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SCOPE ); REG64_FLD( EQ_HTM_MEM_HTMSC_SCOPE_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SCOPE_LEN ); REG64_FLD( EQ_HTM_MEM_HTMSC_PRIORITY , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_PRIORITY ); REG64_FLD( EQ_HTM_MEM_HTMSC_SIZE_SMALL , 5 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SIZE_SMALL ); REG64_FLD( EQ_HTM_MEM_HTMSC_SPARE , 6 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE ); REG64_FLD( EQ_HTM_MEM_HTMSC_SPARE_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE_LEN ); REG64_FLD( EQ_HTM_MEM_HTMSC_BASE , 8 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_BASE ); REG64_FLD( EQ_HTM_MEM_HTMSC_BASE_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_BASE_LEN ); REG64_FLD( EQ_HTM_MEM_HTMSC_SIZE , 40 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SIZE ); REG64_FLD( EQ_HTM_MEM_HTMSC_SIZE_LEN , 9 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SIZE_LEN ); REG64_FLD( EX_HTM_MEM_HTMSC_ALLOC , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_ALLOC ); REG64_FLD( EX_HTM_MEM_HTMSC_SCOPE , 1 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SCOPE ); REG64_FLD( EX_HTM_MEM_HTMSC_SCOPE_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SCOPE_LEN ); REG64_FLD( EX_HTM_MEM_HTMSC_PRIORITY , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_PRIORITY ); REG64_FLD( EX_HTM_MEM_HTMSC_SIZE_SMALL , 5 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SIZE_SMALL ); REG64_FLD( EX_HTM_MEM_HTMSC_SPARE , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE ); REG64_FLD( EX_HTM_MEM_HTMSC_SPARE_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE_LEN ); REG64_FLD( EX_HTM_MEM_HTMSC_BASE , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_BASE ); REG64_FLD( EX_HTM_MEM_HTMSC_BASE_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_BASE_LEN ); REG64_FLD( EX_HTM_MEM_HTMSC_SIZE , 40 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SIZE ); REG64_FLD( EX_HTM_MEM_HTMSC_SIZE_LEN , 9 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SIZE_LEN ); REG64_FLD( EQ_HTM_MODE_HTMSC_ENABLE , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_ENABLE ); REG64_FLD( EQ_HTM_MODE_HTMSC_CONTENT_SEL , 1 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CONTENT_SEL ); REG64_FLD( EQ_HTM_MODE_HTMSC_CONTENT_SEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CONTENT_SEL_LEN ); REG64_FLD( EQ_HTM_MODE_HTMSC_SPARE0 , 3 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE0 ); REG64_FLD( EQ_HTM_MODE_HTMSC_CAPTURE , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CAPTURE ); REG64_FLD( EQ_HTM_MODE_HTMSC_CAPTURE_LEN , 6 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CAPTURE_LEN ); REG64_FLD( EQ_HTM_MODE_HTMSC_DD1EQUIV , 10 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DD1EQUIV ); REG64_FLD( EQ_HTM_MODE_HTMSC_SPARE_1TO2 , 11 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE_1TO2 ); REG64_FLD( EQ_HTM_MODE_HTMSC_SPARE_1TO2_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE_1TO2_LEN ); REG64_FLD( EQ_HTM_MODE_HTMSC_WRAP , 13 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_WRAP ); REG64_FLD( EQ_HTM_MODE_HTMSC_DIS_TSTAMP , 14 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DIS_TSTAMP ); REG64_FLD( EQ_HTM_MODE_HTMSC_SINGLE_TSTAMP , 15 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SINGLE_TSTAMP ); REG64_FLD( EQ_HTM_MODE_HTMSC_DIS_STALL , 16 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DIS_STALL ); REG64_FLD( EQ_HTM_MODE_HTMSC_MARKERS_ONLY , 17 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARKERS_ONLY ); REG64_FLD( EQ_HTM_MODE_HTMSC_DIS_GROUP , 18 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DIS_GROUP ); REG64_FLD( EQ_HTM_MODE_HTMSC_SPARES , 19 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARES ); REG64_FLD( EQ_HTM_MODE_HTMSC_SPARES_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARES_LEN ); REG64_FLD( EQ_HTM_MODE_HTMSC_VGTARGET , 24 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_VGTARGET ); REG64_FLD( EQ_HTM_MODE_HTMSC_VGTARGET_LEN , 16 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_VGTARGET_LEN ); REG64_FLD( EX_HTM_MODE_HTMSC_ENABLE , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_ENABLE ); REG64_FLD( EX_HTM_MODE_HTMSC_CONTENT_SEL , 1 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CONTENT_SEL ); REG64_FLD( EX_HTM_MODE_HTMSC_CONTENT_SEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CONTENT_SEL_LEN ); REG64_FLD( EX_HTM_MODE_HTMSC_SPARE0 , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE0 ); REG64_FLD( EX_HTM_MODE_HTMSC_CAPTURE , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CAPTURE ); REG64_FLD( EX_HTM_MODE_HTMSC_CAPTURE_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CAPTURE_LEN ); REG64_FLD( EX_HTM_MODE_HTMSC_DD1EQUIV , 10 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DD1EQUIV ); REG64_FLD( EX_HTM_MODE_HTMSC_SPARE_1TO2 , 11 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE_1TO2 ); REG64_FLD( EX_HTM_MODE_HTMSC_SPARE_1TO2_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE_1TO2_LEN ); REG64_FLD( EX_HTM_MODE_HTMSC_WRAP , 13 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_WRAP ); REG64_FLD( EX_HTM_MODE_HTMSC_DIS_TSTAMP , 14 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DIS_TSTAMP ); REG64_FLD( EX_HTM_MODE_HTMSC_SINGLE_TSTAMP , 15 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SINGLE_TSTAMP ); REG64_FLD( EX_HTM_MODE_HTMSC_DIS_STALL , 16 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DIS_STALL ); REG64_FLD( EX_HTM_MODE_HTMSC_MARKERS_ONLY , 17 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARKERS_ONLY ); REG64_FLD( EX_HTM_MODE_HTMSC_DIS_GROUP , 18 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DIS_GROUP ); REG64_FLD( EX_HTM_MODE_HTMSC_SPARES , 19 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARES ); REG64_FLD( EX_HTM_MODE_HTMSC_SPARES_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARES_LEN ); REG64_FLD( EX_HTM_MODE_HTMSC_VGTARGET , 24 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_VGTARGET ); REG64_FLD( EX_HTM_MODE_HTMSC_VGTARGET_LEN , 16 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_VGTARGET_LEN ); REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_PURGE_IN_PROG , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_PURGE_IN_PROG ); REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_PURGE_DONE , 1 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_PURGE_DONE ); REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_CRESP_OV , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_CRESP_OV ); REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_REPAIR , 3 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_REPAIR ); REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_BUF_WAIT , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_BUF_WAIT ); REG64_FLD( EQ_HTM_STAT_STATUS_TRIG_DROPPED_Q , 5 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_STATUS_TRIG_DROPPED_Q ); REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_ADDR_ERROR , 6 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_ADDR_ERROR ); REG64_FLD( EQ_HTM_STAT_STATUS_REC_DROPPED_Q , 7 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_STATUS_REC_DROPPED_Q ); REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_INIT , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_INIT ); REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_PREREQ , 9 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_PREREQ ); REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_READY , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_READY ); REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_TRACING , 11 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_TRACING ); REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_PAUSED , 12 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_PAUSED ); REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_FLUSH , 13 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_FLUSH ); REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_COMPLETE , 14 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_COMPLETE ); REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_ENABLE , 15 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_ENABLE ); REG64_FLD( EQ_HTM_STAT_HTMCO_STATUS_STAMP , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_STAMP ); REG64_FLD( EQ_HTM_STAT_STATUS_SCOM_ERROR , 17 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_STATUS_SCOM_ERROR ); REG64_FLD( EQ_HTM_STAT_STATUS_UNUSED , 18 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_STATUS_UNUSED ); REG64_FLD( EQ_HTM_STAT_STATUS_UNUSED_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_STATUS_UNUSED_LEN ); REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_PURGE_IN_PROG , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_PURGE_IN_PROG ); REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_PURGE_DONE , 1 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_PURGE_DONE ); REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_CRESP_OV , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_CRESP_OV ); REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_REPAIR , 3 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_REPAIR ); REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_BUF_WAIT , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_BUF_WAIT ); REG64_FLD( EX_HTM_STAT_STATUS_TRIG_DROPPED_Q , 5 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_STATUS_TRIG_DROPPED_Q ); REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_ADDR_ERROR , 6 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_ADDR_ERROR ); REG64_FLD( EX_HTM_STAT_STATUS_REC_DROPPED_Q , 7 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_STATUS_REC_DROPPED_Q ); REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_INIT , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_INIT ); REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_PREREQ , 9 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_PREREQ ); REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_READY , 10 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_READY ); REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_TRACING , 11 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_TRACING ); REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_PAUSED , 12 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_PAUSED ); REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_FLUSH , 13 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_FLUSH ); REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_COMPLETE , 14 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_COMPLETE ); REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_ENABLE , 15 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_ENABLE ); REG64_FLD( EX_HTM_STAT_HTMCO_STATUS_STAMP , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_STAMP ); REG64_FLD( EX_HTM_STAT_STATUS_SCOM_ERROR , 17 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_STATUS_SCOM_ERROR ); REG64_FLD( EX_HTM_STAT_STATUS_UNUSED , 18 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_STATUS_UNUSED ); REG64_FLD( EX_HTM_STAT_STATUS_UNUSED_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_STATUS_UNUSED_LEN ); REG64_FLD( EQ_HTM_TRIG_HTMSC_START , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_START ); REG64_FLD( EQ_HTM_TRIG_HTMSC_STOP , 1 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_STOP ); REG64_FLD( EQ_HTM_TRIG_HTMSC_PAUSE , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_PAUSE ); REG64_FLD( EQ_HTM_TRIG_HTMSC_STOP_ALT , 3 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_STOP_ALT ); REG64_FLD( EQ_HTM_TRIG_HTMSC_RESET , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_RESET ); REG64_FLD( EQ_HTM_TRIG_HTMSC_MARK_VALID , 5 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARK_VALID ); REG64_FLD( EQ_HTM_TRIG_HTMSC_MARK_TYPE , 6 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARK_TYPE ); REG64_FLD( EQ_HTM_TRIG_HTMSC_MARK_TYPE_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARK_TYPE_LEN ); REG64_FLD( EX_HTM_TRIG_HTMSC_START , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_START ); REG64_FLD( EX_HTM_TRIG_HTMSC_STOP , 1 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_STOP ); REG64_FLD( EX_HTM_TRIG_HTMSC_PAUSE , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_PAUSE ); REG64_FLD( EX_HTM_TRIG_HTMSC_STOP_ALT , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_STOP_ALT ); REG64_FLD( EX_HTM_TRIG_HTMSC_RESET , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_RESET ); REG64_FLD( EX_HTM_TRIG_HTMSC_MARK_VALID , 5 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARK_VALID ); REG64_FLD( EX_HTM_TRIG_HTMSC_MARK_TYPE , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARK_TYPE ); REG64_FLD( EX_HTM_TRIG_HTMSC_MARK_TYPE_LEN , 10 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARK_TYPE_LEN ); REG64_FLD( EX_L2_HV_STATE_VT0_MSR_HV , 56 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT0_MSR_HV ); REG64_FLD( EX_L2_HV_STATE_VT1_MSR_HV , 57 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT1_MSR_HV ); REG64_FLD( EX_L2_HV_STATE_VT2_MSR_HV , 58 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT2_MSR_HV ); REG64_FLD( EX_L2_HV_STATE_VT3_MSR_HV , 59 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT3_MSR_HV ); REG64_FLD( EX_L2_HV_STATE_VT0_MSR_PR , 60 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT0_MSR_PR ); REG64_FLD( EX_L2_HV_STATE_VT1_MSR_PR , 61 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT1_MSR_PR ); REG64_FLD( EX_L2_HV_STATE_VT2_MSR_PR , 62 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT2_MSR_PR ); REG64_FLD( EX_L2_HV_STATE_VT3_MSR_PR , 63 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT3_MSR_PR ); REG64_FLD( C_HV_STATE_VT0_MSR_HV , 56 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT0_MSR_HV ); REG64_FLD( C_HV_STATE_VT1_MSR_HV , 57 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT1_MSR_HV ); REG64_FLD( C_HV_STATE_VT2_MSR_HV , 58 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT2_MSR_HV ); REG64_FLD( C_HV_STATE_VT3_MSR_HV , 59 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT3_MSR_HV ); REG64_FLD( C_HV_STATE_VT0_MSR_PR , 60 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT0_MSR_PR ); REG64_FLD( C_HV_STATE_VT1_MSR_PR , 61 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT1_MSR_PR ); REG64_FLD( C_HV_STATE_VT2_MSR_PR , 62 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT2_MSR_PR ); REG64_FLD( C_HV_STATE_VT3_MSR_PR , 63 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT3_MSR_PR ); REG64_FLD( EX_L2_IFU_HOLD_OUT_0_UNUSED , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_UNUSED ); REG64_FLD( EX_L2_IFU_HOLD_OUT_0_UNUSED_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_UNUSED_LEN ); REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFBC_EAT_OVERFLOW_HOLD_OUT_2 , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFBC_EAT_OVERFLOW_HOLD_OUT_2 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFBC_EATAG_MISMATCHES_IFAR_HOLD_OUT_2 , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFBC_EATAG_MISMATCHES_IFAR_HOLD_OUT_2 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFBC_IFAR_PARITY_HOLD_OUT_2 , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFBC_IFAR_PARITY_HOLD_OUT_2 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFBC_LNK_STK_OR_CC_PTY_HOLD_OUT_2 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFBC_LNK_STK_OR_CC_PTY_HOLD_OUT_2 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFBC_MULTI_THREAD_HOLD_OUT_2 , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFBC_MULTI_THREAD_HOLD_OUT_2 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFBC_EAT_UNDERFLOW_HOLD_OUT_2 , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFBC_EAT_UNDERFLOW_HOLD_OUT_2 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFSE_SPR_PARITY_HOLD_OUT_2 , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFSE_SPR_PARITY_HOLD_OUT_2 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFAC_EAT_WRITE_CONFLICT_HOLD_OUT_2 , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFAC_EAT_WRITE_CONFLICT_HOLD_OUT_2 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFEC_DYNAMIC_IC_DELETE_HOLD_OUT , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFEC_DYNAMIC_IC_DELETE_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFEC_EADIR_ILLEGAL_HOLD_OUT , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFEC_EADIR_ILLEGAL_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFEC_ERAT_PTY_HOLD_OUT , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFEC_ERAT_PTY_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_0_IFFEC_ICACHE_MISSING_EADIR_WRT_HOLD_OUT , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFEC_ICACHE_MISSING_EADIR_WRT_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_0_UNUSED , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_UNUSED ); REG64_FLD( C_IFU_HOLD_OUT_0_UNUSED_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_UNUSED_LEN ); REG64_FLD( C_IFU_HOLD_OUT_0_IFFBC_EAT_OVERFLOW_HOLD_OUT_2 , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFBC_EAT_OVERFLOW_HOLD_OUT_2 ); REG64_FLD( C_IFU_HOLD_OUT_0_IFFBC_EATAG_MISMATCHES_IFAR_HOLD_OUT_2 , 5 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFBC_EATAG_MISMATCHES_IFAR_HOLD_OUT_2 ); REG64_FLD( C_IFU_HOLD_OUT_0_IFFBC_IFAR_PARITY_HOLD_OUT_2 , 6 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFBC_IFAR_PARITY_HOLD_OUT_2 ); REG64_FLD( C_IFU_HOLD_OUT_0_IFFBC_LNK_STK_OR_CC_PTY_HOLD_OUT_2 , 7 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFBC_LNK_STK_OR_CC_PTY_HOLD_OUT_2 ); REG64_FLD( C_IFU_HOLD_OUT_0_IFFBC_MULTI_THREAD_HOLD_OUT_2 , 8 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFBC_MULTI_THREAD_HOLD_OUT_2 ); REG64_FLD( C_IFU_HOLD_OUT_0_IFFBC_EAT_UNDERFLOW_HOLD_OUT_2 , 9 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFBC_EAT_UNDERFLOW_HOLD_OUT_2 ); REG64_FLD( C_IFU_HOLD_OUT_0_IFFSE_SPR_PARITY_HOLD_OUT_2 , 10 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFSE_SPR_PARITY_HOLD_OUT_2 ); REG64_FLD( C_IFU_HOLD_OUT_0_IFFAC_EAT_WRITE_CONFLICT_HOLD_OUT_2 , 11 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFAC_EAT_WRITE_CONFLICT_HOLD_OUT_2 ); REG64_FLD( C_IFU_HOLD_OUT_0_IFFEC_DYNAMIC_IC_DELETE_HOLD_OUT , 12 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFEC_DYNAMIC_IC_DELETE_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_0_IFFEC_EADIR_ILLEGAL_HOLD_OUT , 13 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFEC_EADIR_ILLEGAL_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_0_IFFEC_ERAT_PTY_HOLD_OUT , 14 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFEC_ERAT_PTY_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_0_IFFEC_ICACHE_MISSING_EADIR_WRT_HOLD_OUT , 15 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFEC_ICACHE_MISSING_EADIR_WRT_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFFEC_ICACHE_PE_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFEC_ICACHE_PE_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFFEC_IDIR_EA_PTY_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFEC_IDIR_EA_PTY_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFFEC_IDIR_PTY_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFEC_IDIR_PTY_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFFEC_IERAT_WRT_EA_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFEC_IERAT_WRT_EA_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFFEC_IFAR_CHECK1_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFEC_IFAR_CHECK1_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFFEC_IFAR_CHECK2_HOLD_OUT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFEC_IFAR_CHECK2_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFFEC_IFFIW_IDIR_HOLD_OUT , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFEC_IFFIW_IDIR_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_0 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_0 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2 , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_2 , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_2 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_3 , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_3 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_4 , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_4 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_5 , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_5 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFFLC_WRITE_COLL_HOLD_OUT_2 , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFLC_WRITE_COLL_HOLD_OUT_2 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFDFE_IDU_FETCH_LENGTH_ERROR_HOLD_OUT_2 , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFDFE_IDU_FETCH_LENGTH_ERROR_HOLD_OUT_2 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_1_IFDFE_IBUF_OVERRUN_ERROR_HOLD_OUT_2 , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFDFE_IBUF_OVERRUN_ERROR_HOLD_OUT_2 ); REG64_FLD( C_IFU_HOLD_OUT_1_IFFEC_ICACHE_PE_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFEC_ICACHE_PE_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_1_IFFEC_IDIR_EA_PTY_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFEC_IDIR_EA_PTY_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_1_IFFEC_IDIR_PTY_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFEC_IDIR_PTY_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_1_IFFEC_IERAT_WRT_EA_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFEC_IERAT_WRT_EA_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_1_IFFEC_IFAR_CHECK1_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFEC_IFAR_CHECK1_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_1_IFFEC_IFAR_CHECK2_HOLD_OUT , 5 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFEC_IFAR_CHECK2_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_1_IFFEC_IFFIW_IDIR_HOLD_OUT , 6 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFEC_IFFIW_IDIR_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_0 , 7 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_0 ); REG64_FLD( C_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2 , 8 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2 ); REG64_FLD( C_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_2 , 9 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_2 ); REG64_FLD( C_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_3 , 10 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_3 ); REG64_FLD( C_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_4 , 11 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_4 ); REG64_FLD( C_IFU_HOLD_OUT_1_IFDPOP_IBUF_PERR_HOLD_OUT_2_5 , 12 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFDPOP_IBUF_PERR_HOLD_OUT_2_5 ); REG64_FLD( C_IFU_HOLD_OUT_1_IFFLC_WRITE_COLL_HOLD_OUT_2 , 13 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFLC_WRITE_COLL_HOLD_OUT_2 ); REG64_FLD( C_IFU_HOLD_OUT_1_IFDFE_IDU_FETCH_LENGTH_ERROR_HOLD_OUT_2 , 14 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFDFE_IDU_FETCH_LENGTH_ERROR_HOLD_OUT_2 ); REG64_FLD( C_IFU_HOLD_OUT_1_IFDFE_IBUF_OVERRUN_ERROR_HOLD_OUT_2 , 15 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFDFE_IBUF_OVERRUN_ERROR_HOLD_OUT_2 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFFSE_MFSPR_COLLISION_ERR_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFSE_MFSPR_COLLISION_ERR_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFFPF_IFAR_VLD_IN_QERR_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFPF_IFAR_VLD_IN_QERR_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFFPF_L2_RELOAD_COMING_QERR_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFPF_L2_RELOAD_COMING_QERR_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFFPF_L2_RELOAD_INTERF_QERR_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFPF_L2_RELOAD_INTERF_QERR_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFFPF_MULTI_RLDM_HAS_SAME_EA_QERR_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFPF_MULTI_RLDM_HAS_SAME_EA_QERR_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFFCP_CIABR_PERR_HOLD_OUT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFCP_CIABR_PERR_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_2_UNUSED_1 , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_UNUSED_1 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFFMSR_MSR_DATA_PERR_HOLD_OUT_3 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFMSR_MSR_DATA_PERR_HOLD_OUT_3 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFBBC_BREX_PRED_CHECKER_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFBBC_BREX_PRED_CHECKER_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFBBX_RFILE_EAT_BR_ERR_HOLD_OUT_3 , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFBBX_RFILE_EAT_BR_ERR_HOLD_OUT_3 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFBBX_RFILE_EAT_BRP1_ERR_HOLD_OUT_3 , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFBBX_RFILE_EAT_BRP1_ERR_HOLD_OUT_3 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT0_ARF_ERR_HOLD_OUT_3 , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFBBX_RFILE_LKCT0_ARF_ERR_HOLD_OUT_3 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT0_ROB_ERR_HOLD_OUT_3 , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFBBX_RFILE_LKCT0_ROB_ERR_HOLD_OUT_3 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT1_ARF_ERR_HOLD_OUT_3 , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFBBX_RFILE_LKCT1_ARF_ERR_HOLD_OUT_3 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT1_ROB_ERR_HOLD_OUT_3 , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFBBX_RFILE_LKCT1_ROB_ERR_HOLD_OUT_3 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_2_IFBBC_BREX_ROB_WR_COLLISION_HOLD_OUT , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFBBC_BREX_ROB_WR_COLLISION_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_2_IFFSE_MFSPR_COLLISION_ERR_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFSE_MFSPR_COLLISION_ERR_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_2_IFFPF_IFAR_VLD_IN_QERR_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFPF_IFAR_VLD_IN_QERR_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_2_IFFPF_L2_RELOAD_COMING_QERR_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFPF_L2_RELOAD_COMING_QERR_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_2_IFFPF_L2_RELOAD_INTERF_QERR_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFPF_L2_RELOAD_INTERF_QERR_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_2_IFFPF_MULTI_RLDM_HAS_SAME_EA_QERR_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFPF_MULTI_RLDM_HAS_SAME_EA_QERR_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_2_IFFCP_CIABR_PERR_HOLD_OUT , 5 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFCP_CIABR_PERR_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_2_UNUSED_1 , 6 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_UNUSED_1 ); REG64_FLD( C_IFU_HOLD_OUT_2_IFFMSR_MSR_DATA_PERR_HOLD_OUT_3 , 7 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFMSR_MSR_DATA_PERR_HOLD_OUT_3 ); REG64_FLD( C_IFU_HOLD_OUT_2_IFBBC_BREX_PRED_CHECKER_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFBBC_BREX_PRED_CHECKER_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_2_IFBBX_RFILE_EAT_BR_ERR_HOLD_OUT_3 , 9 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFBBX_RFILE_EAT_BR_ERR_HOLD_OUT_3 ); REG64_FLD( C_IFU_HOLD_OUT_2_IFBBX_RFILE_EAT_BRP1_ERR_HOLD_OUT_3 , 10 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFBBX_RFILE_EAT_BRP1_ERR_HOLD_OUT_3 ); REG64_FLD( C_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT0_ARF_ERR_HOLD_OUT_3 , 11 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFBBX_RFILE_LKCT0_ARF_ERR_HOLD_OUT_3 ); REG64_FLD( C_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT0_ROB_ERR_HOLD_OUT_3 , 12 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFBBX_RFILE_LKCT0_ROB_ERR_HOLD_OUT_3 ); REG64_FLD( C_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT1_ARF_ERR_HOLD_OUT_3 , 13 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFBBX_RFILE_LKCT1_ARF_ERR_HOLD_OUT_3 ); REG64_FLD( C_IFU_HOLD_OUT_2_IFBBX_RFILE_LKCT1_ROB_ERR_HOLD_OUT_3 , 14 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFBBX_RFILE_LKCT1_ROB_ERR_HOLD_OUT_3 ); REG64_FLD( C_IFU_HOLD_OUT_2_IFBBC_BREX_ROB_WR_COLLISION_HOLD_OUT , 15 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFBBC_BREX_ROB_WR_COLLISION_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFBSC_MFSPR_LOG_CRIT_P_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFBSC_MFSPR_LOG_CRIT_P_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFBSC_MFSPR_LOG_NONCRIT_P_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFBSC_MFSPR_LOG_NONCRIT_P_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFBSC_MFSPR_RFILE_CRIT_P_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFBSC_MFSPR_RFILE_CRIT_P_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFBSC_MFSPR_RFILE_NONCRIT_P_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFBSC_MFSPR_RFILE_NONCRIT_P_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFBBC_BREX_EATAG_OUTOFRANGE_HOLD_OUT_2 , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFBBC_BREX_EATAG_OUTOFRANGE_HOLD_OUT_2 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFBBC_BREX_FLUSH_CHECKER_HOLD_OUT_2 , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFBBC_BREX_FLUSH_CHECKER_HOLD_OUT_2 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFFAC_S0_NIA_P_HOLD_OUT , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFAC_S0_NIA_P_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFFAC_S0_TAIL_P_HOLD_OUT , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFAC_S0_TAIL_P_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFFAC_REFETCH_OUTOFRANGE_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFAC_REFETCH_OUTOFRANGE_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFFAC_S0_COMP_EATAG_OUTOFRANGE_HOLD_OUT , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFAC_S0_COMP_EATAG_OUTOFRANGE_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFFAC_S0_NIA_EATAG_OUTOFRANGE_HOLD_OUT , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFAC_S0_NIA_EATAG_OUTOFRANGE_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_3_UNUSED_2 , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_UNUSED_2 ); REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFFRC_REFETCH_EAT_P_HOLD_OUT , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFRC_REFETCH_EAT_P_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_3_IFFRC_REFETCH_SPR_P_HOLD_OUT , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IFFRC_REFETCH_SPR_P_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_3_TCC_TC_FIR_SCOM_HOLD_OUT , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_TCC_TC_FIR_SCOM_HOLD_OUT ); REG64_FLD( EX_L2_IFU_HOLD_OUT_3_UNUSED , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_UNUSED ); REG64_FLD( C_IFU_HOLD_OUT_3_IFBSC_MFSPR_LOG_CRIT_P_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFBSC_MFSPR_LOG_CRIT_P_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_3_IFBSC_MFSPR_LOG_NONCRIT_P_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFBSC_MFSPR_LOG_NONCRIT_P_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_3_IFBSC_MFSPR_RFILE_CRIT_P_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFBSC_MFSPR_RFILE_CRIT_P_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_3_IFBSC_MFSPR_RFILE_NONCRIT_P_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFBSC_MFSPR_RFILE_NONCRIT_P_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_3_IFBBC_BREX_EATAG_OUTOFRANGE_HOLD_OUT_2 , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFBBC_BREX_EATAG_OUTOFRANGE_HOLD_OUT_2 ); REG64_FLD( C_IFU_HOLD_OUT_3_IFBBC_BREX_FLUSH_CHECKER_HOLD_OUT_2 , 5 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFBBC_BREX_FLUSH_CHECKER_HOLD_OUT_2 ); REG64_FLD( C_IFU_HOLD_OUT_3_IFFAC_S0_NIA_P_HOLD_OUT , 6 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFAC_S0_NIA_P_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_3_IFFAC_S0_TAIL_P_HOLD_OUT , 7 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFAC_S0_TAIL_P_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_3_IFFAC_REFETCH_OUTOFRANGE_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFAC_REFETCH_OUTOFRANGE_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_3_IFFAC_S0_COMP_EATAG_OUTOFRANGE_HOLD_OUT , 9 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFAC_S0_COMP_EATAG_OUTOFRANGE_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_3_IFFAC_S0_NIA_EATAG_OUTOFRANGE_HOLD_OUT , 10 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFAC_S0_NIA_EATAG_OUTOFRANGE_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_3_UNUSED_2 , 11 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_UNUSED_2 ); REG64_FLD( C_IFU_HOLD_OUT_3_IFFRC_REFETCH_EAT_P_HOLD_OUT , 12 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFRC_REFETCH_EAT_P_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_3_IFFRC_REFETCH_SPR_P_HOLD_OUT , 13 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IFFRC_REFETCH_SPR_P_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_3_TCC_TC_FIR_SCOM_HOLD_OUT , 14 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_TCC_TC_FIR_SCOM_HOLD_OUT ); REG64_FLD( C_IFU_HOLD_OUT_3_UNUSED , 15 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_UNUSED ); REG64_FLD( EX_IMA_EVENT_MASK_ECONL_0 , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECONL_0 ); REG64_FLD( EX_IMA_EVENT_MASK_ECRL_0 , 1 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECRL_0 ); REG64_FLD( EX_IMA_EVENT_MASK_ECH_0 , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECH_0 ); REG64_FLD( EX_IMA_EVENT_MASK_ECP_0 , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECP_0 ); REG64_FLD( EX_IMA_EVENT_MASK_ECS_0 , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECS_0 ); REG64_FLD( EX_IMA_EVENT_MASK_ECA_0 , 5 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECA_0 ); REG64_FLD( EX_IMA_EVENT_MASK_ECTA0_0 , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECTA0_0 ); REG64_FLD( EX_IMA_EVENT_MASK_ECTA1_0 , 7 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECTA1_0 ); REG64_FLD( EX_IMA_EVENT_MASK_ECUS0_0 , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECUS0_0 ); REG64_FLD( EX_IMA_EVENT_MASK_ECUS1_0 , 9 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECUS1_0 ); REG64_FLD( EX_IMA_EVENT_MASK_ECONL_1 , 10 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECONL_1 ); REG64_FLD( EX_IMA_EVENT_MASK_ECRL_1 , 11 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECRL_1 ); REG64_FLD( EX_IMA_EVENT_MASK_ECH_1 , 12 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECH_1 ); REG64_FLD( EX_IMA_EVENT_MASK_ECP_1 , 13 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECP_1 ); REG64_FLD( EX_IMA_EVENT_MASK_ECS_1 , 14 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECS_1 ); REG64_FLD( EX_IMA_EVENT_MASK_ECA_1 , 15 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECA_1 ); REG64_FLD( EX_IMA_EVENT_MASK_ECTA0_1 , 16 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECTA0_1 ); REG64_FLD( EX_IMA_EVENT_MASK_ECTA1_1 , 17 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECTA1_1 ); REG64_FLD( EX_IMA_EVENT_MASK_ECUS0_1 , 18 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECUS0_1 ); REG64_FLD( EX_IMA_EVENT_MASK_ECUS1_1 , 19 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECUS1_1 ); REG64_FLD( EX_IMA_EVENT_MASK_ECONL_2 , 20 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECONL_2 ); REG64_FLD( EX_IMA_EVENT_MASK_ECRL_2 , 21 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECRL_2 ); REG64_FLD( EX_IMA_EVENT_MASK_ECH_2 , 22 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECH_2 ); REG64_FLD( EX_IMA_EVENT_MASK_ECP_2 , 23 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECP_2 ); REG64_FLD( EX_IMA_EVENT_MASK_ECS_2 , 24 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECS_2 ); REG64_FLD( EX_IMA_EVENT_MASK_ECA_2 , 25 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECA_2 ); REG64_FLD( EX_IMA_EVENT_MASK_ECTA0_2 , 26 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECTA0_2 ); REG64_FLD( EX_IMA_EVENT_MASK_ECTA1_2 , 27 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECTA1_2 ); REG64_FLD( EX_IMA_EVENT_MASK_ECUS0_2 , 28 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECUS0_2 ); REG64_FLD( EX_IMA_EVENT_MASK_ECUS1_2 , 29 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_ECUS1_2 ); REG64_FLD( EX_IMA_EVENT_MASK_IC_TAP , 30 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_IC_TAP ); REG64_FLD( EX_IMA_EVENT_MASK_IC_TAP_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_IC_TAP_LEN ); REG64_FLD( EX_IMA_EVENT_MASK_DISABLE_WRAP , 33 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DISABLE_WRAP ); REG64_FLD( EX_IMA_EVENT_MASK_CME_POWSAV , 34 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_CME_POWSAV ); REG64_FLD( C_IMA_EVENT_MASK_ECONL_0 , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECONL_0 ); REG64_FLD( C_IMA_EVENT_MASK_ECRL_0 , 1 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECRL_0 ); REG64_FLD( C_IMA_EVENT_MASK_ECH_0 , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECH_0 ); REG64_FLD( C_IMA_EVENT_MASK_ECP_0 , 3 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECP_0 ); REG64_FLD( C_IMA_EVENT_MASK_ECS_0 , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECS_0 ); REG64_FLD( C_IMA_EVENT_MASK_ECA_0 , 5 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECA_0 ); REG64_FLD( C_IMA_EVENT_MASK_ECTA0_0 , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECTA0_0 ); REG64_FLD( C_IMA_EVENT_MASK_ECTA1_0 , 7 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECTA1_0 ); REG64_FLD( C_IMA_EVENT_MASK_ECUS0_0 , 8 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECUS0_0 ); REG64_FLD( C_IMA_EVENT_MASK_ECUS1_0 , 9 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECUS1_0 ); REG64_FLD( C_IMA_EVENT_MASK_ECONL_1 , 10 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECONL_1 ); REG64_FLD( C_IMA_EVENT_MASK_ECRL_1 , 11 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECRL_1 ); REG64_FLD( C_IMA_EVENT_MASK_ECH_1 , 12 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECH_1 ); REG64_FLD( C_IMA_EVENT_MASK_ECP_1 , 13 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECP_1 ); REG64_FLD( C_IMA_EVENT_MASK_ECS_1 , 14 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECS_1 ); REG64_FLD( C_IMA_EVENT_MASK_ECA_1 , 15 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECA_1 ); REG64_FLD( C_IMA_EVENT_MASK_ECTA0_1 , 16 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECTA0_1 ); REG64_FLD( C_IMA_EVENT_MASK_ECTA1_1 , 17 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECTA1_1 ); REG64_FLD( C_IMA_EVENT_MASK_ECUS0_1 , 18 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECUS0_1 ); REG64_FLD( C_IMA_EVENT_MASK_ECUS1_1 , 19 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECUS1_1 ); REG64_FLD( C_IMA_EVENT_MASK_ECONL_2 , 20 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECONL_2 ); REG64_FLD( C_IMA_EVENT_MASK_ECRL_2 , 21 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECRL_2 ); REG64_FLD( C_IMA_EVENT_MASK_ECH_2 , 22 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECH_2 ); REG64_FLD( C_IMA_EVENT_MASK_ECP_2 , 23 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECP_2 ); REG64_FLD( C_IMA_EVENT_MASK_ECS_2 , 24 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECS_2 ); REG64_FLD( C_IMA_EVENT_MASK_ECA_2 , 25 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECA_2 ); REG64_FLD( C_IMA_EVENT_MASK_ECTA0_2 , 26 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECTA0_2 ); REG64_FLD( C_IMA_EVENT_MASK_ECTA1_2 , 27 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECTA1_2 ); REG64_FLD( C_IMA_EVENT_MASK_ECUS0_2 , 28 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECUS0_2 ); REG64_FLD( C_IMA_EVENT_MASK_ECUS1_2 , 29 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ECUS1_2 ); REG64_FLD( C_IMA_EVENT_MASK_IC_TAP , 30 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_IC_TAP ); REG64_FLD( C_IMA_EVENT_MASK_IC_TAP_LEN , 3 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_IC_TAP_LEN ); REG64_FLD( C_IMA_EVENT_MASK_DISABLE_WRAP , 33 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_DISABLE_WRAP ); REG64_FLD( C_IMA_EVENT_MASK_CME_POWSAV , 34 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_CME_POWSAV ); REG64_FLD( EX_IMA_TRACE_SAMPSEL , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SAMPSEL ); REG64_FLD( EX_IMA_TRACE_SAMPSEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SAMPSEL_LEN ); REG64_FLD( EX_IMA_TRACE_CPMC_LOAD , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_CPMC_LOAD ); REG64_FLD( EX_IMA_TRACE_CPMC_LOAD_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_CPMC_LOAD_LEN ); REG64_FLD( EX_IMA_TRACE_CPMC1SEL , 34 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_CPMC1SEL ); REG64_FLD( EX_IMA_TRACE_CPMC1SEL_LEN , 7 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_CPMC1SEL_LEN ); REG64_FLD( EX_IMA_TRACE_CPMC2SEL , 41 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_CPMC2SEL ); REG64_FLD( EX_IMA_TRACE_CPMC2SEL_LEN , 7 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_CPMC2SEL_LEN ); REG64_FLD( C_IMA_TRACE_SAMPSEL , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SAMPSEL ); REG64_FLD( C_IMA_TRACE_SAMPSEL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SAMPSEL_LEN ); REG64_FLD( C_IMA_TRACE_CPMC_LOAD , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_CPMC_LOAD ); REG64_FLD( C_IMA_TRACE_CPMC_LOAD_LEN , 32 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_CPMC_LOAD_LEN ); REG64_FLD( C_IMA_TRACE_CPMC1SEL , 34 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_CPMC1SEL ); REG64_FLD( C_IMA_TRACE_CPMC1SEL_LEN , 7 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_CPMC1SEL_LEN ); REG64_FLD( C_IMA_TRACE_CPMC2SEL , 41 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_CPMC2SEL ); REG64_FLD( C_IMA_TRACE_CPMC2SEL_LEN , 7 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_CPMC2SEL_LEN ); REG64_FLD( EQ_INJECT_REG_THERM_TRIP , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_THERM_TRIP ); REG64_FLD( EQ_INJECT_REG_THERM_TRIP_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_THERM_TRIP_LEN ); REG64_FLD( EQ_INJECT_REG_THERM_MODE , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_THERM_MODE ); REG64_FLD( EQ_INJECT_REG_THERM_MODE_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_THERM_MODE_LEN ); REG64_FLD( EX_INJECT_REG_THERM_TRIP , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_THERM_TRIP ); REG64_FLD( EX_INJECT_REG_THERM_TRIP_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_THERM_TRIP_LEN ); REG64_FLD( EX_INJECT_REG_THERM_MODE , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_THERM_MODE ); REG64_FLD( EX_INJECT_REG_THERM_MODE_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_THERM_MODE_LEN ); REG64_FLD( C_INJECT_REG_THERM_TRIP , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_THERM_TRIP ); REG64_FLD( C_INJECT_REG_THERM_TRIP_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_THERM_TRIP_LEN ); REG64_FLD( C_INJECT_REG_THERM_MODE , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_THERM_MODE ); REG64_FLD( C_INJECT_REG_THERM_MODE_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_THERM_MODE_LEN ); REG64_FLD( EQ_INJ_REG_STQ_ERR , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STQ_ERR ); REG64_FLD( EQ_INJ_REG_STQ_ERR_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STQ_ERR_LEN ); REG64_FLD( EX_INJ_REG_STQ_ERR , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STQ_ERR ); REG64_FLD( EX_INJ_REG_STQ_ERR_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STQ_ERR_LEN ); REG64_FLD( EX_L2_INV_ERATE_INVALIDATE_ERAT , 63 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_INVALIDATE_ERAT ); REG64_FLD( C_INV_ERATE_INVALIDATE_ERAT , 63 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INVALIDATE_ERAT ); REG64_FLD( EX_L2_ISU_DEBUG_CTRL_ISU_HLD_OUT_REG6 , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ISU_HLD_OUT_REG6 ); REG64_FLD( EX_L2_ISU_DEBUG_CTRL_ISU_HLD_OUT_REG6_LEN , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ISU_HLD_OUT_REG6_LEN ); REG64_FLD( C_ISU_DEBUG_CTRL_ISU_HLD_OUT_REG6 , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ISU_HLD_OUT_REG6 ); REG64_FLD( C_ISU_DEBUG_CTRL_ISU_HLD_OUT_REG6_LEN , 18 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ISU_HLD_OUT_REG6_LEN ); REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_HEIR_CHKSTOP_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T0_HEIR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_HSRR1_CHKSTOP_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T0_HSRR1_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_MSR_CHKSTOP_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T0_MSR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_SRR1_CHKSTOP_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T0_SRR1_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_VRSAVE_BKUP_CHKSTOP_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T0_VRSAVE_BKUP_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_VRSAVE_CHKSTOP_HOLD_OUT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T0_VRSAVE_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_FSCR_CHKSTOP_HOLD_OUT , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T0_FSCR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_HFSCR_CHKSTOP_HOLD_OUT , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T0_HFSCR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_TEXASR_CHKSTOP_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T0_TEXASR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_BESCR_CHKSTOP_HOLD_OUT , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T0_BESCR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCX_SDCU_T0_MCHK_AND_ME_EQ_0_HOLD_OUT , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCU_T0_MCHK_AND_ME_EQ_0_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCR_ERR_INJ , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCR_ERR_INJ ); REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCC_T0_HEAD_TAIL_XSTOP , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCC_T0_HEAD_TAIL_XSTOP ); REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCC_T1_HEAD_TAIL_XSTOP , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCC_T1_HEAD_TAIL_XSTOP ); REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCC_T2_HEAD_TAIL_XSTOP , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCC_T2_HEAD_TAIL_XSTOP ); REG64_FLD( EX_L2_ISU_REG0_HOLD_OUT_SDCC_T3_HEAD_TAIL_XSTOP , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCC_T3_HEAD_TAIL_XSTOP ); REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_HEIR_CHKSTOP_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T0_HEIR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_HSRR1_CHKSTOP_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T0_HSRR1_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_MSR_CHKSTOP_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T0_MSR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_SRR1_CHKSTOP_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T0_SRR1_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_VRSAVE_BKUP_CHKSTOP_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T0_VRSAVE_BKUP_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_VRSAVE_CHKSTOP_HOLD_OUT , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T0_VRSAVE_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_FSCR_CHKSTOP_HOLD_OUT , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T0_FSCR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_HFSCR_CHKSTOP_HOLD_OUT , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T0_HFSCR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_TEXASR_CHKSTOP_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T0_TEXASR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCO_T0_BESCR_CHKSTOP_HOLD_OUT , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T0_BESCR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCX_SDCU_T0_MCHK_AND_ME_EQ_0_HOLD_OUT , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCU_T0_MCHK_AND_ME_EQ_0_HOLD_OUT ); REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCR_ERR_INJ , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCR_ERR_INJ ); REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCC_T0_HEAD_TAIL_XSTOP , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCC_T0_HEAD_TAIL_XSTOP ); REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCC_T1_HEAD_TAIL_XSTOP , 15 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCC_T1_HEAD_TAIL_XSTOP ); REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCC_T2_HEAD_TAIL_XSTOP , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCC_T2_HEAD_TAIL_XSTOP ); REG64_FLD( C_ISU_REG0_HOLD_OUT_SDCC_T3_HEAD_TAIL_XSTOP , 17 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCC_T3_HEAD_TAIL_XSTOP ); REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_HEIR_CHKSTOP_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T1_HEIR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_HSRR1_CHKSTOP_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T1_HSRR1_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_MSR_CHKSTOP_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T1_MSR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_SRR1_CHKSTOP_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T1_SRR1_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_VRSAVE_BKUP_CHKSTOP_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T1_VRSAVE_BKUP_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_VRSAVE_CHKSTOP_HOLD_OUT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T1_VRSAVE_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_FSCR_CHKSTOP_HOLD_OUT , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T1_FSCR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_HFSCR_CHKSTOP_HOLD_OUT , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T1_HFSCR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_TEXASR_CHKSTOP_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T1_TEXASR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_BESCR_CHKSTOP_HOLD_OUT , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T1_BESCR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCX_SDCU_T1_MCHK_AND_ME_EQ_0_HOLD_OUT , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCU_T1_MCHK_AND_ME_EQ_0_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_ERR_INJ_RECOV , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_ERR_INJ_RECOV ); REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCCC_T0_COMP_RCOV , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCCC_T0_COMP_RCOV ); REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCCC_T1_COMP_RCOV , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCCC_T1_COMP_RCOV ); REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCCC_T2_COMP_RCOV , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCCC_T2_COMP_RCOV ); REG64_FLD( EX_L2_ISU_REG1_HOLD_OUT_SDCCC_T3_COMP_RCOV , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCCC_T3_COMP_RCOV ); REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_HEIR_CHKSTOP_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T1_HEIR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_HSRR1_CHKSTOP_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T1_HSRR1_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_MSR_CHKSTOP_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T1_MSR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_SRR1_CHKSTOP_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T1_SRR1_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_VRSAVE_BKUP_CHKSTOP_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T1_VRSAVE_BKUP_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_VRSAVE_CHKSTOP_HOLD_OUT , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T1_VRSAVE_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_FSCR_CHKSTOP_HOLD_OUT , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T1_FSCR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_HFSCR_CHKSTOP_HOLD_OUT , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T1_HFSCR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_TEXASR_CHKSTOP_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T1_TEXASR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCO_T1_BESCR_CHKSTOP_HOLD_OUT , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T1_BESCR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCX_SDCU_T1_MCHK_AND_ME_EQ_0_HOLD_OUT , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCU_T1_MCHK_AND_ME_EQ_0_HOLD_OUT ); REG64_FLD( C_ISU_REG1_HOLD_OUT_ERR_INJ_RECOV , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ERR_INJ_RECOV ); REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCCC_T0_COMP_RCOV , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCCC_T0_COMP_RCOV ); REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCCC_T1_COMP_RCOV , 15 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCCC_T1_COMP_RCOV ); REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCCC_T2_COMP_RCOV , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCCC_T2_COMP_RCOV ); REG64_FLD( C_ISU_REG1_HOLD_OUT_SDCCC_T3_COMP_RCOV , 17 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCCC_T3_COMP_RCOV ); REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_HEIR_CHKSTOP_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T2_HEIR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_HSRR1_CHKSTOP_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T2_HSRR1_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_MSR_CHKSTOP_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T2_MSR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_SRR1_CHKSTOP_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T2_SRR1_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_VRSAVE_BKUP_CHKSTOP_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T2_VRSAVE_BKUP_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_VRSAVE_CHKSTOP_HOLD_OUT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T2_VRSAVE_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_FSCR_CHKSTOP_HOLD_OUT , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T2_FSCR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_HFSCR_CHKSTOP_HOLD_OUT , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T2_HFSCR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_TEXASR_CHKSTOP_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T2_TEXASR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_BESCR_CHKSTOP_HOLD_OUT , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T2_BESCR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCX_SDCU_T2_MCHK_AND_ME_EQ_0_HOLD_OUT , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCU_T2_MCHK_AND_ME_EQ_0_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_WAT_INJECT_INT , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_WAT_INJECT_INT ); REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCA_RCOV , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCA_RCOV ); REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCU_RAM_XSTOP , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCU_RAM_XSTOP ); REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_SDCU_XSTOP , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCU_XSTOP ); REG64_FLD( EX_L2_ISU_REG2_HOLD_OUT_WAT_INJECT_INT_RECOV , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_WAT_INJECT_INT_RECOV ); REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_HEIR_CHKSTOP_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T2_HEIR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_HSRR1_CHKSTOP_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T2_HSRR1_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_MSR_CHKSTOP_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T2_MSR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_SRR1_CHKSTOP_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T2_SRR1_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_VRSAVE_BKUP_CHKSTOP_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T2_VRSAVE_BKUP_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_VRSAVE_CHKSTOP_HOLD_OUT , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T2_VRSAVE_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_FSCR_CHKSTOP_HOLD_OUT , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T2_FSCR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_HFSCR_CHKSTOP_HOLD_OUT , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T2_HFSCR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_TEXASR_CHKSTOP_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T2_TEXASR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCO_T2_BESCR_CHKSTOP_HOLD_OUT , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T2_BESCR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCX_SDCU_T2_MCHK_AND_ME_EQ_0_HOLD_OUT , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCU_T2_MCHK_AND_ME_EQ_0_HOLD_OUT ); REG64_FLD( C_ISU_REG2_HOLD_OUT_WAT_INJECT_INT , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WAT_INJECT_INT ); REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCA_RCOV , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCA_RCOV ); REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCU_RAM_XSTOP , 15 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCU_RAM_XSTOP ); REG64_FLD( C_ISU_REG2_HOLD_OUT_SDCU_XSTOP , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCU_XSTOP ); REG64_FLD( C_ISU_REG2_HOLD_OUT_WAT_INJECT_INT_RECOV , 17 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WAT_INJECT_INT_RECOV ); REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_HEIR_CHKSTOP_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T3_HEIR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_HSRR1_CHKSTOP_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T3_HSRR1_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_MSR_CHKSTOP_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T3_MSR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_SRR1_CHKSTOP_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T3_SRR1_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_VRSAVE_BKUP_CHKSTOP_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T3_VRSAVE_BKUP_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_VRSAVE_CHKSTOP_HOLD_OUT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T3_VRSAVE_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_FSCR_CHKSTOP_HOLD_OUT , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T3_FSCR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_HFSCR_CHKSTOP_HOLD_OUT , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T3_HFSCR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_TEXASR_CHKSTOP_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T3_TEXASR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_BESCR_CHKSTOP_HOLD_OUT , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T3_BESCR_CHKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCX_SDCU_T3_MCHK_AND_ME_EQ_0_HOLD_OUT , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCX_SDCU_T3_MCHK_AND_ME_EQ_0_HOLD_OUT ); REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCV_T0_FLUSH_XSTOP , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCV_T0_FLUSH_XSTOP ); REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCV_T1_FLUSH_XSTOP , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCV_T1_FLUSH_XSTOP ); REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCV_T2_FLUSH_XSTOP , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCV_T2_FLUSH_XSTOP ); REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDCV_T3_FLUSH_XSTOP , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCV_T3_FLUSH_XSTOP ); REG64_FLD( EX_L2_ISU_REG3_HOLD_OUT_SDKSMRF_SS0_EVEN_S0_1B , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_EVEN_S0_1B ); REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_HEIR_CHKSTOP_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T3_HEIR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_HSRR1_CHKSTOP_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T3_HSRR1_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_MSR_CHKSTOP_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T3_MSR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_SRR1_CHKSTOP_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T3_SRR1_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_VRSAVE_BKUP_CHKSTOP_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T3_VRSAVE_BKUP_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_VRSAVE_CHKSTOP_HOLD_OUT , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T3_VRSAVE_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_FSCR_CHKSTOP_HOLD_OUT , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T3_FSCR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_HFSCR_CHKSTOP_HOLD_OUT , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T3_HFSCR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_TEXASR_CHKSTOP_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T3_TEXASR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCO_T3_BESCR_CHKSTOP_HOLD_OUT , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCO_T3_BESCR_CHKSTOP_HOLD_OUT ); REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCX_SDCU_T3_MCHK_AND_ME_EQ_0_HOLD_OUT , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCX_SDCU_T3_MCHK_AND_ME_EQ_0_HOLD_OUT ); REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCV_T0_FLUSH_XSTOP , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCV_T0_FLUSH_XSTOP ); REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCV_T1_FLUSH_XSTOP , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCV_T1_FLUSH_XSTOP ); REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCV_T2_FLUSH_XSTOP , 15 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCV_T2_FLUSH_XSTOP ); REG64_FLD( C_ISU_REG3_HOLD_OUT_SDCV_T3_FLUSH_XSTOP , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCV_T3_FLUSH_XSTOP ); REG64_FLD( C_ISU_REG3_HOLD_OUT_SDKSMRF_SS0_EVEN_S0_1B , 17 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_EVEN_S0_1B ); REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_EVEN_S1_1B , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_EVEN_S1_1B ); REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_EVEN_S2_1B , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_EVEN_S2_1B ); REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S0_1B , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_ODD_S0_1B ); REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S1_1B , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_ODD_S1_1B ); REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S2_1B , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_ODD_S2_1B ); REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_EVEN_S0_1B , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_EVEN_S0_1B ); REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_EVEN_S1_1B , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_EVEN_S1_1B ); REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_EVEN_S2_1B , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_EVEN_S2_1B ); REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_ODD_S0_1B , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_ODD_S0_1B ); REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_ODD_S1_1B , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_ODD_S1_1B ); REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_ODD_S2_1B , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_ODD_S2_1B ); REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_EVEN_S0_2B_XSTOP , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_EVEN_S0_2B_XSTOP ); REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_EVEN_S1_2B_XSTOP , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_EVEN_S1_2B_XSTOP ); REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_EVEN_S2_2B_XSTOP , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_EVEN_S2_2B_XSTOP ); REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S0_2B_XSTOP , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_ODD_S0_2B_XSTOP ); REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S1_2B_XSTOP , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_ODD_S1_2B_XSTOP ); REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S2_2B_XSTOP , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_ODD_S2_2B_XSTOP ); REG64_FLD( EX_L2_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_EVEN_S0_2B_XSTOP , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_EVEN_S0_2B_XSTOP ); REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_EVEN_S1_1B , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_EVEN_S1_1B ); REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_EVEN_S2_1B , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_EVEN_S2_1B ); REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S0_1B , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_ODD_S0_1B ); REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S1_1B , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_ODD_S1_1B ); REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S2_1B , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_ODD_S2_1B ); REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_EVEN_S0_1B , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_EVEN_S0_1B ); REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_EVEN_S1_1B , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_EVEN_S1_1B ); REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_EVEN_S2_1B , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_EVEN_S2_1B ); REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_ODD_S0_1B , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_ODD_S0_1B ); REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_ODD_S1_1B , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_ODD_S1_1B ); REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_ODD_S2_1B , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_ODD_S2_1B ); REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_EVEN_S0_2B_XSTOP , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_EVEN_S0_2B_XSTOP ); REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_EVEN_S1_2B_XSTOP , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_EVEN_S1_2B_XSTOP ); REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_EVEN_S2_2B_XSTOP , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_EVEN_S2_2B_XSTOP ); REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S0_2B_XSTOP , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_ODD_S0_2B_XSTOP ); REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S1_2B_XSTOP , 15 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_ODD_S1_2B_XSTOP ); REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS0_ODD_S2_2B_XSTOP , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS0_ODD_S2_2B_XSTOP ); REG64_FLD( C_ISU_REG4_HOLD_OUT_SDKSMRF_SS1_EVEN_S0_2B_XSTOP , 17 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_EVEN_S0_2B_XSTOP ); REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_SDKSMRF_SS1_EVEN_S1_2B_XSTOP , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_EVEN_S1_2B_XSTOP ); REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_SDKSMRF_SS1_EVEN_S2_2B_XSTOP , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_EVEN_S2_2B_XSTOP ); REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_SDKSMRF_SS1_ODD_S0_2B_XSTOP , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_ODD_S0_2B_XSTOP ); REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_SDKSMRF_SS1_ODD_S1_2B_XSTOP , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_ODD_S1_2B_XSTOP ); REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_SDKSMRF_SS1_ODD_S2_2B_XSTOP , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_ODD_S2_2B_XSTOP ); REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_SDCXC_ERR_RPT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCXC_ERR_RPT ); REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_SDCC_T0_CRITICAL_IS_XSTOP , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCC_T0_CRITICAL_IS_XSTOP ); REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_SDCC_T1_CRITICAL_IS_XSTOP , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCC_T1_CRITICAL_IS_XSTOP ); REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_SDCC_T2_CRITICAL_IS_XSTOP , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCC_T2_CRITICAL_IS_XSTOP ); REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_SDCC_T3_CRITICAL_IS_XSTOP , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SDCC_T3_CRITICAL_IS_XSTOP ); REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_GND , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_GND ); REG64_FLD( EX_L2_ISU_REG5_HOLD_OUT_GND_LEN , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_GND_LEN ); REG64_FLD( C_ISU_REG5_HOLD_OUT_SDKSMRF_SS1_EVEN_S1_2B_XSTOP , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_EVEN_S1_2B_XSTOP ); REG64_FLD( C_ISU_REG5_HOLD_OUT_SDKSMRF_SS1_EVEN_S2_2B_XSTOP , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_EVEN_S2_2B_XSTOP ); REG64_FLD( C_ISU_REG5_HOLD_OUT_SDKSMRF_SS1_ODD_S0_2B_XSTOP , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_ODD_S0_2B_XSTOP ); REG64_FLD( C_ISU_REG5_HOLD_OUT_SDKSMRF_SS1_ODD_S1_2B_XSTOP , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_ODD_S1_2B_XSTOP ); REG64_FLD( C_ISU_REG5_HOLD_OUT_SDKSMRF_SS1_ODD_S2_2B_XSTOP , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDKSMRF_SS1_ODD_S2_2B_XSTOP ); REG64_FLD( C_ISU_REG5_HOLD_OUT_SDCXC_ERR_RPT , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCXC_ERR_RPT ); REG64_FLD( C_ISU_REG5_HOLD_OUT_SDCC_T0_CRITICAL_IS_XSTOP , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCC_T0_CRITICAL_IS_XSTOP ); REG64_FLD( C_ISU_REG5_HOLD_OUT_SDCC_T1_CRITICAL_IS_XSTOP , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCC_T1_CRITICAL_IS_XSTOP ); REG64_FLD( C_ISU_REG5_HOLD_OUT_SDCC_T2_CRITICAL_IS_XSTOP , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCC_T2_CRITICAL_IS_XSTOP ); REG64_FLD( C_ISU_REG5_HOLD_OUT_SDCC_T3_CRITICAL_IS_XSTOP , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SDCC_T3_CRITICAL_IS_XSTOP ); REG64_FLD( C_ISU_REG5_HOLD_OUT_GND , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GND ); REG64_FLD( C_ISU_REG5_HOLD_OUT_GND_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GND_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WRITE_ON_RUN_MODE ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXTEND_TRIG_MODE ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXTEND_TRIG_MODE_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_BANK_MODE ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENH_MODE ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SELCT_CONTROL ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SELCT_CONTROL_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_CONTROL ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT_LEN ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); REG64_FLD( EQ_L3TRA0_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_LT ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WRITE_ON_RUN_MODE ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXTEND_TRIG_MODE ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXTEND_TRIG_MODE_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_BANK_MODE ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENH_MODE ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SELCT_CONTROL ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SELCT_CONTROL_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_CONTROL ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT_LEN ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); REG64_FLD( EQ_L3TRA0_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_LT ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WRITE_ON_RUN_MODE ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXTEND_TRIG_MODE ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXTEND_TRIG_MODE_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_BANK_MODE ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENH_MODE ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SELCT_CONTROL ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SELCT_CONTROL_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_CONTROL ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT_LEN ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); REG64_FLD( EQ_L3TRA1_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_LT ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WRITE_ON_RUN_MODE ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXTEND_TRIG_MODE ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXTEND_TRIG_MODE_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_BANK_MODE ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENH_MODE ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SELCT_CONTROL ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SELCT_CONTROL_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_CONTROL ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT_LEN ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); REG64_FLD( EQ_L3TRA1_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_LT ); REG64_FLD( EQ_L3_ERR_RPT0_REG_L3SDRTL0_BAD_HPC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3SDRTL0_BAD_HPC ); REG64_FLD( EQ_L3_ERR_RPT0_REG_L3SDRTL1_BAD_HPC , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3SDRTL1_BAD_HPC ); REG64_FLD( EQ_L3_ERR_RPT0_REG_L3CORTR_NO_LCO_TGTS , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3CORTR_NO_LCO_TGTS ); REG64_FLD( EQ_L3_ERR_RPT0_REG_SN0_RCMD_TTAG_P , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SN0_RCMD_TTAG_P ); REG64_FLD( EQ_L3_ERR_RPT0_REG_SN1_RCMD_TTAG_P , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SN1_RCMD_TTAG_P ); REG64_FLD( EQ_L3_ERR_RPT0_REG_SN0_RCMD_ADDR_P , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SN0_RCMD_ADDR_P ); REG64_FLD( EQ_L3_ERR_RPT0_REG_SN1_RCMD_ADDR_P , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SN1_RCMD_ADDR_P ); REG64_FLD( EQ_L3_ERR_RPT0_REG_SN0_CRESP_TTAG_P , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SN0_CRESP_TTAG_P ); REG64_FLD( EQ_L3_ERR_RPT0_REG_SN1_CRESP_TTAG_P , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SN1_CRESP_TTAG_P ); REG64_FLD( EQ_L3_ERR_RPT0_REG_SN0_CRESP_ATAG_P , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SN0_CRESP_ATAG_P ); REG64_FLD( EQ_L3_ERR_RPT0_REG_SN1_CRESP_ATAG_P , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SN1_CRESP_ATAG_P ); REG64_FLD( EQ_L3_ERR_RPT0_REG_DATA_RTAG_P , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DATA_RTAG_P ); REG64_FLD( EQ_L3_ERR_RPT0_REG_PF_UNSOLICITED_CRESP , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PF_UNSOLICITED_CRESP ); REG64_FLD( EQ_L3_ERR_RPT0_REG_SN_UNSOLICITED_CRESP , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SN_UNSOLICITED_CRESP ); REG64_FLD( EQ_L3_ERR_RPT0_REG_CO_UNSOLICITED_CRESP , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CO_UNSOLICITED_CRESP ); REG64_FLD( EQ_L3_ERR_RPT0_REG_SPARE_15 , 15 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_15 ); REG64_FLD( EQ_L3_ERR_RPT0_REG_SPARE_16 , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_16 ); REG64_FLD( EQ_L3_ERR_RPT0_REG_SPARE_17 , 17 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_17 ); REG64_FLD( EQ_L3_ERR_RPT0_REG_WI_UNSOLICITED_DATA , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WI_UNSOLICITED_DATA ); REG64_FLD( EQ_L3_ERR_RPT0_REG_PF_UNSOLICITED_DATA , 19 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PF_UNSOLICITED_DATA ); REG64_FLD( EQ_L3_ERR_RPT0_REG_TM_CAM , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TM_CAM ); REG64_FLD( EQ_L3_ERR_RPT0_REG_TM_CAM_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TM_CAM_LEN ); REG64_FLD( EQ_L3_ERR_RPT0_REG_COFSM_ADDR , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COFSM_ADDR ); REG64_FLD( EQ_L3_ERR_RPT0_REG_SNFSM_ADDR , 25 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SNFSM_ADDR ); REG64_FLD( EQ_L3_ERR_RPT0_REG_L3SDRTL0_CACHE_INHIBIT , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3SDRTL0_CACHE_INHIBIT ); REG64_FLD( EQ_L3_ERR_RPT0_REG_L3SDRTL1_CACHE_INHIBIT , 27 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3SDRTL1_CACHE_INHIBIT ); REG64_FLD( EQ_L3_ERR_RPT0_REG_L3SDRTL2_CACHE_INHIBIT , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3SDRTL2_CACHE_INHIBIT ); REG64_FLD( EQ_L3_ERR_RPT0_REG_L3SDRTL3_CACHE_INHIBIT , 29 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3SDRTL3_CACHE_INHIBIT ); REG64_FLD( EQ_L3_ERR_RPT0_REG_L3SDRTL2_BAD_HPC , 30 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3SDRTL2_BAD_HPC ); REG64_FLD( EQ_L3_ERR_RPT0_REG_L3SDRTL3_BAD_HPC , 31 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3SDRTL3_BAD_HPC ); REG64_FLD( EQ_L3_ERR_RPT0_REG_SN_MACHINE_HANG , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SN_MACHINE_HANG ); REG64_FLD( EQ_L3_ERR_RPT0_REG_RD_MACHINE_HANG , 33 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RD_MACHINE_HANG ); REG64_FLD( EQ_L3_ERR_RPT0_REG_CI_MACHINE_HANG , 34 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CI_MACHINE_HANG ); REG64_FLD( EQ_L3_ERR_RPT0_REG_CO_MACHINE_HANG , 35 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CO_MACHINE_HANG ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_L3SDRTL0_BAD_HPC , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3SDRTL0_BAD_HPC ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_L3SDRTL1_BAD_HPC , 1 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3SDRTL1_BAD_HPC ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_L3CORTR_NO_LCO_TGTS , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3CORTR_NO_LCO_TGTS ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SN0_RCMD_TTAG_P , 3 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SN0_RCMD_TTAG_P ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SN1_RCMD_TTAG_P , 4 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SN1_RCMD_TTAG_P ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SN0_RCMD_ADDR_P , 5 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SN0_RCMD_ADDR_P ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SN1_RCMD_ADDR_P , 6 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SN1_RCMD_ADDR_P ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SN0_CRESP_TTAG_P , 7 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SN0_CRESP_TTAG_P ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SN1_CRESP_TTAG_P , 8 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SN1_CRESP_TTAG_P ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SN0_CRESP_ATAG_P , 9 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SN0_CRESP_ATAG_P ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SN1_CRESP_ATAG_P , 10 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SN1_CRESP_ATAG_P ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_DATA_RTAG_P , 11 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_DATA_RTAG_P ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_PF_UNSOLICITED_CRESP , 12 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_PF_UNSOLICITED_CRESP ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SN_UNSOLICITED_CRESP , 13 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SN_UNSOLICITED_CRESP ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_CO_UNSOLICITED_CRESP , 14 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_CO_UNSOLICITED_CRESP ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SPARE_15 , 15 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SPARE_15 ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SPARE_16 , 16 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SPARE_16 ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SPARE_17 , 17 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SPARE_17 ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_WI_UNSOLICITED_DATA , 18 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_WI_UNSOLICITED_DATA ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_PF_UNSOLICITED_DATA , 19 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_PF_UNSOLICITED_DATA ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_TM_CAM , 20 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_TM_CAM ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_TM_CAM_LEN , 4 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_TM_CAM_LEN ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_COFSM_ADDR , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_COFSM_ADDR ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SNFSM_ADDR , 25 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SNFSM_ADDR ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_L3SDRTL0_CACHE_INHIBIT , 26 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3SDRTL0_CACHE_INHIBIT ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_L3SDRTL1_CACHE_INHIBIT , 27 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3SDRTL1_CACHE_INHIBIT ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_L3SDRTL2_CACHE_INHIBIT , 28 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3SDRTL2_CACHE_INHIBIT ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_L3SDRTL3_CACHE_INHIBIT , 29 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3SDRTL3_CACHE_INHIBIT ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_L3SDRTL2_BAD_HPC , 30 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3SDRTL2_BAD_HPC ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_L3SDRTL3_BAD_HPC , 31 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3SDRTL3_BAD_HPC ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_SN_MACHINE_HANG , 32 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SN_MACHINE_HANG ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_RD_MACHINE_HANG , 33 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_RD_MACHINE_HANG ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_CI_MACHINE_HANG , 34 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_CI_MACHINE_HANG ); REG64_FLD( EX_L3_L3_ERR_RPT0_REG_CO_MACHINE_HANG , 35 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_CO_MACHINE_HANG ); REG64_FLD( EQ_L3_ERR_RPT1_REG_PF_MACHINE_HANG , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PF_MACHINE_HANG ); REG64_FLD( EQ_L3_ERR_RPT1_REG_WI_MACHINE_HANG , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WI_MACHINE_HANG ); REG64_FLD( EQ_L3_ERR_RPT1_REG_L3L2CTL_RD_OVERRUN_CK , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3L2CTL_RD_OVERRUN_CK ); REG64_FLD( EQ_L3_ERR_RPT1_REG_L3L2CTL_PF_OVERRUN_CK , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3L2CTL_PF_OVERRUN_CK ); REG64_FLD( EQ_L3_ERR_RPT1_REG_L3CICTL_CI_OVERRUN_CK , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3CICTL_CI_OVERRUN_CK ); REG64_FLD( EQ_L3_ERR_RPT1_REG_L3XMEMA0_DW_DIR_HIT , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3XMEMA0_DW_DIR_HIT ); REG64_FLD( EQ_L3_ERR_RPT1_REG_L3XMEMA1_DW_DIR_HIT , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3XMEMA1_DW_DIR_HIT ); REG64_FLD( EQ_L3_ERR_RPT1_REG_L3XMEMA0_CRW_DIR_HIT , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3XMEMA0_CRW_DIR_HIT ); REG64_FLD( EQ_L3_ERR_RPT1_REG_L3XMEMA1_CRW_DIR_HIT , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3XMEMA1_CRW_DIR_HIT ); REG64_FLD( EQ_L3_ERR_RPT1_REG_PBEXCA0_CMD_REQ_ERR0 , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PBEXCA0_CMD_REQ_ERR0 ); REG64_FLD( EQ_L3_ERR_RPT1_REG_PBEXCA0_CMD_REQ_ERR1 , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PBEXCA0_CMD_REQ_ERR1 ); REG64_FLD( EQ_L3_ERR_RPT1_REG_PBEXCA0_CMD_REQ_ERR2 , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PBEXCA0_CMD_REQ_ERR2 ); REG64_FLD( EQ_L3_ERR_RPT1_REG_PBEXCA1_CMD_REQ_ERR0 , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PBEXCA1_CMD_REQ_ERR0 ); REG64_FLD( EQ_L3_ERR_RPT1_REG_PBEXCA1_CMD_REQ_ERR1 , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PBEXCA1_CMD_REQ_ERR1 ); REG64_FLD( EQ_L3_ERR_RPT1_REG_PBEXCA1_CMD_REQ_ERR2 , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PBEXCA1_CMD_REQ_ERR2 ); REG64_FLD( EQ_L3_ERR_RPT1_REG_MC_FP_MATE_CMD_ERR0 , 15 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MC_FP_MATE_CMD_ERR0 ); REG64_FLD( EQ_L3_ERR_RPT1_REG_MC_FP_MATE_CMD_ERR1 , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MC_FP_MATE_CMD_ERR1 ); REG64_FLD( EQ_L3_ERR_RPT1_REG_L3PBEXCA0_OVERFLOW , 17 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3PBEXCA0_OVERFLOW ); REG64_FLD( EQ_L3_ERR_RPT1_REG_L3PBEXCA1_OVERFLOW , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3PBEXCA1_OVERFLOW ); REG64_FLD( EQ_L3_ERR_RPT1_REG_L3PBEXCA0_UNDERFLOW , 19 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3PBEXCA0_UNDERFLOW ); REG64_FLD( EQ_L3_ERR_RPT1_REG_L3PBEXCA1_UNDERFLOW , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3PBEXCA1_UNDERFLOW ); REG64_FLD( EQ_L3_ERR_RPT1_REG_PF_MACHINE_W4DT_HANG , 21 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PF_MACHINE_W4DT_HANG ); REG64_FLD( EQ_L3_ERR_RPT1_REG_WI_MACHINE_W4DT_HANG , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WI_MACHINE_W4DT_HANG ); REG64_FLD( EQ_L3_ERR_RPT1_REG_CO_CRESP_ACK_DEAD , 23 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CO_CRESP_ACK_DEAD ); REG64_FLD( EQ_L3_ERR_RPT1_REG_SN_CRESP_ACK_DEAD , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SN_CRESP_ACK_DEAD ); REG64_FLD( EQ_L3_ERR_RPT1_REG_SN2_RCMD_TTAG_P , 25 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SN2_RCMD_TTAG_P ); REG64_FLD( EQ_L3_ERR_RPT1_REG_SN3_RCMD_TTAG_P , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SN3_RCMD_TTAG_P ); REG64_FLD( EQ_L3_ERR_RPT1_REG_SN2_RCMD_ADDR_P , 27 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SN2_RCMD_ADDR_P ); REG64_FLD( EQ_L3_ERR_RPT1_REG_SN3_RCMD_ADDR_P , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SN3_RCMD_ADDR_P ); REG64_FLD( EQ_L3_ERR_RPT1_REG_SN2_CRESP_TTAG_P , 29 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SN2_CRESP_TTAG_P ); REG64_FLD( EQ_L3_ERR_RPT1_REG_SN3_CRESP_TTAG_P , 30 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SN3_CRESP_TTAG_P ); REG64_FLD( EQ_L3_ERR_RPT1_REG_SN2_CRESP_ATAG_P , 31 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SN2_CRESP_ATAG_P ); REG64_FLD( EQ_L3_ERR_RPT1_REG_SN3_CRESP_ATAG_P , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SN3_CRESP_ATAG_P ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_PF_MACHINE_HANG , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_PF_MACHINE_HANG ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_WI_MACHINE_HANG , 1 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_WI_MACHINE_HANG ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3L2CTL_RD_OVERRUN_CK , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3L2CTL_RD_OVERRUN_CK ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3L2CTL_PF_OVERRUN_CK , 3 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3L2CTL_PF_OVERRUN_CK ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3CICTL_CI_OVERRUN_CK , 4 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3CICTL_CI_OVERRUN_CK ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3XMEMA0_DW_DIR_HIT , 5 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3XMEMA0_DW_DIR_HIT ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3XMEMA1_DW_DIR_HIT , 6 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3XMEMA1_DW_DIR_HIT ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3XMEMA0_CRW_DIR_HIT , 7 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3XMEMA0_CRW_DIR_HIT ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3XMEMA1_CRW_DIR_HIT , 8 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3XMEMA1_CRW_DIR_HIT ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_PBEXCA0_CMD_REQ_ERR0 , 9 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_PBEXCA0_CMD_REQ_ERR0 ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_PBEXCA0_CMD_REQ_ERR1 , 10 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_PBEXCA0_CMD_REQ_ERR1 ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_PBEXCA0_CMD_REQ_ERR2 , 11 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_PBEXCA0_CMD_REQ_ERR2 ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_PBEXCA1_CMD_REQ_ERR0 , 12 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_PBEXCA1_CMD_REQ_ERR0 ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_PBEXCA1_CMD_REQ_ERR1 , 13 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_PBEXCA1_CMD_REQ_ERR1 ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_PBEXCA1_CMD_REQ_ERR2 , 14 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_PBEXCA1_CMD_REQ_ERR2 ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_MC_FP_MATE_CMD_ERR0 , 15 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_MC_FP_MATE_CMD_ERR0 ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_MC_FP_MATE_CMD_ERR1 , 16 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_MC_FP_MATE_CMD_ERR1 ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3PBEXCA0_OVERFLOW , 17 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3PBEXCA0_OVERFLOW ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3PBEXCA1_OVERFLOW , 18 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3PBEXCA1_OVERFLOW ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3PBEXCA0_UNDERFLOW , 19 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3PBEXCA0_UNDERFLOW ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_L3PBEXCA1_UNDERFLOW , 20 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3PBEXCA1_UNDERFLOW ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_PF_MACHINE_W4DT_HANG , 21 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_PF_MACHINE_W4DT_HANG ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_WI_MACHINE_W4DT_HANG , 22 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_WI_MACHINE_W4DT_HANG ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_CO_CRESP_ACK_DEAD , 23 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_CO_CRESP_ACK_DEAD ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_SN_CRESP_ACK_DEAD , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SN_CRESP_ACK_DEAD ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_SN2_RCMD_TTAG_P , 25 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SN2_RCMD_TTAG_P ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_SN3_RCMD_TTAG_P , 26 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SN3_RCMD_TTAG_P ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_SN2_RCMD_ADDR_P , 27 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SN2_RCMD_ADDR_P ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_SN3_RCMD_ADDR_P , 28 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SN3_RCMD_ADDR_P ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_SN2_CRESP_TTAG_P , 29 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SN2_CRESP_TTAG_P ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_SN3_CRESP_TTAG_P , 30 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SN3_CRESP_TTAG_P ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_SN2_CRESP_ATAG_P , 31 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SN2_CRESP_ATAG_P ); REG64_FLD( EX_L3_L3_ERR_RPT1_REG_SN3_CRESP_ATAG_P , 32 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_SN3_CRESP_ATAG_P ); REG64_FLD( EQ_L3_RD_EPSILON_CFG_REG_WT4CR_TIER0_EPS_VAL , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WT4CR_TIER0_EPS_VAL ); REG64_FLD( EQ_L3_RD_EPSILON_CFG_REG_WT4CR_TIER0_EPS_VAL_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WT4CR_TIER0_EPS_VAL_LEN ); REG64_FLD( EQ_L3_RD_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WT4CR_TIER1_EPS_VAL ); REG64_FLD( EQ_L3_RD_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WT4CR_TIER1_EPS_VAL_LEN ); REG64_FLD( EQ_L3_RD_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WT4CR_TIER2_EPS_VAL ); REG64_FLD( EQ_L3_RD_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WT4CR_TIER2_EPS_VAL_LEN ); REG64_FLD( EQ_L3_RD_EPSILON_CFG_REG_EPS_MODE_SEL , 36 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EPS_MODE_SEL ); REG64_FLD( EX_L3_RD_EPSILON_CFG_REG_WT4CR_TIER0_EPS_VAL , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WT4CR_TIER0_EPS_VAL ); REG64_FLD( EX_L3_RD_EPSILON_CFG_REG_WT4CR_TIER0_EPS_VAL_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WT4CR_TIER0_EPS_VAL_LEN ); REG64_FLD( EX_L3_RD_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WT4CR_TIER1_EPS_VAL ); REG64_FLD( EX_L3_RD_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WT4CR_TIER1_EPS_VAL_LEN ); REG64_FLD( EX_L3_RD_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WT4CR_TIER2_EPS_VAL ); REG64_FLD( EX_L3_RD_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WT4CR_TIER2_EPS_VAL_LEN ); REG64_FLD( EX_L3_RD_EPSILON_CFG_REG_EPS_MODE_SEL , 36 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EPS_MODE_SEL ); REG64_FLD( EQ_L3_RTIM_PERIOD_MONITOR_MON , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MON ); REG64_FLD( EQ_L3_RTIM_PERIOD_MONITOR_MON_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MON_LEN ); REG64_FLD( EX_L3_L3_RTIM_PERIOD_MONITOR_MON , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_MON ); REG64_FLD( EX_L3_L3_RTIM_PERIOD_MONITOR_MON_LEN , 8 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_MON_LEN ); REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WT4CR_TIER1_EPS_VAL ); REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WT4CR_TIER1_EPS_VAL_LEN ); REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WT4CR_TIER2_EPS_VAL ); REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WT4CR_TIER2_EPS_VAL_LEN ); REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_EN_WT4CR_EPS_ON_LCO , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EN_WT4CR_EPS_ON_LCO ); REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_EN_WT4CR_EXTENDED_MODE , 25 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EN_WT4CR_EXTENDED_MODE ); REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_EPS_STEP_MODE , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EPS_STEP_MODE ); REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_EPS_STEP_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EPS_STEP_MODE_LEN ); REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_EPS_DIVIDER_MODE , 30 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EPS_DIVIDER_MODE ); REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_EPS_DIVIDER_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EPS_DIVIDER_MODE_LEN ); REG64_FLD( EQ_L3_WR_EPSILON_CFG_REG_EPS_CNT_USE_DIVIDER_EN , 34 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EPS_CNT_USE_DIVIDER_EN ); REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_WT4CR_TIER1_EPS_VAL ); REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_WT4CR_TIER1_EPS_VAL_LEN , 12 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_WT4CR_TIER1_EPS_VAL_LEN ); REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL , 12 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_WT4CR_TIER2_EPS_VAL ); REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_WT4CR_TIER2_EPS_VAL_LEN , 12 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_WT4CR_TIER2_EPS_VAL_LEN ); REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_EN_WT4CR_EPS_ON_LCO , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_EN_WT4CR_EPS_ON_LCO ); REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_EN_WT4CR_EXTENDED_MODE , 25 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_EN_WT4CR_EXTENDED_MODE ); REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_EPS_STEP_MODE , 26 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_EPS_STEP_MODE ); REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_EPS_STEP_MODE_LEN , 4 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_EPS_STEP_MODE_LEN ); REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_EPS_DIVIDER_MODE , 30 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_EPS_DIVIDER_MODE ); REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_EPS_DIVIDER_MODE_LEN , 4 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_EPS_DIVIDER_MODE_LEN ); REG64_FLD( EX_L3_L3_WR_EPSILON_CFG_REG_EPS_CNT_USE_DIVIDER_EN , 34 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_EPS_CNT_USE_DIVIDER_EN ); REG64_FLD( EQ_LINEDEL_TRIG_REG_TRIG , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG ); REG64_FLD( EQ_LINEDEL_TRIG_REG_DONE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DONE ); REG64_FLD( EQ_LINEDEL_TRIG_REG_SPARE , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE ); REG64_FLD( EQ_LINEDEL_TRIG_REG_SPARE_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); REG64_FLD( EX_L2_LINEDEL_TRIG_REG_TRIG , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_TRIG ); REG64_FLD( EX_L2_LINEDEL_TRIG_REG_DONE , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DONE ); REG64_FLD( EX_L2_LINEDEL_TRIG_REG_SPARE , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SPARE ); REG64_FLD( EX_L2_LINEDEL_TRIG_REG_SPARE_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); REG64_FLD( EQ_LINE_DELETED_MEMBERS_REG_L3 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3 ); REG64_FLD( EQ_LINE_DELETED_MEMBERS_REG_L3_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_LEN ); REG64_FLD( EX_L3_LINE_DELETED_MEMBERS_REG_L3 , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3 ); REG64_FLD( EX_L3_LINE_DELETED_MEMBERS_REG_L3_LEN , 5 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_LEN ); REG64_FLD( EQ_LOCAL_FIR_IN0 , 0 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN0 ); REG64_FLD( EQ_LOCAL_FIR_IN1 , 1 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN1 ); REG64_FLD( EQ_LOCAL_FIR_IN2 , 2 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN2 ); REG64_FLD( EQ_LOCAL_FIR_IN3 , 3 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN3 ); REG64_FLD( EQ_LOCAL_FIR_IN4 , 4 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN4 ); REG64_FLD( EQ_LOCAL_FIR_IN5 , 5 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN5 ); REG64_FLD( EQ_LOCAL_FIR_IN6 , 6 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN6 ); REG64_FLD( EQ_LOCAL_FIR_IN7 , 7 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN7 ); REG64_FLD( EQ_LOCAL_FIR_IN8 , 8 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN8 ); REG64_FLD( EQ_LOCAL_FIR_IN9 , 9 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN9 ); REG64_FLD( EQ_LOCAL_FIR_IN10 , 10 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN10 ); REG64_FLD( EQ_LOCAL_FIR_IN11 , 11 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN11 ); REG64_FLD( EQ_LOCAL_FIR_IN12 , 12 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN12 ); REG64_FLD( EQ_LOCAL_FIR_IN13 , 13 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN13 ); REG64_FLD( EQ_LOCAL_FIR_IN14 , 14 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN14 ); REG64_FLD( EQ_LOCAL_FIR_IN15 , 15 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN15 ); REG64_FLD( EQ_LOCAL_FIR_IN16 , 16 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN16 ); REG64_FLD( EQ_LOCAL_FIR_IN17 , 17 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN17 ); REG64_FLD( EQ_LOCAL_FIR_IN18 , 18 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN18 ); REG64_FLD( EQ_LOCAL_FIR_IN19 , 19 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN19 ); REG64_FLD( EQ_LOCAL_FIR_IN20 , 20 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN20 ); REG64_FLD( EQ_LOCAL_FIR_IN21 , 21 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN21 ); REG64_FLD( EQ_LOCAL_FIR_IN22 , 22 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN22 ); REG64_FLD( EQ_LOCAL_FIR_IN23 , 23 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN23 ); REG64_FLD( EQ_LOCAL_FIR_IN24 , 24 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN24 ); REG64_FLD( EQ_LOCAL_FIR_IN25 , 25 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN25 ); REG64_FLD( EQ_LOCAL_FIR_IN26 , 26 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN26 ); REG64_FLD( EQ_LOCAL_FIR_IN27 , 27 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN27 ); REG64_FLD( EQ_LOCAL_FIR_IN28 , 28 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN28 ); REG64_FLD( EQ_LOCAL_FIR_IN29 , 29 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN29 ); REG64_FLD( EQ_LOCAL_FIR_IN30 , 30 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN30 ); REG64_FLD( EQ_LOCAL_FIR_IN31 , 31 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN31 ); REG64_FLD( EQ_LOCAL_FIR_IN32 , 32 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN32 ); REG64_FLD( EQ_LOCAL_FIR_IN33 , 33 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN33 ); REG64_FLD( EQ_LOCAL_FIR_IN34 , 34 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN34 ); REG64_FLD( EQ_LOCAL_FIR_IN35 , 35 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN35 ); REG64_FLD( EQ_LOCAL_FIR_IN36 , 36 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN36 ); REG64_FLD( EQ_LOCAL_FIR_IN37 , 37 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN37 ); REG64_FLD( EQ_LOCAL_FIR_IN38 , 38 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN38 ); REG64_FLD( EQ_LOCAL_FIR_IN39 , 39 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN39 ); REG64_FLD( EQ_LOCAL_FIR_IN40 , 40 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN40 ); REG64_FLD( EQ_LOCAL_FIR_IN41 , 41 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IN41 ); REG64_FLD( EX_LOCAL_FIR_IN0 , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN0 ); REG64_FLD( EX_LOCAL_FIR_IN1 , 1 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN1 ); REG64_FLD( EX_LOCAL_FIR_IN2 , 2 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN2 ); REG64_FLD( EX_LOCAL_FIR_IN3 , 3 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN3 ); REG64_FLD( EX_LOCAL_FIR_IN4 , 4 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN4 ); REG64_FLD( EX_LOCAL_FIR_IN5 , 5 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN5 ); REG64_FLD( EX_LOCAL_FIR_IN6 , 6 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN6 ); REG64_FLD( EX_LOCAL_FIR_IN7 , 7 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN7 ); REG64_FLD( EX_LOCAL_FIR_IN8 , 8 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN8 ); REG64_FLD( EX_LOCAL_FIR_IN9 , 9 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN9 ); REG64_FLD( EX_LOCAL_FIR_IN10 , 10 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN10 ); REG64_FLD( EX_LOCAL_FIR_IN11 , 11 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN11 ); REG64_FLD( EX_LOCAL_FIR_IN12 , 12 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN12 ); REG64_FLD( EX_LOCAL_FIR_IN13 , 13 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN13 ); REG64_FLD( EX_LOCAL_FIR_IN14 , 14 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN14 ); REG64_FLD( EX_LOCAL_FIR_IN15 , 15 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN15 ); REG64_FLD( EX_LOCAL_FIR_IN16 , 16 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN16 ); REG64_FLD( EX_LOCAL_FIR_IN17 , 17 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN17 ); REG64_FLD( EX_LOCAL_FIR_IN18 , 18 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN18 ); REG64_FLD( EX_LOCAL_FIR_IN19 , 19 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN19 ); REG64_FLD( EX_LOCAL_FIR_IN20 , 20 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN20 ); REG64_FLD( EX_LOCAL_FIR_IN21 , 21 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN21 ); REG64_FLD( EX_LOCAL_FIR_IN22 , 22 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN22 ); REG64_FLD( EX_LOCAL_FIR_IN23 , 23 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN23 ); REG64_FLD( EX_LOCAL_FIR_IN24 , 24 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN24 ); REG64_FLD( EX_LOCAL_FIR_IN25 , 25 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN25 ); REG64_FLD( EX_LOCAL_FIR_IN26 , 26 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN26 ); REG64_FLD( EX_LOCAL_FIR_IN27 , 27 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN27 ); REG64_FLD( EX_LOCAL_FIR_IN28 , 28 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN28 ); REG64_FLD( EX_LOCAL_FIR_IN29 , 29 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN29 ); REG64_FLD( EX_LOCAL_FIR_IN30 , 30 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN30 ); REG64_FLD( EX_LOCAL_FIR_IN31 , 31 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN31 ); REG64_FLD( EX_LOCAL_FIR_IN32 , 32 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN32 ); REG64_FLD( EX_LOCAL_FIR_IN33 , 33 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN33 ); REG64_FLD( EX_LOCAL_FIR_IN34 , 34 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN34 ); REG64_FLD( EX_LOCAL_FIR_IN35 , 35 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN35 ); REG64_FLD( EX_LOCAL_FIR_IN36 , 36 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN36 ); REG64_FLD( EX_LOCAL_FIR_IN37 , 37 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN37 ); REG64_FLD( EX_LOCAL_FIR_IN38 , 38 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN38 ); REG64_FLD( EX_LOCAL_FIR_IN39 , 39 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN39 ); REG64_FLD( EX_LOCAL_FIR_IN40 , 40 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN40 ); REG64_FLD( EX_LOCAL_FIR_IN41 , 41 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IN41 ); REG64_FLD( C_LOCAL_FIR_IN0 , 0 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN0 ); REG64_FLD( C_LOCAL_FIR_IN1 , 1 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN1 ); REG64_FLD( C_LOCAL_FIR_IN2 , 2 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN2 ); REG64_FLD( C_LOCAL_FIR_IN3 , 3 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN3 ); REG64_FLD( C_LOCAL_FIR_IN4 , 4 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN4 ); REG64_FLD( C_LOCAL_FIR_IN5 , 5 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN5 ); REG64_FLD( C_LOCAL_FIR_IN6 , 6 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN6 ); REG64_FLD( C_LOCAL_FIR_IN7 , 7 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN7 ); REG64_FLD( C_LOCAL_FIR_IN8 , 8 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN8 ); REG64_FLD( C_LOCAL_FIR_IN9 , 9 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN9 ); REG64_FLD( C_LOCAL_FIR_IN10 , 10 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN10 ); REG64_FLD( C_LOCAL_FIR_IN11 , 11 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN11 ); REG64_FLD( C_LOCAL_FIR_IN12 , 12 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN12 ); REG64_FLD( C_LOCAL_FIR_IN13 , 13 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN13 ); REG64_FLD( C_LOCAL_FIR_IN14 , 14 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN14 ); REG64_FLD( C_LOCAL_FIR_IN15 , 15 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN15 ); REG64_FLD( C_LOCAL_FIR_IN16 , 16 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN16 ); REG64_FLD( C_LOCAL_FIR_IN17 , 17 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN17 ); REG64_FLD( C_LOCAL_FIR_IN18 , 18 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN18 ); REG64_FLD( C_LOCAL_FIR_IN19 , 19 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN19 ); REG64_FLD( C_LOCAL_FIR_IN20 , 20 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN20 ); REG64_FLD( C_LOCAL_FIR_IN21 , 21 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN21 ); REG64_FLD( C_LOCAL_FIR_IN22 , 22 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN22 ); REG64_FLD( C_LOCAL_FIR_IN23 , 23 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN23 ); REG64_FLD( C_LOCAL_FIR_IN24 , 24 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN24 ); REG64_FLD( C_LOCAL_FIR_IN25 , 25 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN25 ); REG64_FLD( C_LOCAL_FIR_IN26 , 26 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN26 ); REG64_FLD( C_LOCAL_FIR_IN27 , 27 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN27 ); REG64_FLD( C_LOCAL_FIR_IN28 , 28 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN28 ); REG64_FLD( C_LOCAL_FIR_IN29 , 29 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN29 ); REG64_FLD( C_LOCAL_FIR_IN30 , 30 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN30 ); REG64_FLD( C_LOCAL_FIR_IN31 , 31 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN31 ); REG64_FLD( C_LOCAL_FIR_IN32 , 32 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN32 ); REG64_FLD( C_LOCAL_FIR_IN33 , 33 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN33 ); REG64_FLD( C_LOCAL_FIR_IN34 , 34 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN34 ); REG64_FLD( C_LOCAL_FIR_IN35 , 35 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN35 ); REG64_FLD( C_LOCAL_FIR_IN36 , 36 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN36 ); REG64_FLD( C_LOCAL_FIR_IN37 , 37 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN37 ); REG64_FLD( C_LOCAL_FIR_IN38 , 38 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN38 ); REG64_FLD( C_LOCAL_FIR_IN39 , 39 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN39 ); REG64_FLD( C_LOCAL_FIR_IN40 , 40 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN40 ); REG64_FLD( C_LOCAL_FIR_IN41 , 41 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IN41 ); REG64_FLD( EQ_LOCAL_FIR_ACTION0_IN , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( EQ_LOCAL_FIR_ACTION0_IN_LEN , 42 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( EX_LOCAL_FIR_ACTION0_IN , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( EX_LOCAL_FIR_ACTION0_IN_LEN , 42 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( C_LOCAL_FIR_ACTION0_IN , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( C_LOCAL_FIR_ACTION0_IN_LEN , 42 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( EQ_LOCAL_FIR_ACTION1_IN , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( EQ_LOCAL_FIR_ACTION1_IN_LEN , 42 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( EX_LOCAL_FIR_ACTION1_IN , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( EX_LOCAL_FIR_ACTION1_IN_LEN , 42 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( C_LOCAL_FIR_ACTION1_IN , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( C_LOCAL_FIR_ACTION1_IN_LEN , 42 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( EQ_LOCAL_FIR_MASK_LFIR_IN , 0 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_LFIR_IN ); REG64_FLD( EQ_LOCAL_FIR_MASK_LFIR_IN_LEN , 42 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_LFIR_IN_LEN ); REG64_FLD( EX_LOCAL_FIR_MASK_LFIR_IN , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_LFIR_IN ); REG64_FLD( EX_LOCAL_FIR_MASK_LFIR_IN_LEN , 42 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_LFIR_IN_LEN ); REG64_FLD( C_LOCAL_FIR_MASK_LFIR_IN , 0 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_LFIR_IN ); REG64_FLD( C_LOCAL_FIR_MASK_LFIR_IN_LEN , 42 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_LFIR_IN_LEN ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN0 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN0 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN1 , 1 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN1 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN2 , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN2 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN3 , 3 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN3 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN4 , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN4 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN5 , 5 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN5 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN6 , 6 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN6 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN7 , 7 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN7 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN8 , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN8 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN9 , 9 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN9 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN10 , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN10 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN11 , 11 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN11 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN12 , 12 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN12 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN13 , 13 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN13 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN14 , 14 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN14 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN15 , 15 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN15 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN16 , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN16 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN17 , 17 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN17 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN18 , 18 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN18 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN19 , 19 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN19 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN20 , 20 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN20 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN21 , 21 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN21 ); REG64_FLD( EQ_LOCAL_XSTOP_ERR_IN22 , 22 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IN22 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN0 , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN0 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN1 , 1 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN1 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN2 , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN2 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN3 , 3 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN3 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN4 , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN4 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN5 , 5 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN5 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN6 , 6 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN6 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN7 , 7 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN7 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN8 , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN8 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN9 , 9 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN9 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN10 , 10 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN10 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN11 , 11 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN11 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN12 , 12 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN12 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN13 , 13 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN13 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN14 , 14 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN14 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN15 , 15 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN15 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN16 , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN16 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN17 , 17 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN17 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN18 , 18 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN18 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN19 , 19 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN19 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN20 , 20 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN20 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN21 , 21 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN21 ); REG64_FLD( EX_LOCAL_XSTOP_ERR_IN22 , 22 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IN22 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN0 , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN0 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN1 , 1 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN1 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN2 , 2 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN2 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN3 , 3 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN3 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN4 , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN4 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN5 , 5 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN5 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN6 , 6 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN6 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN7 , 7 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN7 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN8 , 8 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN8 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN9 , 9 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN9 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN10 , 10 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN10 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN11 , 11 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN11 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN12 , 12 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN12 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN13 , 13 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN13 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN14 , 14 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN14 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN15 , 15 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN15 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN16 , 16 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN16 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN17 , 17 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN17 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN18 , 18 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN18 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN19 , 19 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN19 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN20 , 20 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN20 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN21 , 21 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN21 ); REG64_FLD( C_LOCAL_XSTOP_ERR_IN22 , 22 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IN22 ); REG64_FLD( EQ_LOCAL_XSTOP_MASK_IN , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( EQ_LOCAL_XSTOP_MASK_IN_LEN , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( EX_LOCAL_XSTOP_MASK_IN , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( EX_LOCAL_XSTOP_MASK_IN_LEN , 22 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( C_LOCAL_XSTOP_MASK_IN , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( C_LOCAL_XSTOP_MASK_IN_LEN , 22 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( EQ_LRU_VIC_ALLOC_REG_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG ); REG64_FLD( EQ_LRU_VIC_ALLOC_REG_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG_LEN , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG_LEN ); REG64_FLD( EQ_LRU_VIC_ALLOC_REG_L3_COLUMN_MD_CFG , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_COLUMN_MD_CFG ); REG64_FLD( EQ_LRU_VIC_ALLOC_REG_L3_COLUMN_MD_CFG_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_COLUMN_MD_CFG_LEN ); REG64_FLD( EX_L3_LRU_VIC_ALLOC_REG_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG ); REG64_FLD( EX_L3_LRU_VIC_ALLOC_REG_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG_LEN , 20 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_COLUMN_SEGR_LCO_COLUMN_L2_CFG_LEN ); REG64_FLD( EX_L3_LRU_VIC_ALLOC_REG_L3_COLUMN_MD_CFG , 20 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_COLUMN_MD_CFG ); REG64_FLD( EX_L3_LRU_VIC_ALLOC_REG_L3_COLUMN_MD_CFG_LEN , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_COLUMN_MD_CFG_LEN ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_LSEXEC_HYPERV_TRAP_CHECKSTOP_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSEXEC_HYPERV_TRAP_CHECKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_LSEXEC_BAD_DVAL_FINISH_CHECKSTOP_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSEXEC_BAD_DVAL_FINISH_CHECKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_LSEXEC_REJECT_FINISH_CHECKSTOP_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSEXEC_REJECT_FINISH_CHECKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_FLSH_FFN_AND_NOT_UC_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_FLSH_FFN_AND_NOT_UC_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_FLSH_FLUSH_NEXT_UCODE_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_FLSH_FLUSH_NEXT_UCODE_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_FLSH_INVALID_FLUSH_CASE_HOLD_OUT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_FLSH_INVALID_FLUSH_CASE_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_FLSH_FLUSH_CRITICAL_OP_HOLD_OUT , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_FLSH_FLUSH_CRITICAL_OP_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_FLSH_FLUSH_NEXT_NON_CRIT_ATOMIC_HOLD_OUT , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_FLSH_FLUSH_NEXT_NON_CRIT_ATOMIC_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_LSLRQE_CI_CDF_STUCK_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSLRQE_CI_CDF_STUCK_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_LSLRQE_OVERFLOW_HOLD_OUT , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSLRQE_OVERFLOW_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_LSLRQF_OVERFLOW_HOLD_OUT , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSLRQF_OVERFLOW_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_LSLSAQ_OVERFLOW_HOLD_OUT , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSLSAQ_OVERFLOW_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_LSLMQE_BAD_MC_RLD_DTYPE_ERR_HOLD_OUT , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSLMQE_BAD_MC_RLD_DTYPE_ERR_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_LSLMQE_GOT_SV_TWICE_ERR_HOLD_OUT , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSLMQE_GOT_SV_TWICE_ERR_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_LSLMQE_INV_RD_ERR_HOLD_OUT , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSLMQE_INV_RD_ERR_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG0_SCOM_PARITY_HOLD_OUT , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_SCOM_PARITY_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG0_LSEXEC_HYPERV_TRAP_CHECKSTOP_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSEXEC_HYPERV_TRAP_CHECKSTOP_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG0_LSEXEC_BAD_DVAL_FINISH_CHECKSTOP_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSEXEC_BAD_DVAL_FINISH_CHECKSTOP_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG0_LSEXEC_REJECT_FINISH_CHECKSTOP_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSEXEC_REJECT_FINISH_CHECKSTOP_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG0_FLSH_FFN_AND_NOT_UC_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_FLSH_FFN_AND_NOT_UC_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG0_FLSH_FLUSH_NEXT_UCODE_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_FLSH_FLUSH_NEXT_UCODE_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG0_FLSH_INVALID_FLUSH_CASE_HOLD_OUT , 5 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_FLSH_INVALID_FLUSH_CASE_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG0_FLSH_FLUSH_CRITICAL_OP_HOLD_OUT , 6 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_FLSH_FLUSH_CRITICAL_OP_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG0_FLSH_FLUSH_NEXT_NON_CRIT_ATOMIC_HOLD_OUT , 7 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_FLSH_FLUSH_NEXT_NON_CRIT_ATOMIC_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG0_LSLRQE_CI_CDF_STUCK_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSLRQE_CI_CDF_STUCK_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG0_LSLRQE_OVERFLOW_HOLD_OUT , 9 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSLRQE_OVERFLOW_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG0_LSLRQF_OVERFLOW_HOLD_OUT , 10 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSLRQF_OVERFLOW_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG0_LSLSAQ_OVERFLOW_HOLD_OUT , 11 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSLSAQ_OVERFLOW_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG0_LSLMQE_BAD_MC_RLD_DTYPE_ERR_HOLD_OUT , 12 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSLMQE_BAD_MC_RLD_DTYPE_ERR_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG0_LSLMQE_GOT_SV_TWICE_ERR_HOLD_OUT , 13 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSLMQE_GOT_SV_TWICE_ERR_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG0_LSLMQE_INV_RD_ERR_HOLD_OUT , 14 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSLMQE_INV_RD_ERR_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG0_SCOM_PARITY_HOLD_OUT , 15 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_SCOM_PARITY_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_BUSY_CHECKSTOP_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSSLBC_MULTI_BUSY_CHECKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_ERAT_WRITE_CHECKSTOP_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSSLBC_MULTI_ERAT_WRITE_CHECKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_GRANT_CHECKSTOP_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSSLBC_MULTI_GRANT_CHECKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_PGSEL_CHECKSTOP_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSSLBC_MULTI_PGSEL_CHECKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSPRQ_CONTROL_ERROR_CORE_XSTOP_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSPRQ_CONTROL_ERROR_CORE_XSTOP_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSPRQ_CONTROL_ERROR_SYS_XSTOP_HOLD_OUT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSPRQ_CONTROL_ERROR_SYS_XSTOP_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LS_S2QR_PERR_P2_HOLD_OUT , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LS_S2QR_PERR_P2_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSPRQ_SPR_PERR_HOLD_OUT , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSPRQ_SPR_PERR_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSAMRD_SPR_PERR_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSAMRD_SPR_PERR_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSAMRS_SPR_PERR_HOLD_OUT , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSAMRS_SPR_PERR_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSINTR_SPR_PERR_HOLD_OUT , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSINTR_SPR_PERR_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSXREG_SPR_PERR_HOLD_OUT , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSXREG_SPR_PERR_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_GRBC_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_GRBC_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_WPPM_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_WPPM_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSPRQ_CONTROL_ERROR_RECOV_HOLD_OUT , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSPRQ_CONTROL_ERROR_RECOV_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG1_LSS2Q_ERRC_RTYPE_CHECKSTOP_HOLD_OUT , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSS2Q_ERRC_RTYPE_CHECKSTOP_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_BUSY_CHECKSTOP_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSSLBC_MULTI_BUSY_CHECKSTOP_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_ERAT_WRITE_CHECKSTOP_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSSLBC_MULTI_ERAT_WRITE_CHECKSTOP_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_GRANT_CHECKSTOP_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSSLBC_MULTI_GRANT_CHECKSTOP_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG1_LSSLBC_MULTI_PGSEL_CHECKSTOP_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSSLBC_MULTI_PGSEL_CHECKSTOP_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG1_LSPRQ_CONTROL_ERROR_CORE_XSTOP_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSPRQ_CONTROL_ERROR_CORE_XSTOP_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG1_LSPRQ_CONTROL_ERROR_SYS_XSTOP_HOLD_OUT , 5 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSPRQ_CONTROL_ERROR_SYS_XSTOP_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG1_LS_S2QR_PERR_P2_HOLD_OUT , 6 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LS_S2QR_PERR_P2_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG1_LSPRQ_SPR_PERR_HOLD_OUT , 7 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSPRQ_SPR_PERR_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG1_LSAMRD_SPR_PERR_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSAMRD_SPR_PERR_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG1_LSAMRS_SPR_PERR_HOLD_OUT , 9 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSAMRS_SPR_PERR_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG1_LSINTR_SPR_PERR_HOLD_OUT , 10 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSINTR_SPR_PERR_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG1_LSXREG_SPR_PERR_HOLD_OUT , 11 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSXREG_SPR_PERR_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG1_GRBC_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT , 12 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_GRBC_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG1_WPPM_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT , 13 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_WPPM_SPR_PARITY_ERROR_CORE_XSTOP_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG1_LSPRQ_CONTROL_ERROR_RECOV_HOLD_OUT , 14 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSPRQ_CONTROL_ERROR_RECOV_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG1_LSS2Q_ERRC_RTYPE_CHECKSTOP_HOLD_OUT , 15 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSS2Q_ERRC_RTYPE_CHECKSTOP_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_LS0_DCAC_FIN_PERR_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LS0_DCAC_FIN_PERR_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_LS1_DCAC_FIN_PERR_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LS1_DCAC_FIN_PERR_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_LS2_DCAC_FIN_PERR_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LS2_DCAC_FIN_PERR_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_LS3_DCAC_FIN_PERR_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LS3_DCAC_FIN_PERR_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_SETC_RC6_RD23_PARITY_ERROR_TOTAL_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_SETC_RC6_RD23_PARITY_ERROR_TOTAL_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_WDRD0_RC9_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_WDRD0_RC9_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_WDRD1_RC8_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_WDRD1_RC8_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_DYNAM_SET_DELETED_HOLD_OUT , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_DYNAM_SET_DELETED_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_LS_SLB_MULTIHIT_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LS_SLB_MULTIHIT_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_LS_SLB_P_HOLD_OUT , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LS_SLB_P_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_LS_TLB_MULTIHIT_HOLD_OUT , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LS_TLB_MULTIHIT_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_LS_TLB_P_HOLD_OUT , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LS_TLB_P_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_STPM0_RP2_SETP_PERR_HOLD_OUT , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_STPM0_RP2_SETP_PERR_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_STPM1_RP2_SETP_PERR_HOLD_OUT , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_STPM1_RP2_SETP_PERR_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_STPM2_RP1_SETP_PERR_HOLD_OUT , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_STPM2_RP1_SETP_PERR_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG2_STPM3_RP1_SETP_PERR_HOLD_OUT , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_STPM3_RP1_SETP_PERR_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG2_LS0_DCAC_FIN_PERR_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LS0_DCAC_FIN_PERR_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG2_LS1_DCAC_FIN_PERR_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LS1_DCAC_FIN_PERR_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG2_LS2_DCAC_FIN_PERR_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LS2_DCAC_FIN_PERR_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG2_LS3_DCAC_FIN_PERR_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LS3_DCAC_FIN_PERR_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG2_SETC_RC6_RD23_PARITY_ERROR_TOTAL_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_SETC_RC6_RD23_PARITY_ERROR_TOTAL_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG2_WDRD0_RC9_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT , 5 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_WDRD0_RC9_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG2_WDRD1_RC8_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT , 6 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_WDRD1_RC8_DDIR_ANY_ERROR_ANY_SET_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG2_DYNAM_SET_DELETED_HOLD_OUT , 7 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_DYNAM_SET_DELETED_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG2_LS_SLB_MULTIHIT_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LS_SLB_MULTIHIT_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG2_LS_SLB_P_HOLD_OUT , 9 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LS_SLB_P_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG2_LS_TLB_MULTIHIT_HOLD_OUT , 10 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LS_TLB_MULTIHIT_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG2_LS_TLB_P_HOLD_OUT , 11 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LS_TLB_P_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG2_STPM0_RP2_SETP_PERR_HOLD_OUT , 12 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_STPM0_RP2_SETP_PERR_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG2_STPM1_RP2_SETP_PERR_HOLD_OUT , 13 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_STPM1_RP2_SETP_PERR_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG2_STPM2_RP1_SETP_PERR_HOLD_OUT , 14 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_STPM2_RP1_SETP_PERR_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG2_STPM3_RP1_SETP_PERR_HOLD_OUT , 15 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_STPM3_RP1_SETP_PERR_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_DMAG0_FIN_RF_PARITY_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_DMAG0_FIN_RF_PARITY_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_DMAG1_FIN_RF_PARITY_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_DMAG1_FIN_RF_PARITY_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_DMAG2_RP2_RF_PARITY_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_DMAG2_RP2_RF_PARITY_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_DMAG3_RP2_RF_PARITY_HOLD_OUT , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_DMAG3_RP2_RF_PARITY_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_LS0_RP2_RSVT_MULTILMQ_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LS0_RP2_RSVT_MULTILMQ_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_LS1_RP2_RSVT_MULTILMQ_HOLD_OUT , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LS1_RP2_RSVT_MULTILMQ_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_LS2_RP1_RSVT_MULTILMQ_HOLD_OUT , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LS2_RP1_RSVT_MULTILMQ_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_LS3_RP1_RSVT_MULTILMQ_HOLD_OUT , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LS3_RP1_RSVT_MULTILMQ_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_LSERTD_FIN_P_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSERTD_FIN_P_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_LSERTD_FIN_ERATMHE_HOLD_OUT , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSERTD_FIN_ERATMHE_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_LSS2Q_PC_S2Q_QUEUE_OVERFLOW_HOLD_OUT , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSS2Q_PC_S2Q_QUEUE_OVERFLOW_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_LSSRQ_RES_OVERFLOW_HOLD_OUT , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_LSSRQ_RES_OVERFLOW_HOLD_OUT ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_RESERVED0 , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_RESERVED0 ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_RESERVED1 , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_RESERVED1 ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_RESERVED2 , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_RESERVED2 ); REG64_FLD( EX_L2_LSU_HOLD_OUT_REG3_RESERVED3 , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_RESERVED3 ); REG64_FLD( C_LSU_HOLD_OUT_REG3_DMAG0_FIN_RF_PARITY_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_DMAG0_FIN_RF_PARITY_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG3_DMAG1_FIN_RF_PARITY_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_DMAG1_FIN_RF_PARITY_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG3_DMAG2_RP2_RF_PARITY_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_DMAG2_RP2_RF_PARITY_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG3_DMAG3_RP2_RF_PARITY_HOLD_OUT , 3 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_DMAG3_RP2_RF_PARITY_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG3_LS0_RP2_RSVT_MULTILMQ_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LS0_RP2_RSVT_MULTILMQ_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG3_LS1_RP2_RSVT_MULTILMQ_HOLD_OUT , 5 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LS1_RP2_RSVT_MULTILMQ_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG3_LS2_RP1_RSVT_MULTILMQ_HOLD_OUT , 6 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LS2_RP1_RSVT_MULTILMQ_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG3_LS3_RP1_RSVT_MULTILMQ_HOLD_OUT , 7 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LS3_RP1_RSVT_MULTILMQ_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG3_LSERTD_FIN_P_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSERTD_FIN_P_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG3_LSERTD_FIN_ERATMHE_HOLD_OUT , 9 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSERTD_FIN_ERATMHE_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG3_LSS2Q_PC_S2Q_QUEUE_OVERFLOW_HOLD_OUT , 10 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSS2Q_PC_S2Q_QUEUE_OVERFLOW_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG3_LSSRQ_RES_OVERFLOW_HOLD_OUT , 11 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LSSRQ_RES_OVERFLOW_HOLD_OUT ); REG64_FLD( C_LSU_HOLD_OUT_REG3_RESERVED0 , 12 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_RESERVED0 ); REG64_FLD( C_LSU_HOLD_OUT_REG3_RESERVED1 , 13 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_RESERVED1 ); REG64_FLD( C_LSU_HOLD_OUT_REG3_RESERVED2 , 14 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_RESERVED2 ); REG64_FLD( C_LSU_HOLD_OUT_REG3_RESERVED3 , 15 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_RESERVED3 ); REG64_FLD( EQ_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR ); REG64_FLD( EQ_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( EQ_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); REG64_FLD( EQ_MIB_XIICAC_CME_SCOM_XISIB_PIB_IFETCH_PENDING , 34 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_CME_SCOM_XISIB_PIB_IFETCH_PENDING ); REG64_FLD( EQ_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( EQ_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID ); REG64_FLD( EQ_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID_LEN ); REG64_FLD( EQ_MIB_XIICAC_ICACHE_LINE2_VALID , 40 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ICACHE_LINE2_VALID ); REG64_FLD( EQ_MIB_XIICAC_ICACHE_LINE2_VALID_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ICACHE_LINE2_VALID_LEN ); REG64_FLD( EQ_MIB_XIICAC_ICACHE_LINE_PTR , 45 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ICACHE_LINE_PTR ); REG64_FLD( EQ_MIB_XIICAC_ICACHE_LINE2_ERR , 46 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ICACHE_LINE2_ERR ); REG64_FLD( EQ_MIB_XIICAC_ICACHE_PREFETCH_PENDING , 47 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ICACHE_PREFETCH_PENDING ); REG64_FLD( EX_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR ); REG64_FLD( EX_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( EX_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); REG64_FLD( EX_MIB_XIICAC_CME_SCOM_XISIB_PIB_IFETCH_PENDING , 34 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_CME_SCOM_XISIB_PIB_IFETCH_PENDING ); REG64_FLD( EX_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( EX_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID ); REG64_FLD( EX_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID_LEN ); REG64_FLD( EX_MIB_XIICAC_ICACHE_LINE2_VALID , 40 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ICACHE_LINE2_VALID ); REG64_FLD( EX_MIB_XIICAC_ICACHE_LINE2_VALID_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ICACHE_LINE2_VALID_LEN ); REG64_FLD( EX_MIB_XIICAC_ICACHE_LINE_PTR , 45 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ICACHE_LINE_PTR ); REG64_FLD( EX_MIB_XIICAC_ICACHE_LINE2_ERR , 46 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ICACHE_LINE2_ERR ); REG64_FLD( EX_MIB_XIICAC_ICACHE_PREFETCH_PENDING , 47 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ICACHE_PREFETCH_PENDING ); REG64_FLD( EQ_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); REG64_FLD( EQ_MIB_XIMEM_MEM_ADDR_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR_LEN ); REG64_FLD( EQ_MIB_XIMEM_MEM_R_NW , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_MEM_R_NW ); REG64_FLD( EQ_MIB_XIMEM_MEM_BUSY , 33 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_MEM_BUSY ); REG64_FLD( EQ_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING , 34 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_MEM_IMPRECISE_ERROR_PENDING ); REG64_FLD( EQ_MIB_XIMEM_MEM_BYTE_ENABLE , 35 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_MEM_BYTE_ENABLE ); REG64_FLD( EQ_MIB_XIMEM_MEM_BYTE_ENABLE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_MEM_BYTE_ENABLE_LEN ); REG64_FLD( EQ_MIB_XIMEM_MEM_LINE_MODE , 43 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_MEM_LINE_MODE ); REG64_FLD( EQ_MIB_XIMEM_MEM_ERROR , 49 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_MEM_ERROR ); REG64_FLD( EQ_MIB_XIMEM_MEM_ERROR_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_MEM_ERROR_LEN ); REG64_FLD( EQ_MIB_XIMEM_MEM_IFETCH_PENDING , 62 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_MEM_IFETCH_PENDING ); REG64_FLD( EQ_MIB_XIMEM_MEM_DATAOP_PENDING , 63 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_MEM_DATAOP_PENDING ); REG64_FLD( EX_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); REG64_FLD( EX_MIB_XIMEM_MEM_ADDR_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR_LEN ); REG64_FLD( EX_MIB_XIMEM_MEM_R_NW , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MEM_R_NW ); REG64_FLD( EX_MIB_XIMEM_MEM_BUSY , 33 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MEM_BUSY ); REG64_FLD( EX_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING , 34 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MEM_IMPRECISE_ERROR_PENDING ); REG64_FLD( EX_MIB_XIMEM_MEM_BYTE_ENABLE , 35 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MEM_BYTE_ENABLE ); REG64_FLD( EX_MIB_XIMEM_MEM_BYTE_ENABLE_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MEM_BYTE_ENABLE_LEN ); REG64_FLD( EX_MIB_XIMEM_MEM_LINE_MODE , 43 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MEM_LINE_MODE ); REG64_FLD( EX_MIB_XIMEM_MEM_ERROR , 49 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MEM_ERROR ); REG64_FLD( EX_MIB_XIMEM_MEM_ERROR_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MEM_ERROR_LEN ); REG64_FLD( EX_MIB_XIMEM_MEM_IFETCH_PENDING , 62 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MEM_IFETCH_PENDING ); REG64_FLD( EX_MIB_XIMEM_MEM_DATAOP_PENDING , 63 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_MEM_DATAOP_PENDING ); REG64_FLD( EQ_MIB_XISGB_STORE_ADDRESS , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_STORE_ADDRESS ); REG64_FLD( EQ_MIB_XISGB_STORE_ADDRESS_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_STORE_ADDRESS_LEN ); REG64_FLD( EQ_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING , 35 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING ); REG64_FLD( EQ_MIB_XISGB_SGB_BYTE_VALID , 36 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SGB_BYTE_VALID ); REG64_FLD( EQ_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SGB_BYTE_VALID_LEN ); REG64_FLD( EQ_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); REG64_FLD( EX_MIB_XISGB_STORE_ADDRESS , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_STORE_ADDRESS ); REG64_FLD( EX_MIB_XISGB_STORE_ADDRESS_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_STORE_ADDRESS_LEN ); REG64_FLD( EX_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING , 35 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING ); REG64_FLD( EX_MIB_XISGB_SGB_BYTE_VALID , 36 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SGB_BYTE_VALID ); REG64_FLD( EX_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SGB_BYTE_VALID_LEN ); REG64_FLD( EX_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); REG64_FLD( EQ_MODE_REG_IN0 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN0 ); REG64_FLD( EQ_MODE_REG_IN1 , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN1 ); REG64_FLD( EQ_MODE_REG_IN2 , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN2 ); REG64_FLD( EQ_MODE_REG_IN3 , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN3 ); REG64_FLD( EQ_MODE_REG_IN4 , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN4 ); REG64_FLD( EQ_MODE_REG_IN5 , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN5 ); REG64_FLD( EQ_MODE_REG_IN6 , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN6 ); REG64_FLD( EQ_MODE_REG_IN7 , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN7 ); REG64_FLD( EQ_MODE_REG_IN8 , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN8 ); REG64_FLD( EQ_MODE_REG_IN9 , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN9 ); REG64_FLD( EQ_MODE_REG_IN10 , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN10 ); REG64_FLD( EQ_MODE_REG_IN11 , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN11 ); REG64_FLD( EQ_MODE_REG_IN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( EQ_MODE_REG_IN_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( EX_MODE_REG_IN0 , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN0 ); REG64_FLD( EX_MODE_REG_IN1 , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN1 ); REG64_FLD( EX_MODE_REG_IN2 , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN2 ); REG64_FLD( EX_MODE_REG_IN3 , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN3 ); REG64_FLD( EX_MODE_REG_IN4 , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN4 ); REG64_FLD( EX_MODE_REG_IN5 , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN5 ); REG64_FLD( EX_MODE_REG_IN6 , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN6 ); REG64_FLD( EX_MODE_REG_IN7 , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN7 ); REG64_FLD( EX_MODE_REG_IN8 , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN8 ); REG64_FLD( EX_MODE_REG_IN9 , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN9 ); REG64_FLD( EX_MODE_REG_IN10 , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN10 ); REG64_FLD( EX_MODE_REG_IN11 , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN11 ); REG64_FLD( EX_MODE_REG_IN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( EX_MODE_REG_IN_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( C_MODE_REG_IN0 , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN0 ); REG64_FLD( C_MODE_REG_IN1 , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN1 ); REG64_FLD( C_MODE_REG_IN2 , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN2 ); REG64_FLD( C_MODE_REG_IN3 , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN3 ); REG64_FLD( C_MODE_REG_IN4 , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN4 ); REG64_FLD( C_MODE_REG_IN5 , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN5 ); REG64_FLD( C_MODE_REG_IN6 , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN6 ); REG64_FLD( C_MODE_REG_IN7 , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN7 ); REG64_FLD( C_MODE_REG_IN8 , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN8 ); REG64_FLD( C_MODE_REG_IN9 , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN9 ); REG64_FLD( C_MODE_REG_IN10 , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN10 ); REG64_FLD( C_MODE_REG_IN11 , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN11 ); REG64_FLD( C_MODE_REG_IN , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( C_MODE_REG_IN_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( EQ_MODE_REG0_L3_DISABLED_CFG , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_DISABLED_CFG ); REG64_FLD( EQ_MODE_REG0_L3_DMAP_CI_EN_CFG , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_DMAP_CI_EN_CFG ); REG64_FLD( EQ_MODE_REG0_L3_RDSN_LINEDEL_UE_EN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_RDSN_LINEDEL_UE_EN ); REG64_FLD( EQ_MODE_REG0_L3_NO_ALLOCATE_EN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_NO_ALLOCATE_EN ); REG64_FLD( EQ_MODE_REG0_L3_NO_ALLOCATE_ACTIVE , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_NO_ALLOCATE_ACTIVE ); REG64_FLD( EQ_MODE_REG0_L3_SPARE5 , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_SPARE5 ); REG64_FLD( EQ_MODE_REG0_L3_SPARE6 , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_SPARE6 ); REG64_FLD( EQ_MODE_REG0_L3_SPARE7 , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_SPARE7 ); REG64_FLD( EQ_MODE_REG0_L3_LCO_RTY_LIMIT_DISABLE , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_LCO_RTY_LIMIT_DISABLE ); REG64_FLD( EQ_MODE_REG0_L3_DYN_LCO_BLK_DIS_CFG , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_DYN_LCO_BLK_DIS_CFG ); REG64_FLD( EQ_MODE_REG0_L3_LCO_ADDR_TGT_ENABLE , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_LCO_ADDR_TGT_ENABLE ); REG64_FLD( EQ_MODE_REG0_L3_ADDR_HASH_EN_CFG , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_ADDR_HASH_EN_CFG ); REG64_FLD( EQ_MODE_REG0_L3CERRS_CFG_DCACHE_CAPP , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3CERRS_CFG_DCACHE_CAPP ); REG64_FLD( EQ_MODE_REG0_L3CERRS_LCO_RETRY_THROTL_DIS , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3CERRS_LCO_RETRY_THROTL_DIS ); REG64_FLD( EQ_MODE_REG0_L3_HANG_POLL_PULSE_DIV , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_HANG_POLL_PULSE_DIV ); REG64_FLD( EQ_MODE_REG0_L3_HANG_POLL_PULSE_DIV_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_HANG_POLL_PULSE_DIV_LEN ); REG64_FLD( EQ_MODE_REG0_L3_DATA_POLL_PULSE_DIV , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_DATA_POLL_PULSE_DIV ); REG64_FLD( EQ_MODE_REG0_L3_DATA_POLL_PULSE_DIV_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_DATA_POLL_PULSE_DIV_LEN ); REG64_FLD( EQ_MODE_REG0_L3_SYSMAP_SM_NOT_LG_SEL , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_SYSMAP_SM_NOT_LG_SEL ); REG64_FLD( EX_L2_MODE_REG0_CFG_LRU_DIRECT_MAP , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_LRU_DIRECT_MAP ); REG64_FLD( EX_L2_MODE_REG0_CFG_RANDOM_EN , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_RANDOM_EN ); REG64_FLD( EX_L2_MODE_REG0_CFG_SINGLE_MEM_EN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_SINGLE_MEM_EN ); REG64_FLD( EX_L2_MODE_REG0_CFG_SINGLE_MEM , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_SINGLE_MEM ); REG64_FLD( EX_L2_MODE_REG0_CFG_SINGLE_MEM_LEN , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_SINGLE_MEM_LEN ); REG64_FLD( EX_L2_MODE_REG0_CFG_L3_DIS , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_L3_DIS ); REG64_FLD( EX_L2_MODE_REG0_CFG_CO_SOFT_PURGE_ME_SX_EN , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_CO_SOFT_PURGE_ME_SX_EN ); REG64_FLD( EX_L2_MODE_REG0_CFG_CO_SOFT_PURGE_ALL_LINES_EN , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_CO_SOFT_PURGE_ALL_LINES_EN ); REG64_FLD( EX_L2_MODE_REG0_CFG_DCBZ_TRASHMODE_EN , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_DCBZ_TRASHMODE_EN ); REG64_FLD( EX_L2_MODE_REG0_CFG_CAC_ERR_REPAIR_EN , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_CAC_ERR_REPAIR_EN ); REG64_FLD( EX_L2_MODE_REG0_CFG_LINEDEL_ON_CAC_UE_EN , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_LINEDEL_ON_CAC_UE_EN ); REG64_FLD( EX_L2_MODE_REG0_CFG_HW_TRIG_LINEDEL_LDDISP_CE_EN , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_HW_TRIG_LINEDEL_LDDISP_CE_EN ); REG64_FLD( EX_L2_MODE_REG0_CFG_C0_L2_PB_ARB_RATE_SEL , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_C0_L2_PB_ARB_RATE_SEL ); REG64_FLD( EX_L2_MODE_REG0_CFG_C0_L2_PB_ARB_RATE_SEL_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_C0_L2_PB_ARB_RATE_SEL_LEN ); REG64_FLD( EX_L2_MODE_REG0_CFG_HASH_L3_ADDR_EN , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_HASH_L3_ADDR_EN ); REG64_FLD( EX_L2_MODE_REG0_CFG_RC_FRC_DISP_EQ_NTM_INIG_SI_TO_RCR_EN , 22 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_RC_FRC_DISP_EQ_NTM_INIG_SI_TO_RCR_EN ); REG64_FLD( EX_L2_MODE_REG0_CFG_SYSMAP_SM_NOT_LG_SEL , 23 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_SYSMAP_SM_NOT_LG_SEL ); REG64_FLD( EX_L2_MODE_REG0_CFG_Q_BIT_TID_MASK , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_Q_BIT_TID_MASK ); REG64_FLD( EX_L2_MODE_REG0_CFG_Q_BIT_TID_MASK_LEN , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_Q_BIT_TID_MASK_LEN ); REG64_FLD( EX_L2_MODE_REG0_CFG_STQ_PF_EN , 32 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_STQ_PF_EN ); REG64_FLD( EX_L2_MODE_REG0_CFG_DCACHE_CAPP_LPC_EN , 33 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_DCACHE_CAPP_LPC_EN ); REG64_FLD( EX_L2_MODE_REG0_CFG_PERFMON_INFO_SRC_ED_SEL , 34 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_PERFMON_INFO_SRC_ED_SEL ); REG64_FLD( EX_L2_MODE_REG0_CFG_C1_L2_PB_ARB_RATE_SEL , 35 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_C1_L2_PB_ARB_RATE_SEL ); REG64_FLD( EX_L2_MODE_REG0_CFG_C1_L2_PB_ARB_RATE_SEL_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_C1_L2_PB_ARB_RATE_SEL_LEN ); REG64_FLD( EX_L2_MODE_REG0_CFG_SKIP_GRP_SCOPE_EN , 38 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_SKIP_GRP_SCOPE_EN ); REG64_FLD( EX_L2_MODE_REG0_MODE_REG0_SPARE , 39 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_MODE_REG0_SPARE ); REG64_FLD( EX_L3_MODE_REG0_L3_DISABLED_CFG , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_DISABLED_CFG ); REG64_FLD( EX_L3_MODE_REG0_L3_DMAP_CI_EN_CFG , 1 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_DMAP_CI_EN_CFG ); REG64_FLD( EX_L3_MODE_REG0_L3_RDSN_LINEDEL_UE_EN , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_RDSN_LINEDEL_UE_EN ); REG64_FLD( EX_L3_MODE_REG0_L3_NO_ALLOCATE_EN , 3 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_NO_ALLOCATE_EN ); REG64_FLD( EX_L3_MODE_REG0_L3_NO_ALLOCATE_ACTIVE , 4 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_NO_ALLOCATE_ACTIVE ); REG64_FLD( EX_L3_MODE_REG0_L3_SPARE5 , 5 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_SPARE5 ); REG64_FLD( EX_L3_MODE_REG0_L3_SPARE6 , 6 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_SPARE6 ); REG64_FLD( EX_L3_MODE_REG0_L3_SPARE7 , 7 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_SPARE7 ); REG64_FLD( EX_L3_MODE_REG0_L3_LCO_RTY_LIMIT_DISABLE , 8 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_LCO_RTY_LIMIT_DISABLE ); REG64_FLD( EX_L3_MODE_REG0_L3_DYN_LCO_BLK_DIS_CFG , 9 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_DYN_LCO_BLK_DIS_CFG ); REG64_FLD( EX_L3_MODE_REG0_L3_LCO_ADDR_TGT_ENABLE , 10 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_LCO_ADDR_TGT_ENABLE ); REG64_FLD( EX_L3_MODE_REG0_L3_ADDR_HASH_EN_CFG , 11 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_ADDR_HASH_EN_CFG ); REG64_FLD( EX_L3_MODE_REG0_L3CERRS_CFG_DCACHE_CAPP , 12 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3CERRS_CFG_DCACHE_CAPP ); REG64_FLD( EX_L3_MODE_REG0_L3CERRS_LCO_RETRY_THROTL_DIS , 13 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3CERRS_LCO_RETRY_THROTL_DIS ); REG64_FLD( EX_L3_MODE_REG0_L3_HANG_POLL_PULSE_DIV , 14 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_HANG_POLL_PULSE_DIV ); REG64_FLD( EX_L3_MODE_REG0_L3_HANG_POLL_PULSE_DIV_LEN , 4 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_HANG_POLL_PULSE_DIV_LEN ); REG64_FLD( EX_L3_MODE_REG0_L3_DATA_POLL_PULSE_DIV , 18 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_DATA_POLL_PULSE_DIV ); REG64_FLD( EX_L3_MODE_REG0_L3_DATA_POLL_PULSE_DIV_LEN , 4 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_DATA_POLL_PULSE_DIV_LEN ); REG64_FLD( EX_L3_MODE_REG0_L3_SYSMAP_SM_NOT_LG_SEL , 22 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_SYSMAP_SM_NOT_LG_SEL ); REG64_FLD( EQ_MODE_REG1_L3_LCO_ENABLE_CFG , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_LCO_ENABLE_CFG ); REG64_FLD( EQ_MODE_REG1_L3_LCO_TARGET_GROUP , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_LCO_TARGET_GROUP ); REG64_FLD( EQ_MODE_REG1_L3_LCO_TARGET_ID , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_LCO_TARGET_ID ); REG64_FLD( EQ_MODE_REG1_L3_LCO_TARGET_ID_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_LCO_TARGET_ID_LEN ); REG64_FLD( EQ_MODE_REG1_L3_LCO_TARGET_VICTIMS , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_LCO_TARGET_VICTIMS ); REG64_FLD( EQ_MODE_REG1_L3_LCO_TARGET_VICTIMS_LEN , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_LCO_TARGET_VICTIMS_LEN ); REG64_FLD( EQ_MODE_REG1_L3_SCOM_CINJ_LCO_DIS , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_SCOM_CINJ_LCO_DIS ); REG64_FLD( EX_L2_MODE_REG1_CFG_ECCCK_CE_UE_SUE_ERR_DET_DIS , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_ECCCK_CE_UE_SUE_ERR_DET_DIS ); REG64_FLD( EX_L2_MODE_REG1_CFG_ECCCK_UE_SUE_DET_DIS , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CFG_ECCCK_UE_SUE_DET_DIS ); REG64_FLD( EX_L2_MODE_REG1_MODE_REG1_SPARE0 , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_MODE_REG1_SPARE0 ); REG64_FLD( EX_L2_MODE_REG1_MODE_REG1_SPARE0_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_MODE_REG1_SPARE0_LEN ); REG64_FLD( EX_L2_MODE_REG1_HANG_POLL_PULSE_DIV , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_HANG_POLL_PULSE_DIV ); REG64_FLD( EX_L2_MODE_REG1_HANG_POLL_PULSE_DIV_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_HANG_POLL_PULSE_DIV_LEN ); REG64_FLD( EX_L2_MODE_REG1_DATA_POLL_PULSE_DIV , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DATA_POLL_PULSE_DIV ); REG64_FLD( EX_L2_MODE_REG1_DATA_POLL_PULSE_DIV_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DATA_POLL_PULSE_DIV_LEN ); REG64_FLD( EX_L2_MODE_REG1_MODE_REG1_SPARE1 , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_MODE_REG1_SPARE1 ); REG64_FLD( EX_L2_MODE_REG1_MODE_REG1_SPARE1_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_MODE_REG1_SPARE1_LEN ); REG64_FLD( EX_L2_MODE_REG1_PM03_SMT_ROTATION_DIS , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PM03_SMT_ROTATION_DIS ); REG64_FLD( EX_L2_MODE_REG1_PM47_SMT_ROTATION_DIS , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PM47_SMT_ROTATION_DIS ); REG64_FLD( EX_L2_MODE_REG1_MODE_REG1_SPARE2 , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_MODE_REG1_SPARE2 ); REG64_FLD( EX_L2_MODE_REG1_MODE_REG1_SPARE2_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_MODE_REG1_SPARE2_LEN ); REG64_FLD( EX_L2_MODE_REG1_PM07_TID_ROTATE_PLSS_RATE , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PM07_TID_ROTATE_PLSS_RATE ); REG64_FLD( EX_L2_MODE_REG1_PM07_TID_ROTATE_PLSS_RATE_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PM07_TID_ROTATE_PLSS_RATE_LEN ); REG64_FLD( EX_L2_MODE_REG1_MODE_REG1_SPARE3 , 23 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_MODE_REG1_SPARE3 ); REG64_FLD( EX_L2_MODE_REG1_MODE_REG1_SPARE3_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_MODE_REG1_SPARE3_LEN ); REG64_FLD( EX_L2_MODE_REG1_PM03_L23_EVENT_TID_SEL_EN , 25 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PM03_L23_EVENT_TID_SEL_EN ); REG64_FLD( EX_L2_MODE_REG1_PM03_L23_EVENT_TID_SEL_NUM , 26 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PM03_L23_EVENT_TID_SEL_NUM ); REG64_FLD( EX_L2_MODE_REG1_PM03_L23_EVENT_TID_SEL_NUM_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PM03_L23_EVENT_TID_SEL_NUM_LEN ); REG64_FLD( EX_L2_MODE_REG1_PM47_L23_EVENT_TID_SEL_EN , 29 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PM47_L23_EVENT_TID_SEL_EN ); REG64_FLD( EX_L2_MODE_REG1_PM47_L23_EVENT_TID_SEL_NUM , 30 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PM47_L23_EVENT_TID_SEL_NUM ); REG64_FLD( EX_L2_MODE_REG1_PM47_L23_EVENT_TID_SEL_NUM_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PM47_L23_EVENT_TID_SEL_NUM_LEN ); REG64_FLD( EX_L3_MODE_REG1_L3_LCO_ENABLE_CFG , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_LCO_ENABLE_CFG ); REG64_FLD( EX_L3_MODE_REG1_L3_LCO_TARGET_GROUP , 1 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_LCO_TARGET_GROUP ); REG64_FLD( EX_L3_MODE_REG1_L3_LCO_TARGET_ID , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_LCO_TARGET_ID ); REG64_FLD( EX_L3_MODE_REG1_L3_LCO_TARGET_ID_LEN , 4 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_LCO_TARGET_ID_LEN ); REG64_FLD( EX_L3_MODE_REG1_L3_LCO_TARGET_VICTIMS , 6 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_LCO_TARGET_VICTIMS ); REG64_FLD( EX_L3_MODE_REG1_L3_LCO_TARGET_VICTIMS_LEN , 16 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_LCO_TARGET_VICTIMS_LEN ); REG64_FLD( EX_L3_MODE_REG1_L3_SCOM_CINJ_LCO_DIS , 22 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_SCOM_CINJ_LCO_DIS ); REG64_FLD( EQ_MULTICAST_GROUP_1_MULTICAST1 , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MULTICAST1 ); REG64_FLD( EQ_MULTICAST_GROUP_1_MULTICAST1_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MULTICAST1_LEN ); REG64_FLD( EX_MULTICAST_GROUP_1_MULTICAST1 , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MULTICAST1 ); REG64_FLD( EX_MULTICAST_GROUP_1_MULTICAST1_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MULTICAST1_LEN ); REG64_FLD( C_MULTICAST_GROUP_1_MULTICAST1 , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MULTICAST1 ); REG64_FLD( C_MULTICAST_GROUP_1_MULTICAST1_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MULTICAST1_LEN ); REG64_FLD( EQ_MULTICAST_GROUP_2_MULTICAST2 , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MULTICAST2 ); REG64_FLD( EQ_MULTICAST_GROUP_2_MULTICAST2_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MULTICAST2_LEN ); REG64_FLD( EX_MULTICAST_GROUP_2_MULTICAST2 , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MULTICAST2 ); REG64_FLD( EX_MULTICAST_GROUP_2_MULTICAST2_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MULTICAST2_LEN ); REG64_FLD( C_MULTICAST_GROUP_2_MULTICAST2 , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MULTICAST2 ); REG64_FLD( C_MULTICAST_GROUP_2_MULTICAST2_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MULTICAST2_LEN ); REG64_FLD( EQ_MULTICAST_GROUP_3_MULTICAST3 , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MULTICAST3 ); REG64_FLD( EQ_MULTICAST_GROUP_3_MULTICAST3_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MULTICAST3_LEN ); REG64_FLD( EX_MULTICAST_GROUP_3_MULTICAST3 , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MULTICAST3 ); REG64_FLD( EX_MULTICAST_GROUP_3_MULTICAST3_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MULTICAST3_LEN ); REG64_FLD( C_MULTICAST_GROUP_3_MULTICAST3 , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MULTICAST3 ); REG64_FLD( C_MULTICAST_GROUP_3_MULTICAST3_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MULTICAST3_LEN ); REG64_FLD( EQ_MULTICAST_GROUP_4_MULTICAST4 , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MULTICAST4 ); REG64_FLD( EQ_MULTICAST_GROUP_4_MULTICAST4_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MULTICAST4_LEN ); REG64_FLD( EX_MULTICAST_GROUP_4_MULTICAST4 , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MULTICAST4 ); REG64_FLD( EX_MULTICAST_GROUP_4_MULTICAST4_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MULTICAST4_LEN ); REG64_FLD( C_MULTICAST_GROUP_4_MULTICAST4 , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MULTICAST4 ); REG64_FLD( C_MULTICAST_GROUP_4_MULTICAST4_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MULTICAST4_LEN ); REG64_FLD( EQ_NCU_DARN_BAR_REG_EN , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EN ); REG64_FLD( EQ_NCU_DARN_BAR_REG_ADDR , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ADDR ); REG64_FLD( EQ_NCU_DARN_BAR_REG_ADDR_LEN , 44 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ADDR_LEN ); REG64_FLD( EX_NCU_DARN_BAR_REG_EN , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EN ); REG64_FLD( EX_NCU_DARN_BAR_REG_ADDR , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ADDR ); REG64_FLD( EX_NCU_DARN_BAR_REG_ADDR_LEN , 44 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ADDR_LEN ); REG64_FLD( EQ_NCU_MODE_REG_HTM_QUEUE_LIMIT , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_HTM_QUEUE_LIMIT ); REG64_FLD( EQ_NCU_MODE_REG_HTM_QUEUE_LIMIT_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_HTM_QUEUE_LIMIT_LEN ); REG64_FLD( EQ_NCU_MODE_REG_TRASH_EN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRASH_EN ); REG64_FLD( EQ_NCU_MODE_REG_FENCE_TLBIE , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FENCE_TLBIE ); REG64_FLD( EQ_NCU_MODE_REG_DROP_PRIORITY_MASK , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DROP_PRIORITY_MASK ); REG64_FLD( EQ_NCU_MODE_REG_DROP_PRIORITY_MASK_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DROP_PRIORITY_MASK_LEN ); REG64_FLD( EQ_NCU_MODE_REG_TLBI_GROUP_PUMP_EN , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLBI_GROUP_PUMP_EN ); REG64_FLD( EQ_NCU_MODE_REG_SLBI_GROUP_PUMP_EN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SLBI_GROUP_PUMP_EN ); REG64_FLD( EQ_NCU_MODE_REG_SYSMAP_SM_NOT_LG_SEL , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SYSMAP_SM_NOT_LG_SEL ); REG64_FLD( EQ_NCU_MODE_REG_TLBIE_PACING_CNT_EN , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLBIE_PACING_CNT_EN ); REG64_FLD( EQ_NCU_MODE_REG_TLBIE_DEC_RATE , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLBIE_DEC_RATE ); REG64_FLD( EQ_NCU_MODE_REG_TLBIE_DEC_RATE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLBIE_DEC_RATE_LEN ); REG64_FLD( EQ_NCU_MODE_REG_TLBIE_INC_RATE , 19 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLBIE_INC_RATE ); REG64_FLD( EQ_NCU_MODE_REG_TLBIE_INC_RATE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLBIE_INC_RATE_LEN ); REG64_FLD( EQ_NCU_MODE_REG_TLBIE_CNT_THRESH , 27 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLBIE_CNT_THRESH ); REG64_FLD( EQ_NCU_MODE_REG_TLBIE_CNT_THRESH_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLBIE_CNT_THRESH_LEN ); REG64_FLD( EQ_NCU_MODE_REG_TLBIE_CNT_WT4TX_CORE_EN , 35 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLBIE_CNT_WT4TX_CORE_EN ); REG64_FLD( EQ_NCU_MODE_REG_TLB_CHK_WAIT_DEC , 36 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLB_CHK_WAIT_DEC ); REG64_FLD( EQ_NCU_MODE_REG_TLB_CHK_WAIT_DEC_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLB_CHK_WAIT_DEC_LEN ); REG64_FLD( EX_NCU_MODE_REG_HTM_QUEUE_LIMIT , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_HTM_QUEUE_LIMIT ); REG64_FLD( EX_NCU_MODE_REG_HTM_QUEUE_LIMIT_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_HTM_QUEUE_LIMIT_LEN ); REG64_FLD( EX_NCU_MODE_REG_TRASH_EN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRASH_EN ); REG64_FLD( EX_NCU_MODE_REG_FENCE_TLBIE , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FENCE_TLBIE ); REG64_FLD( EX_NCU_MODE_REG_DROP_PRIORITY_MASK , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DROP_PRIORITY_MASK ); REG64_FLD( EX_NCU_MODE_REG_DROP_PRIORITY_MASK_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DROP_PRIORITY_MASK_LEN ); REG64_FLD( EX_NCU_MODE_REG_TLBI_GROUP_PUMP_EN , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLBI_GROUP_PUMP_EN ); REG64_FLD( EX_NCU_MODE_REG_SLBI_GROUP_PUMP_EN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SLBI_GROUP_PUMP_EN ); REG64_FLD( EX_NCU_MODE_REG_SYSMAP_SM_NOT_LG_SEL , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SYSMAP_SM_NOT_LG_SEL ); REG64_FLD( EX_NCU_MODE_REG_TLBIE_PACING_CNT_EN , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLBIE_PACING_CNT_EN ); REG64_FLD( EX_NCU_MODE_REG_TLBIE_DEC_RATE , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLBIE_DEC_RATE ); REG64_FLD( EX_NCU_MODE_REG_TLBIE_DEC_RATE_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLBIE_DEC_RATE_LEN ); REG64_FLD( EX_NCU_MODE_REG_TLBIE_INC_RATE , 19 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLBIE_INC_RATE ); REG64_FLD( EX_NCU_MODE_REG_TLBIE_INC_RATE_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLBIE_INC_RATE_LEN ); REG64_FLD( EX_NCU_MODE_REG_TLBIE_CNT_THRESH , 27 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLBIE_CNT_THRESH ); REG64_FLD( EX_NCU_MODE_REG_TLBIE_CNT_THRESH_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLBIE_CNT_THRESH_LEN ); REG64_FLD( EX_NCU_MODE_REG_TLBIE_CNT_WT4TX_CORE_EN , 35 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLBIE_CNT_WT4TX_CORE_EN ); REG64_FLD( EX_NCU_MODE_REG_TLB_CHK_WAIT_DEC , 36 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLB_CHK_WAIT_DEC ); REG64_FLD( EX_NCU_MODE_REG_TLB_CHK_WAIT_DEC_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLB_CHK_WAIT_DEC_LEN ); REG64_FLD( EQ_NCU_MODE_REG2_HANG_POLL_PULSE_DIV , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_HANG_POLL_PULSE_DIV ); REG64_FLD( EQ_NCU_MODE_REG2_HANG_POLL_PULSE_DIV_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_HANG_POLL_PULSE_DIV_LEN ); REG64_FLD( EQ_NCU_MODE_REG2_MASTER_CP_DATA_POLL_PULSE_DIV , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASTER_CP_DATA_POLL_PULSE_DIV ); REG64_FLD( EQ_NCU_MODE_REG2_MASTER_CP_DATA_POLL_PULSE_DIV_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASTER_CP_DATA_POLL_PULSE_DIV_LEN ); REG64_FLD( EQ_NCU_MODE_REG2_TLB_SNOOP_DATA_POLL_PULSE_DIV , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLB_SNOOP_DATA_POLL_PULSE_DIV ); REG64_FLD( EQ_NCU_MODE_REG2_TLB_SNOOP_DATA_POLL_PULSE_DIV_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLB_SNOOP_DATA_POLL_PULSE_DIV_LEN ); REG64_FLD( EQ_NCU_MODE_REG2_TLB_STG1_HANG_POLL_PULSE_DIV , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLB_STG1_HANG_POLL_PULSE_DIV ); REG64_FLD( EQ_NCU_MODE_REG2_TLB_STG1_HANG_POLL_PULSE_DIV_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLB_STG1_HANG_POLL_PULSE_DIV_LEN ); REG64_FLD( EQ_NCU_MODE_REG2_TLB_STG2_HANG_POLL_PULSE_DIV , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLB_STG2_HANG_POLL_PULSE_DIV ); REG64_FLD( EQ_NCU_MODE_REG2_TLB_STG2_HANG_POLL_PULSE_DIV_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLB_STG2_HANG_POLL_PULSE_DIV_LEN ); REG64_FLD( EQ_NCU_MODE_REG2_MASTER_TLB_DATA_POLL_PULSE_DIV , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASTER_TLB_DATA_POLL_PULSE_DIV ); REG64_FLD( EQ_NCU_MODE_REG2_MASTER_TLB_DATA_POLL_PULSE_DIV_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASTER_TLB_DATA_POLL_PULSE_DIV_LEN ); REG64_FLD( EX_NCU_MODE_REG2_HANG_POLL_PULSE_DIV , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_HANG_POLL_PULSE_DIV ); REG64_FLD( EX_NCU_MODE_REG2_HANG_POLL_PULSE_DIV_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_HANG_POLL_PULSE_DIV_LEN ); REG64_FLD( EX_NCU_MODE_REG2_MASTER_CP_DATA_POLL_PULSE_DIV , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASTER_CP_DATA_POLL_PULSE_DIV ); REG64_FLD( EX_NCU_MODE_REG2_MASTER_CP_DATA_POLL_PULSE_DIV_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASTER_CP_DATA_POLL_PULSE_DIV_LEN ); REG64_FLD( EX_NCU_MODE_REG2_TLB_SNOOP_DATA_POLL_PULSE_DIV , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLB_SNOOP_DATA_POLL_PULSE_DIV ); REG64_FLD( EX_NCU_MODE_REG2_TLB_SNOOP_DATA_POLL_PULSE_DIV_LEN , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLB_SNOOP_DATA_POLL_PULSE_DIV_LEN ); REG64_FLD( EX_NCU_MODE_REG2_TLB_STG1_HANG_POLL_PULSE_DIV , 18 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLB_STG1_HANG_POLL_PULSE_DIV ); REG64_FLD( EX_NCU_MODE_REG2_TLB_STG1_HANG_POLL_PULSE_DIV_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLB_STG1_HANG_POLL_PULSE_DIV_LEN ); REG64_FLD( EX_NCU_MODE_REG2_TLB_STG2_HANG_POLL_PULSE_DIV , 22 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLB_STG2_HANG_POLL_PULSE_DIV ); REG64_FLD( EX_NCU_MODE_REG2_TLB_STG2_HANG_POLL_PULSE_DIV_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLB_STG2_HANG_POLL_PULSE_DIV_LEN ); REG64_FLD( EX_NCU_MODE_REG2_MASTER_TLB_DATA_POLL_PULSE_DIV , 26 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASTER_TLB_DATA_POLL_PULSE_DIV ); REG64_FLD( EX_NCU_MODE_REG2_MASTER_TLB_DATA_POLL_PULSE_DIV_LEN , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASTER_TLB_DATA_POLL_PULSE_DIV_LEN ); REG64_FLD( EQ_NCU_MODE_REG3_TLBIE_STALL_EN , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLBIE_STALL_EN ); REG64_FLD( EQ_NCU_MODE_REG3_TLBIE_STALL_THRESHOLD , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLBIE_STALL_THRESHOLD ); REG64_FLD( EQ_NCU_MODE_REG3_TLBIE_STALL_THRESHOLD_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLBIE_STALL_THRESHOLD_LEN ); REG64_FLD( EQ_NCU_MODE_REG3_TLBIE_STALL_CMPLT_CNT , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLBIE_STALL_CMPLT_CNT ); REG64_FLD( EQ_NCU_MODE_REG3_TLBIE_STALL_CMPLT_CNT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLBIE_STALL_CMPLT_CNT_LEN ); REG64_FLD( EQ_NCU_MODE_REG3_TLBIE_STALL_DELAY_CNT , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLBIE_STALL_DELAY_CNT ); REG64_FLD( EQ_NCU_MODE_REG3_TLBIE_STALL_DELAY_CNT_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TLBIE_STALL_DELAY_CNT_LEN ); REG64_FLD( EX_NCU_MODE_REG3_TLBIE_STALL_EN , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLBIE_STALL_EN ); REG64_FLD( EX_NCU_MODE_REG3_TLBIE_STALL_THRESHOLD , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLBIE_STALL_THRESHOLD ); REG64_FLD( EX_NCU_MODE_REG3_TLBIE_STALL_THRESHOLD_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLBIE_STALL_THRESHOLD_LEN ); REG64_FLD( EX_NCU_MODE_REG3_TLBIE_STALL_CMPLT_CNT , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLBIE_STALL_CMPLT_CNT ); REG64_FLD( EX_NCU_MODE_REG3_TLBIE_STALL_CMPLT_CNT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLBIE_STALL_CMPLT_CNT_LEN ); REG64_FLD( EX_NCU_MODE_REG3_TLBIE_STALL_DELAY_CNT , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLBIE_STALL_DELAY_CNT ); REG64_FLD( EX_NCU_MODE_REG3_TLBIE_STALL_DELAY_CNT_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TLBIE_STALL_DELAY_CNT_LEN ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY8_VALID , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY8_VALID ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY8_ID , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY8_ID ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY8_ID_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY8_ID_LEN ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY7_VALID , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY7_VALID ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY7_ID , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY7_ID ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY7_ID_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY7_ID_LEN ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY6_VALID , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY6_VALID ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY6_ID , 27 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY6_ID ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY6_ID_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY6_ID_LEN ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY5_VALID , 39 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY5_VALID ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY5_ID , 40 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY5_ID ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG0_DELAY5_ID_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY5_ID_LEN ); REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY8_VALID , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY8_VALID ); REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY8_ID , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY8_ID ); REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY8_ID_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY8_ID_LEN ); REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY7_VALID , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY7_VALID ); REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY7_ID , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY7_ID ); REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY7_ID_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY7_ID_LEN ); REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY6_VALID , 26 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY6_VALID ); REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY6_ID , 27 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY6_ID ); REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY6_ID_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY6_ID_LEN ); REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY5_VALID , 39 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY5_VALID ); REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY5_ID , 40 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY5_ID ); REG64_FLD( EX_NCU_SLOW_LPAR_REG0_DELAY5_ID_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY5_ID_LEN ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY4_VALID , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY4_VALID ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY4_ID , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY4_ID ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY4_ID_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY4_ID_LEN ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY3_VALID , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY3_VALID ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY3_ID , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY3_ID ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY3_ID_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY3_ID_LEN ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY2_VALID , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY2_VALID ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY2_ID , 27 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY2_ID ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY2_ID_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY2_ID_LEN ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY1_VALID , 39 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY1_VALID ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY1_ID , 40 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY1_ID ); REG64_FLD( EQ_NCU_SLOW_LPAR_REG1_DELAY1_ID_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DELAY1_ID_LEN ); REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY4_VALID , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY4_VALID ); REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY4_ID , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY4_ID ); REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY4_ID_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY4_ID_LEN ); REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY3_VALID , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY3_VALID ); REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY3_ID , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY3_ID ); REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY3_ID_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY3_ID_LEN ); REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY2_VALID , 26 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY2_VALID ); REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY2_ID , 27 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY2_ID ); REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY2_ID_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY2_ID_LEN ); REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY1_VALID , 39 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY1_VALID ); REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY1_ID , 40 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY1_ID ); REG64_FLD( EX_NCU_SLOW_LPAR_REG1_DELAY1_ID_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DELAY1_ID_LEN ); REG64_FLD( EQ_NCU_SPEC_BAR_REG_EN , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EN ); REG64_FLD( EQ_NCU_SPEC_BAR_REG_256K , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_256K ); REG64_FLD( EQ_NCU_SPEC_BAR_REG_ADDR , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ADDR ); REG64_FLD( EQ_NCU_SPEC_BAR_REG_ADDR_LEN , 42 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ADDR_LEN ); REG64_FLD( EX_NCU_SPEC_BAR_REG_EN , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EN ); REG64_FLD( EX_NCU_SPEC_BAR_REG_256K , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_256K ); REG64_FLD( EX_NCU_SPEC_BAR_REG_ADDR , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ADDR ); REG64_FLD( EX_NCU_SPEC_BAR_REG_ADDR_LEN , 42 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ADDR_LEN ); REG64_FLD( EQ_NCU_STATUS_REG_CORE0_REQ_ACTIVE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CORE0_REQ_ACTIVE ); REG64_FLD( EQ_NCU_STATUS_REG_CORE1_REQ_ACTIVE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CORE1_REQ_ACTIVE ); REG64_FLD( EQ_NCU_STATUS_REG_CORE_OR_SNP_REQ_ACTIVE , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CORE_OR_SNP_REQ_ACTIVE ); REG64_FLD( EQ_NCU_STATUS_REG_ANY_REQ_ACTIVE , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ANY_REQ_ACTIVE ); REG64_FLD( EX_NCU_STATUS_REG_CORE0_REQ_ACTIVE , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CORE0_REQ_ACTIVE ); REG64_FLD( EX_NCU_STATUS_REG_CORE1_REQ_ACTIVE , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CORE1_REQ_ACTIVE ); REG64_FLD( EX_NCU_STATUS_REG_CORE_OR_SNP_REQ_ACTIVE , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CORE_OR_SNP_REQ_ACTIVE ); REG64_FLD( EX_NCU_STATUS_REG_ANY_REQ_ACTIVE , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ANY_REQ_ACTIVE ); REG64_FLD( EQ_NET_CTRL0_CHIPLET_ENABLE , 0 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_CHIPLET_ENABLE ); REG64_FLD( EQ_NET_CTRL0_PCB_EP_RESET , 1 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_PCB_EP_RESET ); REG64_FLD( EQ_NET_CTRL0_CLK_ASYNC_RESET , 2 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_CLK_ASYNC_RESET ); REG64_FLD( EQ_NET_CTRL0_PLL_TEST_EN , 3 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_PLL_TEST_EN ); REG64_FLD( EQ_NET_CTRL0_PLL_RESET , 4 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_PLL_RESET ); REG64_FLD( EQ_NET_CTRL0_PLL_BYPASS , 5 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_PLL_BYPASS ); REG64_FLD( EQ_NET_CTRL0_VITAL_SCAN , 6 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_VITAL_SCAN ); REG64_FLD( EQ_NET_CTRL0_VITAL_SCAN_IN , 7 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_VITAL_SCAN_IN ); REG64_FLD( EQ_NET_CTRL0_VITAL_PHASE , 8 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_VITAL_PHASE ); REG64_FLD( EQ_NET_CTRL0_FLUSH_ALIGN_OVR , 9 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_FLUSH_ALIGN_OVR ); REG64_FLD( EQ_NET_CTRL0_VITAL_AL , 10 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_VITAL_AL ); REG64_FLD( EQ_NET_CTRL0_ACT_DIS , 11 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_ACT_DIS ); REG64_FLD( EQ_NET_CTRL0_MPW1 , 12 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_MPW1 ); REG64_FLD( EQ_NET_CTRL0_MPW2 , 13 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_MPW2 ); REG64_FLD( EQ_NET_CTRL0_MPW3 , 14 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_MPW3 ); REG64_FLD( EQ_NET_CTRL0_DELAY_LCLKR , 15 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_DELAY_LCLKR ); REG64_FLD( EQ_NET_CTRL0_VITAL_THOLD , 16 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_VITAL_THOLD ); REG64_FLD( EQ_NET_CTRL0_FLUSH_SCAN_N , 17 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_FLUSH_SCAN_N ); REG64_FLD( EQ_NET_CTRL0_FENCE_EN , 18 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_FENCE_EN ); REG64_FLD( EQ_NET_CTRL0_CPLT_RCTRL , 19 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_CPLT_RCTRL ); REG64_FLD( EQ_NET_CTRL0_CPLT_DCTRL , 20 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_CPLT_DCTRL ); REG64_FLD( EQ_NET_CTRL0_ADJ_FUNC_CLKSEL , 22 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_ADJ_FUNC_CLKSEL ); REG64_FLD( EQ_NET_CTRL0_TP_FENCE_PCB , 25 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_TP_FENCE_PCB ); REG64_FLD( EQ_NET_CTRL0_LVLTRANS_FENCE , 26 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_LVLTRANS_FENCE ); REG64_FLD( EQ_NET_CTRL0_ARRAY_WRITE_ASSIST_EN , 27 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_ARRAY_WRITE_ASSIST_EN ); REG64_FLD( EQ_NET_CTRL0_HTB_INTEST , 28 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_HTB_INTEST ); REG64_FLD( EQ_NET_CTRL0_HTB_EXTEST , 29 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_HTB_EXTEST ); REG64_FLD( EQ_NET_CTRL0_PM_ACCESS , 30 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_PM_ACCESS ); REG64_FLD( EQ_NET_CTRL0_PLLFORCE_OUT_EN , 31 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_PLLFORCE_OUT_EN ); REG64_FLD( EX_NET_CTRL0_CHIPLET_ENABLE , 0 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_CHIPLET_ENABLE ); REG64_FLD( EX_NET_CTRL0_PCB_EP_RESET , 1 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_PCB_EP_RESET ); REG64_FLD( EX_NET_CTRL0_CLK_ASYNC_RESET , 2 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_CLK_ASYNC_RESET ); REG64_FLD( EX_NET_CTRL0_PLL_TEST_EN , 3 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_PLL_TEST_EN ); REG64_FLD( EX_NET_CTRL0_PLL_RESET , 4 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_PLL_RESET ); REG64_FLD( EX_NET_CTRL0_PLL_BYPASS , 5 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_PLL_BYPASS ); REG64_FLD( EX_NET_CTRL0_VITAL_SCAN , 6 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_VITAL_SCAN ); REG64_FLD( EX_NET_CTRL0_VITAL_SCAN_IN , 7 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_VITAL_SCAN_IN ); REG64_FLD( EX_NET_CTRL0_VITAL_PHASE , 8 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_VITAL_PHASE ); REG64_FLD( EX_NET_CTRL0_FLUSH_ALIGN_OVR , 9 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_FLUSH_ALIGN_OVR ); REG64_FLD( EX_NET_CTRL0_VITAL_AL , 10 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_VITAL_AL ); REG64_FLD( EX_NET_CTRL0_ACT_DIS , 11 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_ACT_DIS ); REG64_FLD( EX_NET_CTRL0_MPW1 , 12 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_MPW1 ); REG64_FLD( EX_NET_CTRL0_MPW2 , 13 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_MPW2 ); REG64_FLD( EX_NET_CTRL0_MPW3 , 14 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_MPW3 ); REG64_FLD( EX_NET_CTRL0_DELAY_LCLKR , 15 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_DELAY_LCLKR ); REG64_FLD( EX_NET_CTRL0_VITAL_THOLD , 16 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_VITAL_THOLD ); REG64_FLD( EX_NET_CTRL0_FLUSH_SCAN_N , 17 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_FLUSH_SCAN_N ); REG64_FLD( EX_NET_CTRL0_FENCE_EN , 18 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_FENCE_EN ); REG64_FLD( EX_NET_CTRL0_CPLT_RCTRL , 19 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_CPLT_RCTRL ); REG64_FLD( EX_NET_CTRL0_CPLT_DCTRL , 20 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_CPLT_DCTRL ); REG64_FLD( EX_NET_CTRL0_ADJ_FUNC_CLKSEL , 22 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_ADJ_FUNC_CLKSEL ); REG64_FLD( EX_NET_CTRL0_TP_FENCE_PCB , 25 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_TP_FENCE_PCB ); REG64_FLD( EX_NET_CTRL0_LVLTRANS_FENCE , 26 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_LVLTRANS_FENCE ); REG64_FLD( EX_NET_CTRL0_ARRAY_WRITE_ASSIST_EN , 27 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_ARRAY_WRITE_ASSIST_EN ); REG64_FLD( EX_NET_CTRL0_HTB_INTEST , 28 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_HTB_INTEST ); REG64_FLD( EX_NET_CTRL0_HTB_EXTEST , 29 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_HTB_EXTEST ); REG64_FLD( EX_NET_CTRL0_PM_ACCESS , 30 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_PM_ACCESS ); REG64_FLD( EX_NET_CTRL0_PLLFORCE_OUT_EN , 31 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_PLLFORCE_OUT_EN ); REG64_FLD( C_NET_CTRL0_CHIPLET_ENABLE , 0 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_CHIPLET_ENABLE ); REG64_FLD( C_NET_CTRL0_PCB_EP_RESET , 1 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_PCB_EP_RESET ); REG64_FLD( C_NET_CTRL0_CLK_ASYNC_RESET , 2 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_CLK_ASYNC_RESET ); REG64_FLD( C_NET_CTRL0_PLL_TEST_EN , 3 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_PLL_TEST_EN ); REG64_FLD( C_NET_CTRL0_PLL_RESET , 4 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_PLL_RESET ); REG64_FLD( C_NET_CTRL0_PLL_BYPASS , 5 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_PLL_BYPASS ); REG64_FLD( C_NET_CTRL0_VITAL_SCAN , 6 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_VITAL_SCAN ); REG64_FLD( C_NET_CTRL0_VITAL_SCAN_IN , 7 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_VITAL_SCAN_IN ); REG64_FLD( C_NET_CTRL0_VITAL_PHASE , 8 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_VITAL_PHASE ); REG64_FLD( C_NET_CTRL0_FLUSH_ALIGN_OVR , 9 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_FLUSH_ALIGN_OVR ); REG64_FLD( C_NET_CTRL0_VITAL_AL , 10 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_VITAL_AL ); REG64_FLD( C_NET_CTRL0_ACT_DIS , 11 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_ACT_DIS ); REG64_FLD( C_NET_CTRL0_MPW1 , 12 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_MPW1 ); REG64_FLD( C_NET_CTRL0_MPW2 , 13 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_MPW2 ); REG64_FLD( C_NET_CTRL0_MPW3 , 14 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_MPW3 ); REG64_FLD( C_NET_CTRL0_DELAY_LCLKR , 15 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_DELAY_LCLKR ); REG64_FLD( C_NET_CTRL0_VITAL_THOLD , 16 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_VITAL_THOLD ); REG64_FLD( C_NET_CTRL0_FLUSH_SCAN_N , 17 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_FLUSH_SCAN_N ); REG64_FLD( C_NET_CTRL0_FENCE_EN , 18 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_FENCE_EN ); REG64_FLD( C_NET_CTRL0_CPLT_RCTRL , 19 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_CPLT_RCTRL ); REG64_FLD( C_NET_CTRL0_CPLT_DCTRL , 20 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_CPLT_DCTRL ); REG64_FLD( C_NET_CTRL0_ADJ_FUNC_CLKSEL , 22 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_ADJ_FUNC_CLKSEL ); REG64_FLD( C_NET_CTRL0_TP_FENCE_PCB , 25 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_TP_FENCE_PCB ); REG64_FLD( C_NET_CTRL0_LVLTRANS_FENCE , 26 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_LVLTRANS_FENCE ); REG64_FLD( C_NET_CTRL0_ARRAY_WRITE_ASSIST_EN , 27 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_ARRAY_WRITE_ASSIST_EN ); REG64_FLD( C_NET_CTRL0_HTB_INTEST , 28 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_HTB_INTEST ); REG64_FLD( C_NET_CTRL0_HTB_EXTEST , 29 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_HTB_EXTEST ); REG64_FLD( C_NET_CTRL0_PM_ACCESS , 30 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_PM_ACCESS ); REG64_FLD( C_NET_CTRL0_PLLFORCE_OUT_EN , 31 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_PLLFORCE_OUT_EN ); REG64_FLD( EQ_NET_CTRL1_PLL_CLKIN_SEL , 0 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_PLL_CLKIN_SEL ); REG64_FLD( EQ_NET_CTRL1_CLK_DCC_BYPASS_EN , 1 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_CLK_DCC_BYPASS_EN ); REG64_FLD( EQ_NET_CTRL1_CLK_PDLY_BYPASS_EN , 2 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PDLY_BYPASS_EN ); REG64_FLD( EQ_NET_CTRL1_CLK_DIV_BYPASS_EN , 3 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_CLK_DIV_BYPASS_EN ); REG64_FLD( EQ_NET_CTRL1_REFCLK_CLKMUX0_SEL , 4 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_REFCLK_CLKMUX0_SEL ); REG64_FLD( EQ_NET_CTRL1_REFCLK_CLKMUX1_SEL , 5 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_REFCLK_CLKMUX1_SEL ); REG64_FLD( EQ_NET_CTRL1_PLL_BNDY_BYPASS_EN , 6 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_PLL_BNDY_BYPASS_EN ); REG64_FLD( EQ_NET_CTRL1_DPLL_TEST_SEL , 8 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_DPLL_TEST_SEL ); REG64_FLD( EQ_NET_CTRL1_DPLL_TEST_SEL_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_DPLL_TEST_SEL_LEN ); REG64_FLD( EQ_NET_CTRL1_SB_STRENGTH , 16 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_SB_STRENGTH ); REG64_FLD( EQ_NET_CTRL1_SB_STRENGTH_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_SB_STRENGTH_LEN ); REG64_FLD( EQ_NET_CTRL1_ASYNC_TYPE , 20 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_ASYNC_TYPE ); REG64_FLD( EQ_NET_CTRL1_ASYNC_OBS , 21 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_ASYNC_OBS ); REG64_FLD( EQ_NET_CTRL1_CPM_CAL_SET , 22 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_CPM_CAL_SET ); REG64_FLD( EQ_NET_CTRL1_SENSEADJ_RESET0 , 23 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_SENSEADJ_RESET0 ); REG64_FLD( EQ_NET_CTRL1_SENSEADJ_RESET1 , 24 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_SENSEADJ_RESET1 ); REG64_FLD( EQ_NET_CTRL1_CLK_PULSE_EN , 25 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_EN ); REG64_FLD( EQ_NET_CTRL1_CLK_PULSE_MODE , 26 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_MODE ); REG64_FLD( EQ_NET_CTRL1_CLK_PULSE_MODE_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_MODE_LEN ); REG64_FLD( EQ_NET_CTRL1_PCB_ACCESS , 28 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_PCB_ACCESS ); REG64_FLD( EQ_NET_CTRL1_PCB_ACCESS_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2_WOR, SH_FLD_PCB_ACCESS_LEN ); REG64_FLD( EX_NET_CTRL1_PLL_CLKIN_SEL , 0 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_PLL_CLKIN_SEL ); REG64_FLD( EX_NET_CTRL1_CLK_DCC_BYPASS_EN , 1 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_CLK_DCC_BYPASS_EN ); REG64_FLD( EX_NET_CTRL1_CLK_PDLY_BYPASS_EN , 2 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PDLY_BYPASS_EN ); REG64_FLD( EX_NET_CTRL1_CLK_DIV_BYPASS_EN , 3 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_CLK_DIV_BYPASS_EN ); REG64_FLD( EX_NET_CTRL1_REFCLK_CLKMUX0_SEL , 4 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_REFCLK_CLKMUX0_SEL ); REG64_FLD( EX_NET_CTRL1_REFCLK_CLKMUX1_SEL , 5 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_REFCLK_CLKMUX1_SEL ); REG64_FLD( EX_NET_CTRL1_PLL_BNDY_BYPASS_EN , 6 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_PLL_BNDY_BYPASS_EN ); REG64_FLD( EX_NET_CTRL1_DPLL_TEST_SEL , 8 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_DPLL_TEST_SEL ); REG64_FLD( EX_NET_CTRL1_DPLL_TEST_SEL_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_DPLL_TEST_SEL_LEN ); REG64_FLD( EX_NET_CTRL1_SB_STRENGTH , 16 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_SB_STRENGTH ); REG64_FLD( EX_NET_CTRL1_SB_STRENGTH_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_SB_STRENGTH_LEN ); REG64_FLD( EX_NET_CTRL1_ASYNC_TYPE , 20 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_ASYNC_TYPE ); REG64_FLD( EX_NET_CTRL1_ASYNC_OBS , 21 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_ASYNC_OBS ); REG64_FLD( EX_NET_CTRL1_CPM_CAL_SET , 22 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_CPM_CAL_SET ); REG64_FLD( EX_NET_CTRL1_SENSEADJ_RESET0 , 23 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_SENSEADJ_RESET0 ); REG64_FLD( EX_NET_CTRL1_SENSEADJ_RESET1 , 24 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_SENSEADJ_RESET1 ); REG64_FLD( EX_NET_CTRL1_CLK_PULSE_EN , 25 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_EN ); REG64_FLD( EX_NET_CTRL1_CLK_PULSE_MODE , 26 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_MODE ); REG64_FLD( EX_NET_CTRL1_CLK_PULSE_MODE_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_MODE_LEN ); REG64_FLD( EX_NET_CTRL1_PCB_ACCESS , 28 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_PCB_ACCESS ); REG64_FLD( EX_NET_CTRL1_PCB_ACCESS_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2_WOR, SH_FLD_PCB_ACCESS_LEN ); REG64_FLD( C_NET_CTRL1_PLL_CLKIN_SEL , 0 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_PLL_CLKIN_SEL ); REG64_FLD( C_NET_CTRL1_CLK_DCC_BYPASS_EN , 1 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_CLK_DCC_BYPASS_EN ); REG64_FLD( C_NET_CTRL1_CLK_PDLY_BYPASS_EN , 2 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PDLY_BYPASS_EN ); REG64_FLD( C_NET_CTRL1_CLK_DIV_BYPASS_EN , 3 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_CLK_DIV_BYPASS_EN ); REG64_FLD( C_NET_CTRL1_REFCLK_CLKMUX0_SEL , 4 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_REFCLK_CLKMUX0_SEL ); REG64_FLD( C_NET_CTRL1_REFCLK_CLKMUX1_SEL , 5 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_REFCLK_CLKMUX1_SEL ); REG64_FLD( C_NET_CTRL1_PLL_BNDY_BYPASS_EN , 6 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_PLL_BNDY_BYPASS_EN ); REG64_FLD( C_NET_CTRL1_DPLL_TEST_SEL , 8 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_DPLL_TEST_SEL ); REG64_FLD( C_NET_CTRL1_DPLL_TEST_SEL_LEN , 8 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_DPLL_TEST_SEL_LEN ); REG64_FLD( C_NET_CTRL1_SB_STRENGTH , 16 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_SB_STRENGTH ); REG64_FLD( C_NET_CTRL1_SB_STRENGTH_LEN , 4 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_SB_STRENGTH_LEN ); REG64_FLD( C_NET_CTRL1_ASYNC_TYPE , 20 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_ASYNC_TYPE ); REG64_FLD( C_NET_CTRL1_ASYNC_OBS , 21 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_ASYNC_OBS ); REG64_FLD( C_NET_CTRL1_CPM_CAL_SET , 22 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_CPM_CAL_SET ); REG64_FLD( C_NET_CTRL1_SENSEADJ_RESET0 , 23 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_SENSEADJ_RESET0 ); REG64_FLD( C_NET_CTRL1_SENSEADJ_RESET1 , 24 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_SENSEADJ_RESET1 ); REG64_FLD( C_NET_CTRL1_CLK_PULSE_EN , 25 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_EN ); REG64_FLD( C_NET_CTRL1_CLK_PULSE_MODE , 26 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_MODE ); REG64_FLD( C_NET_CTRL1_CLK_PULSE_MODE_LEN , 2 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_MODE_LEN ); REG64_FLD( C_NET_CTRL1_PCB_ACCESS , 28 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_PCB_ACCESS ); REG64_FLD( C_NET_CTRL1_PCB_ACCESS_LEN , 4 , SH_UNT_C , SH_ACS_SCOM2_WOR, SH_FLD_PCB_ACCESS_LEN ); REG64_FLD( EX_L2_OCC_SCOMC_MODE_CX , 54 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_MODE_CX ); REG64_FLD( EX_L2_OCC_SCOMC_MODE_CX_LEN , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_MODE_CX_LEN ); REG64_FLD( C_OCC_SCOMC_MODE_CX , 54 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_MODE_CX ); REG64_FLD( C_OCC_SCOMC_MODE_CX_LEN , 7 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_MODE_CX_LEN ); REG64_FLD( EQ_OPCG_ALIGN_INOP , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INOP ); REG64_FLD( EQ_OPCG_ALIGN_INOP_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INOP_LEN ); REG64_FLD( EQ_OPCG_ALIGN_SNOP , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SNOP ); REG64_FLD( EQ_OPCG_ALIGN_SNOP_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SNOP_LEN ); REG64_FLD( EQ_OPCG_ALIGN_ENOP , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENOP ); REG64_FLD( EQ_OPCG_ALIGN_ENOP_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENOP_LEN ); REG64_FLD( EQ_OPCG_ALIGN_INOP_WAIT , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INOP_WAIT ); REG64_FLD( EQ_OPCG_ALIGN_INOP_WAIT_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INOP_WAIT_LEN ); REG64_FLD( EQ_OPCG_ALIGN_SNOP_WAIT , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SNOP_WAIT ); REG64_FLD( EQ_OPCG_ALIGN_SNOP_WAIT_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SNOP_WAIT_LEN ); REG64_FLD( EQ_OPCG_ALIGN_ENOP_WAIT , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENOP_WAIT ); REG64_FLD( EQ_OPCG_ALIGN_ENOP_WAIT_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENOP_WAIT_LEN ); REG64_FLD( EQ_OPCG_ALIGN_INOP_FORCE_SG , 40 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INOP_FORCE_SG ); REG64_FLD( EQ_OPCG_ALIGN_SNOP_FORCE_SG , 41 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SNOP_FORCE_SG ); REG64_FLD( EQ_OPCG_ALIGN_ENOP_FORCE_SG , 42 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENOP_FORCE_SG ); REG64_FLD( EQ_OPCG_ALIGN_NO_WAIT_ON_CLK_CMD , 43 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NO_WAIT_ON_CLK_CMD ); REG64_FLD( EQ_OPCG_ALIGN_SOURCE_SELECT , 44 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SOURCE_SELECT ); REG64_FLD( EQ_OPCG_ALIGN_SOURCE_SELECT_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SOURCE_SELECT_LEN ); REG64_FLD( EQ_OPCG_ALIGN_UNUSED46 , 46 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED46 ); REG64_FLD( EQ_OPCG_ALIGN_SCAN_RATIO , 47 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SCAN_RATIO ); REG64_FLD( EQ_OPCG_ALIGN_SCAN_RATIO_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SCAN_RATIO_LEN ); REG64_FLD( EQ_OPCG_ALIGN_WAIT_CYCLES , 52 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES ); REG64_FLD( EQ_OPCG_ALIGN_WAIT_CYCLES_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES_LEN ); REG64_FLD( EX_OPCG_ALIGN_INOP , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INOP ); REG64_FLD( EX_OPCG_ALIGN_INOP_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INOP_LEN ); REG64_FLD( EX_OPCG_ALIGN_SNOP , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SNOP ); REG64_FLD( EX_OPCG_ALIGN_SNOP_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SNOP_LEN ); REG64_FLD( EX_OPCG_ALIGN_ENOP , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ENOP ); REG64_FLD( EX_OPCG_ALIGN_ENOP_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ENOP_LEN ); REG64_FLD( EX_OPCG_ALIGN_INOP_WAIT , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INOP_WAIT ); REG64_FLD( EX_OPCG_ALIGN_INOP_WAIT_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INOP_WAIT_LEN ); REG64_FLD( EX_OPCG_ALIGN_SNOP_WAIT , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SNOP_WAIT ); REG64_FLD( EX_OPCG_ALIGN_SNOP_WAIT_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SNOP_WAIT_LEN ); REG64_FLD( EX_OPCG_ALIGN_ENOP_WAIT , 32 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ENOP_WAIT ); REG64_FLD( EX_OPCG_ALIGN_ENOP_WAIT_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ENOP_WAIT_LEN ); REG64_FLD( EX_OPCG_ALIGN_INOP_FORCE_SG , 40 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INOP_FORCE_SG ); REG64_FLD( EX_OPCG_ALIGN_SNOP_FORCE_SG , 41 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SNOP_FORCE_SG ); REG64_FLD( EX_OPCG_ALIGN_ENOP_FORCE_SG , 42 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ENOP_FORCE_SG ); REG64_FLD( EX_OPCG_ALIGN_NO_WAIT_ON_CLK_CMD , 43 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NO_WAIT_ON_CLK_CMD ); REG64_FLD( EX_OPCG_ALIGN_SOURCE_SELECT , 44 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SOURCE_SELECT ); REG64_FLD( EX_OPCG_ALIGN_SOURCE_SELECT_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SOURCE_SELECT_LEN ); REG64_FLD( EX_OPCG_ALIGN_UNUSED46 , 46 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED46 ); REG64_FLD( EX_OPCG_ALIGN_SCAN_RATIO , 47 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SCAN_RATIO ); REG64_FLD( EX_OPCG_ALIGN_SCAN_RATIO_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SCAN_RATIO_LEN ); REG64_FLD( EX_OPCG_ALIGN_WAIT_CYCLES , 52 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES ); REG64_FLD( EX_OPCG_ALIGN_WAIT_CYCLES_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES_LEN ); REG64_FLD( C_OPCG_ALIGN_INOP , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INOP ); REG64_FLD( C_OPCG_ALIGN_INOP_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INOP_LEN ); REG64_FLD( C_OPCG_ALIGN_SNOP , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SNOP ); REG64_FLD( C_OPCG_ALIGN_SNOP_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SNOP_LEN ); REG64_FLD( C_OPCG_ALIGN_ENOP , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ENOP ); REG64_FLD( C_OPCG_ALIGN_ENOP_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ENOP_LEN ); REG64_FLD( C_OPCG_ALIGN_INOP_WAIT , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INOP_WAIT ); REG64_FLD( C_OPCG_ALIGN_INOP_WAIT_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INOP_WAIT_LEN ); REG64_FLD( C_OPCG_ALIGN_SNOP_WAIT , 20 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SNOP_WAIT ); REG64_FLD( C_OPCG_ALIGN_SNOP_WAIT_LEN , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SNOP_WAIT_LEN ); REG64_FLD( C_OPCG_ALIGN_ENOP_WAIT , 32 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ENOP_WAIT ); REG64_FLD( C_OPCG_ALIGN_ENOP_WAIT_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ENOP_WAIT_LEN ); REG64_FLD( C_OPCG_ALIGN_INOP_FORCE_SG , 40 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INOP_FORCE_SG ); REG64_FLD( C_OPCG_ALIGN_SNOP_FORCE_SG , 41 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SNOP_FORCE_SG ); REG64_FLD( C_OPCG_ALIGN_ENOP_FORCE_SG , 42 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ENOP_FORCE_SG ); REG64_FLD( C_OPCG_ALIGN_NO_WAIT_ON_CLK_CMD , 43 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_NO_WAIT_ON_CLK_CMD ); REG64_FLD( C_OPCG_ALIGN_SOURCE_SELECT , 44 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SOURCE_SELECT ); REG64_FLD( C_OPCG_ALIGN_SOURCE_SELECT_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SOURCE_SELECT_LEN ); REG64_FLD( C_OPCG_ALIGN_UNUSED46 , 46 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED46 ); REG64_FLD( C_OPCG_ALIGN_SCAN_RATIO , 47 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SCAN_RATIO ); REG64_FLD( C_OPCG_ALIGN_SCAN_RATIO_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SCAN_RATIO_LEN ); REG64_FLD( C_OPCG_ALIGN_WAIT_CYCLES , 52 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES ); REG64_FLD( C_OPCG_ALIGN_WAIT_CYCLES_LEN , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES_LEN ); REG64_FLD( EQ_OPCG_CAPT1_COUNT , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COUNT ); REG64_FLD( EQ_OPCG_CAPT1_COUNT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COUNT_LEN ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_01 , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_01 ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_01_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_01_LEN ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_02 , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_02 ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_02_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_02_LEN ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_03 , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_03 ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_03_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_03_LEN ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_04 , 19 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_04 ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_04_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_04_LEN ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_05 , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_05 ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_05_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_05_LEN ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_06 , 29 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_06 ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_06_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_06_LEN ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_07 , 34 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_07 ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_07_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_07_LEN ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_08 , 39 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_08 ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_08_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_08_LEN ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_09 , 44 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_09 ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_09_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_09_LEN ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_10 , 49 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_10 ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_10_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_10_LEN ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_11 , 54 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_11 ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_11_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_11_LEN ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_12 , 59 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_12 ); REG64_FLD( EQ_OPCG_CAPT1_SEQ_12_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_12_LEN ); REG64_FLD( EX_OPCG_CAPT1_COUNT , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COUNT ); REG64_FLD( EX_OPCG_CAPT1_COUNT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COUNT_LEN ); REG64_FLD( EX_OPCG_CAPT1_SEQ_01 , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_01 ); REG64_FLD( EX_OPCG_CAPT1_SEQ_01_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_01_LEN ); REG64_FLD( EX_OPCG_CAPT1_SEQ_02 , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_02 ); REG64_FLD( EX_OPCG_CAPT1_SEQ_02_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_02_LEN ); REG64_FLD( EX_OPCG_CAPT1_SEQ_03 , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_03 ); REG64_FLD( EX_OPCG_CAPT1_SEQ_03_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_03_LEN ); REG64_FLD( EX_OPCG_CAPT1_SEQ_04 , 19 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_04 ); REG64_FLD( EX_OPCG_CAPT1_SEQ_04_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_04_LEN ); REG64_FLD( EX_OPCG_CAPT1_SEQ_05 , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_05 ); REG64_FLD( EX_OPCG_CAPT1_SEQ_05_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_05_LEN ); REG64_FLD( EX_OPCG_CAPT1_SEQ_06 , 29 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_06 ); REG64_FLD( EX_OPCG_CAPT1_SEQ_06_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_06_LEN ); REG64_FLD( EX_OPCG_CAPT1_SEQ_07 , 34 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_07 ); REG64_FLD( EX_OPCG_CAPT1_SEQ_07_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_07_LEN ); REG64_FLD( EX_OPCG_CAPT1_SEQ_08 , 39 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_08 ); REG64_FLD( EX_OPCG_CAPT1_SEQ_08_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_08_LEN ); REG64_FLD( EX_OPCG_CAPT1_SEQ_09 , 44 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_09 ); REG64_FLD( EX_OPCG_CAPT1_SEQ_09_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_09_LEN ); REG64_FLD( EX_OPCG_CAPT1_SEQ_10 , 49 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_10 ); REG64_FLD( EX_OPCG_CAPT1_SEQ_10_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_10_LEN ); REG64_FLD( EX_OPCG_CAPT1_SEQ_11 , 54 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_11 ); REG64_FLD( EX_OPCG_CAPT1_SEQ_11_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_11_LEN ); REG64_FLD( EX_OPCG_CAPT1_SEQ_12 , 59 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_12 ); REG64_FLD( EX_OPCG_CAPT1_SEQ_12_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_12_LEN ); REG64_FLD( C_OPCG_CAPT1_COUNT , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COUNT ); REG64_FLD( C_OPCG_CAPT1_COUNT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COUNT_LEN ); REG64_FLD( C_OPCG_CAPT1_SEQ_01 , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_01 ); REG64_FLD( C_OPCG_CAPT1_SEQ_01_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_01_LEN ); REG64_FLD( C_OPCG_CAPT1_SEQ_02 , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_02 ); REG64_FLD( C_OPCG_CAPT1_SEQ_02_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_02_LEN ); REG64_FLD( C_OPCG_CAPT1_SEQ_03 , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_03 ); REG64_FLD( C_OPCG_CAPT1_SEQ_03_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_03_LEN ); REG64_FLD( C_OPCG_CAPT1_SEQ_04 , 19 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_04 ); REG64_FLD( C_OPCG_CAPT1_SEQ_04_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_04_LEN ); REG64_FLD( C_OPCG_CAPT1_SEQ_05 , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_05 ); REG64_FLD( C_OPCG_CAPT1_SEQ_05_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_05_LEN ); REG64_FLD( C_OPCG_CAPT1_SEQ_06 , 29 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_06 ); REG64_FLD( C_OPCG_CAPT1_SEQ_06_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_06_LEN ); REG64_FLD( C_OPCG_CAPT1_SEQ_07 , 34 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_07 ); REG64_FLD( C_OPCG_CAPT1_SEQ_07_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_07_LEN ); REG64_FLD( C_OPCG_CAPT1_SEQ_08 , 39 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_08 ); REG64_FLD( C_OPCG_CAPT1_SEQ_08_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_08_LEN ); REG64_FLD( C_OPCG_CAPT1_SEQ_09 , 44 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_09 ); REG64_FLD( C_OPCG_CAPT1_SEQ_09_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_09_LEN ); REG64_FLD( C_OPCG_CAPT1_SEQ_10 , 49 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_10 ); REG64_FLD( C_OPCG_CAPT1_SEQ_10_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_10_LEN ); REG64_FLD( C_OPCG_CAPT1_SEQ_11 , 54 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_11 ); REG64_FLD( C_OPCG_CAPT1_SEQ_11_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_11_LEN ); REG64_FLD( C_OPCG_CAPT1_SEQ_12 , 59 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_12 ); REG64_FLD( C_OPCG_CAPT1_SEQ_12_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_12_LEN ); REG64_FLD( EQ_OPCG_CAPT2_UNUSED , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( EQ_OPCG_CAPT2_UNUSED_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_13_01EVEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_13_01EVEN ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_13_01EVEN_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_13_01EVEN_LEN ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_14_01ODD , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_14_01ODD ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_14_01ODD_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_14_01ODD_LEN ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_15_02EVEN , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_15_02EVEN ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_15_02EVEN_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_15_02EVEN_LEN ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_16_02ODD , 19 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_16_02ODD ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_16_02ODD_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_16_02ODD_LEN ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_17_03EVEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_17_03EVEN ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_17_03EVEN_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_17_03EVEN_LEN ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_18_03ODD , 29 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_18_03ODD ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_18_03ODD_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_18_03ODD_LEN ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_19_04EVEN , 34 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_19_04EVEN ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_19_04EVEN_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_19_04EVEN_LEN ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_20_04ODD , 39 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_20_04ODD ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_20_04ODD_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_20_04ODD_LEN ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_21_05EVEN , 44 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_21_05EVEN ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_21_05EVEN_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_21_05EVEN_LEN ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_22_05ODD , 49 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_22_05ODD ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_22_05ODD_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_22_05ODD_LEN ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_23_06EVEN , 54 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_23_06EVEN ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_23_06EVEN_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_23_06EVEN_LEN ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_24_06ODD , 59 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_24_06ODD ); REG64_FLD( EQ_OPCG_CAPT2_SEQ_24_06ODD_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_24_06ODD_LEN ); REG64_FLD( EX_OPCG_CAPT2_UNUSED , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( EX_OPCG_CAPT2_UNUSED_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( EX_OPCG_CAPT2_SEQ_13_01EVEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_13_01EVEN ); REG64_FLD( EX_OPCG_CAPT2_SEQ_13_01EVEN_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_13_01EVEN_LEN ); REG64_FLD( EX_OPCG_CAPT2_SEQ_14_01ODD , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_14_01ODD ); REG64_FLD( EX_OPCG_CAPT2_SEQ_14_01ODD_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_14_01ODD_LEN ); REG64_FLD( EX_OPCG_CAPT2_SEQ_15_02EVEN , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_15_02EVEN ); REG64_FLD( EX_OPCG_CAPT2_SEQ_15_02EVEN_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_15_02EVEN_LEN ); REG64_FLD( EX_OPCG_CAPT2_SEQ_16_02ODD , 19 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_16_02ODD ); REG64_FLD( EX_OPCG_CAPT2_SEQ_16_02ODD_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_16_02ODD_LEN ); REG64_FLD( EX_OPCG_CAPT2_SEQ_17_03EVEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_17_03EVEN ); REG64_FLD( EX_OPCG_CAPT2_SEQ_17_03EVEN_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_17_03EVEN_LEN ); REG64_FLD( EX_OPCG_CAPT2_SEQ_18_03ODD , 29 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_18_03ODD ); REG64_FLD( EX_OPCG_CAPT2_SEQ_18_03ODD_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_18_03ODD_LEN ); REG64_FLD( EX_OPCG_CAPT2_SEQ_19_04EVEN , 34 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_19_04EVEN ); REG64_FLD( EX_OPCG_CAPT2_SEQ_19_04EVEN_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_19_04EVEN_LEN ); REG64_FLD( EX_OPCG_CAPT2_SEQ_20_04ODD , 39 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_20_04ODD ); REG64_FLD( EX_OPCG_CAPT2_SEQ_20_04ODD_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_20_04ODD_LEN ); REG64_FLD( EX_OPCG_CAPT2_SEQ_21_05EVEN , 44 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_21_05EVEN ); REG64_FLD( EX_OPCG_CAPT2_SEQ_21_05EVEN_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_21_05EVEN_LEN ); REG64_FLD( EX_OPCG_CAPT2_SEQ_22_05ODD , 49 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_22_05ODD ); REG64_FLD( EX_OPCG_CAPT2_SEQ_22_05ODD_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_22_05ODD_LEN ); REG64_FLD( EX_OPCG_CAPT2_SEQ_23_06EVEN , 54 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_23_06EVEN ); REG64_FLD( EX_OPCG_CAPT2_SEQ_23_06EVEN_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_23_06EVEN_LEN ); REG64_FLD( EX_OPCG_CAPT2_SEQ_24_06ODD , 59 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_24_06ODD ); REG64_FLD( EX_OPCG_CAPT2_SEQ_24_06ODD_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_24_06ODD_LEN ); REG64_FLD( C_OPCG_CAPT2_UNUSED , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( C_OPCG_CAPT2_UNUSED_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( C_OPCG_CAPT2_SEQ_13_01EVEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_13_01EVEN ); REG64_FLD( C_OPCG_CAPT2_SEQ_13_01EVEN_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_13_01EVEN_LEN ); REG64_FLD( C_OPCG_CAPT2_SEQ_14_01ODD , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_14_01ODD ); REG64_FLD( C_OPCG_CAPT2_SEQ_14_01ODD_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_14_01ODD_LEN ); REG64_FLD( C_OPCG_CAPT2_SEQ_15_02EVEN , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_15_02EVEN ); REG64_FLD( C_OPCG_CAPT2_SEQ_15_02EVEN_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_15_02EVEN_LEN ); REG64_FLD( C_OPCG_CAPT2_SEQ_16_02ODD , 19 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_16_02ODD ); REG64_FLD( C_OPCG_CAPT2_SEQ_16_02ODD_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_16_02ODD_LEN ); REG64_FLD( C_OPCG_CAPT2_SEQ_17_03EVEN , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_17_03EVEN ); REG64_FLD( C_OPCG_CAPT2_SEQ_17_03EVEN_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_17_03EVEN_LEN ); REG64_FLD( C_OPCG_CAPT2_SEQ_18_03ODD , 29 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_18_03ODD ); REG64_FLD( C_OPCG_CAPT2_SEQ_18_03ODD_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_18_03ODD_LEN ); REG64_FLD( C_OPCG_CAPT2_SEQ_19_04EVEN , 34 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_19_04EVEN ); REG64_FLD( C_OPCG_CAPT2_SEQ_19_04EVEN_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_19_04EVEN_LEN ); REG64_FLD( C_OPCG_CAPT2_SEQ_20_04ODD , 39 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_20_04ODD ); REG64_FLD( C_OPCG_CAPT2_SEQ_20_04ODD_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_20_04ODD_LEN ); REG64_FLD( C_OPCG_CAPT2_SEQ_21_05EVEN , 44 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_21_05EVEN ); REG64_FLD( C_OPCG_CAPT2_SEQ_21_05EVEN_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_21_05EVEN_LEN ); REG64_FLD( C_OPCG_CAPT2_SEQ_22_05ODD , 49 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_22_05ODD ); REG64_FLD( C_OPCG_CAPT2_SEQ_22_05ODD_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_22_05ODD_LEN ); REG64_FLD( C_OPCG_CAPT2_SEQ_23_06EVEN , 54 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_23_06EVEN ); REG64_FLD( C_OPCG_CAPT2_SEQ_23_06EVEN_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_23_06EVEN_LEN ); REG64_FLD( C_OPCG_CAPT2_SEQ_24_06ODD , 59 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_24_06ODD ); REG64_FLD( C_OPCG_CAPT2_SEQ_24_06ODD_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_24_06ODD_LEN ); REG64_FLD( EQ_OPCG_CAPT3_UNUSED , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( EQ_OPCG_CAPT3_UNUSED_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_07EVEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_07EVEN ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_07EVEN_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_07EVEN_LEN ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_07ODD , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_07ODD ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_07ODD_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_07ODD_LEN ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_08EVEN , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_08EVEN ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_08EVEN_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_08EVEN_LEN ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_08ODD , 19 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_08ODD ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_08ODD_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_08ODD_LEN ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_09EVEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_09EVEN ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_09EVEN_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_09EVEN_LEN ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_09ODD , 29 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_09ODD ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_09ODD_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_09ODD_LEN ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_10EVEN , 34 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_10EVEN ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_10EVEN_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_10EVEN_LEN ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_10ODD , 39 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_10ODD ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_10ODD_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_10ODD_LEN ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_11EVEN , 44 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_11EVEN ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_11EVEN_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_11EVEN_LEN ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_11ODD , 49 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_11ODD ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_11ODD_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_11ODD_LEN ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_12EVEN , 54 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_12EVEN ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_12EVEN_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_12EVEN_LEN ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_12ODD , 59 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_12ODD ); REG64_FLD( EQ_OPCG_CAPT3_SEQ_12ODD_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SEQ_12ODD_LEN ); REG64_FLD( EX_OPCG_CAPT3_UNUSED , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( EX_OPCG_CAPT3_UNUSED_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( EX_OPCG_CAPT3_SEQ_07EVEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_07EVEN ); REG64_FLD( EX_OPCG_CAPT3_SEQ_07EVEN_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_07EVEN_LEN ); REG64_FLD( EX_OPCG_CAPT3_SEQ_07ODD , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_07ODD ); REG64_FLD( EX_OPCG_CAPT3_SEQ_07ODD_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_07ODD_LEN ); REG64_FLD( EX_OPCG_CAPT3_SEQ_08EVEN , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_08EVEN ); REG64_FLD( EX_OPCG_CAPT3_SEQ_08EVEN_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_08EVEN_LEN ); REG64_FLD( EX_OPCG_CAPT3_SEQ_08ODD , 19 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_08ODD ); REG64_FLD( EX_OPCG_CAPT3_SEQ_08ODD_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_08ODD_LEN ); REG64_FLD( EX_OPCG_CAPT3_SEQ_09EVEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_09EVEN ); REG64_FLD( EX_OPCG_CAPT3_SEQ_09EVEN_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_09EVEN_LEN ); REG64_FLD( EX_OPCG_CAPT3_SEQ_09ODD , 29 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_09ODD ); REG64_FLD( EX_OPCG_CAPT3_SEQ_09ODD_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_09ODD_LEN ); REG64_FLD( EX_OPCG_CAPT3_SEQ_10EVEN , 34 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_10EVEN ); REG64_FLD( EX_OPCG_CAPT3_SEQ_10EVEN_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_10EVEN_LEN ); REG64_FLD( EX_OPCG_CAPT3_SEQ_10ODD , 39 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_10ODD ); REG64_FLD( EX_OPCG_CAPT3_SEQ_10ODD_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_10ODD_LEN ); REG64_FLD( EX_OPCG_CAPT3_SEQ_11EVEN , 44 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_11EVEN ); REG64_FLD( EX_OPCG_CAPT3_SEQ_11EVEN_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_11EVEN_LEN ); REG64_FLD( EX_OPCG_CAPT3_SEQ_11ODD , 49 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_11ODD ); REG64_FLD( EX_OPCG_CAPT3_SEQ_11ODD_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_11ODD_LEN ); REG64_FLD( EX_OPCG_CAPT3_SEQ_12EVEN , 54 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_12EVEN ); REG64_FLD( EX_OPCG_CAPT3_SEQ_12EVEN_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_12EVEN_LEN ); REG64_FLD( EX_OPCG_CAPT3_SEQ_12ODD , 59 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_12ODD ); REG64_FLD( EX_OPCG_CAPT3_SEQ_12ODD_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SEQ_12ODD_LEN ); REG64_FLD( C_OPCG_CAPT3_UNUSED , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( C_OPCG_CAPT3_UNUSED_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( C_OPCG_CAPT3_SEQ_07EVEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_07EVEN ); REG64_FLD( C_OPCG_CAPT3_SEQ_07EVEN_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_07EVEN_LEN ); REG64_FLD( C_OPCG_CAPT3_SEQ_07ODD , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_07ODD ); REG64_FLD( C_OPCG_CAPT3_SEQ_07ODD_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_07ODD_LEN ); REG64_FLD( C_OPCG_CAPT3_SEQ_08EVEN , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_08EVEN ); REG64_FLD( C_OPCG_CAPT3_SEQ_08EVEN_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_08EVEN_LEN ); REG64_FLD( C_OPCG_CAPT3_SEQ_08ODD , 19 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_08ODD ); REG64_FLD( C_OPCG_CAPT3_SEQ_08ODD_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_08ODD_LEN ); REG64_FLD( C_OPCG_CAPT3_SEQ_09EVEN , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_09EVEN ); REG64_FLD( C_OPCG_CAPT3_SEQ_09EVEN_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_09EVEN_LEN ); REG64_FLD( C_OPCG_CAPT3_SEQ_09ODD , 29 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_09ODD ); REG64_FLD( C_OPCG_CAPT3_SEQ_09ODD_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_09ODD_LEN ); REG64_FLD( C_OPCG_CAPT3_SEQ_10EVEN , 34 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_10EVEN ); REG64_FLD( C_OPCG_CAPT3_SEQ_10EVEN_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_10EVEN_LEN ); REG64_FLD( C_OPCG_CAPT3_SEQ_10ODD , 39 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_10ODD ); REG64_FLD( C_OPCG_CAPT3_SEQ_10ODD_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_10ODD_LEN ); REG64_FLD( C_OPCG_CAPT3_SEQ_11EVEN , 44 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_11EVEN ); REG64_FLD( C_OPCG_CAPT3_SEQ_11EVEN_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_11EVEN_LEN ); REG64_FLD( C_OPCG_CAPT3_SEQ_11ODD , 49 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_11ODD ); REG64_FLD( C_OPCG_CAPT3_SEQ_11ODD_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_11ODD_LEN ); REG64_FLD( C_OPCG_CAPT3_SEQ_12EVEN , 54 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_12EVEN ); REG64_FLD( C_OPCG_CAPT3_SEQ_12EVEN_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_12EVEN_LEN ); REG64_FLD( C_OPCG_CAPT3_SEQ_12ODD , 59 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_12ODD ); REG64_FLD( C_OPCG_CAPT3_SEQ_12ODD_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SEQ_12ODD_LEN ); REG64_FLD( EQ_OPCG_REG0_RUNN_MODE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RUNN_MODE ); REG64_FLD( EQ_OPCG_REG0_GO , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GO ); REG64_FLD( EQ_OPCG_REG0_RUN_SCAN0 , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RUN_SCAN0 ); REG64_FLD( EQ_OPCG_REG0_SCAN0_MODE , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SCAN0_MODE ); REG64_FLD( EQ_OPCG_REG0_IN_SLAVE_MODE , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN_SLAVE_MODE ); REG64_FLD( EQ_OPCG_REG0_IN_MASTER_MODE , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN_MASTER_MODE ); REG64_FLD( EQ_OPCG_REG0_KEEP_MS_MODE , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_KEEP_MS_MODE ); REG64_FLD( EQ_OPCG_REG0_TRIGGER_ON_UNIT0_SYNC_LVL , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIGGER_ON_UNIT0_SYNC_LVL ); REG64_FLD( EQ_OPCG_REG0_TRIGGER_ON_UNIT1_SYNC_LVL , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIGGER_ON_UNIT1_SYNC_LVL ); REG64_FLD( EQ_OPCG_REG0_RUN_CHIPLET_SCAN0 , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RUN_CHIPLET_SCAN0 ); REG64_FLD( EQ_OPCG_REG0_RUN_CHIPLET_SCAN0_NO_PLL , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RUN_CHIPLET_SCAN0_NO_PLL ); REG64_FLD( EQ_OPCG_REG0_RUN_ON_UPDATE_DR , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RUN_ON_UPDATE_DR ); REG64_FLD( EQ_OPCG_REG0_RUN_ON_CAPTURE_DR , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RUN_ON_CAPTURE_DR ); REG64_FLD( EQ_OPCG_REG0_STOP_RUNN_ON_XSTOP , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STOP_RUNN_ON_XSTOP ); REG64_FLD( EQ_OPCG_REG0_STARTS_BIST , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STARTS_BIST ); REG64_FLD( EQ_OPCG_REG0_UNUSED1520 , 15 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED1520 ); REG64_FLD( EQ_OPCG_REG0_UNUSED1520_LEN , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED1520_LEN ); REG64_FLD( EQ_OPCG_REG0_LOOP_COUNT , 21 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LOOP_COUNT ); REG64_FLD( EQ_OPCG_REG0_LOOP_COUNT_LEN , 43 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LOOP_COUNT_LEN ); REG64_FLD( EX_OPCG_REG0_RUNN_MODE , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RUNN_MODE ); REG64_FLD( EX_OPCG_REG0_GO , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GO ); REG64_FLD( EX_OPCG_REG0_RUN_SCAN0 , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RUN_SCAN0 ); REG64_FLD( EX_OPCG_REG0_SCAN0_MODE , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SCAN0_MODE ); REG64_FLD( EX_OPCG_REG0_IN_SLAVE_MODE , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN_SLAVE_MODE ); REG64_FLD( EX_OPCG_REG0_IN_MASTER_MODE , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN_MASTER_MODE ); REG64_FLD( EX_OPCG_REG0_KEEP_MS_MODE , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_KEEP_MS_MODE ); REG64_FLD( EX_OPCG_REG0_TRIGGER_ON_UNIT0_SYNC_LVL , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIGGER_ON_UNIT0_SYNC_LVL ); REG64_FLD( EX_OPCG_REG0_TRIGGER_ON_UNIT1_SYNC_LVL , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIGGER_ON_UNIT1_SYNC_LVL ); REG64_FLD( EX_OPCG_REG0_RUN_CHIPLET_SCAN0 , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RUN_CHIPLET_SCAN0 ); REG64_FLD( EX_OPCG_REG0_RUN_CHIPLET_SCAN0_NO_PLL , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RUN_CHIPLET_SCAN0_NO_PLL ); REG64_FLD( EX_OPCG_REG0_RUN_ON_UPDATE_DR , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RUN_ON_UPDATE_DR ); REG64_FLD( EX_OPCG_REG0_RUN_ON_CAPTURE_DR , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RUN_ON_CAPTURE_DR ); REG64_FLD( EX_OPCG_REG0_STOP_RUNN_ON_XSTOP , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STOP_RUNN_ON_XSTOP ); REG64_FLD( EX_OPCG_REG0_STARTS_BIST , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STARTS_BIST ); REG64_FLD( EX_OPCG_REG0_UNUSED1520 , 15 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED1520 ); REG64_FLD( EX_OPCG_REG0_UNUSED1520_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED1520_LEN ); REG64_FLD( EX_OPCG_REG0_LOOP_COUNT , 21 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_LOOP_COUNT ); REG64_FLD( EX_OPCG_REG0_LOOP_COUNT_LEN , 43 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_LOOP_COUNT_LEN ); REG64_FLD( C_OPCG_REG0_RUNN_MODE , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RUNN_MODE ); REG64_FLD( C_OPCG_REG0_GO , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GO ); REG64_FLD( C_OPCG_REG0_RUN_SCAN0 , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RUN_SCAN0 ); REG64_FLD( C_OPCG_REG0_SCAN0_MODE , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SCAN0_MODE ); REG64_FLD( C_OPCG_REG0_IN_SLAVE_MODE , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN_SLAVE_MODE ); REG64_FLD( C_OPCG_REG0_IN_MASTER_MODE , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN_MASTER_MODE ); REG64_FLD( C_OPCG_REG0_KEEP_MS_MODE , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_KEEP_MS_MODE ); REG64_FLD( C_OPCG_REG0_TRIGGER_ON_UNIT0_SYNC_LVL , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIGGER_ON_UNIT0_SYNC_LVL ); REG64_FLD( C_OPCG_REG0_TRIGGER_ON_UNIT1_SYNC_LVL , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIGGER_ON_UNIT1_SYNC_LVL ); REG64_FLD( C_OPCG_REG0_RUN_CHIPLET_SCAN0 , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RUN_CHIPLET_SCAN0 ); REG64_FLD( C_OPCG_REG0_RUN_CHIPLET_SCAN0_NO_PLL , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RUN_CHIPLET_SCAN0_NO_PLL ); REG64_FLD( C_OPCG_REG0_RUN_ON_UPDATE_DR , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RUN_ON_UPDATE_DR ); REG64_FLD( C_OPCG_REG0_RUN_ON_CAPTURE_DR , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RUN_ON_CAPTURE_DR ); REG64_FLD( C_OPCG_REG0_STOP_RUNN_ON_XSTOP , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STOP_RUNN_ON_XSTOP ); REG64_FLD( C_OPCG_REG0_STARTS_BIST , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STARTS_BIST ); REG64_FLD( C_OPCG_REG0_UNUSED1520 , 15 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED1520 ); REG64_FLD( C_OPCG_REG0_UNUSED1520_LEN , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED1520_LEN ); REG64_FLD( C_OPCG_REG0_LOOP_COUNT , 21 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LOOP_COUNT ); REG64_FLD( C_OPCG_REG0_LOOP_COUNT_LEN , 43 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LOOP_COUNT_LEN ); REG64_FLD( EQ_OPCG_REG1_SCAN_COUNT , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SCAN_COUNT ); REG64_FLD( EQ_OPCG_REG1_SCAN_COUNT_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SCAN_COUNT_LEN ); REG64_FLD( EQ_OPCG_REG1_MISR_A_VAL , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MISR_A_VAL ); REG64_FLD( EQ_OPCG_REG1_MISR_A_VAL_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MISR_A_VAL_LEN ); REG64_FLD( EQ_OPCG_REG1_MISR_B_VAL , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MISR_B_VAL ); REG64_FLD( EQ_OPCG_REG1_MISR_B_VAL_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MISR_B_VAL_LEN ); REG64_FLD( EQ_OPCG_REG1_MISR_INIT_WAIT , 36 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MISR_INIT_WAIT ); REG64_FLD( EQ_OPCG_REG1_MISR_INIT_WAIT_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MISR_INIT_WAIT_LEN ); REG64_FLD( EQ_OPCG_REG1_SUPPRESS_LAST_RUNN_CLK , 48 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SUPPRESS_LAST_RUNN_CLK ); REG64_FLD( EQ_OPCG_REG1_SCAN_CLK_USE_EVEN , 49 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SCAN_CLK_USE_EVEN ); REG64_FLD( EQ_OPCG_REG1_UNUSED2 , 50 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED2 ); REG64_FLD( EQ_OPCG_REG1_UNUSED2_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED2_LEN ); REG64_FLD( EQ_OPCG_REG1_RTIM_THOLD_FORCE , 52 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RTIM_THOLD_FORCE ); REG64_FLD( EQ_OPCG_REG1_DISABLE_ARY_CLK_DURING_FILL , 53 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DISABLE_ARY_CLK_DURING_FILL ); REG64_FLD( EQ_OPCG_REG1_SG_HIGH_DURING_FILL , 54 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SG_HIGH_DURING_FILL ); REG64_FLD( EQ_OPCG_REG1_LBIST_SKITTER_CTL , 55 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LBIST_SKITTER_CTL ); REG64_FLD( EQ_OPCG_REG1_LBIST_SKITTER_CTL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LBIST_SKITTER_CTL_LEN ); REG64_FLD( EQ_OPCG_REG1_MISR_MODE , 57 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MISR_MODE ); REG64_FLD( EQ_OPCG_REG1_INFINITE_MODE , 58 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INFINITE_MODE ); REG64_FLD( EQ_OPCG_REG1_NSL_FILL_COUNT , 59 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NSL_FILL_COUNT ); REG64_FLD( EQ_OPCG_REG1_NSL_FILL_COUNT_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NSL_FILL_COUNT_LEN ); REG64_FLD( EX_OPCG_REG1_SCAN_COUNT , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SCAN_COUNT ); REG64_FLD( EX_OPCG_REG1_SCAN_COUNT_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SCAN_COUNT_LEN ); REG64_FLD( EX_OPCG_REG1_MISR_A_VAL , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MISR_A_VAL ); REG64_FLD( EX_OPCG_REG1_MISR_A_VAL_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MISR_A_VAL_LEN ); REG64_FLD( EX_OPCG_REG1_MISR_B_VAL , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MISR_B_VAL ); REG64_FLD( EX_OPCG_REG1_MISR_B_VAL_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MISR_B_VAL_LEN ); REG64_FLD( EX_OPCG_REG1_MISR_INIT_WAIT , 36 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MISR_INIT_WAIT ); REG64_FLD( EX_OPCG_REG1_MISR_INIT_WAIT_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MISR_INIT_WAIT_LEN ); REG64_FLD( EX_OPCG_REG1_SUPPRESS_LAST_RUNN_CLK , 48 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SUPPRESS_LAST_RUNN_CLK ); REG64_FLD( EX_OPCG_REG1_SCAN_CLK_USE_EVEN , 49 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SCAN_CLK_USE_EVEN ); REG64_FLD( EX_OPCG_REG1_UNUSED2 , 50 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED2 ); REG64_FLD( EX_OPCG_REG1_UNUSED2_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED2_LEN ); REG64_FLD( EX_OPCG_REG1_RTIM_THOLD_FORCE , 52 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RTIM_THOLD_FORCE ); REG64_FLD( EX_OPCG_REG1_DISABLE_ARY_CLK_DURING_FILL , 53 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DISABLE_ARY_CLK_DURING_FILL ); REG64_FLD( EX_OPCG_REG1_SG_HIGH_DURING_FILL , 54 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SG_HIGH_DURING_FILL ); REG64_FLD( EX_OPCG_REG1_LBIST_SKITTER_CTL , 55 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_LBIST_SKITTER_CTL ); REG64_FLD( EX_OPCG_REG1_LBIST_SKITTER_CTL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_LBIST_SKITTER_CTL_LEN ); REG64_FLD( EX_OPCG_REG1_MISR_MODE , 57 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MISR_MODE ); REG64_FLD( EX_OPCG_REG1_INFINITE_MODE , 58 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INFINITE_MODE ); REG64_FLD( EX_OPCG_REG1_NSL_FILL_COUNT , 59 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NSL_FILL_COUNT ); REG64_FLD( EX_OPCG_REG1_NSL_FILL_COUNT_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NSL_FILL_COUNT_LEN ); REG64_FLD( C_OPCG_REG1_SCAN_COUNT , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SCAN_COUNT ); REG64_FLD( C_OPCG_REG1_SCAN_COUNT_LEN , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SCAN_COUNT_LEN ); REG64_FLD( C_OPCG_REG1_MISR_A_VAL , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MISR_A_VAL ); REG64_FLD( C_OPCG_REG1_MISR_A_VAL_LEN , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MISR_A_VAL_LEN ); REG64_FLD( C_OPCG_REG1_MISR_B_VAL , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MISR_B_VAL ); REG64_FLD( C_OPCG_REG1_MISR_B_VAL_LEN , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MISR_B_VAL_LEN ); REG64_FLD( C_OPCG_REG1_MISR_INIT_WAIT , 36 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MISR_INIT_WAIT ); REG64_FLD( C_OPCG_REG1_MISR_INIT_WAIT_LEN , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MISR_INIT_WAIT_LEN ); REG64_FLD( C_OPCG_REG1_SUPPRESS_LAST_RUNN_CLK , 48 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SUPPRESS_LAST_RUNN_CLK ); REG64_FLD( C_OPCG_REG1_SCAN_CLK_USE_EVEN , 49 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SCAN_CLK_USE_EVEN ); REG64_FLD( C_OPCG_REG1_UNUSED2 , 50 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED2 ); REG64_FLD( C_OPCG_REG1_UNUSED2_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED2_LEN ); REG64_FLD( C_OPCG_REG1_RTIM_THOLD_FORCE , 52 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RTIM_THOLD_FORCE ); REG64_FLD( C_OPCG_REG1_DISABLE_ARY_CLK_DURING_FILL , 53 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DISABLE_ARY_CLK_DURING_FILL ); REG64_FLD( C_OPCG_REG1_SG_HIGH_DURING_FILL , 54 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SG_HIGH_DURING_FILL ); REG64_FLD( C_OPCG_REG1_LBIST_SKITTER_CTL , 55 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LBIST_SKITTER_CTL ); REG64_FLD( C_OPCG_REG1_LBIST_SKITTER_CTL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LBIST_SKITTER_CTL_LEN ); REG64_FLD( C_OPCG_REG1_MISR_MODE , 57 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MISR_MODE ); REG64_FLD( C_OPCG_REG1_INFINITE_MODE , 58 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INFINITE_MODE ); REG64_FLD( C_OPCG_REG1_NSL_FILL_COUNT , 59 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_NSL_FILL_COUNT ); REG64_FLD( C_OPCG_REG1_NSL_FILL_COUNT_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_NSL_FILL_COUNT_LEN ); REG64_FLD( EQ_OPCG_REG2_GO2 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GO2 ); REG64_FLD( EQ_OPCG_REG2_PRPG_WEIGHTING , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PRPG_WEIGHTING ); REG64_FLD( EQ_OPCG_REG2_PRPG_WEIGHTING_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PRPG_WEIGHTING_LEN ); REG64_FLD( EQ_OPCG_REG2_PRPG_VALUE , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PRPG_VALUE ); REG64_FLD( EQ_OPCG_REG2_PRPG_VALUE_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PRPG_VALUE_LEN ); REG64_FLD( EQ_OPCG_REG2_PRPG_A_VAL , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PRPG_A_VAL ); REG64_FLD( EQ_OPCG_REG2_PRPG_A_VAL_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PRPG_A_VAL_LEN ); REG64_FLD( EQ_OPCG_REG2_PRPG_B_VAL , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PRPG_B_VAL ); REG64_FLD( EQ_OPCG_REG2_PRPG_B_VAL_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PRPG_B_VAL_LEN ); REG64_FLD( EQ_OPCG_REG2_PRPG_MODE , 40 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PRPG_MODE ); REG64_FLD( EQ_OPCG_REG2_UNUSED41_63 , 41 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED41_63 ); REG64_FLD( EQ_OPCG_REG2_UNUSED41_63_LEN , 23 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED41_63_LEN ); REG64_FLD( EX_OPCG_REG2_GO2 , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GO2 ); REG64_FLD( EX_OPCG_REG2_PRPG_WEIGHTING , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PRPG_WEIGHTING ); REG64_FLD( EX_OPCG_REG2_PRPG_WEIGHTING_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PRPG_WEIGHTING_LEN ); REG64_FLD( EX_OPCG_REG2_PRPG_VALUE , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PRPG_VALUE ); REG64_FLD( EX_OPCG_REG2_PRPG_VALUE_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PRPG_VALUE_LEN ); REG64_FLD( EX_OPCG_REG2_PRPG_A_VAL , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PRPG_A_VAL ); REG64_FLD( EX_OPCG_REG2_PRPG_A_VAL_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PRPG_A_VAL_LEN ); REG64_FLD( EX_OPCG_REG2_PRPG_B_VAL , 28 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PRPG_B_VAL ); REG64_FLD( EX_OPCG_REG2_PRPG_B_VAL_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PRPG_B_VAL_LEN ); REG64_FLD( EX_OPCG_REG2_PRPG_MODE , 40 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PRPG_MODE ); REG64_FLD( EX_OPCG_REG2_UNUSED41_63 , 41 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED41_63 ); REG64_FLD( EX_OPCG_REG2_UNUSED41_63_LEN , 23 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED41_63_LEN ); REG64_FLD( C_OPCG_REG2_GO2 , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GO2 ); REG64_FLD( C_OPCG_REG2_PRPG_WEIGHTING , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PRPG_WEIGHTING ); REG64_FLD( C_OPCG_REG2_PRPG_WEIGHTING_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PRPG_WEIGHTING_LEN ); REG64_FLD( C_OPCG_REG2_PRPG_VALUE , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PRPG_VALUE ); REG64_FLD( C_OPCG_REG2_PRPG_VALUE_LEN , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PRPG_VALUE_LEN ); REG64_FLD( C_OPCG_REG2_PRPG_A_VAL , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PRPG_A_VAL ); REG64_FLD( C_OPCG_REG2_PRPG_A_VAL_LEN , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PRPG_A_VAL_LEN ); REG64_FLD( C_OPCG_REG2_PRPG_B_VAL , 28 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PRPG_B_VAL ); REG64_FLD( C_OPCG_REG2_PRPG_B_VAL_LEN , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PRPG_B_VAL_LEN ); REG64_FLD( C_OPCG_REG2_PRPG_MODE , 40 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PRPG_MODE ); REG64_FLD( C_OPCG_REG2_UNUSED41_63 , 41 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED41_63 ); REG64_FLD( C_OPCG_REG2_UNUSED41_63_LEN , 23 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED41_63_LEN ); REG64_FLD( EQ_PHYP_PURGE_CMD_REG_TRIGGER , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIGGER ); REG64_FLD( EQ_PHYP_PURGE_CMD_REG_TYPE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TYPE ); REG64_FLD( EQ_PHYP_PURGE_CMD_REG_TYPE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TYPE_LEN ); REG64_FLD( EQ_PHYP_PURGE_CMD_REG_BUSY , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_BUSY ); REG64_FLD( EQ_PHYP_PURGE_CMD_REG_PRGSM_BUSY_ON_THIS , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PRGSM_BUSY_ON_THIS ); REG64_FLD( EQ_PHYP_PURGE_CMD_REG_PRGSM_BUSY , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PRGSM_BUSY ); REG64_FLD( EQ_PHYP_PURGE_CMD_REG_MEM , 17 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MEM ); REG64_FLD( EQ_PHYP_PURGE_CMD_REG_MEM_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MEM_LEN ); REG64_FLD( EQ_PHYP_PURGE_CMD_REG_CGC , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CGC ); REG64_FLD( EQ_PHYP_PURGE_CMD_REG_CGC_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CGC_LEN ); REG64_FLD( EQ_PHYP_PURGE_CMD_REG_BANK , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_BANK ); REG64_FLD( EQ_PHYP_PURGE_CMD_REG_ERR , 29 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERR ); REG64_FLD( EX_PHYP_PURGE_CMD_REG_TRIGGER , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIGGER ); REG64_FLD( EX_PHYP_PURGE_CMD_REG_TYPE , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TYPE ); REG64_FLD( EX_PHYP_PURGE_CMD_REG_TYPE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TYPE_LEN ); REG64_FLD( EX_PHYP_PURGE_CMD_REG_BUSY , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_BUSY ); REG64_FLD( EX_PHYP_PURGE_CMD_REG_PRGSM_BUSY_ON_THIS , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PRGSM_BUSY_ON_THIS ); REG64_FLD( EX_PHYP_PURGE_CMD_REG_PRGSM_BUSY , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PRGSM_BUSY ); REG64_FLD( EX_PHYP_PURGE_CMD_REG_MEM , 17 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MEM ); REG64_FLD( EX_PHYP_PURGE_CMD_REG_MEM_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MEM_LEN ); REG64_FLD( EX_PHYP_PURGE_CMD_REG_CGC , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CGC ); REG64_FLD( EX_PHYP_PURGE_CMD_REG_CGC_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CGC_LEN ); REG64_FLD( EX_PHYP_PURGE_CMD_REG_BANK , 28 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_BANK ); REG64_FLD( EX_PHYP_PURGE_CMD_REG_ERR , 29 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ERR ); REG64_FLD( EQ_PHYP_PURGE_REG_L3_REQ , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_REQ ); REG64_FLD( EQ_PHYP_PURGE_REG_L3_TTYPE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_TTYPE ); REG64_FLD( EQ_PHYP_PURGE_REG_L3_TTYPE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_TTYPE_LEN ); REG64_FLD( EQ_PHYP_PURGE_REG_L3_LINE_DEL_ON_NEXT_CE , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_LINE_DEL_ON_NEXT_CE ); REG64_FLD( EQ_PHYP_PURGE_REG_L3_LINE_DEL_ON_ALL_CE , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_LINE_DEL_ON_ALL_CE ); REG64_FLD( EQ_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_1 , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_PHYP_PURGE_RESERVED_1 ); REG64_FLD( EQ_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_1_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_PHYP_PURGE_RESERVED_1_LEN ); REG64_FLD( EQ_PHYP_PURGE_REG_L3_BUSY_ERR , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_BUSY_ERR ); REG64_FLD( EQ_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_2 , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_PHYP_PURGE_RESERVED_2 ); REG64_FLD( EQ_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_2_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_PHYP_PURGE_RESERVED_2_LEN ); REG64_FLD( EQ_PHYP_PURGE_REG_L3_MEMBER , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_MEMBER ); REG64_FLD( EQ_PHYP_PURGE_REG_L3_MEMBER_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_MEMBER_LEN ); REG64_FLD( EQ_PHYP_PURGE_REG_L3_DIR_ADDR , 17 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_DIR_ADDR ); REG64_FLD( EQ_PHYP_PURGE_REG_L3_DIR_ADDR_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_DIR_ADDR_LEN ); REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_REQ , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_REQ ); REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_TTYPE , 1 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_TTYPE ); REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_TTYPE_LEN , 4 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_TTYPE_LEN ); REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_LINE_DEL_ON_NEXT_CE , 5 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_LINE_DEL_ON_NEXT_CE ); REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_LINE_DEL_ON_ALL_CE , 6 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_LINE_DEL_ON_ALL_CE ); REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_1 , 7 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_PHYP_PURGE_RESERVED_1 ); REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_1_LEN , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_PHYP_PURGE_RESERVED_1_LEN ); REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_BUSY_ERR , 9 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_BUSY_ERR ); REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_2 , 10 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_PHYP_PURGE_RESERVED_2 ); REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_PHYP_PURGE_RESERVED_2_LEN , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_PHYP_PURGE_RESERVED_2_LEN ); REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_MEMBER , 12 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_MEMBER ); REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_MEMBER_LEN , 5 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_MEMBER_LEN ); REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_DIR_ADDR , 17 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_DIR_ADDR ); REG64_FLD( EX_L3_PHYP_PURGE_REG_L3_DIR_ADDR_LEN , 12 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_DIR_ADDR_LEN ); REG64_FLD( EQ_PLL_LOCK_REG_LOCK , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LOCK ); REG64_FLD( EQ_PLL_LOCK_REG_LOCK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LOCK_LEN ); REG64_FLD( EX_PLL_LOCK_REG_LOCK , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_LOCK ); REG64_FLD( EX_PLL_LOCK_REG_LOCK_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_LOCK_LEN ); REG64_FLD( C_PLL_LOCK_REG_LOCK , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LOCK ); REG64_FLD( C_PLL_LOCK_REG_LOCK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LOCK_LEN ); REG64_FLD( EX_L2_PMU_HOLD_OUT_PMUT0_SPR_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PMUT0_SPR_HOLD_OUT ); REG64_FLD( EX_L2_PMU_HOLD_OUT_PMUT0_SPR_HOLD_OUT_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PMUT0_SPR_HOLD_OUT_LEN ); REG64_FLD( EX_L2_PMU_HOLD_OUT_PMUT1_SPR_HOLD_OUT , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PMUT1_SPR_HOLD_OUT ); REG64_FLD( EX_L2_PMU_HOLD_OUT_PMUT1_SPR_HOLD_OUT_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PMUT1_SPR_HOLD_OUT_LEN ); REG64_FLD( EX_L2_PMU_HOLD_OUT_PMUT2_SPR_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PMUT2_SPR_HOLD_OUT ); REG64_FLD( EX_L2_PMU_HOLD_OUT_PMUT2_SPR_HOLD_OUT_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PMUT2_SPR_HOLD_OUT_LEN ); REG64_FLD( EX_L2_PMU_HOLD_OUT_PMUT3_SPR_HOLD_OUT , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PMUT3_SPR_HOLD_OUT ); REG64_FLD( EX_L2_PMU_HOLD_OUT_PMUT3_SPR_HOLD_OUT_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PMUT3_SPR_HOLD_OUT_LEN ); REG64_FLD( C_PMU_HOLD_OUT_PMUT0_SPR_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PMUT0_SPR_HOLD_OUT ); REG64_FLD( C_PMU_HOLD_OUT_PMUT0_SPR_HOLD_OUT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PMUT0_SPR_HOLD_OUT_LEN ); REG64_FLD( C_PMU_HOLD_OUT_PMUT1_SPR_HOLD_OUT , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PMUT1_SPR_HOLD_OUT ); REG64_FLD( C_PMU_HOLD_OUT_PMUT1_SPR_HOLD_OUT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PMUT1_SPR_HOLD_OUT_LEN ); REG64_FLD( C_PMU_HOLD_OUT_PMUT2_SPR_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PMUT2_SPR_HOLD_OUT ); REG64_FLD( C_PMU_HOLD_OUT_PMUT2_SPR_HOLD_OUT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PMUT2_SPR_HOLD_OUT_LEN ); REG64_FLD( C_PMU_HOLD_OUT_PMUT3_SPR_HOLD_OUT , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PMUT3_SPR_HOLD_OUT ); REG64_FLD( C_PMU_HOLD_OUT_PMUT3_SPR_HOLD_OUT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PMUT3_SPR_HOLD_OUT_LEN ); REG64_FLD( EX_L2_PMU_SCOMC_PMC1 , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_PMC1 ); REG64_FLD( EX_L2_PMU_SCOMC_PMC2 , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_PMC2 ); REG64_FLD( EX_L2_PMU_SCOMC_PMC3 , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_PMC3 ); REG64_FLD( EX_L2_PMU_SCOMC_PMC4 , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_PMC4 ); REG64_FLD( EX_L2_PMU_SCOMC_PMC5 , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_PMC5 ); REG64_FLD( EX_L2_PMU_SCOMC_PMC6 , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_PMC6 ); REG64_FLD( EX_L2_PMU_SCOMC_MMCRC , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_MMCRC ); REG64_FLD( EX_L2_PMU_SCOMC_MMCR0 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_MMCR0 ); REG64_FLD( EX_L2_PMU_SCOMC_MMCR1 , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_MMCR1 ); REG64_FLD( EX_L2_PMU_SCOMC_MMCR2 , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_MMCR2 ); REG64_FLD( EX_L2_PMU_SCOMC_MMCRA , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_MMCRA ); REG64_FLD( EX_L2_PMU_SCOMC_SIER , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_SIER ); REG64_FLD( EX_L2_PMU_SCOMC_THREAD_ID , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_THREAD_ID ); REG64_FLD( EX_L2_PMU_SCOMC_THREAD_ID_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_THREAD_ID_LEN ); REG64_FLD( C_PMU_SCOMC_PMC1 , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PMC1 ); REG64_FLD( C_PMU_SCOMC_PMC2 , 1 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PMC2 ); REG64_FLD( C_PMU_SCOMC_PMC3 , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PMC3 ); REG64_FLD( C_PMU_SCOMC_PMC4 , 3 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PMC4 ); REG64_FLD( C_PMU_SCOMC_PMC5 , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PMC5 ); REG64_FLD( C_PMU_SCOMC_PMC6 , 5 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PMC6 ); REG64_FLD( C_PMU_SCOMC_MMCRC , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_MMCRC ); REG64_FLD( C_PMU_SCOMC_MMCR0 , 7 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_MMCR0 ); REG64_FLD( C_PMU_SCOMC_MMCR1 , 8 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_MMCR1 ); REG64_FLD( C_PMU_SCOMC_MMCR2 , 9 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_MMCR2 ); REG64_FLD( C_PMU_SCOMC_MMCRA , 10 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_MMCRA ); REG64_FLD( C_PMU_SCOMC_SIER , 11 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SIER ); REG64_FLD( C_PMU_SCOMC_THREAD_ID , 12 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_THREAD_ID ); REG64_FLD( C_PMU_SCOMC_THREAD_ID_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_THREAD_ID_LEN ); REG64_FLD( EX_L2_PMU_SCOMC_EN_ENABLE_INDIRECT_PMU_SCOM , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_ENABLE_INDIRECT_PMU_SCOM ); REG64_FLD( C_PMU_SCOMC_EN_ENABLE_INDIRECT_PMU_SCOM , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_ENABLE_INDIRECT_PMU_SCOM ); REG64_FLD( EQ_PM_L2_RCMD_DIS_REG_L3_CFG , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_CFG ); REG64_FLD( EX_PM_L2_RCMD_DIS_REG_L3_CFG , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_CFG ); REG64_FLD( EQ_PM_LCO_DIS_REG_L3_CFG , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_CFG ); REG64_FLD( EX_L3_PM_LCO_DIS_REG_L3_CFG , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_CFG ); REG64_FLD( EQ_PM_PURGE_REG_L3_REQ , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_REQ ); REG64_FLD( EQ_PM_PURGE_REG_L3_BUSY_ERR , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_BUSY_ERR ); REG64_FLD( EQ_PM_PURGE_REG_L3_ABORT , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_ABORT ); REG64_FLD( EX_L3_PM_PURGE_REG_L3_REQ , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_REQ ); REG64_FLD( EX_L3_PM_PURGE_REG_L3_BUSY_ERR , 1 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_BUSY_ERR ); REG64_FLD( EX_L3_PM_PURGE_REG_L3_ABORT , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_L3_ABORT ); REG64_FLD( EQ_PPE_XIDBGPRO_XSR_HS , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_HS ); REG64_FLD( EQ_PPE_XIDBGPRO_XSR_HC , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_HC ); REG64_FLD( EQ_PPE_XIDBGPRO_XSR_HC_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_HC_LEN ); REG64_FLD( EQ_PPE_XIDBGPRO_XSR_HCP , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_HCP ); REG64_FLD( EQ_PPE_XIDBGPRO_XSR_RIP , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_RIP ); REG64_FLD( EQ_PPE_XIDBGPRO_XSR_SIP , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_SIP ); REG64_FLD( EQ_PPE_XIDBGPRO_XSR_TRAP , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_TRAP ); REG64_FLD( EQ_PPE_XIDBGPRO_XSR_IAC , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_IAC ); REG64_FLD( EQ_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( EQ_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); REG64_FLD( EQ_PPE_XIDBGPRO_XSR_DACR , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_DACR ); REG64_FLD( EQ_PPE_XIDBGPRO_XSR_DACW , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_DACW ); REG64_FLD( EQ_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); REG64_FLD( EQ_PPE_XIDBGPRO_XSR_TRH , 15 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_TRH ); REG64_FLD( EQ_PPE_XIDBGPRO_XSR_SMS , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_SMS ); REG64_FLD( EQ_PPE_XIDBGPRO_XSR_SMS_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_SMS_LEN ); REG64_FLD( EQ_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); REG64_FLD( EQ_PPE_XIDBGPRO_XSR_EP , 21 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_EP ); REG64_FLD( EQ_PPE_XIDBGPRO_XSR_PTR , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_PTR ); REG64_FLD( EQ_PPE_XIDBGPRO_XSR_ST , 25 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_ST ); REG64_FLD( EQ_PPE_XIDBGPRO_XSR_MFE , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_MFE ); REG64_FLD( EQ_PPE_XIDBGPRO_XSR_MCS , 29 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_MCS ); REG64_FLD( EQ_PPE_XIDBGPRO_XSR_MCS_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_MCS_LEN ); REG64_FLD( EQ_PPE_XIDBGPRO_IAR , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IAR ); REG64_FLD( EQ_PPE_XIDBGPRO_IAR_LEN , 30 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IAR_LEN ); REG64_FLD( EX_PPE_XIDBGPRO_XSR_HS , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_HS ); REG64_FLD( EX_PPE_XIDBGPRO_XSR_HC , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_HC ); REG64_FLD( EX_PPE_XIDBGPRO_XSR_HC_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_HC_LEN ); REG64_FLD( EX_PPE_XIDBGPRO_XSR_HCP , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_HCP ); REG64_FLD( EX_PPE_XIDBGPRO_XSR_RIP , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_RIP ); REG64_FLD( EX_PPE_XIDBGPRO_XSR_SIP , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_SIP ); REG64_FLD( EX_PPE_XIDBGPRO_XSR_TRAP , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_TRAP ); REG64_FLD( EX_PPE_XIDBGPRO_XSR_IAC , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_IAC ); REG64_FLD( EX_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( EX_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); REG64_FLD( EX_PPE_XIDBGPRO_XSR_DACR , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_DACR ); REG64_FLD( EX_PPE_XIDBGPRO_XSR_DACW , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_DACW ); REG64_FLD( EX_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); REG64_FLD( EX_PPE_XIDBGPRO_XSR_TRH , 15 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_TRH ); REG64_FLD( EX_PPE_XIDBGPRO_XSR_SMS , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_SMS ); REG64_FLD( EX_PPE_XIDBGPRO_XSR_SMS_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_SMS_LEN ); REG64_FLD( EX_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); REG64_FLD( EX_PPE_XIDBGPRO_XSR_EP , 21 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_EP ); REG64_FLD( EX_PPE_XIDBGPRO_XSR_PTR , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_PTR ); REG64_FLD( EX_PPE_XIDBGPRO_XSR_ST , 25 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_ST ); REG64_FLD( EX_PPE_XIDBGPRO_XSR_MFE , 28 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_MFE ); REG64_FLD( EX_PPE_XIDBGPRO_XSR_MCS , 29 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_MCS ); REG64_FLD( EX_PPE_XIDBGPRO_XSR_MCS_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_MCS_LEN ); REG64_FLD( EX_PPE_XIDBGPRO_IAR , 32 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IAR ); REG64_FLD( EX_PPE_XIDBGPRO_IAR_LEN , 30 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IAR_LEN ); REG64_FLD( EQ_PPE_XIRAMDBG_XSR_HS , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_HS ); REG64_FLD( EQ_PPE_XIRAMDBG_XSR_HC , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_HC ); REG64_FLD( EQ_PPE_XIRAMDBG_XSR_HC_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_HC_LEN ); REG64_FLD( EQ_PPE_XIRAMDBG_XSR_HCP , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_HCP ); REG64_FLD( EQ_PPE_XIRAMDBG_XSR_RIP , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_RIP ); REG64_FLD( EQ_PPE_XIRAMDBG_XSR_SIP , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_SIP ); REG64_FLD( EQ_PPE_XIRAMDBG_XSR_TRAP , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_TRAP ); REG64_FLD( EQ_PPE_XIRAMDBG_XSR_IAC , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_IAC ); REG64_FLD( EQ_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( EQ_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); REG64_FLD( EQ_PPE_XIRAMDBG_XSR_DACR , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_DACR ); REG64_FLD( EQ_PPE_XIRAMDBG_XSR_DACW , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_DACW ); REG64_FLD( EQ_PPE_XIRAMDBG_NULL_MSR_WE , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); REG64_FLD( EQ_PPE_XIRAMDBG_XSR_TRH , 15 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_TRH ); REG64_FLD( EQ_PPE_XIRAMDBG_XSR_SMS , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_SMS ); REG64_FLD( EQ_PPE_XIRAMDBG_XSR_SMS_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_SMS_LEN ); REG64_FLD( EQ_PPE_XIRAMDBG_NULL_MSR_LP , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); REG64_FLD( EQ_PPE_XIRAMDBG_XSR_EP , 21 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_EP ); REG64_FLD( EQ_PPE_XIRAMDBG_XSR_PTR , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_PTR ); REG64_FLD( EQ_PPE_XIRAMDBG_XSR_ST , 25 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_ST ); REG64_FLD( EQ_PPE_XIRAMDBG_XSR_MFE , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_MFE ); REG64_FLD( EQ_PPE_XIRAMDBG_XSR_MCS , 29 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_MCS ); REG64_FLD( EQ_PPE_XIRAMDBG_XSR_MCS_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSR_MCS_LEN ); REG64_FLD( EQ_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( EQ_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0_LEN ); REG64_FLD( EX_PPE_XIRAMDBG_XSR_HS , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_HS ); REG64_FLD( EX_PPE_XIRAMDBG_XSR_HC , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_HC ); REG64_FLD( EX_PPE_XIRAMDBG_XSR_HC_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_HC_LEN ); REG64_FLD( EX_PPE_XIRAMDBG_XSR_HCP , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_HCP ); REG64_FLD( EX_PPE_XIRAMDBG_XSR_RIP , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_RIP ); REG64_FLD( EX_PPE_XIRAMDBG_XSR_SIP , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_SIP ); REG64_FLD( EX_PPE_XIRAMDBG_XSR_TRAP , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_TRAP ); REG64_FLD( EX_PPE_XIRAMDBG_XSR_IAC , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_IAC ); REG64_FLD( EX_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( EX_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); REG64_FLD( EX_PPE_XIRAMDBG_XSR_DACR , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_DACR ); REG64_FLD( EX_PPE_XIRAMDBG_XSR_DACW , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_DACW ); REG64_FLD( EX_PPE_XIRAMDBG_NULL_MSR_WE , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); REG64_FLD( EX_PPE_XIRAMDBG_XSR_TRH , 15 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_TRH ); REG64_FLD( EX_PPE_XIRAMDBG_XSR_SMS , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_SMS ); REG64_FLD( EX_PPE_XIRAMDBG_XSR_SMS_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_SMS_LEN ); REG64_FLD( EX_PPE_XIRAMDBG_NULL_MSR_LP , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); REG64_FLD( EX_PPE_XIRAMDBG_XSR_EP , 21 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_EP ); REG64_FLD( EX_PPE_XIRAMDBG_XSR_PTR , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_PTR ); REG64_FLD( EX_PPE_XIRAMDBG_XSR_ST , 25 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_ST ); REG64_FLD( EX_PPE_XIRAMDBG_XSR_MFE , 28 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_MFE ); REG64_FLD( EX_PPE_XIRAMDBG_XSR_MCS , 29 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_MCS ); REG64_FLD( EX_PPE_XIRAMDBG_XSR_MCS_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSR_MCS_LEN ); REG64_FLD( EX_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( EX_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0_LEN ); REG64_FLD( EQ_PPE_XIRAMEDR_XIRAMGA_IR , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XIRAMGA_IR ); REG64_FLD( EQ_PPE_XIRAMEDR_XIRAMGA_IR_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XIRAMGA_IR_LEN ); REG64_FLD( EQ_PPE_XIRAMEDR_EDR , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EDR ); REG64_FLD( EQ_PPE_XIRAMEDR_EDR_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EDR_LEN ); REG64_FLD( EX_PPE_XIRAMEDR_XIRAMGA_IR , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XIRAMGA_IR ); REG64_FLD( EX_PPE_XIRAMEDR_XIRAMGA_IR_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XIRAMGA_IR_LEN ); REG64_FLD( EX_PPE_XIRAMEDR_EDR , 32 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EDR ); REG64_FLD( EX_PPE_XIRAMEDR_EDR_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EDR_LEN ); REG64_FLD( EQ_PPE_XIRAMGA_IR , 0 , SH_UNT_EQ , SH_ACS_SCOM_WO , SH_FLD_IR ); REG64_FLD( EQ_PPE_XIRAMGA_IR_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM_WO , SH_FLD_IR_LEN ); REG64_FLD( EQ_PPE_XIRAMGA_XIRAMRA_SPRG0 , 32 , SH_UNT_EQ , SH_ACS_SCOM_WO , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( EQ_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM_WO , SH_FLD_XIRAMRA_SPRG0_LEN ); REG64_FLD( EX_PPE_XIRAMGA_IR , 0 , SH_UNT_EX , SH_ACS_SCOM_WO , SH_FLD_IR ); REG64_FLD( EX_PPE_XIRAMGA_IR_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM_WO , SH_FLD_IR_LEN ); REG64_FLD( EX_PPE_XIRAMGA_XIRAMRA_SPRG0 , 32 , SH_UNT_EX , SH_ACS_SCOM_WO , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( EX_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM_WO , SH_FLD_XIRAMRA_SPRG0_LEN ); REG64_FLD( EQ_PPE_XIRAMRA_XIXCR_XCR , 1 , SH_UNT_EQ , SH_ACS_SCOM_WO , SH_FLD_XIXCR_XCR ); REG64_FLD( EQ_PPE_XIRAMRA_XIXCR_XCR_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM_WO , SH_FLD_XIXCR_XCR_LEN ); REG64_FLD( EQ_PPE_XIRAMRA_SPRG0 , 32 , SH_UNT_EQ , SH_ACS_SCOM_WO , SH_FLD_SPRG0 ); REG64_FLD( EQ_PPE_XIRAMRA_SPRG0_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM_WO , SH_FLD_SPRG0_LEN ); REG64_FLD( EX_PPE_XIRAMRA_XIXCR_XCR , 1 , SH_UNT_EX , SH_ACS_SCOM_WO , SH_FLD_XIXCR_XCR ); REG64_FLD( EX_PPE_XIRAMRA_XIXCR_XCR_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_WO , SH_FLD_XIXCR_XCR_LEN ); REG64_FLD( EX_PPE_XIRAMRA_SPRG0 , 32 , SH_UNT_EX , SH_ACS_SCOM_WO , SH_FLD_SPRG0 ); REG64_FLD( EX_PPE_XIRAMRA_SPRG0_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM_WO , SH_FLD_SPRG0_LEN ); REG64_FLD( EQ_PPE_XIXCR_XCR , 1 , SH_UNT_EQ , SH_ACS_SCOM_WO , SH_FLD_XCR ); REG64_FLD( EQ_PPE_XIXCR_XCR_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM_WO , SH_FLD_XCR_LEN ); REG64_FLD( EX_PPE_XIXCR_XCR , 1 , SH_UNT_EX , SH_ACS_SCOM_WO , SH_FLD_XCR ); REG64_FLD( EX_PPE_XIXCR_XCR_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_WO , SH_FLD_XCR_LEN ); REG64_FLD( EQ_PPM_CGCR_CLKGLM_ASYNC_RESET , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_CLKGLM_ASYNC_RESET ); REG64_FLD( EQ_PPM_CGCR_RESERVED_1_2 , 1 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_RESERVED_1_2 ); REG64_FLD( EQ_PPM_CGCR_RESERVED_1_2_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_RESERVED_1_2_LEN ); REG64_FLD( EQ_PPM_CGCR_CLKGLM_SEL , 3 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_CLKGLM_SEL ); REG64_FLD( EX_PPM_CGCR_CLKGLM_ASYNC_RESET , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_CLKGLM_ASYNC_RESET ); REG64_FLD( EX_PPM_CGCR_RESERVED_1_2 , 1 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_RESERVED_1_2 ); REG64_FLD( EX_PPM_CGCR_RESERVED_1_2_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_RESERVED_1_2_LEN ); REG64_FLD( EX_PPM_CGCR_CLKGLM_SEL , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_CLKGLM_SEL ); REG64_FLD( C_PPM_CGCR_CLKGLM_ASYNC_RESET , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_CLKGLM_ASYNC_RESET ); REG64_FLD( C_PPM_CGCR_RESERVED_1_2 , 1 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RESERVED_1_2 ); REG64_FLD( C_PPM_CGCR_RESERVED_1_2_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RESERVED_1_2_LEN ); REG64_FLD( C_PPM_CGCR_CLKGLM_SEL , 3 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_CLKGLM_SEL ); REG64_FLD( EQ_PPM_GPMMR_SPECIAL_WKUP_DONE , 0 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_SPECIAL_WKUP_DONE ); REG64_FLD( EQ_PPM_GPMMR_SPECIAL_WKUP_ACTIVE , 1 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_SPECIAL_WKUP_ACTIVE ); REG64_FLD( EQ_PPM_GPMMR_REGULAR_WKUP_ACTIVE , 2 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_REGULAR_WKUP_ACTIVE ); REG64_FLD( EQ_PPM_GPMMR_SPECIAL_WKUP_REQUESTED , 3 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_SPECIAL_WKUP_REQUESTED ); REG64_FLD( EQ_PPM_GPMMR_REGULAR_WKUP_REQUESTED , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_REGULAR_WKUP_REQUESTED ); REG64_FLD( EQ_PPM_GPMMR_REGULAR_WKUP_PRESENT , 5 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_REGULAR_WKUP_PRESENT ); REG64_FLD( EQ_PPM_GPMMR_BLOCK_REG_WKUP_EVENTS , 6 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_BLOCK_REG_WKUP_EVENTS ); REG64_FLD( EQ_PPM_GPMMR_BLOCK_ALL_WKUP_EVENTS , 7 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_BLOCK_ALL_WKUP_EVENTS ); REG64_FLD( EQ_PPM_GPMMR_WKUP_OVERRIDE_EN , 8 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_WKUP_OVERRIDE_EN ); REG64_FLD( EQ_PPM_GPMMR_SPC_WKUP_OVERRIDE , 9 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_SPC_WKUP_OVERRIDE ); REG64_FLD( EQ_PPM_GPMMR_REG_WKUP_OVERRIDE , 10 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_REG_WKUP_OVERRIDE ); REG64_FLD( EQ_PPM_GPMMR_CHIPLET_ENABLE , 11 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_CHIPLET_ENABLE ); REG64_FLD( EQ_PPM_GPMMR_RESERVED_12_14 , 12 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_RESERVED_12_14 ); REG64_FLD( EQ_PPM_GPMMR_RESERVED_12_14_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_RESERVED_12_14_LEN ); REG64_FLD( EQ_PPM_GPMMR_RESET_STATE_INDICATOR , 15 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_RESET_STATE_INDICATOR ); REG64_FLD( EX_PPM_GPMMR_SPECIAL_WKUP_DONE , 0 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_SPECIAL_WKUP_DONE ); REG64_FLD( EX_PPM_GPMMR_SPECIAL_WKUP_ACTIVE , 1 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_SPECIAL_WKUP_ACTIVE ); REG64_FLD( EX_PPM_GPMMR_REGULAR_WKUP_ACTIVE , 2 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_REGULAR_WKUP_ACTIVE ); REG64_FLD( EX_PPM_GPMMR_SPECIAL_WKUP_REQUESTED , 3 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_SPECIAL_WKUP_REQUESTED ); REG64_FLD( EX_PPM_GPMMR_REGULAR_WKUP_REQUESTED , 4 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_REGULAR_WKUP_REQUESTED ); REG64_FLD( EX_PPM_GPMMR_REGULAR_WKUP_PRESENT , 5 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_REGULAR_WKUP_PRESENT ); REG64_FLD( EX_PPM_GPMMR_BLOCK_REG_WKUP_EVENTS , 6 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_BLOCK_REG_WKUP_EVENTS ); REG64_FLD( EX_PPM_GPMMR_BLOCK_ALL_WKUP_EVENTS , 7 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_BLOCK_ALL_WKUP_EVENTS ); REG64_FLD( EX_PPM_GPMMR_WKUP_OVERRIDE_EN , 8 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_WKUP_OVERRIDE_EN ); REG64_FLD( EX_PPM_GPMMR_SPC_WKUP_OVERRIDE , 9 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_SPC_WKUP_OVERRIDE ); REG64_FLD( EX_PPM_GPMMR_REG_WKUP_OVERRIDE , 10 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_REG_WKUP_OVERRIDE ); REG64_FLD( EX_PPM_GPMMR_CHIPLET_ENABLE , 11 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_CHIPLET_ENABLE ); REG64_FLD( EX_PPM_GPMMR_RESERVED_12_14 , 12 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_RESERVED_12_14 ); REG64_FLD( EX_PPM_GPMMR_RESERVED_12_14_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_RESERVED_12_14_LEN ); REG64_FLD( EX_PPM_GPMMR_RESET_STATE_INDICATOR , 15 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_RESET_STATE_INDICATOR ); REG64_FLD( C_PPM_GPMMR_SPECIAL_WKUP_DONE , 0 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_SPECIAL_WKUP_DONE ); REG64_FLD( C_PPM_GPMMR_SPECIAL_WKUP_ACTIVE , 1 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_SPECIAL_WKUP_ACTIVE ); REG64_FLD( C_PPM_GPMMR_REGULAR_WKUP_ACTIVE , 2 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_REGULAR_WKUP_ACTIVE ); REG64_FLD( C_PPM_GPMMR_SPECIAL_WKUP_REQUESTED , 3 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_SPECIAL_WKUP_REQUESTED ); REG64_FLD( C_PPM_GPMMR_REGULAR_WKUP_REQUESTED , 4 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_REGULAR_WKUP_REQUESTED ); REG64_FLD( C_PPM_GPMMR_REGULAR_WKUP_PRESENT , 5 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_REGULAR_WKUP_PRESENT ); REG64_FLD( C_PPM_GPMMR_BLOCK_REG_WKUP_EVENTS , 6 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_BLOCK_REG_WKUP_EVENTS ); REG64_FLD( C_PPM_GPMMR_BLOCK_ALL_WKUP_EVENTS , 7 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_BLOCK_ALL_WKUP_EVENTS ); REG64_FLD( C_PPM_GPMMR_WKUP_OVERRIDE_EN , 8 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_WKUP_OVERRIDE_EN ); REG64_FLD( C_PPM_GPMMR_SPC_WKUP_OVERRIDE , 9 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_SPC_WKUP_OVERRIDE ); REG64_FLD( C_PPM_GPMMR_REG_WKUP_OVERRIDE , 10 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_REG_WKUP_OVERRIDE ); REG64_FLD( C_PPM_GPMMR_CHIPLET_ENABLE , 11 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_CHIPLET_ENABLE ); REG64_FLD( C_PPM_GPMMR_RESERVED_12_14 , 12 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_RESERVED_12_14 ); REG64_FLD( C_PPM_GPMMR_RESERVED_12_14_LEN , 3 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_RESERVED_12_14_LEN ); REG64_FLD( C_PPM_GPMMR_RESET_STATE_INDICATOR , 15 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_RESET_STATE_INDICATOR ); REG64_FLD( EQ_PPM_IVRMAVR_IVRM_IVID , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IVRM_IVID ); REG64_FLD( EQ_PPM_IVRMAVR_IVRM_IVID_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IVRM_IVID_LEN ); REG64_FLD( EQ_PPM_IVRMAVR_IVRM_PROTECT_ACTIVE , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IVRM_PROTECT_ACTIVE ); REG64_FLD( EQ_PPM_IVRMAVR_IVRM_PFET_STRENGTH , 11 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IVRM_PFET_STRENGTH ); REG64_FLD( EQ_PPM_IVRMAVR_IVRM_PFET_STRENGTH_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IVRM_PFET_STRENGTH_LEN ); REG64_FLD( EQ_PPM_IVRMAVR_IVRM_VID_VALID , 24 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IVRM_VID_VALID ); REG64_FLD( EQ_PPM_IVRMAVR_IVRM_BYPASS_B , 25 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IVRM_BYPASS_B ); REG64_FLD( EQ_PPM_IVRMAVR_IVRM_POWERON , 26 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IVRM_POWERON ); REG64_FLD( EQ_PPM_IVRMAVR_IVRM_VREG_SLOW_DC , 27 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IVRM_VREG_SLOW_DC ); REG64_FLD( EX_PPM_IVRMAVR_IVRM_IVID , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IVRM_IVID ); REG64_FLD( EX_PPM_IVRMAVR_IVRM_IVID_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IVRM_IVID_LEN ); REG64_FLD( EX_PPM_IVRMAVR_IVRM_PROTECT_ACTIVE , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IVRM_PROTECT_ACTIVE ); REG64_FLD( EX_PPM_IVRMAVR_IVRM_PFET_STRENGTH , 11 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IVRM_PFET_STRENGTH ); REG64_FLD( EX_PPM_IVRMAVR_IVRM_PFET_STRENGTH_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IVRM_PFET_STRENGTH_LEN ); REG64_FLD( EX_PPM_IVRMAVR_IVRM_VID_VALID , 24 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IVRM_VID_VALID ); REG64_FLD( EX_PPM_IVRMAVR_IVRM_BYPASS_B , 25 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IVRM_BYPASS_B ); REG64_FLD( EX_PPM_IVRMAVR_IVRM_POWERON , 26 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IVRM_POWERON ); REG64_FLD( EX_PPM_IVRMAVR_IVRM_VREG_SLOW_DC , 27 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IVRM_VREG_SLOW_DC ); REG64_FLD( C_PPM_IVRMAVR_IVRM_IVID , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IVRM_IVID ); REG64_FLD( C_PPM_IVRMAVR_IVRM_IVID_LEN , 8 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IVRM_IVID_LEN ); REG64_FLD( C_PPM_IVRMAVR_IVRM_PROTECT_ACTIVE , 8 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IVRM_PROTECT_ACTIVE ); REG64_FLD( C_PPM_IVRMAVR_IVRM_PFET_STRENGTH , 11 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IVRM_PFET_STRENGTH ); REG64_FLD( C_PPM_IVRMAVR_IVRM_PFET_STRENGTH_LEN , 5 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IVRM_PFET_STRENGTH_LEN ); REG64_FLD( C_PPM_IVRMAVR_IVRM_VID_VALID , 24 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IVRM_VID_VALID ); REG64_FLD( C_PPM_IVRMAVR_IVRM_BYPASS_B , 25 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IVRM_BYPASS_B ); REG64_FLD( C_PPM_IVRMAVR_IVRM_POWERON , 26 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IVRM_POWERON ); REG64_FLD( C_PPM_IVRMAVR_IVRM_VREG_SLOW_DC , 27 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IVRM_VREG_SLOW_DC ); REG64_FLD( EQ_PPM_IVRMCR_IVRM_VID_VALID , 0 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IVRM_VID_VALID ); REG64_FLD( EQ_PPM_IVRMCR_IVRM_BYPASS_B , 1 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IVRM_BYPASS_B ); REG64_FLD( EQ_PPM_IVRMCR_IVRM_POWERON , 2 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IVRM_POWERON ); REG64_FLD( EQ_PPM_IVRMCR_IVRM_VREG_SLOW_DC , 3 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_IVRM_VREG_SLOW_DC ); REG64_FLD( EQ_PPM_IVRMCR_RESERVED_4_7 , 4 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_4_7 ); REG64_FLD( EQ_PPM_IVRMCR_RESERVED_4_7_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_4_7_LEN ); REG64_FLD( EX_PPM_IVRMCR_IVRM_VID_VALID , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IVRM_VID_VALID ); REG64_FLD( EX_PPM_IVRMCR_IVRM_BYPASS_B , 1 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IVRM_BYPASS_B ); REG64_FLD( EX_PPM_IVRMCR_IVRM_POWERON , 2 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IVRM_POWERON ); REG64_FLD( EX_PPM_IVRMCR_IVRM_VREG_SLOW_DC , 3 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_IVRM_VREG_SLOW_DC ); REG64_FLD( EX_PPM_IVRMCR_RESERVED_4_7 , 4 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_4_7 ); REG64_FLD( EX_PPM_IVRMCR_RESERVED_4_7_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_4_7_LEN ); REG64_FLD( C_PPM_IVRMCR_IVRM_VID_VALID , 0 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IVRM_VID_VALID ); REG64_FLD( C_PPM_IVRMCR_IVRM_BYPASS_B , 1 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IVRM_BYPASS_B ); REG64_FLD( C_PPM_IVRMCR_IVRM_POWERON , 2 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IVRM_POWERON ); REG64_FLD( C_PPM_IVRMCR_IVRM_VREG_SLOW_DC , 3 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_IVRM_VREG_SLOW_DC ); REG64_FLD( C_PPM_IVRMCR_RESERVED_4_7 , 4 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_4_7 ); REG64_FLD( C_PPM_IVRMCR_RESERVED_4_7_LEN , 4 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_4_7_LEN ); REG64_FLD( EQ_PPM_IVRMDVR_IVRM_IVID , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_IVRM_IVID ); REG64_FLD( EQ_PPM_IVRMDVR_IVRM_IVID_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_IVRM_IVID_LEN ); REG64_FLD( EQ_PPM_IVRMDVR_RESERVED_8_10 , 8 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_RESERVED_8_10 ); REG64_FLD( EQ_PPM_IVRMDVR_RESERVED_8_10_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_RESERVED_8_10_LEN ); REG64_FLD( EQ_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CORE , 11 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_IVRM_PFET_STRENGTH_CORE ); REG64_FLD( EQ_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CORE_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_IVRM_PFET_STRENGTH_CORE_LEN ); REG64_FLD( EQ_PPM_IVRMDVR_RESERVED_16_18 , 16 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_RESERVED_16_18 ); REG64_FLD( EQ_PPM_IVRMDVR_RESERVED_16_18_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_RESERVED_16_18_LEN ); REG64_FLD( EQ_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CACHE , 19 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_IVRM_PFET_STRENGTH_CACHE ); REG64_FLD( EQ_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CACHE_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_IVRM_PFET_STRENGTH_CACHE_LEN ); REG64_FLD( EX_PPM_IVRMDVR_IVRM_IVID , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_IVRM_IVID ); REG64_FLD( EX_PPM_IVRMDVR_IVRM_IVID_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_IVRM_IVID_LEN ); REG64_FLD( EX_PPM_IVRMDVR_RESERVED_8_10 , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_RESERVED_8_10 ); REG64_FLD( EX_PPM_IVRMDVR_RESERVED_8_10_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_RESERVED_8_10_LEN ); REG64_FLD( EX_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CORE , 11 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_IVRM_PFET_STRENGTH_CORE ); REG64_FLD( EX_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CORE_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_IVRM_PFET_STRENGTH_CORE_LEN ); REG64_FLD( EX_PPM_IVRMDVR_RESERVED_16_18 , 16 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_RESERVED_16_18 ); REG64_FLD( EX_PPM_IVRMDVR_RESERVED_16_18_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_RESERVED_16_18_LEN ); REG64_FLD( EX_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CACHE , 19 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_IVRM_PFET_STRENGTH_CACHE ); REG64_FLD( EX_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CACHE_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_IVRM_PFET_STRENGTH_CACHE_LEN ); REG64_FLD( C_PPM_IVRMDVR_IVRM_IVID , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_IVRM_IVID ); REG64_FLD( C_PPM_IVRMDVR_IVRM_IVID_LEN , 8 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_IVRM_IVID_LEN ); REG64_FLD( C_PPM_IVRMDVR_RESERVED_8_10 , 8 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RESERVED_8_10 ); REG64_FLD( C_PPM_IVRMDVR_RESERVED_8_10_LEN , 3 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RESERVED_8_10_LEN ); REG64_FLD( C_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CORE , 11 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_IVRM_PFET_STRENGTH_CORE ); REG64_FLD( C_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CORE_LEN , 5 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_IVRM_PFET_STRENGTH_CORE_LEN ); REG64_FLD( C_PPM_IVRMDVR_RESERVED_16_18 , 16 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RESERVED_16_18 ); REG64_FLD( C_PPM_IVRMDVR_RESERVED_16_18_LEN , 3 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RESERVED_16_18_LEN ); REG64_FLD( C_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CACHE , 19 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_IVRM_PFET_STRENGTH_CACHE ); REG64_FLD( C_PPM_IVRMDVR_IVRM_PFET_STRENGTH_CACHE_LEN , 5 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_IVRM_PFET_STRENGTH_CACHE_LEN ); REG64_FLD( EQ_PPM_IVRMST_IVRM_VID_DONE , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IVRM_VID_DONE ); REG64_FLD( EX_PPM_IVRMST_IVRM_VID_DONE , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_IVRM_VID_DONE ); REG64_FLD( C_PPM_IVRMST_IVRM_VID_DONE , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IVRM_VID_DONE ); REG64_FLD( EQ_PPM_PFCS_VDD_PFET_FORCE_STATE , 0 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_FORCE_STATE ); REG64_FLD( EQ_PPM_PFCS_VDD_PFET_FORCE_STATE_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_FORCE_STATE_LEN ); REG64_FLD( EQ_PPM_PFCS_VCS_PFET_FORCE_STATE , 2 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_FORCE_STATE ); REG64_FLD( EQ_PPM_PFCS_VCS_PFET_FORCE_STATE_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_FORCE_STATE_LEN ); REG64_FLD( EQ_PPM_PFCS_VDD_PFET_VAL_OVERRIDE , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_VAL_OVERRIDE ); REG64_FLD( EQ_PPM_PFCS_VDD_PFET_SEL_OVERRIDE , 5 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_SEL_OVERRIDE ); REG64_FLD( EQ_PPM_PFCS_VCS_PFET_VAL_OVERRIDE , 6 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_VAL_OVERRIDE ); REG64_FLD( EQ_PPM_PFCS_VCS_PFET_SEL_OVERRIDE , 7 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_SEL_OVERRIDE ); REG64_FLD( EQ_PPM_PFCS_VDD_PFET_REGULATION_FINGER_EN , 8 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_REGULATION_FINGER_EN ); REG64_FLD( EQ_PPM_PFCS_VDD_PFET_REGULATION_FINGER_VALUE , 9 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_REGULATION_FINGER_VALUE ); REG64_FLD( EQ_PPM_PFCS_RESERVED_10_11 , 10 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_RESERVED_10_11 ); REG64_FLD( EQ_PPM_PFCS_RESERVED_10_11_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_RESERVED_10_11_LEN ); REG64_FLD( EQ_PPM_PFCS_VDD_PFET_ENABLE_VALUE , 12 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_ENABLE_VALUE ); REG64_FLD( EQ_PPM_PFCS_VDD_PFET_ENABLE_VALUE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_ENABLE_VALUE_LEN ); REG64_FLD( EQ_PPM_PFCS_VDD_PFET_SEL_VALUE , 20 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_SEL_VALUE ); REG64_FLD( EQ_PPM_PFCS_VDD_PFET_SEL_VALUE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_SEL_VALUE_LEN ); REG64_FLD( EQ_PPM_PFCS_VCS_PFET_ENABLE_VALUE , 24 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_ENABLE_VALUE ); REG64_FLD( EQ_PPM_PFCS_VCS_PFET_ENABLE_VALUE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_ENABLE_VALUE_LEN ); REG64_FLD( EQ_PPM_PFCS_VCS_PFET_SEL_VALUE , 32 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_SEL_VALUE ); REG64_FLD( EQ_PPM_PFCS_VCS_PFET_SEL_VALUE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_SEL_VALUE_LEN ); REG64_FLD( EQ_PPM_PFCS_VDD_PG_STATE , 42 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VDD_PG_STATE ); REG64_FLD( EQ_PPM_PFCS_VDD_PG_STATE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VDD_PG_STATE_LEN ); REG64_FLD( EQ_PPM_PFCS_VDD_PG_SEL , 46 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VDD_PG_SEL ); REG64_FLD( EQ_PPM_PFCS_VDD_PG_SEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VDD_PG_SEL_LEN ); REG64_FLD( EQ_PPM_PFCS_VCS_PG_STATE , 50 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VCS_PG_STATE ); REG64_FLD( EQ_PPM_PFCS_VCS_PG_STATE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VCS_PG_STATE_LEN ); REG64_FLD( EQ_PPM_PFCS_VCS_PG_SEL , 54 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VCS_PG_SEL ); REG64_FLD( EQ_PPM_PFCS_VCS_PG_SEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_VCS_PG_SEL_LEN ); REG64_FLD( EX_PPM_PFCS_VDD_PFET_FORCE_STATE , 0 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_FORCE_STATE ); REG64_FLD( EX_PPM_PFCS_VDD_PFET_FORCE_STATE_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_FORCE_STATE_LEN ); REG64_FLD( EX_PPM_PFCS_VCS_PFET_FORCE_STATE , 2 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_FORCE_STATE ); REG64_FLD( EX_PPM_PFCS_VCS_PFET_FORCE_STATE_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_FORCE_STATE_LEN ); REG64_FLD( EX_PPM_PFCS_VDD_PFET_VAL_OVERRIDE , 4 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_VAL_OVERRIDE ); REG64_FLD( EX_PPM_PFCS_VDD_PFET_SEL_OVERRIDE , 5 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_SEL_OVERRIDE ); REG64_FLD( EX_PPM_PFCS_VCS_PFET_VAL_OVERRIDE , 6 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_VAL_OVERRIDE ); REG64_FLD( EX_PPM_PFCS_VCS_PFET_SEL_OVERRIDE , 7 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_SEL_OVERRIDE ); REG64_FLD( EX_PPM_PFCS_VDD_PFET_REGULATION_FINGER_EN , 8 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_REGULATION_FINGER_EN ); REG64_FLD( EX_PPM_PFCS_VDD_PFET_REGULATION_FINGER_VALUE , 9 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_REGULATION_FINGER_VALUE ); REG64_FLD( EX_PPM_PFCS_RESERVED_10_11 , 10 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_RESERVED_10_11 ); REG64_FLD( EX_PPM_PFCS_RESERVED_10_11_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_RESERVED_10_11_LEN ); REG64_FLD( EX_PPM_PFCS_VDD_PFET_ENABLE_VALUE , 12 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_ENABLE_VALUE ); REG64_FLD( EX_PPM_PFCS_VDD_PFET_ENABLE_VALUE_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_ENABLE_VALUE_LEN ); REG64_FLD( EX_PPM_PFCS_VDD_PFET_SEL_VALUE , 20 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_SEL_VALUE ); REG64_FLD( EX_PPM_PFCS_VDD_PFET_SEL_VALUE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_SEL_VALUE_LEN ); REG64_FLD( EX_PPM_PFCS_VCS_PFET_ENABLE_VALUE , 24 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_ENABLE_VALUE ); REG64_FLD( EX_PPM_PFCS_VCS_PFET_ENABLE_VALUE_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_ENABLE_VALUE_LEN ); REG64_FLD( EX_PPM_PFCS_VCS_PFET_SEL_VALUE , 32 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_SEL_VALUE ); REG64_FLD( EX_PPM_PFCS_VCS_PFET_SEL_VALUE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_SEL_VALUE_LEN ); REG64_FLD( EX_PPM_PFCS_VDD_PG_STATE , 42 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VDD_PG_STATE ); REG64_FLD( EX_PPM_PFCS_VDD_PG_STATE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VDD_PG_STATE_LEN ); REG64_FLD( EX_PPM_PFCS_VDD_PG_SEL , 46 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VDD_PG_SEL ); REG64_FLD( EX_PPM_PFCS_VDD_PG_SEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VDD_PG_SEL_LEN ); REG64_FLD( EX_PPM_PFCS_VCS_PG_STATE , 50 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VCS_PG_STATE ); REG64_FLD( EX_PPM_PFCS_VCS_PG_STATE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VCS_PG_STATE_LEN ); REG64_FLD( EX_PPM_PFCS_VCS_PG_SEL , 54 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VCS_PG_SEL ); REG64_FLD( EX_PPM_PFCS_VCS_PG_SEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM2 , SH_FLD_VCS_PG_SEL_LEN ); REG64_FLD( C_PPM_PFCS_VDD_PFET_FORCE_STATE , 0 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_FORCE_STATE ); REG64_FLD( C_PPM_PFCS_VDD_PFET_FORCE_STATE_LEN , 2 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_FORCE_STATE_LEN ); REG64_FLD( C_PPM_PFCS_VCS_PFET_FORCE_STATE , 2 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_FORCE_STATE ); REG64_FLD( C_PPM_PFCS_VCS_PFET_FORCE_STATE_LEN , 2 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_FORCE_STATE_LEN ); REG64_FLD( C_PPM_PFCS_VDD_PFET_VAL_OVERRIDE , 4 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_VAL_OVERRIDE ); REG64_FLD( C_PPM_PFCS_VDD_PFET_SEL_OVERRIDE , 5 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_SEL_OVERRIDE ); REG64_FLD( C_PPM_PFCS_VCS_PFET_VAL_OVERRIDE , 6 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_VAL_OVERRIDE ); REG64_FLD( C_PPM_PFCS_VCS_PFET_SEL_OVERRIDE , 7 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_SEL_OVERRIDE ); REG64_FLD( C_PPM_PFCS_VDD_PFET_REGULATION_FINGER_EN , 8 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_REGULATION_FINGER_EN ); REG64_FLD( C_PPM_PFCS_VDD_PFET_REGULATION_FINGER_VALUE , 9 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_REGULATION_FINGER_VALUE ); REG64_FLD( C_PPM_PFCS_RESERVED_10_11 , 10 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_RESERVED_10_11 ); REG64_FLD( C_PPM_PFCS_RESERVED_10_11_LEN , 2 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_RESERVED_10_11_LEN ); REG64_FLD( C_PPM_PFCS_VDD_PFET_ENABLE_VALUE , 12 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_ENABLE_VALUE ); REG64_FLD( C_PPM_PFCS_VDD_PFET_ENABLE_VALUE_LEN , 8 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_ENABLE_VALUE_LEN ); REG64_FLD( C_PPM_PFCS_VDD_PFET_SEL_VALUE , 20 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_SEL_VALUE ); REG64_FLD( C_PPM_PFCS_VDD_PFET_SEL_VALUE_LEN , 4 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VDD_PFET_SEL_VALUE_LEN ); REG64_FLD( C_PPM_PFCS_VCS_PFET_ENABLE_VALUE , 24 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_ENABLE_VALUE ); REG64_FLD( C_PPM_PFCS_VCS_PFET_ENABLE_VALUE_LEN , 8 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_ENABLE_VALUE_LEN ); REG64_FLD( C_PPM_PFCS_VCS_PFET_SEL_VALUE , 32 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_SEL_VALUE ); REG64_FLD( C_PPM_PFCS_VCS_PFET_SEL_VALUE_LEN , 4 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VCS_PFET_SEL_VALUE_LEN ); REG64_FLD( C_PPM_PFCS_VDD_PG_STATE , 42 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VDD_PG_STATE ); REG64_FLD( C_PPM_PFCS_VDD_PG_STATE_LEN , 4 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VDD_PG_STATE_LEN ); REG64_FLD( C_PPM_PFCS_VDD_PG_SEL , 46 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VDD_PG_SEL ); REG64_FLD( C_PPM_PFCS_VDD_PG_SEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VDD_PG_SEL_LEN ); REG64_FLD( C_PPM_PFCS_VCS_PG_STATE , 50 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VCS_PG_STATE ); REG64_FLD( C_PPM_PFCS_VCS_PG_STATE_LEN , 4 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VCS_PG_STATE_LEN ); REG64_FLD( C_PPM_PFCS_VCS_PG_SEL , 54 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VCS_PG_SEL ); REG64_FLD( C_PPM_PFCS_VCS_PG_SEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM2 , SH_FLD_VCS_PG_SEL_LEN ); REG64_FLD( EQ_PPM_PFDLY_POWDN_DLY , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_POWDN_DLY ); REG64_FLD( EQ_PPM_PFDLY_POWDN_DLY_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_POWDN_DLY_LEN ); REG64_FLD( EQ_PPM_PFDLY_POWUP_DLY , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_POWUP_DLY ); REG64_FLD( EQ_PPM_PFDLY_POWUP_DLY_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_POWUP_DLY_LEN ); REG64_FLD( EX_PPM_PFDLY_POWDN_DLY , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_POWDN_DLY ); REG64_FLD( EX_PPM_PFDLY_POWDN_DLY_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_POWDN_DLY_LEN ); REG64_FLD( EX_PPM_PFDLY_POWUP_DLY , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_POWUP_DLY ); REG64_FLD( EX_PPM_PFDLY_POWUP_DLY_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_POWUP_DLY_LEN ); REG64_FLD( C_PPM_PFDLY_POWDN_DLY , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_POWDN_DLY ); REG64_FLD( C_PPM_PFDLY_POWDN_DLY_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_POWDN_DLY_LEN ); REG64_FLD( C_PPM_PFDLY_POWUP_DLY , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_POWUP_DLY ); REG64_FLD( C_PPM_PFDLY_POWUP_DLY_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_POWUP_DLY_LEN ); REG64_FLD( EQ_PPM_PFOFF_VDD_VOFF_SEL , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VDD_VOFF_SEL ); REG64_FLD( EQ_PPM_PFOFF_VDD_VOFF_SEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VDD_VOFF_SEL_LEN ); REG64_FLD( EQ_PPM_PFOFF_VCS_VOFF_SEL , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VCS_VOFF_SEL ); REG64_FLD( EQ_PPM_PFOFF_VCS_VOFF_SEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VCS_VOFF_SEL_LEN ); REG64_FLD( EX_PPM_PFOFF_VDD_VOFF_SEL , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_VDD_VOFF_SEL ); REG64_FLD( EX_PPM_PFOFF_VDD_VOFF_SEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_VDD_VOFF_SEL_LEN ); REG64_FLD( EX_PPM_PFOFF_VCS_VOFF_SEL , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_VCS_VOFF_SEL ); REG64_FLD( EX_PPM_PFOFF_VCS_VOFF_SEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_VCS_VOFF_SEL_LEN ); REG64_FLD( C_PPM_PFOFF_VDD_VOFF_SEL , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_VDD_VOFF_SEL ); REG64_FLD( C_PPM_PFOFF_VDD_VOFF_SEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_VDD_VOFF_SEL_LEN ); REG64_FLD( C_PPM_PFOFF_VCS_VOFF_SEL , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_VCS_VOFF_SEL ); REG64_FLD( C_PPM_PFOFF_VCS_VOFF_SEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_VCS_VOFF_SEL_LEN ); REG64_FLD( EQ_PPM_PFSNS_VDD_PFETS_ENABLED_SENSE , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VDD_PFETS_ENABLED_SENSE ); REG64_FLD( EQ_PPM_PFSNS_VDD_PFETS_DISABLED_SENSE , 1 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VDD_PFETS_DISABLED_SENSE ); REG64_FLD( EQ_PPM_PFSNS_VCS_PFETS_ENABLED_SENSE , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VCS_PFETS_ENABLED_SENSE ); REG64_FLD( EQ_PPM_PFSNS_VCS_PFETS_DISABLED_SENSE , 3 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VCS_PFETS_DISABLED_SENSE ); REG64_FLD( EQ_PPM_PFSNS_RESERVED_4_15 , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RESERVED_4_15 ); REG64_FLD( EQ_PPM_PFSNS_RESERVED_4_15_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RESERVED_4_15_LEN ); REG64_FLD( EQ_PPM_PFSNS_TP_VDD_PFET_ENABLE_ACTUAL , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_TP_VDD_PFET_ENABLE_ACTUAL ); REG64_FLD( EQ_PPM_PFSNS_TP_VDD_PFET_ENABLE_ACTUAL_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_TP_VDD_PFET_ENABLE_ACTUAL_LEN ); REG64_FLD( EQ_PPM_PFSNS_TP_VCS_PFET_ENABLE_ACTUAL , 24 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_TP_VCS_PFET_ENABLE_ACTUAL ); REG64_FLD( EQ_PPM_PFSNS_TP_VCS_PFET_ENABLE_ACTUAL_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_TP_VCS_PFET_ENABLE_ACTUAL_LEN ); REG64_FLD( EQ_PPM_PFSNS_VDD_PG_STATE , 42 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VDD_PG_STATE ); REG64_FLD( EQ_PPM_PFSNS_VDD_PG_STATE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VDD_PG_STATE_LEN ); REG64_FLD( EQ_PPM_PFSNS_VDD_PG_SEL , 46 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VDD_PG_SEL ); REG64_FLD( EQ_PPM_PFSNS_VDD_PG_SEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VDD_PG_SEL_LEN ); REG64_FLD( EQ_PPM_PFSNS_VCS_PG_STATE , 50 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VCS_PG_STATE ); REG64_FLD( EQ_PPM_PFSNS_VCS_PG_STATE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VCS_PG_STATE_LEN ); REG64_FLD( EQ_PPM_PFSNS_VCS_PG_SEL , 54 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VCS_PG_SEL ); REG64_FLD( EQ_PPM_PFSNS_VCS_PG_SEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VCS_PG_SEL_LEN ); REG64_FLD( EX_PPM_PFSNS_VDD_PFETS_ENABLED_SENSE , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VDD_PFETS_ENABLED_SENSE ); REG64_FLD( EX_PPM_PFSNS_VDD_PFETS_DISABLED_SENSE , 1 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VDD_PFETS_DISABLED_SENSE ); REG64_FLD( EX_PPM_PFSNS_VCS_PFETS_ENABLED_SENSE , 2 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VCS_PFETS_ENABLED_SENSE ); REG64_FLD( EX_PPM_PFSNS_VCS_PFETS_DISABLED_SENSE , 3 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VCS_PFETS_DISABLED_SENSE ); REG64_FLD( EX_PPM_PFSNS_RESERVED_4_15 , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_RESERVED_4_15 ); REG64_FLD( EX_PPM_PFSNS_RESERVED_4_15_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_RESERVED_4_15_LEN ); REG64_FLD( EX_PPM_PFSNS_TP_VDD_PFET_ENABLE_ACTUAL , 16 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_TP_VDD_PFET_ENABLE_ACTUAL ); REG64_FLD( EX_PPM_PFSNS_TP_VDD_PFET_ENABLE_ACTUAL_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_TP_VDD_PFET_ENABLE_ACTUAL_LEN ); REG64_FLD( EX_PPM_PFSNS_TP_VCS_PFET_ENABLE_ACTUAL , 24 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_TP_VCS_PFET_ENABLE_ACTUAL ); REG64_FLD( EX_PPM_PFSNS_TP_VCS_PFET_ENABLE_ACTUAL_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_TP_VCS_PFET_ENABLE_ACTUAL_LEN ); REG64_FLD( EX_PPM_PFSNS_VDD_PG_STATE , 42 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VDD_PG_STATE ); REG64_FLD( EX_PPM_PFSNS_VDD_PG_STATE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VDD_PG_STATE_LEN ); REG64_FLD( EX_PPM_PFSNS_VDD_PG_SEL , 46 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VDD_PG_SEL ); REG64_FLD( EX_PPM_PFSNS_VDD_PG_SEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VDD_PG_SEL_LEN ); REG64_FLD( EX_PPM_PFSNS_VCS_PG_STATE , 50 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VCS_PG_STATE ); REG64_FLD( EX_PPM_PFSNS_VCS_PG_STATE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VCS_PG_STATE_LEN ); REG64_FLD( EX_PPM_PFSNS_VCS_PG_SEL , 54 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VCS_PG_SEL ); REG64_FLD( EX_PPM_PFSNS_VCS_PG_SEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VCS_PG_SEL_LEN ); REG64_FLD( C_PPM_PFSNS_VDD_PFETS_ENABLED_SENSE , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VDD_PFETS_ENABLED_SENSE ); REG64_FLD( C_PPM_PFSNS_VDD_PFETS_DISABLED_SENSE , 1 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VDD_PFETS_DISABLED_SENSE ); REG64_FLD( C_PPM_PFSNS_VCS_PFETS_ENABLED_SENSE , 2 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VCS_PFETS_ENABLED_SENSE ); REG64_FLD( C_PPM_PFSNS_VCS_PFETS_DISABLED_SENSE , 3 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VCS_PFETS_DISABLED_SENSE ); REG64_FLD( C_PPM_PFSNS_RESERVED_4_15 , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_RESERVED_4_15 ); REG64_FLD( C_PPM_PFSNS_RESERVED_4_15_LEN , 12 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_RESERVED_4_15_LEN ); REG64_FLD( C_PPM_PFSNS_TP_VDD_PFET_ENABLE_ACTUAL , 16 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_TP_VDD_PFET_ENABLE_ACTUAL ); REG64_FLD( C_PPM_PFSNS_TP_VDD_PFET_ENABLE_ACTUAL_LEN , 8 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_TP_VDD_PFET_ENABLE_ACTUAL_LEN ); REG64_FLD( C_PPM_PFSNS_TP_VCS_PFET_ENABLE_ACTUAL , 24 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_TP_VCS_PFET_ENABLE_ACTUAL ); REG64_FLD( C_PPM_PFSNS_TP_VCS_PFET_ENABLE_ACTUAL_LEN , 8 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_TP_VCS_PFET_ENABLE_ACTUAL_LEN ); REG64_FLD( C_PPM_PFSNS_VDD_PG_STATE , 42 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VDD_PG_STATE ); REG64_FLD( C_PPM_PFSNS_VDD_PG_STATE_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VDD_PG_STATE_LEN ); REG64_FLD( C_PPM_PFSNS_VDD_PG_SEL , 46 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VDD_PG_SEL ); REG64_FLD( C_PPM_PFSNS_VDD_PG_SEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VDD_PG_SEL_LEN ); REG64_FLD( C_PPM_PFSNS_VCS_PG_STATE , 50 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VCS_PG_STATE ); REG64_FLD( C_PPM_PFSNS_VCS_PG_STATE_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VCS_PG_STATE_LEN ); REG64_FLD( C_PPM_PFSNS_VCS_PG_SEL , 54 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VCS_PG_SEL ); REG64_FLD( C_PPM_PFSNS_VCS_PG_SEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VCS_PG_SEL_LEN ); REG64_FLD( EQ_PPM_PIG_REQ_INTR_TYPE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_REQ_INTR_TYPE ); REG64_FLD( EQ_PPM_PIG_REQ_INTR_TYPE_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_REQ_INTR_TYPE_LEN ); REG64_FLD( EQ_PPM_PIG_REQ_INTR_PAYLOAD , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_REQ_INTR_PAYLOAD ); REG64_FLD( EQ_PPM_PIG_REQ_INTR_PAYLOAD_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_REQ_INTR_PAYLOAD_LEN ); REG64_FLD( EQ_PPM_PIG_GRANTED_PACKET , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GRANTED_PACKET ); REG64_FLD( EQ_PPM_PIG_GRANTED_PACKET_LEN , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GRANTED_PACKET_LEN ); REG64_FLD( EQ_PPM_PIG_INTR_GRANTED , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INTR_GRANTED ); REG64_FLD( EQ_PPM_PIG_GRANTED_SOURCE , 34 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GRANTED_SOURCE ); REG64_FLD( EQ_PPM_PIG_GRANTED_SOURCE_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GRANTED_SOURCE_LEN ); REG64_FLD( EQ_PPM_PIG_PENDING_SOURCE , 37 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PENDING_SOURCE ); REG64_FLD( EQ_PPM_PIG_PENDING_SOURCE_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PENDING_SOURCE_LEN ); REG64_FLD( EQ_PPM_PIG_NETWORK_RESET_OCCURRED , 40 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_NETWORK_RESET_OCCURRED ); REG64_FLD( EX_PPM_PIG_REQ_INTR_TYPE , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_REQ_INTR_TYPE ); REG64_FLD( EX_PPM_PIG_REQ_INTR_TYPE_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_REQ_INTR_TYPE_LEN ); REG64_FLD( EX_PPM_PIG_REQ_INTR_PAYLOAD , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_REQ_INTR_PAYLOAD ); REG64_FLD( EX_PPM_PIG_REQ_INTR_PAYLOAD_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_REQ_INTR_PAYLOAD_LEN ); REG64_FLD( EX_PPM_PIG_GRANTED_PACKET , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GRANTED_PACKET ); REG64_FLD( EX_PPM_PIG_GRANTED_PACKET_LEN , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GRANTED_PACKET_LEN ); REG64_FLD( EX_PPM_PIG_INTR_GRANTED , 32 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INTR_GRANTED ); REG64_FLD( EX_PPM_PIG_GRANTED_SOURCE , 34 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GRANTED_SOURCE ); REG64_FLD( EX_PPM_PIG_GRANTED_SOURCE_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GRANTED_SOURCE_LEN ); REG64_FLD( EX_PPM_PIG_PENDING_SOURCE , 37 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PENDING_SOURCE ); REG64_FLD( EX_PPM_PIG_PENDING_SOURCE_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PENDING_SOURCE_LEN ); REG64_FLD( EX_PPM_PIG_NETWORK_RESET_OCCURRED , 40 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_NETWORK_RESET_OCCURRED ); REG64_FLD( C_PPM_PIG_REQ_INTR_TYPE , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_REQ_INTR_TYPE ); REG64_FLD( C_PPM_PIG_REQ_INTR_TYPE_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_REQ_INTR_TYPE_LEN ); REG64_FLD( C_PPM_PIG_REQ_INTR_PAYLOAD , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_REQ_INTR_PAYLOAD ); REG64_FLD( C_PPM_PIG_REQ_INTR_PAYLOAD_LEN , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_REQ_INTR_PAYLOAD_LEN ); REG64_FLD( C_PPM_PIG_GRANTED_PACKET , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GRANTED_PACKET ); REG64_FLD( C_PPM_PIG_GRANTED_PACKET_LEN , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GRANTED_PACKET_LEN ); REG64_FLD( C_PPM_PIG_INTR_GRANTED , 32 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INTR_GRANTED ); REG64_FLD( C_PPM_PIG_GRANTED_SOURCE , 34 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GRANTED_SOURCE ); REG64_FLD( C_PPM_PIG_GRANTED_SOURCE_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GRANTED_SOURCE_LEN ); REG64_FLD( C_PPM_PIG_PENDING_SOURCE , 37 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PENDING_SOURCE ); REG64_FLD( C_PPM_PIG_PENDING_SOURCE_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PENDING_SOURCE_LEN ); REG64_FLD( C_PPM_PIG_NETWORK_RESET_OCCURRED , 40 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_NETWORK_RESET_OCCURRED ); REG64_FLD( EQ_PPM_SCRATCH0_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( EQ_PPM_SCRATCH0_DATA_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( EX_PPM_SCRATCH0_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( EX_PPM_SCRATCH0_DATA_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( C_PPM_SCRATCH0_DATA , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( C_PPM_SCRATCH0_DATA_LEN , 64 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( EQ_PPM_SCRATCH1_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( EQ_PPM_SCRATCH1_DATA_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( EX_PPM_SCRATCH1_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( EX_PPM_SCRATCH1_DATA_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( C_PPM_SCRATCH1_DATA , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( C_PPM_SCRATCH1_DATA_LEN , 64 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( EQ_PPM_SPWKUP_FSP_FSP_SPECIAL_WKUP , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_FSP_SPECIAL_WKUP ); REG64_FLD( EX_PPM_SPWKUP_FSP_FSP_SPECIAL_WKUP , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_FSP_SPECIAL_WKUP ); REG64_FLD( C_PPM_SPWKUP_FSP_FSP_SPECIAL_WKUP , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_FSP_SPECIAL_WKUP ); REG64_FLD( EQ_PPM_SPWKUP_HYP_HYP_SPECIAL_WKUP , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HYP_SPECIAL_WKUP ); REG64_FLD( EX_PPM_SPWKUP_HYP_HYP_SPECIAL_WKUP , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_HYP_SPECIAL_WKUP ); REG64_FLD( C_PPM_SPWKUP_HYP_HYP_SPECIAL_WKUP , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_HYP_SPECIAL_WKUP ); REG64_FLD( EQ_PPM_SPWKUP_OCC_OCC_SPECIAL_WKUP , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_OCC_SPECIAL_WKUP ); REG64_FLD( EX_PPM_SPWKUP_OCC_OCC_SPECIAL_WKUP , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_OCC_SPECIAL_WKUP ); REG64_FLD( C_PPM_SPWKUP_OCC_OCC_SPECIAL_WKUP , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_OCC_SPECIAL_WKUP ); REG64_FLD( EQ_PPM_SPWKUP_OTR_OTR_SPECIAL_WKUP , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_OTR_SPECIAL_WKUP ); REG64_FLD( EX_PPM_SPWKUP_OTR_OTR_SPECIAL_WKUP , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_OTR_SPECIAL_WKUP ); REG64_FLD( C_PPM_SPWKUP_OTR_OTR_SPECIAL_WKUP , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_OTR_SPECIAL_WKUP ); REG64_FLD( EQ_PPM_SSHFSP_STOP_GATED , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STOP_GATED ); REG64_FLD( EQ_PPM_SSHFSP_SPECIAL_WKUP_DONE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPECIAL_WKUP_DONE ); REG64_FLD( EQ_PPM_SSHFSP_STOP_TRANSITION , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION ); REG64_FLD( EQ_PPM_SSHFSP_STOP_TRANSITION_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION_LEN ); REG64_FLD( EQ_PPM_SSHFSP_REQ_STOP_LEVEL , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL ); REG64_FLD( EQ_PPM_SSHFSP_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL_LEN ); REG64_FLD( EQ_PPM_SSHFSP_ACT_STOP_LEVEL , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL ); REG64_FLD( EQ_PPM_SSHFSP_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL_LEN ); REG64_FLD( EQ_PPM_SSHFSP_DEEPEST_REQ_STOP_LEVEL_FSP , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_FSP ); REG64_FLD( EQ_PPM_SSHFSP_DEEPEST_REQ_STOP_LEVEL_FSP_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_FSP_LEN ); REG64_FLD( EQ_PPM_SSHFSP_DEEPEST_ACT_STOP_LEVEL_FSP , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_FSP ); REG64_FLD( EQ_PPM_SSHFSP_DEEPEST_ACT_STOP_LEVEL_FSP_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_FSP_LEN ); REG64_FLD( EQ_PPM_SSHFSP_IVRM_ENABLED_HISTORY_FSP , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IVRM_ENABLED_HISTORY_FSP ); REG64_FLD( EX_PPM_SSHFSP_STOP_GATED , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STOP_GATED ); REG64_FLD( EX_PPM_SSHFSP_SPECIAL_WKUP_DONE , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SPECIAL_WKUP_DONE ); REG64_FLD( EX_PPM_SSHFSP_STOP_TRANSITION , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION ); REG64_FLD( EX_PPM_SSHFSP_STOP_TRANSITION_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION_LEN ); REG64_FLD( EX_PPM_SSHFSP_REQ_STOP_LEVEL , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL ); REG64_FLD( EX_PPM_SSHFSP_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL_LEN ); REG64_FLD( EX_PPM_SSHFSP_ACT_STOP_LEVEL , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL ); REG64_FLD( EX_PPM_SSHFSP_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL_LEN ); REG64_FLD( EX_PPM_SSHFSP_DEEPEST_REQ_STOP_LEVEL_FSP , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_FSP ); REG64_FLD( EX_PPM_SSHFSP_DEEPEST_REQ_STOP_LEVEL_FSP_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_FSP_LEN ); REG64_FLD( EX_PPM_SSHFSP_DEEPEST_ACT_STOP_LEVEL_FSP , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_FSP ); REG64_FLD( EX_PPM_SSHFSP_DEEPEST_ACT_STOP_LEVEL_FSP_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_FSP_LEN ); REG64_FLD( EX_PPM_SSHFSP_IVRM_ENABLED_HISTORY_FSP , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IVRM_ENABLED_HISTORY_FSP ); REG64_FLD( C_PPM_SSHFSP_STOP_GATED , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STOP_GATED ); REG64_FLD( C_PPM_SSHFSP_SPECIAL_WKUP_DONE , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SPECIAL_WKUP_DONE ); REG64_FLD( C_PPM_SSHFSP_STOP_TRANSITION , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION ); REG64_FLD( C_PPM_SSHFSP_STOP_TRANSITION_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION_LEN ); REG64_FLD( C_PPM_SSHFSP_REQ_STOP_LEVEL , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL ); REG64_FLD( C_PPM_SSHFSP_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL_LEN ); REG64_FLD( C_PPM_SSHFSP_ACT_STOP_LEVEL , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL ); REG64_FLD( C_PPM_SSHFSP_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL_LEN ); REG64_FLD( C_PPM_SSHFSP_DEEPEST_REQ_STOP_LEVEL_FSP , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_FSP ); REG64_FLD( C_PPM_SSHFSP_DEEPEST_REQ_STOP_LEVEL_FSP_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_FSP_LEN ); REG64_FLD( C_PPM_SSHFSP_DEEPEST_ACT_STOP_LEVEL_FSP , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_FSP ); REG64_FLD( C_PPM_SSHFSP_DEEPEST_ACT_STOP_LEVEL_FSP_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_FSP_LEN ); REG64_FLD( C_PPM_SSHFSP_IVRM_ENABLED_HISTORY_FSP , 20 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IVRM_ENABLED_HISTORY_FSP ); REG64_FLD( EQ_PPM_SSHHYP_STOP_GATED , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STOP_GATED ); REG64_FLD( EQ_PPM_SSHHYP_SPECIAL_WKUP_DONE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPECIAL_WKUP_DONE ); REG64_FLD( EQ_PPM_SSHHYP_STOP_TRANSITION , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION ); REG64_FLD( EQ_PPM_SSHHYP_STOP_TRANSITION_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION_LEN ); REG64_FLD( EQ_PPM_SSHHYP_REQ_STOP_LEVEL , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL ); REG64_FLD( EQ_PPM_SSHHYP_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL_LEN ); REG64_FLD( EQ_PPM_SSHHYP_ACT_STOP_LEVEL , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL ); REG64_FLD( EQ_PPM_SSHHYP_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL_LEN ); REG64_FLD( EQ_PPM_SSHHYP_DEEPEST_REQ_STOP_LEVEL_HYP , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_HYP ); REG64_FLD( EQ_PPM_SSHHYP_DEEPEST_REQ_STOP_LEVEL_HYP_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_HYP_LEN ); REG64_FLD( EQ_PPM_SSHHYP_DEEPEST_ACT_STOP_LEVEL_HYP , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_HYP ); REG64_FLD( EQ_PPM_SSHHYP_DEEPEST_ACT_STOP_LEVEL_HYP_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_HYP_LEN ); REG64_FLD( EQ_PPM_SSHHYP_IVRM_ENABLED_HISTORY_HYP , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IVRM_ENABLED_HISTORY_HYP ); REG64_FLD( EX_PPM_SSHHYP_STOP_GATED , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STOP_GATED ); REG64_FLD( EX_PPM_SSHHYP_SPECIAL_WKUP_DONE , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SPECIAL_WKUP_DONE ); REG64_FLD( EX_PPM_SSHHYP_STOP_TRANSITION , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION ); REG64_FLD( EX_PPM_SSHHYP_STOP_TRANSITION_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION_LEN ); REG64_FLD( EX_PPM_SSHHYP_REQ_STOP_LEVEL , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL ); REG64_FLD( EX_PPM_SSHHYP_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL_LEN ); REG64_FLD( EX_PPM_SSHHYP_ACT_STOP_LEVEL , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL ); REG64_FLD( EX_PPM_SSHHYP_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL_LEN ); REG64_FLD( EX_PPM_SSHHYP_DEEPEST_REQ_STOP_LEVEL_HYP , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_HYP ); REG64_FLD( EX_PPM_SSHHYP_DEEPEST_REQ_STOP_LEVEL_HYP_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_HYP_LEN ); REG64_FLD( EX_PPM_SSHHYP_DEEPEST_ACT_STOP_LEVEL_HYP , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_HYP ); REG64_FLD( EX_PPM_SSHHYP_DEEPEST_ACT_STOP_LEVEL_HYP_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_HYP_LEN ); REG64_FLD( EX_PPM_SSHHYP_IVRM_ENABLED_HISTORY_HYP , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IVRM_ENABLED_HISTORY_HYP ); REG64_FLD( C_PPM_SSHHYP_STOP_GATED , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STOP_GATED ); REG64_FLD( C_PPM_SSHHYP_SPECIAL_WKUP_DONE , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SPECIAL_WKUP_DONE ); REG64_FLD( C_PPM_SSHHYP_STOP_TRANSITION , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION ); REG64_FLD( C_PPM_SSHHYP_STOP_TRANSITION_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION_LEN ); REG64_FLD( C_PPM_SSHHYP_REQ_STOP_LEVEL , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL ); REG64_FLD( C_PPM_SSHHYP_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL_LEN ); REG64_FLD( C_PPM_SSHHYP_ACT_STOP_LEVEL , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL ); REG64_FLD( C_PPM_SSHHYP_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL_LEN ); REG64_FLD( C_PPM_SSHHYP_DEEPEST_REQ_STOP_LEVEL_HYP , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_HYP ); REG64_FLD( C_PPM_SSHHYP_DEEPEST_REQ_STOP_LEVEL_HYP_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_HYP_LEN ); REG64_FLD( C_PPM_SSHHYP_DEEPEST_ACT_STOP_LEVEL_HYP , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_HYP ); REG64_FLD( C_PPM_SSHHYP_DEEPEST_ACT_STOP_LEVEL_HYP_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_HYP_LEN ); REG64_FLD( C_PPM_SSHHYP_IVRM_ENABLED_HISTORY_HYP , 20 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IVRM_ENABLED_HISTORY_HYP ); REG64_FLD( EQ_PPM_SSHOCC_STOP_GATED , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STOP_GATED ); REG64_FLD( EQ_PPM_SSHOCC_SPECIAL_WKUP_DONE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPECIAL_WKUP_DONE ); REG64_FLD( EQ_PPM_SSHOCC_STOP_TRANSITION , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION ); REG64_FLD( EQ_PPM_SSHOCC_STOP_TRANSITION_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION_LEN ); REG64_FLD( EQ_PPM_SSHOCC_REQ_STOP_LEVEL , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL ); REG64_FLD( EQ_PPM_SSHOCC_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL_LEN ); REG64_FLD( EQ_PPM_SSHOCC_ACT_STOP_LEVEL , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL ); REG64_FLD( EQ_PPM_SSHOCC_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL_LEN ); REG64_FLD( EQ_PPM_SSHOCC_DEEPEST_REQ_STOP_LEVEL_OCC , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_OCC ); REG64_FLD( EQ_PPM_SSHOCC_DEEPEST_REQ_STOP_LEVEL_OCC_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_OCC_LEN ); REG64_FLD( EQ_PPM_SSHOCC_DEEPEST_ACT_STOP_LEVEL_OCC , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_OCC ); REG64_FLD( EQ_PPM_SSHOCC_DEEPEST_ACT_STOP_LEVEL_OCC_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_OCC_LEN ); REG64_FLD( EQ_PPM_SSHOCC_IVRM_ENABLED_HISTORY_OCC , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IVRM_ENABLED_HISTORY_OCC ); REG64_FLD( EX_PPM_SSHOCC_STOP_GATED , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STOP_GATED ); REG64_FLD( EX_PPM_SSHOCC_SPECIAL_WKUP_DONE , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SPECIAL_WKUP_DONE ); REG64_FLD( EX_PPM_SSHOCC_STOP_TRANSITION , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION ); REG64_FLD( EX_PPM_SSHOCC_STOP_TRANSITION_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION_LEN ); REG64_FLD( EX_PPM_SSHOCC_REQ_STOP_LEVEL , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL ); REG64_FLD( EX_PPM_SSHOCC_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL_LEN ); REG64_FLD( EX_PPM_SSHOCC_ACT_STOP_LEVEL , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL ); REG64_FLD( EX_PPM_SSHOCC_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL_LEN ); REG64_FLD( EX_PPM_SSHOCC_DEEPEST_REQ_STOP_LEVEL_OCC , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_OCC ); REG64_FLD( EX_PPM_SSHOCC_DEEPEST_REQ_STOP_LEVEL_OCC_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_OCC_LEN ); REG64_FLD( EX_PPM_SSHOCC_DEEPEST_ACT_STOP_LEVEL_OCC , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_OCC ); REG64_FLD( EX_PPM_SSHOCC_DEEPEST_ACT_STOP_LEVEL_OCC_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_OCC_LEN ); REG64_FLD( EX_PPM_SSHOCC_IVRM_ENABLED_HISTORY_OCC , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IVRM_ENABLED_HISTORY_OCC ); REG64_FLD( C_PPM_SSHOCC_STOP_GATED , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STOP_GATED ); REG64_FLD( C_PPM_SSHOCC_SPECIAL_WKUP_DONE , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SPECIAL_WKUP_DONE ); REG64_FLD( C_PPM_SSHOCC_STOP_TRANSITION , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION ); REG64_FLD( C_PPM_SSHOCC_STOP_TRANSITION_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION_LEN ); REG64_FLD( C_PPM_SSHOCC_REQ_STOP_LEVEL , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL ); REG64_FLD( C_PPM_SSHOCC_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL_LEN ); REG64_FLD( C_PPM_SSHOCC_ACT_STOP_LEVEL , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL ); REG64_FLD( C_PPM_SSHOCC_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL_LEN ); REG64_FLD( C_PPM_SSHOCC_DEEPEST_REQ_STOP_LEVEL_OCC , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_OCC ); REG64_FLD( C_PPM_SSHOCC_DEEPEST_REQ_STOP_LEVEL_OCC_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_OCC_LEN ); REG64_FLD( C_PPM_SSHOCC_DEEPEST_ACT_STOP_LEVEL_OCC , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_OCC ); REG64_FLD( C_PPM_SSHOCC_DEEPEST_ACT_STOP_LEVEL_OCC_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_OCC_LEN ); REG64_FLD( C_PPM_SSHOCC_IVRM_ENABLED_HISTORY_OCC , 20 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IVRM_ENABLED_HISTORY_OCC ); REG64_FLD( EQ_PPM_SSHOTR_STOP_GATED , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STOP_GATED ); REG64_FLD( EQ_PPM_SSHOTR_SPECIAL_WKUP_DONE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPECIAL_WKUP_DONE ); REG64_FLD( EQ_PPM_SSHOTR_STOP_TRANSITION , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION ); REG64_FLD( EQ_PPM_SSHOTR_STOP_TRANSITION_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION_LEN ); REG64_FLD( EQ_PPM_SSHOTR_REQ_STOP_LEVEL , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL ); REG64_FLD( EQ_PPM_SSHOTR_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL_LEN ); REG64_FLD( EQ_PPM_SSHOTR_ACT_STOP_LEVEL , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL ); REG64_FLD( EQ_PPM_SSHOTR_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL_LEN ); REG64_FLD( EQ_PPM_SSHOTR_DEEPEST_REQ_STOP_LEVEL_OTR , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_OTR ); REG64_FLD( EQ_PPM_SSHOTR_DEEPEST_REQ_STOP_LEVEL_OTR_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_OTR_LEN ); REG64_FLD( EQ_PPM_SSHOTR_DEEPEST_ACT_STOP_LEVEL_OTR , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_OTR ); REG64_FLD( EQ_PPM_SSHOTR_DEEPEST_ACT_STOP_LEVEL_OTR_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_OTR_LEN ); REG64_FLD( EQ_PPM_SSHOTR_IVRM_ENABLED_HISTORY_OTR , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IVRM_ENABLED_HISTORY_OTR ); REG64_FLD( EX_PPM_SSHOTR_STOP_GATED , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STOP_GATED ); REG64_FLD( EX_PPM_SSHOTR_SPECIAL_WKUP_DONE , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SPECIAL_WKUP_DONE ); REG64_FLD( EX_PPM_SSHOTR_STOP_TRANSITION , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION ); REG64_FLD( EX_PPM_SSHOTR_STOP_TRANSITION_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION_LEN ); REG64_FLD( EX_PPM_SSHOTR_REQ_STOP_LEVEL , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL ); REG64_FLD( EX_PPM_SSHOTR_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL_LEN ); REG64_FLD( EX_PPM_SSHOTR_ACT_STOP_LEVEL , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL ); REG64_FLD( EX_PPM_SSHOTR_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL_LEN ); REG64_FLD( EX_PPM_SSHOTR_DEEPEST_REQ_STOP_LEVEL_OTR , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_OTR ); REG64_FLD( EX_PPM_SSHOTR_DEEPEST_REQ_STOP_LEVEL_OTR_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_OTR_LEN ); REG64_FLD( EX_PPM_SSHOTR_DEEPEST_ACT_STOP_LEVEL_OTR , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_OTR ); REG64_FLD( EX_PPM_SSHOTR_DEEPEST_ACT_STOP_LEVEL_OTR_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_OTR_LEN ); REG64_FLD( EX_PPM_SSHOTR_IVRM_ENABLED_HISTORY_OTR , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IVRM_ENABLED_HISTORY_OTR ); REG64_FLD( C_PPM_SSHOTR_STOP_GATED , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STOP_GATED ); REG64_FLD( C_PPM_SSHOTR_SPECIAL_WKUP_DONE , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SPECIAL_WKUP_DONE ); REG64_FLD( C_PPM_SSHOTR_STOP_TRANSITION , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION ); REG64_FLD( C_PPM_SSHOTR_STOP_TRANSITION_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION_LEN ); REG64_FLD( C_PPM_SSHOTR_REQ_STOP_LEVEL , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL ); REG64_FLD( C_PPM_SSHOTR_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL_LEN ); REG64_FLD( C_PPM_SSHOTR_ACT_STOP_LEVEL , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL ); REG64_FLD( C_PPM_SSHOTR_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL_LEN ); REG64_FLD( C_PPM_SSHOTR_DEEPEST_REQ_STOP_LEVEL_OTR , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_OTR ); REG64_FLD( C_PPM_SSHOTR_DEEPEST_REQ_STOP_LEVEL_OTR_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DEEPEST_REQ_STOP_LEVEL_OTR_LEN ); REG64_FLD( C_PPM_SSHOTR_DEEPEST_ACT_STOP_LEVEL_OTR , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_OTR ); REG64_FLD( C_PPM_SSHOTR_DEEPEST_ACT_STOP_LEVEL_OTR_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DEEPEST_ACT_STOP_LEVEL_OTR_LEN ); REG64_FLD( C_PPM_SSHOTR_IVRM_ENABLED_HISTORY_OTR , 20 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IVRM_ENABLED_HISTORY_OTR ); REG64_FLD( EQ_PPM_SSHSRC_STOP_GATED , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STOP_GATED ); REG64_FLD( EQ_PPM_SSHSRC_SPECIAL_WKUP_DONE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPECIAL_WKUP_DONE ); REG64_FLD( EQ_PPM_SSHSRC_STOP_TRANSITION , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION ); REG64_FLD( EQ_PPM_SSHSRC_STOP_TRANSITION_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION_LEN ); REG64_FLD( EQ_PPM_SSHSRC_REQ_STOP_LEVEL , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL ); REG64_FLD( EQ_PPM_SSHSRC_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL_LEN ); REG64_FLD( EQ_PPM_SSHSRC_ACT_STOP_LEVEL , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL ); REG64_FLD( EQ_PPM_SSHSRC_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL_LEN ); REG64_FLD( EQ_PPM_SSHSRC_REQ_WRITE_ENABLE , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_REQ_WRITE_ENABLE ); REG64_FLD( EQ_PPM_SSHSRC_ACT_WRITE_ENABLE , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACT_WRITE_ENABLE ); REG64_FLD( EX_PPM_SSHSRC_STOP_GATED , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STOP_GATED ); REG64_FLD( EX_PPM_SSHSRC_SPECIAL_WKUP_DONE , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SPECIAL_WKUP_DONE ); REG64_FLD( EX_PPM_SSHSRC_STOP_TRANSITION , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION ); REG64_FLD( EX_PPM_SSHSRC_STOP_TRANSITION_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION_LEN ); REG64_FLD( EX_PPM_SSHSRC_REQ_STOP_LEVEL , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL ); REG64_FLD( EX_PPM_SSHSRC_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL_LEN ); REG64_FLD( EX_PPM_SSHSRC_ACT_STOP_LEVEL , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL ); REG64_FLD( EX_PPM_SSHSRC_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL_LEN ); REG64_FLD( EX_PPM_SSHSRC_REQ_WRITE_ENABLE , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_REQ_WRITE_ENABLE ); REG64_FLD( EX_PPM_SSHSRC_ACT_WRITE_ENABLE , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACT_WRITE_ENABLE ); REG64_FLD( C_PPM_SSHSRC_STOP_GATED , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STOP_GATED ); REG64_FLD( C_PPM_SSHSRC_SPECIAL_WKUP_DONE , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SPECIAL_WKUP_DONE ); REG64_FLD( C_PPM_SSHSRC_STOP_TRANSITION , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION ); REG64_FLD( C_PPM_SSHSRC_STOP_TRANSITION_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_STOP_TRANSITION_LEN ); REG64_FLD( C_PPM_SSHSRC_REQ_STOP_LEVEL , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL ); REG64_FLD( C_PPM_SSHSRC_REQ_STOP_LEVEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_REQ_STOP_LEVEL_LEN ); REG64_FLD( C_PPM_SSHSRC_ACT_STOP_LEVEL , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL ); REG64_FLD( C_PPM_SSHSRC_ACT_STOP_LEVEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACT_STOP_LEVEL_LEN ); REG64_FLD( C_PPM_SSHSRC_REQ_WRITE_ENABLE , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_REQ_WRITE_ENABLE ); REG64_FLD( C_PPM_SSHSRC_ACT_WRITE_ENABLE , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACT_WRITE_ENABLE ); REG64_FLD( EQ_PPM_VDMCR_VDM_POWERON , 0 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_VDM_POWERON ); REG64_FLD( EQ_PPM_VDMCR_VDM_DISABLE , 1 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_VDM_DISABLE ); REG64_FLD( EX_PPM_VDMCR_VDM_POWERON , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_VDM_POWERON ); REG64_FLD( EX_PPM_VDMCR_VDM_DISABLE , 1 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_VDM_DISABLE ); REG64_FLD( C_PPM_VDMCR_VDM_POWERON , 0 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_VDM_POWERON ); REG64_FLD( C_PPM_VDMCR_VDM_DISABLE , 1 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_VDM_DISABLE ); REG64_FLD( EQ_PRD_PURGE_CMD_REG_TRIGGER , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIGGER ); REG64_FLD( EQ_PRD_PURGE_CMD_REG_TYPE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TYPE ); REG64_FLD( EQ_PRD_PURGE_CMD_REG_TYPE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TYPE_LEN ); REG64_FLD( EQ_PRD_PURGE_CMD_REG_BUSY , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_BUSY ); REG64_FLD( EQ_PRD_PURGE_CMD_REG_PRGSM_BUSY_ON_THIS , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PRGSM_BUSY_ON_THIS ); REG64_FLD( EQ_PRD_PURGE_CMD_REG_PRGSM_BUSY , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PRGSM_BUSY ); REG64_FLD( EQ_PRD_PURGE_CMD_REG_MEM , 17 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MEM ); REG64_FLD( EQ_PRD_PURGE_CMD_REG_MEM_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MEM_LEN ); REG64_FLD( EQ_PRD_PURGE_CMD_REG_CGC , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CGC ); REG64_FLD( EQ_PRD_PURGE_CMD_REG_CGC_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CGC_LEN ); REG64_FLD( EQ_PRD_PURGE_CMD_REG_BANK , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_BANK ); REG64_FLD( EQ_PRD_PURGE_CMD_REG_ERR , 29 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERR ); REG64_FLD( EX_PRD_PURGE_CMD_REG_TRIGGER , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIGGER ); REG64_FLD( EX_PRD_PURGE_CMD_REG_TYPE , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TYPE ); REG64_FLD( EX_PRD_PURGE_CMD_REG_TYPE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TYPE_LEN ); REG64_FLD( EX_PRD_PURGE_CMD_REG_BUSY , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_BUSY ); REG64_FLD( EX_PRD_PURGE_CMD_REG_PRGSM_BUSY_ON_THIS , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PRGSM_BUSY_ON_THIS ); REG64_FLD( EX_PRD_PURGE_CMD_REG_PRGSM_BUSY , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PRGSM_BUSY ); REG64_FLD( EX_PRD_PURGE_CMD_REG_MEM , 17 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MEM ); REG64_FLD( EX_PRD_PURGE_CMD_REG_MEM_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MEM_LEN ); REG64_FLD( EX_PRD_PURGE_CMD_REG_CGC , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CGC ); REG64_FLD( EX_PRD_PURGE_CMD_REG_CGC_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CGC_LEN ); REG64_FLD( EX_PRD_PURGE_CMD_REG_BANK , 28 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_BANK ); REG64_FLD( EX_PRD_PURGE_CMD_REG_ERR , 29 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ERR ); REG64_FLD( EQ_PRD_PURGE_REG_L3_REQ , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_REQ ); REG64_FLD( EQ_PRD_PURGE_REG_L3_TTYPE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_TTYPE ); REG64_FLD( EQ_PRD_PURGE_REG_L3_TTYPE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_TTYPE_LEN ); REG64_FLD( EQ_PRD_PURGE_REG_L3_LINE_DEL_ON_NEXT_CE , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_LINE_DEL_ON_NEXT_CE ); REG64_FLD( EQ_PRD_PURGE_REG_L3_LINE_DEL_ON_ALL_CE , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_LINE_DEL_ON_ALL_CE ); REG64_FLD( EQ_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_1 , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_PRD_PURGE_RESERVED_1 ); REG64_FLD( EQ_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_1_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_PRD_PURGE_RESERVED_1_LEN ); REG64_FLD( EQ_PRD_PURGE_REG_L3_BUSY_ERR , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_BUSY_ERR ); REG64_FLD( EQ_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_2 , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_PRD_PURGE_RESERVED_2 ); REG64_FLD( EQ_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_2_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_PRD_PURGE_RESERVED_2_LEN ); REG64_FLD( EQ_PRD_PURGE_REG_L3_MEMBER , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_MEMBER ); REG64_FLD( EQ_PRD_PURGE_REG_L3_MEMBER_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_MEMBER_LEN ); REG64_FLD( EQ_PRD_PURGE_REG_L3_DIR_ADDR , 17 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_DIR_ADDR ); REG64_FLD( EQ_PRD_PURGE_REG_L3_DIR_ADDR_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L3_DIR_ADDR_LEN ); REG64_FLD( EX_PRD_PURGE_REG_L3_REQ , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_REQ ); REG64_FLD( EX_PRD_PURGE_REG_L3_TTYPE , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_TTYPE ); REG64_FLD( EX_PRD_PURGE_REG_L3_TTYPE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_TTYPE_LEN ); REG64_FLD( EX_PRD_PURGE_REG_L3_LINE_DEL_ON_NEXT_CE , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_LINE_DEL_ON_NEXT_CE ); REG64_FLD( EX_PRD_PURGE_REG_L3_LINE_DEL_ON_ALL_CE , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_LINE_DEL_ON_ALL_CE ); REG64_FLD( EX_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_1 , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_PRD_PURGE_RESERVED_1 ); REG64_FLD( EX_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_1_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_PRD_PURGE_RESERVED_1_LEN ); REG64_FLD( EX_PRD_PURGE_REG_L3_BUSY_ERR , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_BUSY_ERR ); REG64_FLD( EX_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_2 , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_PRD_PURGE_RESERVED_2 ); REG64_FLD( EX_PRD_PURGE_REG_L3_PRD_PURGE_RESERVED_2_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_PRD_PURGE_RESERVED_2_LEN ); REG64_FLD( EX_PRD_PURGE_REG_L3_MEMBER , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_MEMBER ); REG64_FLD( EX_PRD_PURGE_REG_L3_MEMBER_LEN , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_MEMBER_LEN ); REG64_FLD( EX_PRD_PURGE_REG_L3_DIR_ADDR , 17 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_DIR_ADDR ); REG64_FLD( EX_PRD_PURGE_REG_L3_DIR_ADDR_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_L3_DIR_ADDR_LEN ); REG64_FLD( EQ_PRE_COUNTER_REG_COUNTER , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COUNTER ); REG64_FLD( EQ_PRE_COUNTER_REG_COUNTER_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_COUNTER_LEN ); REG64_FLD( EX_PRE_COUNTER_REG_COUNTER , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COUNTER ); REG64_FLD( EX_PRE_COUNTER_REG_COUNTER_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_COUNTER_LEN ); REG64_FLD( C_PRE_COUNTER_REG_COUNTER , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COUNTER ); REG64_FLD( C_PRE_COUNTER_REG_COUNTER_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COUNTER_LEN ); REG64_FLD( EQ_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PRIMARY_ADDRESS ); REG64_FLD( EQ_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS_LEN , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PRIMARY_ADDRESS_LEN ); REG64_FLD( EX_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PRIMARY_ADDRESS ); REG64_FLD( EX_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PRIMARY_ADDRESS_LEN ); REG64_FLD( C_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PRIMARY_ADDRESS ); REG64_FLD( C_PRIMARY_ADDRESS_REG_PRIMARY_ADDRESS_LEN , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PRIMARY_ADDRESS_LEN ); REG64_FLD( EQ_PROTECT_MODE_REG_READ_ENABLE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_READ_ENABLE ); REG64_FLD( EQ_PROTECT_MODE_REG_WRITE_ENABLE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WRITE_ENABLE ); REG64_FLD( EX_PROTECT_MODE_REG_READ_ENABLE , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_READ_ENABLE ); REG64_FLD( EX_PROTECT_MODE_REG_WRITE_ENABLE , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WRITE_ENABLE ); REG64_FLD( C_PROTECT_MODE_REG_READ_ENABLE , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_READ_ENABLE ); REG64_FLD( C_PROTECT_MODE_REG_WRITE_ENABLE , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WRITE_ENABLE ); REG64_FLD( EQ_PSCOM_ERROR_MASK_PCB_WDATA_PARITY , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PCB_WDATA_PARITY ); REG64_FLD( EQ_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_PARITY ); REG64_FLD( EQ_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DL_RETURN_WDATA_PARITY ); REG64_FLD( EQ_PSCOM_ERROR_MASK_DL_RETURN_P0 , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DL_RETURN_P0 ); REG64_FLD( EQ_PSCOM_ERROR_MASK_UL_RDATA_PARITY , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UL_RDATA_PARITY ); REG64_FLD( EQ_PSCOM_ERROR_MASK_UL_P0 , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UL_P0 ); REG64_FLD( EQ_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( EQ_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PARITY_ON_P2S_MACHINE ); REG64_FLD( EQ_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( EQ_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( EQ_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( EQ_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PARALLEL_WRITE_NVLD ); REG64_FLD( EQ_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PARALLEL_READ_NVLD ); REG64_FLD( EQ_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PARALLEL_ADDR_INVALID ); REG64_FLD( EQ_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PCB_COMMAND_PARITY ); REG64_FLD( EQ_PSCOM_ERROR_MASK_GENERAL_TIMEOUT , 15 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_GENERAL_TIMEOUT ); REG64_FLD( EQ_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( EQ_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( EX_PSCOM_ERROR_MASK_PCB_WDATA_PARITY , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PCB_WDATA_PARITY ); REG64_FLD( EX_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_PARITY ); REG64_FLD( EX_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DL_RETURN_WDATA_PARITY ); REG64_FLD( EX_PSCOM_ERROR_MASK_DL_RETURN_P0 , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DL_RETURN_P0 ); REG64_FLD( EX_PSCOM_ERROR_MASK_UL_RDATA_PARITY , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UL_RDATA_PARITY ); REG64_FLD( EX_PSCOM_ERROR_MASK_UL_P0 , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UL_P0 ); REG64_FLD( EX_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( EX_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PARITY_ON_P2S_MACHINE ); REG64_FLD( EX_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( EX_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( EX_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( EX_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PARALLEL_WRITE_NVLD ); REG64_FLD( EX_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PARALLEL_READ_NVLD ); REG64_FLD( EX_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PARALLEL_ADDR_INVALID ); REG64_FLD( EX_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PCB_COMMAND_PARITY ); REG64_FLD( EX_PSCOM_ERROR_MASK_GENERAL_TIMEOUT , 15 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_GENERAL_TIMEOUT ); REG64_FLD( EX_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( EX_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( C_PSCOM_ERROR_MASK_PCB_WDATA_PARITY , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_WDATA_PARITY ); REG64_FLD( C_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_PARITY ); REG64_FLD( C_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DL_RETURN_WDATA_PARITY ); REG64_FLD( C_PSCOM_ERROR_MASK_DL_RETURN_P0 , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DL_RETURN_P0 ); REG64_FLD( C_PSCOM_ERROR_MASK_UL_RDATA_PARITY , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UL_RDATA_PARITY ); REG64_FLD( C_PSCOM_ERROR_MASK_UL_P0 , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UL_P0 ); REG64_FLD( C_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( C_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PARITY_ON_P2S_MACHINE ); REG64_FLD( C_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( C_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( C_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( C_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PARALLEL_WRITE_NVLD ); REG64_FLD( C_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PARALLEL_READ_NVLD ); REG64_FLD( C_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PARALLEL_ADDR_INVALID ); REG64_FLD( C_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PCB_COMMAND_PARITY ); REG64_FLD( C_PSCOM_ERROR_MASK_GENERAL_TIMEOUT , 15 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_GENERAL_TIMEOUT ); REG64_FLD( C_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( C_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( EQ_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR ); REG64_FLD( EQ_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR ); REG64_FLD( EQ_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR ); REG64_FLD( EQ_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR ); REG64_FLD( EQ_PSCOM_MODE_REG_WATCHDOG_ENABLE , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WATCHDOG_ENABLE ); REG64_FLD( EQ_PSCOM_MODE_REG_SCOM_HANG_LIMIT , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SCOM_HANG_LIMIT ); REG64_FLD( EQ_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SCOM_HANG_LIMIT_LEN ); REG64_FLD( EQ_PSCOM_MODE_REG_FORCE_ALL_RINGS , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FORCE_ALL_RINGS ); REG64_FLD( EQ_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE ); REG64_FLD( EQ_PSCOM_MODE_REG_RESERVED_LT , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RESERVED_LT ); REG64_FLD( EQ_PSCOM_MODE_REG_RESERVED_LT_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RESERVED_LT_LEN ); REG64_FLD( EX_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR ); REG64_FLD( EX_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR ); REG64_FLD( EX_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR ); REG64_FLD( EX_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR ); REG64_FLD( EX_PSCOM_MODE_REG_WATCHDOG_ENABLE , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WATCHDOG_ENABLE ); REG64_FLD( EX_PSCOM_MODE_REG_SCOM_HANG_LIMIT , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SCOM_HANG_LIMIT ); REG64_FLD( EX_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SCOM_HANG_LIMIT_LEN ); REG64_FLD( EX_PSCOM_MODE_REG_FORCE_ALL_RINGS , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FORCE_ALL_RINGS ); REG64_FLD( EX_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE ); REG64_FLD( EX_PSCOM_MODE_REG_RESERVED_LT , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESERVED_LT ); REG64_FLD( EX_PSCOM_MODE_REG_RESERVED_LT_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESERVED_LT_LEN ); REG64_FLD( C_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR ); REG64_FLD( C_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR ); REG64_FLD( C_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR ); REG64_FLD( C_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR ); REG64_FLD( C_PSCOM_MODE_REG_WATCHDOG_ENABLE , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WATCHDOG_ENABLE ); REG64_FLD( C_PSCOM_MODE_REG_SCOM_HANG_LIMIT , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SCOM_HANG_LIMIT ); REG64_FLD( C_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SCOM_HANG_LIMIT_LEN ); REG64_FLD( C_PSCOM_MODE_REG_FORCE_ALL_RINGS , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FORCE_ALL_RINGS ); REG64_FLD( C_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE ); REG64_FLD( C_PSCOM_MODE_REG_RESERVED_LT , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESERVED_LT ); REG64_FLD( C_PSCOM_MODE_REG_RESERVED_LT_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESERVED_LT_LEN ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_WDATA_PARITY ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACCUMULATED_DL_RETURN_P0 ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACCUMULATED_UL_RDATA_PARITY ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACCUMULATED_UL_P0 ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACCUMULATED_GENERAL_TIMEOUT ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_WDATA_PARITY ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_ADDRESS_PARITY ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 , 21 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRAPPED_DL_RETURN_P0 ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRAPPED_UL_RDATA_PARITY ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 , 23 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRAPPED_UL_P0 ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_READ_NVLD ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_COMMAND_PARITY ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT , 33 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRAPPED_GENERAL_TIMEOUT ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( EQ_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_WDATA_PARITY ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACCUMULATED_DL_RETURN_P0 ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACCUMULATED_UL_RDATA_PARITY ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACCUMULATED_UL_P0 ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACCUMULATED_GENERAL_TIMEOUT ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY , 18 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_WDATA_PARITY ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_ADDRESS_PARITY ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 , 21 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRAPPED_DL_RETURN_P0 ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY , 22 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRAPPED_UL_RDATA_PARITY ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 , 23 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRAPPED_UL_P0 ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_READ_NVLD ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_COMMAND_PARITY ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT , 33 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRAPPED_GENERAL_TIMEOUT ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( EX_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_WDATA_PARITY ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACCUMULATED_DL_RETURN_P0 ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACCUMULATED_UL_RDATA_PARITY ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACCUMULATED_UL_P0 ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACCUMULATED_GENERAL_TIMEOUT ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY , 18 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_WDATA_PARITY ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_ADDRESS_PARITY ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 , 21 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRAPPED_DL_RETURN_P0 ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY , 22 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRAPPED_UL_RDATA_PARITY ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 , 23 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRAPPED_UL_P0 ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_READ_NVLD ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_COMMAND_PARITY ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT , 33 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRAPPED_GENERAL_TIMEOUT ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( C_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( EX_L2_PWM_EVENTS_RESERVED_32 , 32 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32 ); REG64_FLD( EX_L2_PWM_EVENTS_FREQ_SCALE_A_THRESHOLD , 33 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_FREQ_SCALE_A_THRESHOLD ); REG64_FLD( EX_L2_PWM_EVENTS_FREQ_SCALE_A_THRESHOLD_LEN , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_FREQ_SCALE_A_THRESHOLD_LEN ); REG64_FLD( EX_L2_PWM_EVENTS_RESERVED_40 , 40 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_RESERVED_40 ); REG64_FLD( EX_L2_PWM_EVENTS_FREQ_SCALE_B_THRESHOLD , 41 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_FREQ_SCALE_B_THRESHOLD ); REG64_FLD( EX_L2_PWM_EVENTS_FREQ_SCALE_B_THRESHOLD_LEN , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_FREQ_SCALE_B_THRESHOLD_LEN ); REG64_FLD( EX_L2_PWM_EVENTS_RESERVED_48 , 48 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_RESERVED_48 ); REG64_FLD( EX_L2_PWM_EVENTS_PSTATE_A_THRESHOLD , 49 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_PSTATE_A_THRESHOLD ); REG64_FLD( EX_L2_PWM_EVENTS_PSTATE_A_THRESHOLD_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_PSTATE_A_THRESHOLD_LEN ); REG64_FLD( EX_L2_PWM_EVENTS_RESERVED_52 , 52 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_RESERVED_52 ); REG64_FLD( EX_L2_PWM_EVENTS_PSTATE_B_THRESHOLD , 53 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_PSTATE_B_THRESHOLD ); REG64_FLD( EX_L2_PWM_EVENTS_PSTATE_B_THRESHOLD_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_PSTATE_B_THRESHOLD_LEN ); REG64_FLD( EX_L2_PWM_EVENTS_RESERVED_56 , 56 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56 ); REG64_FLD( EX_L2_PWM_EVENTS_RESERVED_57 , 57 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_RESERVED_57 ); REG64_FLD( EX_L2_PWM_EVENTS_EVENT_MUX_SELECTS , 58 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_EVENT_MUX_SELECTS ); REG64_FLD( EX_L2_PWM_EVENTS_EVENT_MUX_SELECTS_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_EVENT_MUX_SELECTS_LEN ); REG64_FLD( EX_L2_PWM_EVENTS_RESERVED_60 , 60 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_RESERVED_60 ); REG64_FLD( EX_L2_PWM_EVENTS_RESERVED_61 , 61 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_RESERVED_61 ); REG64_FLD( EX_L2_PWM_EVENTS_PMCM_THRESHOLD , 62 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_PMCM_THRESHOLD ); REG64_FLD( EX_L2_PWM_EVENTS_PMCM_THRESHOLD_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_PMCM_THRESHOLD_LEN ); REG64_FLD( C_PWM_EVENTS_RESERVED_32 , 32 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32 ); REG64_FLD( C_PWM_EVENTS_FREQ_SCALE_A_THRESHOLD , 33 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_FREQ_SCALE_A_THRESHOLD ); REG64_FLD( C_PWM_EVENTS_FREQ_SCALE_A_THRESHOLD_LEN , 7 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_FREQ_SCALE_A_THRESHOLD_LEN ); REG64_FLD( C_PWM_EVENTS_RESERVED_40 , 40 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RESERVED_40 ); REG64_FLD( C_PWM_EVENTS_FREQ_SCALE_B_THRESHOLD , 41 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_FREQ_SCALE_B_THRESHOLD ); REG64_FLD( C_PWM_EVENTS_FREQ_SCALE_B_THRESHOLD_LEN , 7 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_FREQ_SCALE_B_THRESHOLD_LEN ); REG64_FLD( C_PWM_EVENTS_RESERVED_48 , 48 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RESERVED_48 ); REG64_FLD( C_PWM_EVENTS_PSTATE_A_THRESHOLD , 49 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PSTATE_A_THRESHOLD ); REG64_FLD( C_PWM_EVENTS_PSTATE_A_THRESHOLD_LEN , 3 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PSTATE_A_THRESHOLD_LEN ); REG64_FLD( C_PWM_EVENTS_RESERVED_52 , 52 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RESERVED_52 ); REG64_FLD( C_PWM_EVENTS_PSTATE_B_THRESHOLD , 53 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PSTATE_B_THRESHOLD ); REG64_FLD( C_PWM_EVENTS_PSTATE_B_THRESHOLD_LEN , 3 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PSTATE_B_THRESHOLD_LEN ); REG64_FLD( C_PWM_EVENTS_RESERVED_56 , 56 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56 ); REG64_FLD( C_PWM_EVENTS_RESERVED_57 , 57 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RESERVED_57 ); REG64_FLD( C_PWM_EVENTS_EVENT_MUX_SELECTS , 58 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_EVENT_MUX_SELECTS ); REG64_FLD( C_PWM_EVENTS_EVENT_MUX_SELECTS_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_EVENT_MUX_SELECTS_LEN ); REG64_FLD( C_PWM_EVENTS_RESERVED_60 , 60 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RESERVED_60 ); REG64_FLD( C_PWM_EVENTS_RESERVED_61 , 61 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RESERVED_61 ); REG64_FLD( C_PWM_EVENTS_PMCM_THRESHOLD , 62 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PMCM_THRESHOLD ); REG64_FLD( C_PWM_EVENTS_PMCM_THRESHOLD_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PMCM_THRESHOLD_LEN ); REG64_FLD( EQ_QPPM_DPLL_CTRL_LOCK_SEL , 0 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_LOCK_SEL ); REG64_FLD( EQ_QPPM_DPLL_CTRL_ENABLE_JUMP_PROTECT , 1 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_ENABLE_JUMP_PROTECT ); REG64_FLD( EQ_QPPM_DPLL_CTRL_FF_BYPASS , 2 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_FF_BYPASS ); REG64_FLD( EQ_QPPM_DPLL_CTRL_DCO_OVERRIDE , 3 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_DCO_OVERRIDE ); REG64_FLD( EQ_QPPM_DPLL_CTRL_DCO_INCR , 4 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_DCO_INCR ); REG64_FLD( EQ_QPPM_DPLL_CTRL_DCO_DECR , 5 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_DCO_DECR ); REG64_FLD( EQ_QPPM_DPLL_CTRL_FF_SLEWRATE , 6 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_FF_SLEWRATE ); REG64_FLD( EQ_QPPM_DPLL_CTRL_FF_SLEWRATE_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_FF_SLEWRATE_LEN ); REG64_FLD( EQ_QPPM_DPLL_CTRL_SS_ENABLE , 16 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_SS_ENABLE ); REG64_FLD( EQ_QPPM_DPLL_CTRL_RESERVED_17_19 , 17 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_17_19 ); REG64_FLD( EQ_QPPM_DPLL_CTRL_RESERVED_17_19_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_17_19_LEN ); REG64_FLD( EQ_QPPM_DPLL_CTRL_SLEW_DN_SEL , 20 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_SLEW_DN_SEL ); REG64_FLD( EQ_QPPM_DPLL_CTRL_ENABLE_JUMP_TARGET_UPDATE , 21 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_ENABLE_JUMP_TARGET_UPDATE ); REG64_FLD( EQ_QPPM_DPLL_CTRL_ENABLE_FMIN_TARGET , 22 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_ENABLE_FMIN_TARGET ); REG64_FLD( EQ_QPPM_DPLL_CTRL_ENABLE_FMAX_TARGET , 23 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_ENABLE_FMAX_TARGET ); REG64_FLD( EQ_QPPM_DPLL_FREQ_FMAX , 1 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_FMAX ); REG64_FLD( EQ_QPPM_DPLL_FREQ_FMAX_LEN , 11 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_FMAX_LEN ); REG64_FLD( EQ_QPPM_DPLL_FREQ_HIRES_FMAX , 12 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HIRES_FMAX ); REG64_FLD( EQ_QPPM_DPLL_FREQ_HIRES_FMAX_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HIRES_FMAX_LEN ); REG64_FLD( EQ_QPPM_DPLL_FREQ_FMULT , 17 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_FMULT ); REG64_FLD( EQ_QPPM_DPLL_FREQ_FMULT_LEN , 11 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_FMULT_LEN ); REG64_FLD( EQ_QPPM_DPLL_FREQ_HIRES_FMULT , 28 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HIRES_FMULT ); REG64_FLD( EQ_QPPM_DPLL_FREQ_HIRES_FMULT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HIRES_FMULT_LEN ); REG64_FLD( EQ_QPPM_DPLL_FREQ_FMIN , 33 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_FMIN ); REG64_FLD( EQ_QPPM_DPLL_FREQ_FMIN_LEN , 11 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_FMIN_LEN ); REG64_FLD( EQ_QPPM_DPLL_FREQ_HIRES_FMIN , 44 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HIRES_FMIN ); REG64_FLD( EQ_QPPM_DPLL_FREQ_HIRES_FMIN_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_HIRES_FMIN_LEN ); REG64_FLD( EQ_QPPM_DPLL_ICHAR_FREQIN_AVG , 1 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_FREQIN_AVG ); REG64_FLD( EQ_QPPM_DPLL_ICHAR_FREQIN_AVG_LEN , 11 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_FREQIN_AVG_LEN ); REG64_FLD( EQ_QPPM_DPLL_ICHAR_HIRES_FREQIN_AVG , 12 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HIRES_FREQIN_AVG ); REG64_FLD( EQ_QPPM_DPLL_ICHAR_HIRES_FREQIN_AVG_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HIRES_FREQIN_AVG_LEN ); REG64_FLD( EQ_QPPM_DPLL_ICHAR_FREQIN_MAX , 21 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_FREQIN_MAX ); REG64_FLD( EQ_QPPM_DPLL_ICHAR_FREQIN_MAX_LEN , 11 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_FREQIN_MAX_LEN ); REG64_FLD( EQ_QPPM_DPLL_ICHAR_HIRES_FREQIN_MAX , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HIRES_FREQIN_MAX ); REG64_FLD( EQ_QPPM_DPLL_ICHAR_HIRES_FREQIN_MAX_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HIRES_FREQIN_MAX_LEN ); REG64_FLD( EQ_QPPM_DPLL_ICHAR_FREQIN_MIN , 41 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_FREQIN_MIN ); REG64_FLD( EQ_QPPM_DPLL_ICHAR_FREQIN_MIN_LEN , 11 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_FREQIN_MIN_LEN ); REG64_FLD( EQ_QPPM_DPLL_ICHAR_HIRES_FREQIN_MIN , 52 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HIRES_FREQIN_MIN ); REG64_FLD( EQ_QPPM_DPLL_ICHAR_HIRES_FREQIN_MIN_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HIRES_FREQIN_MIN_LEN ); REG64_FLD( EQ_QPPM_DPLL_OCHAR_FREQOUT_MAX , 1 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_FREQOUT_MAX ); REG64_FLD( EQ_QPPM_DPLL_OCHAR_FREQOUT_MAX_LEN , 11 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_FREQOUT_MAX_LEN ); REG64_FLD( EQ_QPPM_DPLL_OCHAR_HIRES_FREQOUT_MAX , 12 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HIRES_FREQOUT_MAX ); REG64_FLD( EQ_QPPM_DPLL_OCHAR_HIRES_FREQOUT_MAX_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HIRES_FREQOUT_MAX_LEN ); REG64_FLD( EQ_QPPM_DPLL_OCHAR_FREQOUT_AVG , 21 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_FREQOUT_AVG ); REG64_FLD( EQ_QPPM_DPLL_OCHAR_FREQOUT_AVG_LEN , 11 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_FREQOUT_AVG_LEN ); REG64_FLD( EQ_QPPM_DPLL_OCHAR_HIRES_FREQOUT_AVG , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HIRES_FREQOUT_AVG ); REG64_FLD( EQ_QPPM_DPLL_OCHAR_HIRES_FREQOUT_AVG_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HIRES_FREQOUT_AVG_LEN ); REG64_FLD( EQ_QPPM_DPLL_OCHAR_FREQOUT_MIN , 41 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_FREQOUT_MIN ); REG64_FLD( EQ_QPPM_DPLL_OCHAR_FREQOUT_MIN_LEN , 11 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_FREQOUT_MIN_LEN ); REG64_FLD( EQ_QPPM_DPLL_OCHAR_HIRES_FREQOUT_MIN , 52 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HIRES_FREQOUT_MIN ); REG64_FLD( EQ_QPPM_DPLL_OCHAR_HIRES_FREQOUT_MIN_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HIRES_FREQOUT_MIN_LEN ); REG64_FLD( EQ_QPPM_DPLL_STAT_FREQOUT , 1 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_FREQOUT ); REG64_FLD( EQ_QPPM_DPLL_STAT_FREQOUT_LEN , 11 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_FREQOUT_LEN ); REG64_FLD( EQ_QPPM_DPLL_STAT_HIRES_FREQOUT , 12 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HIRES_FREQOUT ); REG64_FLD( EQ_QPPM_DPLL_STAT_HIRES_FREQOUT_LEN , 5 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HIRES_FREQOUT_LEN ); REG64_FLD( EQ_QPPM_DPLL_STAT_RESERVED_57_59 , 57 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RESERVED_57_59 ); REG64_FLD( EQ_QPPM_DPLL_STAT_RESERVED_57_59_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RESERVED_57_59_LEN ); REG64_FLD( EQ_QPPM_DPLL_STAT_FSAFE_ACTIVE , 59 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_FSAFE_ACTIVE ); REG64_FLD( EQ_QPPM_DPLL_STAT_UPDATE_COMPLETE , 60 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_UPDATE_COMPLETE ); REG64_FLD( EQ_QPPM_DPLL_STAT_FREQ_CHANGE , 61 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_FREQ_CHANGE ); REG64_FLD( EQ_QPPM_DPLL_STAT_BLOCK_ACTIVE , 62 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_BLOCK_ACTIVE ); REG64_FLD( EQ_QPPM_DPLL_STAT_LOCK , 63 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LOCK ); REG64_FLD( EQ_QPPM_ERR_PCB_INTERRUPT_PROTOCOL , 0 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_PCB_INTERRUPT_PROTOCOL ); REG64_FLD( EQ_QPPM_ERR_SPECIAL_WKUP_PROTOCOL , 1 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_SPECIAL_WKUP_PROTOCOL ); REG64_FLD( EQ_QPPM_ERR_SPECIAL_WKUP_DONE_PROTOCOL , 2 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_SPECIAL_WKUP_DONE_PROTOCOL ); REG64_FLD( EQ_QPPM_ERR_PFET_SEQ_PROGRAM , 3 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_PFET_SEQ_PROGRAM ); REG64_FLD( EQ_QPPM_ERR_OCC_HEARTBEAT_LOSS , 4 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_OCC_HEARTBEAT_LOSS ); REG64_FLD( EQ_QPPM_ERR_L2_EX0_CLK_SYNC , 5 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_L2_EX0_CLK_SYNC ); REG64_FLD( EQ_QPPM_ERR_L2_EX1_CLK_SYNC , 6 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_L2_EX1_CLK_SYNC ); REG64_FLD( EQ_QPPM_ERR_EDRAM_SEQUENCE , 7 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_EDRAM_SEQUENCE ); REG64_FLD( EQ_QPPM_ERR_EDRAM_PGATE , 8 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_EDRAM_PGATE ); REG64_FLD( EQ_QPPM_ERR_DPLL_INT , 9 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_DPLL_INT ); REG64_FLD( EQ_QPPM_ERR_DPLL_DYN_FMIN , 10 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_DPLL_DYN_FMIN ); REG64_FLD( EQ_QPPM_ERR_DPLL_DCO_FULL , 11 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_DPLL_DCO_FULL ); REG64_FLD( EQ_QPPM_ERR_DPLL_DCO_EMPTY , 12 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_DPLL_DCO_EMPTY ); REG64_FLD( EQ_QPPM_ERR_INVERTED_VDM_DATA , 13 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_INVERTED_VDM_DATA ); REG64_FLD( EQ_QPPM_ERR_INVERTED_VDM_DATA_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_INVERTED_VDM_DATA_LEN ); REG64_FLD( EQ_QPPM_ERR_CME0_IVRM_DROPOUT , 17 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_CME0_IVRM_DROPOUT ); REG64_FLD( EQ_QPPM_ERR_CME1_IVRM_DROPOUT , 18 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_CME1_IVRM_DROPOUT ); REG64_FLD( EQ_QPPM_ERR_SPARE_19 , 19 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_SPARE_19 ); REG64_FLD( EQ_QPPM_ERR_SPARE_20_23 , 20 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_SPARE_20_23 ); REG64_FLD( EQ_QPPM_ERR_SPARE_20_23_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_SPARE_20_23_LEN ); REG64_FLD( EQ_QPPM_ERRMSK_RESERVED_0_23 , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_23 ); REG64_FLD( EQ_QPPM_ERRMSK_RESERVED_0_23_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_23_LEN ); REG64_FLD( EQ_QPPM_ERRSUM_PM_ERROR , 0 , SH_UNT_EQ , SH_ACS_SCOM_WCLEAR, SH_FLD_PM_ERROR ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SB_STRENGTH , 0 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX0_CLK_SB_STRENGTH ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SB_STRENGTH_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX0_CLK_SB_STRENGTH_LEN ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SB_SPARE0 , 4 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX0_CLK_SB_SPARE0 ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SB_PULSE_MODE_EN , 5 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX0_CLK_SB_PULSE_MODE_EN ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SB_PULSE_MODE , 6 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX0_CLK_SB_PULSE_MODE ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SB_PULSE_MODE_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX0_CLK_SB_PULSE_MODE_LEN ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SW_RESCLK , 8 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX0_CLK_SW_RESCLK ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SW_RESCLK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX0_CLK_SW_RESCLK_LEN ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SW_SPARE1 , 12 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX0_CLK_SW_SPARE1 ); REG64_FLD( EQ_QPPM_EXCGCR_RESERVED_13_15 , 13 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_13_15 ); REG64_FLD( EQ_QPPM_EXCGCR_RESERVED_13_15_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_13_15_LEN ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SB_STRENGTH , 16 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX1_CLK_SB_STRENGTH ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SB_STRENGTH_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX1_CLK_SB_STRENGTH_LEN ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SB_SPARE0 , 20 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX1_CLK_SB_SPARE0 ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SB_PULSE_MODE_EN , 21 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX1_CLK_SB_PULSE_MODE_EN ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SB_PULSE_MODE , 22 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX1_CLK_SB_PULSE_MODE ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SB_PULSE_MODE_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX1_CLK_SB_PULSE_MODE_LEN ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SW_RESCLK , 24 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX1_CLK_SW_RESCLK ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SW_RESCLK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX1_CLK_SW_RESCLK_LEN ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SW_SPARE1 , 28 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX1_CLK_SW_SPARE1 ); REG64_FLD( EQ_QPPM_EXCGCR_RESERVED_29_31 , 29 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_29_31 ); REG64_FLD( EQ_QPPM_EXCGCR_RESERVED_29_31_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_29_31_LEN ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLKGLM_ASYNC_RESET , 32 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX0_CLKGLM_ASYNC_RESET ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLKGLM_ASYNC_RESET , 33 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX1_CLKGLM_ASYNC_RESET ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLKGLM_SEL , 34 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX0_CLKGLM_SEL ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLKGLM_SEL , 35 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX1_CLKGLM_SEL ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SYNC_ENABLE , 36 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX0_CLK_SYNC_ENABLE ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SYNC_ENABLE , 37 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX1_CLK_SYNC_ENABLE ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SB_OVERRIDE , 38 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX0_CLK_SB_OVERRIDE ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SB_OVERRIDE , 39 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX1_CLK_SB_OVERRIDE ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX0_CLK_SW_OVERRIDE , 40 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX0_CLK_SW_OVERRIDE ); REG64_FLD( EQ_QPPM_EXCGCR_L2_EX1_CLK_SW_OVERRIDE , 41 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L2_EX1_CLK_SW_OVERRIDE ); REG64_FLD( EQ_QPPM_OCCHB_OCC_HEARTBEAT_COUNT , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_OCC_HEARTBEAT_COUNT ); REG64_FLD( EQ_QPPM_OCCHB_OCC_HEARTBEAT_COUNT_LEN , 16 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_OCC_HEARTBEAT_COUNT_LEN ); REG64_FLD( EQ_QPPM_OCCHB_OCC_HEARTBEAT_ENABLE , 16 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_OCC_HEARTBEAT_ENABLE ); REG64_FLD( EQ_QPPM_QACCR_COMMON_CLK_SB_STRENGTH , 0 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_COMMON_CLK_SB_STRENGTH ); REG64_FLD( EQ_QPPM_QACCR_COMMON_CLK_SB_STRENGTH_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_COMMON_CLK_SB_STRENGTH_LEN ); REG64_FLD( EQ_QPPM_QACCR_COMMON_CLK_SB_SPARE , 4 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_COMMON_CLK_SB_SPARE ); REG64_FLD( EQ_QPPM_QACCR_COMMON_CLK_SB_PULSE_MODE_EN , 5 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_COMMON_CLK_SB_PULSE_MODE_EN ); REG64_FLD( EQ_QPPM_QACCR_COMMON_CLK_SB_PULSE_MODE , 6 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_COMMON_CLK_SB_PULSE_MODE ); REG64_FLD( EQ_QPPM_QACCR_COMMON_CLK_SB_PULSE_MODE_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_COMMON_CLK_SB_PULSE_MODE_LEN ); REG64_FLD( EQ_QPPM_QACCR_COMMON_CLK_SW_RESCLK , 8 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_COMMON_CLK_SW_RESCLK ); REG64_FLD( EQ_QPPM_QACCR_COMMON_CLK_SW_RESCLK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_COMMON_CLK_SW_RESCLK_LEN ); REG64_FLD( EQ_QPPM_QACCR_COMMON_CLK_SW_SPARE , 12 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_COMMON_CLK_SW_SPARE ); REG64_FLD( EQ_QPPM_QACCR_RESERVED_13_15 , 13 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_13_15 ); REG64_FLD( EQ_QPPM_QACCR_RESERVED_13_15_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_13_15_LEN ); REG64_FLD( EQ_QPPM_QACCR_L3_CLK_SB_STRENGTH , 16 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L3_CLK_SB_STRENGTH ); REG64_FLD( EQ_QPPM_QACCR_L3_CLK_SB_STRENGTH_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L3_CLK_SB_STRENGTH_LEN ); REG64_FLD( EQ_QPPM_QACCR_L3_CLK_SB_SPARE0 , 20 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L3_CLK_SB_SPARE0 ); REG64_FLD( EQ_QPPM_QACCR_L3_CLK_SB_PULSE_MODE_EN , 21 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L3_CLK_SB_PULSE_MODE_EN ); REG64_FLD( EQ_QPPM_QACCR_L3_CLK_SB_PULSE_MODE , 22 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L3_CLK_SB_PULSE_MODE ); REG64_FLD( EQ_QPPM_QACCR_L3_CLK_SB_PULSE_MODE_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_L3_CLK_SB_PULSE_MODE_LEN ); REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SB_STRENGTH , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_L2_EX0_CLK_SB_STRENGTH ); REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SB_STRENGTH_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_L2_EX0_CLK_SB_STRENGTH_LEN ); REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SB_SPARE0 , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_L2_EX0_CLK_SB_SPARE0 ); REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE_EN , 5 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE_EN ); REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE , 6 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE ); REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_L2_EX0_CLK_SB_PULSE_MODE_LEN ); REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SW_RESCLK , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_L2_EX0_CLK_SW_RESCLK ); REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SW_RESCLK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_L2_EX0_CLK_SW_RESCLK_LEN ); REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX0_CLK_SW_SPARE1 , 12 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_L2_EX0_CLK_SW_SPARE1 ); REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SB_STRENGTH , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_L2_EX1_CLK_SB_STRENGTH ); REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SB_STRENGTH_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_L2_EX1_CLK_SB_STRENGTH_LEN ); REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SB_SPARE0 , 20 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_L2_EX1_CLK_SB_SPARE0 ); REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE_EN , 21 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE_EN ); REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE , 22 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE ); REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_L2_EX1_CLK_SB_PULSE_MODE_LEN ); REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SW_RESCLK , 24 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_L2_EX1_CLK_SW_RESCLK ); REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SW_RESCLK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_L2_EX1_CLK_SW_RESCLK_LEN ); REG64_FLD( EQ_QPPM_QACSR_ACTUAL_L2_EX1_CLK_SW_SPARE1 , 28 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ACTUAL_L2_EX1_CLK_SW_SPARE1 ); REG64_FLD( EQ_QPPM_QACSR_L2_EX0_CLK_SYNC_DONE , 36 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_L2_EX0_CLK_SYNC_DONE ); REG64_FLD( EQ_QPPM_QACSR_L2_EX1_CLK_SYNC_DONE , 37 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_L2_EX1_CLK_SYNC_DONE ); REG64_FLD( EQ_QPPM_QCCR_L3_EX0_EDRAM_ENABLE_ENCODE , 0 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_L3_EX0_EDRAM_ENABLE_ENCODE ); REG64_FLD( EQ_QPPM_QCCR_L3_EX0_EDRAM_ENABLE_ENCODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_L3_EX0_EDRAM_ENABLE_ENCODE_LEN ); REG64_FLD( EQ_QPPM_QCCR_L3_EX1_EDRAM_ENABLE_ENCODE , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_L3_EX1_EDRAM_ENABLE_ENCODE ); REG64_FLD( EQ_QPPM_QCCR_L3_EX1_EDRAM_ENABLE_ENCODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_L3_EX1_EDRAM_ENABLE_ENCODE_LEN ); REG64_FLD( EQ_QPPM_QCCR_SPARE_8_11 , 8 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_SPARE_8_11 ); REG64_FLD( EQ_QPPM_QCCR_SPARE_8_11_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_SPARE_8_11_LEN ); REG64_FLD( EQ_QPPM_QCCR_DROOP_PROTECT_DATA , 12 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_DROOP_PROTECT_DATA ); REG64_FLD( EQ_QPPM_QCCR_DROOP_PROTECT_DATA_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_DROOP_PROTECT_DATA_LEN ); REG64_FLD( EQ_QPPM_QCCR_FORCE_DROOP_DATA , 16 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_FORCE_DROOP_DATA ); REG64_FLD( EQ_QPPM_QCCR_FORCE_DROOP_DATA_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_FORCE_DROOP_DATA_LEN ); REG64_FLD( EQ_QPPM_QCCR_PULSE_DROOP_DATA , 20 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PULSE_DROOP_DATA ); REG64_FLD( EQ_QPPM_QCCR_PULSE_DROOP_DATA_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PULSE_DROOP_DATA_LEN ); REG64_FLD( EQ_QPPM_QCCR_PULSE_DROOP_ENABLE , 24 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PULSE_DROOP_ENABLE ); REG64_FLD( EQ_QPPM_QCCR_PB_PURGE_REQ , 30 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PB_PURGE_REQ ); REG64_FLD( EQ_QPPM_QCCR_PB_PURGE_DONE_LVL , 31 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_PB_PURGE_DONE_LVL ); REG64_FLD( EQ_QPPM_QCCR_L3_EX0_EDRAM_ENABLE_ACTUAL , 32 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_L3_EX0_EDRAM_ENABLE_ACTUAL ); REG64_FLD( EQ_QPPM_QCCR_L3_EX0_EDRAM_ENABLE_ACTUAL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_L3_EX0_EDRAM_ENABLE_ACTUAL_LEN ); REG64_FLD( EQ_QPPM_QCCR_L3_EX1_EDRAM_ENABLE_ACTUAL , 36 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_L3_EX1_EDRAM_ENABLE_ACTUAL ); REG64_FLD( EQ_QPPM_QCCR_L3_EX1_EDRAM_ENABLE_ACTUAL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_L3_EX1_EDRAM_ENABLE_ACTUAL_LEN ); REG64_FLD( EQ_QPPM_QCCR_L3_EDRAM_SEQ_ERR , 40 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_L3_EDRAM_SEQ_ERR ); REG64_FLD( EQ_QPPM_QCCR_L3_EDRAM_PGATE_ERR , 41 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_L3_EDRAM_PGATE_ERR ); REG64_FLD( EQ_QPPM_QCCR_L3_EX0_EDRAM_UNLOCKED , 42 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_L3_EX0_EDRAM_UNLOCKED ); REG64_FLD( EQ_QPPM_QCCR_L3_EX1_EDRAM_UNLOCKED , 43 , SH_UNT_EQ , SH_ACS_SCOM2 , SH_FLD_L3_EX1_EDRAM_UNLOCKED ); REG64_FLD( EQ_QPPM_QPMMR_FORCE_FSAFE , 0 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_FORCE_FSAFE ); REG64_FLD( EQ_QPPM_QPMMR_FSAFE , 1 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_FSAFE ); REG64_FLD( EQ_QPPM_QPMMR_FSAFE_LEN , 11 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_FSAFE_LEN ); REG64_FLD( EQ_QPPM_QPMMR_ENABLE_FSAFE_UPON_HEARTBEAT_LOSS , 12 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_ENABLE_FSAFE_UPON_HEARTBEAT_LOSS ); REG64_FLD( EQ_QPPM_QPMMR_ENABLE_DROOP_PROTECT_UPON_HEARTBEAT_LOSS , 13 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_ENABLE_DROOP_PROTECT_UPON_HEARTBEAT_LOSS ); REG64_FLD( EQ_QPPM_QPMMR_ENABLE_PFETS_UPON_IVRM_DROPOUT , 14 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_ENABLE_PFETS_UPON_IVRM_DROPOUT ); REG64_FLD( EQ_QPPM_QPMMR_ENABLE_PCB_INTR_UPON_HEARTBEAT_LOSS , 16 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_ENABLE_PCB_INTR_UPON_HEARTBEAT_LOSS ); REG64_FLD( EQ_QPPM_QPMMR_ENABLE_PCB_INTR_UPON_IVRM_DROPOUT , 17 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_ENABLE_PCB_INTR_UPON_IVRM_DROPOUT ); REG64_FLD( EQ_QPPM_QPMMR_ENABLE_PCB_INTR_UPON_LARGE_DROOP , 18 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_ENABLE_PCB_INTR_UPON_LARGE_DROOP ); REG64_FLD( EQ_QPPM_QPMMR_ENABLE_PCB_INTR_UPON_EXTREME_DROOP , 19 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_ENABLE_PCB_INTR_UPON_EXTREME_DROOP ); REG64_FLD( EQ_QPPM_QPMMR_CME_INTERPPM_IVRM_ENABLE , 20 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_CME_INTERPPM_IVRM_ENABLE ); REG64_FLD( EQ_QPPM_QPMMR_CME_INTERPPM_IVRM_SEL , 21 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_CME_INTERPPM_IVRM_SEL ); REG64_FLD( EQ_QPPM_QPMMR_CME_INTERPPM_ACLK_ENABLE , 22 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_CME_INTERPPM_ACLK_ENABLE ); REG64_FLD( EQ_QPPM_QPMMR_CME_INTERPPM_ACLK_SEL , 23 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_CME_INTERPPM_ACLK_SEL ); REG64_FLD( EQ_QPPM_QPMMR_CME_INTERPPM_VDATA_ENABLE , 24 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_CME_INTERPPM_VDATA_ENABLE ); REG64_FLD( EQ_QPPM_QPMMR_CME_INTERPPM_VDATA_SEL , 25 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_CME_INTERPPM_VDATA_SEL ); REG64_FLD( EQ_QPPM_QPMMR_CME_INTERPPM_DPLL_ENABLE , 26 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_CME_INTERPPM_DPLL_ENABLE ); REG64_FLD( EQ_QPPM_QPMMR_CME_INTERPPM_DPLL_SEL , 27 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_CME_INTERPPM_DPLL_SEL ); REG64_FLD( EQ_QPPM_QPMMR_RESERVED28_31 , 28 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_RESERVED28_31 ); REG64_FLD( EQ_QPPM_QPMMR_RESERVED28_31_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM2_OR , SH_FLD_RESERVED28_31_LEN ); REG64_FLD( EQ_QPPM_VDMCFGR_VDM_VID_COMPARE , 0 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VDM_VID_COMPARE ); REG64_FLD( EQ_QPPM_VDMCFGR_VDM_VID_COMPARE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VDM_VID_COMPARE_LEN ); REG64_FLD( EQ_QPPM_VDMCFGR_VDM_OVERVOLT , 8 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VDM_OVERVOLT ); REG64_FLD( EQ_QPPM_VDMCFGR_VDM_OVERVOLT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VDM_OVERVOLT_LEN ); REG64_FLD( EQ_QPPM_VDMCFGR_VDM_DROOP_SMALL , 12 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VDM_DROOP_SMALL ); REG64_FLD( EQ_QPPM_VDMCFGR_VDM_DROOP_SMALL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VDM_DROOP_SMALL_LEN ); REG64_FLD( EQ_QPPM_VDMCFGR_VDM_DROOP_LARGE , 16 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VDM_DROOP_LARGE ); REG64_FLD( EQ_QPPM_VDMCFGR_VDM_DROOP_LARGE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VDM_DROOP_LARGE_LEN ); REG64_FLD( EQ_QPPM_VDMCFGR_VDM_DROOP_XTREME , 20 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VDM_DROOP_XTREME ); REG64_FLD( EQ_QPPM_VDMCFGR_VDM_DROOP_XTREME_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM_RW , SH_FLD_VDM_DROOP_XTREME_LEN ); REG64_FLD( EQ_QPPM_VOLT_CHAR_VID_COMPARE_MAX , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VID_COMPARE_MAX ); REG64_FLD( EQ_QPPM_VOLT_CHAR_VID_COMPARE_MAX_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VID_COMPARE_MAX_LEN ); REG64_FLD( EQ_QPPM_VOLT_CHAR_VID_COMPARE_MIN , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VID_COMPARE_MIN ); REG64_FLD( EQ_QPPM_VOLT_CHAR_VID_COMPARE_MIN_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VID_COMPARE_MIN_LEN ); REG64_FLD( EQ_QPPM_VOLT_CHAR_IVRM_ENABLED_HISTORY , 16 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_IVRM_ENABLED_HISTORY ); REG64_FLD( EX_RAM_CTRL_RAM_VTID , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_RAM_VTID ); REG64_FLD( EX_RAM_CTRL_RAM_VTID_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_RAM_VTID_LEN ); REG64_FLD( EX_RAM_CTRL_PPC_PREDCD , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_PPC_PREDCD ); REG64_FLD( EX_RAM_CTRL_PPC_PREDCD_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_PPC_PREDCD_LEN ); REG64_FLD( EX_RAM_CTRL_SPARE , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SPARE ); REG64_FLD( EX_RAM_CTRL_SPARE_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SPARE_LEN ); REG64_FLD( EX_RAM_CTRL_PPC_INSTR , 8 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_PPC_INSTR ); REG64_FLD( EX_RAM_CTRL_PPC_INSTR_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_PPC_INSTR_LEN ); REG64_FLD( C_RAM_CTRL_RAM_VTID , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RAM_VTID ); REG64_FLD( C_RAM_CTRL_RAM_VTID_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_RAM_VTID_LEN ); REG64_FLD( C_RAM_CTRL_PPC_PREDCD , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PPC_PREDCD ); REG64_FLD( C_RAM_CTRL_PPC_PREDCD_LEN , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PPC_PREDCD_LEN ); REG64_FLD( C_RAM_CTRL_SPARE , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SPARE ); REG64_FLD( C_RAM_CTRL_SPARE_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SPARE_LEN ); REG64_FLD( C_RAM_CTRL_PPC_INSTR , 8 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PPC_INSTR ); REG64_FLD( C_RAM_CTRL_PPC_INSTR_LEN , 32 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_PPC_INSTR_LEN ); REG64_FLD( EX_RAM_MODEREG_MODE_ENABLE , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_MODE_ENABLE ); REG64_FLD( C_RAM_MODEREG_MODE_ENABLE , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_MODE_ENABLE ); REG64_FLD( EX_L2_RAM_STATUS_RAM_CONTROL_ACCESS_DURING_RECOV , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_RAM_CONTROL_ACCESS_DURING_RECOV ); REG64_FLD( EX_L2_RAM_STATUS_RAM_COMPLETION , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_RAM_COMPLETION ); REG64_FLD( EX_L2_RAM_STATUS_RAM_EXCEPTION , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_RAM_EXCEPTION ); REG64_FLD( EX_L2_RAM_STATUS_LSU_EMPTY , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_LSU_EMPTY ); REG64_FLD( C_RAM_STATUS_RAM_CONTROL_ACCESS_DURING_RECOV , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RAM_CONTROL_ACCESS_DURING_RECOV ); REG64_FLD( C_RAM_STATUS_RAM_COMPLETION , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RAM_COMPLETION ); REG64_FLD( C_RAM_STATUS_RAM_EXCEPTION , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RAM_EXCEPTION ); REG64_FLD( C_RAM_STATUS_LSU_EMPTY , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LSU_EMPTY ); REG64_FLD( EX_L2_RAS_MODEREG_MR_DIS_PMON_INTR , 56 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_MR_DIS_PMON_INTR ); REG64_FLD( EX_L2_RAS_MODEREG_MR_FENCE_INTERRUPTS , 57 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_MR_FENCE_INTERRUPTS ); REG64_FLD( EX_L2_RAS_MODEREG_MR_BLOCK_HMI_IN_MAINT , 62 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_MR_BLOCK_HMI_IN_MAINT ); REG64_FLD( EX_L2_RAS_MODEREG_MR_FENCE_INTR_ON_CHECKSTOP , 63 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_MR_FENCE_INTR_ON_CHECKSTOP ); REG64_FLD( C_RAS_MODEREG_MR_DIS_PMON_INTR , 56 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_MR_DIS_PMON_INTR ); REG64_FLD( C_RAS_MODEREG_MR_FENCE_INTERRUPTS , 57 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_MR_FENCE_INTERRUPTS ); REG64_FLD( C_RAS_MODEREG_MR_BLOCK_HMI_IN_MAINT , 62 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_MR_BLOCK_HMI_IN_MAINT ); REG64_FLD( C_RAS_MODEREG_MR_FENCE_INTR_ON_CHECKSTOP , 63 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_MR_FENCE_INTR_ON_CHECKSTOP ); REG64_FLD( EX_L2_RAS_STATUS_T0_CORE_MAINT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_T0_CORE_MAINT ); REG64_FLD( EX_L2_RAS_STATUS_T0_THREAD_QUIESCED , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_T0_THREAD_QUIESCED ); REG64_FLD( EX_L2_RAS_STATUS_T0_ICT_EMPTY , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_T0_ICT_EMPTY ); REG64_FLD( EX_L2_RAS_STATUS_T0_LSU_QUIESCED , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_T0_LSU_QUIESCED ); REG64_FLD( EX_L2_RAS_STATUS_T0_STEP_SUCCESS , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_T0_STEP_SUCCESS ); REG64_FLD( EX_L2_RAS_STATUS_T1_CORE_MAINT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_T1_CORE_MAINT ); REG64_FLD( EX_L2_RAS_STATUS_T1_THREAD_QUIESCED , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_T1_THREAD_QUIESCED ); REG64_FLD( EX_L2_RAS_STATUS_T1_ICT_EMPTY , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_T1_ICT_EMPTY ); REG64_FLD( EX_L2_RAS_STATUS_T1_LSU_QUIESCED , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_T1_LSU_QUIESCED ); REG64_FLD( EX_L2_RAS_STATUS_T1_STEP_SUCCESS , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_T1_STEP_SUCCESS ); REG64_FLD( EX_L2_RAS_STATUS_T2_CORE_MAINT , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_T2_CORE_MAINT ); REG64_FLD( EX_L2_RAS_STATUS_T2_THREAD_QUIESCED , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_T2_THREAD_QUIESCED ); REG64_FLD( EX_L2_RAS_STATUS_T2_ICT_EMPTY , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_T2_ICT_EMPTY ); REG64_FLD( EX_L2_RAS_STATUS_T2_LSU_QUIESCED , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_T2_LSU_QUIESCED ); REG64_FLD( EX_L2_RAS_STATUS_T2_STEP_SUCCESS , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_T2_STEP_SUCCESS ); REG64_FLD( EX_L2_RAS_STATUS_T3_CORE_MAINT , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_T3_CORE_MAINT ); REG64_FLD( EX_L2_RAS_STATUS_T3_THREAD_QUIESCED , 25 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_T3_THREAD_QUIESCED ); REG64_FLD( EX_L2_RAS_STATUS_T3_ICT_EMPTY , 26 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_T3_ICT_EMPTY ); REG64_FLD( EX_L2_RAS_STATUS_T3_LSU_QUIESCED , 27 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_T3_LSU_QUIESCED ); REG64_FLD( EX_L2_RAS_STATUS_T3_STEP_SUCCESS , 28 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_T3_STEP_SUCCESS ); REG64_FLD( C_RAS_STATUS_T0_CORE_MAINT , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_T0_CORE_MAINT ); REG64_FLD( C_RAS_STATUS_T0_THREAD_QUIESCED , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_T0_THREAD_QUIESCED ); REG64_FLD( C_RAS_STATUS_T0_ICT_EMPTY , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_T0_ICT_EMPTY ); REG64_FLD( C_RAS_STATUS_T0_LSU_QUIESCED , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_T0_LSU_QUIESCED ); REG64_FLD( C_RAS_STATUS_T0_STEP_SUCCESS , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_T0_STEP_SUCCESS ); REG64_FLD( C_RAS_STATUS_T1_CORE_MAINT , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_T1_CORE_MAINT ); REG64_FLD( C_RAS_STATUS_T1_THREAD_QUIESCED , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_T1_THREAD_QUIESCED ); REG64_FLD( C_RAS_STATUS_T1_ICT_EMPTY , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_T1_ICT_EMPTY ); REG64_FLD( C_RAS_STATUS_T1_LSU_QUIESCED , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_T1_LSU_QUIESCED ); REG64_FLD( C_RAS_STATUS_T1_STEP_SUCCESS , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_T1_STEP_SUCCESS ); REG64_FLD( C_RAS_STATUS_T2_CORE_MAINT , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_T2_CORE_MAINT ); REG64_FLD( C_RAS_STATUS_T2_THREAD_QUIESCED , 17 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_T2_THREAD_QUIESCED ); REG64_FLD( C_RAS_STATUS_T2_ICT_EMPTY , 18 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_T2_ICT_EMPTY ); REG64_FLD( C_RAS_STATUS_T2_LSU_QUIESCED , 19 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_T2_LSU_QUIESCED ); REG64_FLD( C_RAS_STATUS_T2_STEP_SUCCESS , 20 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_T2_STEP_SUCCESS ); REG64_FLD( C_RAS_STATUS_T3_CORE_MAINT , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_T3_CORE_MAINT ); REG64_FLD( C_RAS_STATUS_T3_THREAD_QUIESCED , 25 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_T3_THREAD_QUIESCED ); REG64_FLD( C_RAS_STATUS_T3_ICT_EMPTY , 26 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_T3_ICT_EMPTY ); REG64_FLD( C_RAS_STATUS_T3_LSU_QUIESCED , 27 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_T3_LSU_QUIESCED ); REG64_FLD( C_RAS_STATUS_T3_STEP_SUCCESS , 28 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_T3_STEP_SUCCESS ); REG64_FLD( EQ_RD_EPS_REG_TIER0_VALUE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TIER0_VALUE ); REG64_FLD( EQ_RD_EPS_REG_TIER0_VALUE_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TIER0_VALUE_LEN ); REG64_FLD( EQ_RD_EPS_REG_TIER1_VALUE , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TIER1_VALUE ); REG64_FLD( EQ_RD_EPS_REG_TIER1_VALUE_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TIER1_VALUE_LEN ); REG64_FLD( EQ_RD_EPS_REG_TIER2_VALUE , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TIER2_VALUE ); REG64_FLD( EQ_RD_EPS_REG_TIER2_VALUE_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TIER2_VALUE_LEN ); REG64_FLD( EX_L2_RD_EPS_REG_TIER0_VALUE , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_TIER0_VALUE ); REG64_FLD( EX_L2_RD_EPS_REG_TIER0_VALUE_LEN , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_TIER0_VALUE_LEN ); REG64_FLD( EX_L2_RD_EPS_REG_TIER1_VALUE , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_TIER1_VALUE ); REG64_FLD( EX_L2_RD_EPS_REG_TIER1_VALUE_LEN , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_TIER1_VALUE_LEN ); REG64_FLD( EX_L2_RD_EPS_REG_TIER2_VALUE , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_TIER2_VALUE ); REG64_FLD( EX_L2_RD_EPS_REG_TIER2_VALUE_LEN , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_TIER2_VALUE_LEN ); REG64_FLD( EX_L2_RECOV_FWD_PROG_CTRL_RESET_FWD_PROG , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_RESET_FWD_PROG ); REG64_FLD( EX_L2_RECOV_FWD_PROG_CTRL_FWD_PROG_THOLD , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FWD_PROG_THOLD ); REG64_FLD( EX_L2_RECOV_FWD_PROG_CTRL_FWD_PROG_THOLD_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_FWD_PROG_THOLD_LEN ); REG64_FLD( C_RECOV_FWD_PROG_CTRL_RESET_FWD_PROG , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESET_FWD_PROG ); REG64_FLD( C_RECOV_FWD_PROG_CTRL_FWD_PROG_THOLD , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FWD_PROG_THOLD ); REG64_FLD( C_RECOV_FWD_PROG_CTRL_FWD_PROG_THOLD_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FWD_PROG_THOLD_LEN ); REG64_FLD( EQ_RECOV_INTERRUPT_REG_RECOV , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RECOV ); REG64_FLD( EX_RECOV_INTERRUPT_REG_RECOV , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RECOV ); REG64_FLD( C_RECOV_INTERRUPT_REG_RECOV , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RECOV ); REG64_FLD( EX_L2_RECOV_THOLD_THRESHOLD_LIMIT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_THRESHOLD_LIMIT ); REG64_FLD( EX_L2_RECOV_THOLD_THRESHOLD_LIMIT_LEN , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_THRESHOLD_LIMIT_LEN ); REG64_FLD( EX_L2_RECOV_THOLD_THRESHOLD_RESET , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_THRESHOLD_RESET ); REG64_FLD( EX_L2_RECOV_THOLD_THRESHOLD_RESET_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_THRESHOLD_RESET_LEN ); REG64_FLD( C_RECOV_THOLD_THRESHOLD_LIMIT , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_THRESHOLD_LIMIT ); REG64_FLD( C_RECOV_THOLD_THRESHOLD_LIMIT_LEN , 8 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_THRESHOLD_LIMIT_LEN ); REG64_FLD( C_RECOV_THOLD_THRESHOLD_RESET , 8 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_THRESHOLD_RESET ); REG64_FLD( C_RECOV_THOLD_THRESHOLD_RESET_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_THRESHOLD_RESET_LEN ); REG64_FLD( EX_L2_RESET_KEEPER_RESET_KEEPER , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_RESET_KEEPER ); REG64_FLD( C_RESET_KEEPER_RESET_KEEPER , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESET_KEEPER ); REG64_FLD( EQ_RFIR_IN0 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN0 ); REG64_FLD( EQ_RFIR_LFIR_RECOV_ERR , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LFIR_RECOV_ERR ); REG64_FLD( EQ_RFIR_IN4 , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN4 ); REG64_FLD( EQ_RFIR_IN5 , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN5 ); REG64_FLD( EQ_RFIR_IN6 , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN6 ); REG64_FLD( EQ_RFIR_IN7 , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN7 ); REG64_FLD( EQ_RFIR_IN8 , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN8 ); REG64_FLD( EQ_RFIR_IN9 , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN9 ); REG64_FLD( EQ_RFIR_IN10 , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN10 ); REG64_FLD( EQ_RFIR_IN11 , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN11 ); REG64_FLD( EQ_RFIR_IN12 , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN12 ); REG64_FLD( EQ_RFIR_IN13 , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN13 ); REG64_FLD( EQ_RFIR_IN13_LEN , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN13_LEN ); REG64_FLD( EX_RFIR_IN0 , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN0 ); REG64_FLD( EX_RFIR_LFIR_RECOV_ERR , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_LFIR_RECOV_ERR ); REG64_FLD( EX_RFIR_IN4 , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN4 ); REG64_FLD( EX_RFIR_IN5 , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN5 ); REG64_FLD( EX_RFIR_IN5_LEN , 21 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN5_LEN ); REG64_FLD( C_RFIR_IN0 , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN0 ); REG64_FLD( C_RFIR_LFIR_RECOV_ERR , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LFIR_RECOV_ERR ); REG64_FLD( C_RFIR_IN4 , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN4 ); REG64_FLD( C_RFIR_IN5 , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN5 ); REG64_FLD( C_RFIR_IN5_LEN , 21 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN5_LEN ); REG64_FLD( EQ_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( EQ_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); REG64_FLD( EX_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( EX_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); REG64_FLD( C_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( C_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); REG64_FLD( EQ_SCAN_REGION_TYPE_SYSTEM_FAST_INIT , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SYSTEM_FAST_INIT ); REG64_FLD( EQ_SCAN_REGION_TYPE_VITL , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_VITL ); REG64_FLD( EQ_SCAN_REGION_TYPE_PERV , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PERV ); REG64_FLD( EQ_SCAN_REGION_TYPE_UNIT1 , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT1 ); REG64_FLD( EQ_SCAN_REGION_TYPE_UNIT2 , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT2 ); REG64_FLD( EQ_SCAN_REGION_TYPE_UNIT3 , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT3 ); REG64_FLD( EQ_SCAN_REGION_TYPE_UNIT4 , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT4 ); REG64_FLD( EQ_SCAN_REGION_TYPE_UNIT5 , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT5 ); REG64_FLD( EQ_SCAN_REGION_TYPE_UNIT6 , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT6 ); REG64_FLD( EQ_SCAN_REGION_TYPE_UNIT7 , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT7 ); REG64_FLD( EQ_SCAN_REGION_TYPE_UNIT8 , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT8 ); REG64_FLD( EQ_SCAN_REGION_TYPE_UNIT9 , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT9 ); REG64_FLD( EQ_SCAN_REGION_TYPE_UNIT10 , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT10 ); REG64_FLD( EQ_SCAN_REGION_TYPE_FUNC , 48 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FUNC ); REG64_FLD( EQ_SCAN_REGION_TYPE_CFG , 49 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CFG ); REG64_FLD( EQ_SCAN_REGION_TYPE_CCFG_GPTR , 50 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CCFG_GPTR ); REG64_FLD( EQ_SCAN_REGION_TYPE_REGF , 51 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_REGF ); REG64_FLD( EQ_SCAN_REGION_TYPE_LBIST , 52 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LBIST ); REG64_FLD( EQ_SCAN_REGION_TYPE_ABIST , 53 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ABIST ); REG64_FLD( EQ_SCAN_REGION_TYPE_REPR , 54 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_REPR ); REG64_FLD( EQ_SCAN_REGION_TYPE_TIME , 55 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TIME ); REG64_FLD( EQ_SCAN_REGION_TYPE_BNDY , 56 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_BNDY ); REG64_FLD( EQ_SCAN_REGION_TYPE_FARR , 57 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FARR ); REG64_FLD( EQ_SCAN_REGION_TYPE_CMSK , 58 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMSK ); REG64_FLD( EQ_SCAN_REGION_TYPE_INEX , 59 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INEX ); REG64_FLD( EX_SCAN_REGION_TYPE_SYSTEM_FAST_INIT , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SYSTEM_FAST_INIT ); REG64_FLD( EX_SCAN_REGION_TYPE_VITL , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_VITL ); REG64_FLD( EX_SCAN_REGION_TYPE_PERV , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PERV ); REG64_FLD( EX_SCAN_REGION_TYPE_UNIT1 , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT1 ); REG64_FLD( EX_SCAN_REGION_TYPE_UNIT2 , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT2 ); REG64_FLD( EX_SCAN_REGION_TYPE_UNIT3 , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT3 ); REG64_FLD( EX_SCAN_REGION_TYPE_UNIT4 , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT4 ); REG64_FLD( EX_SCAN_REGION_TYPE_UNIT5 , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT5 ); REG64_FLD( EX_SCAN_REGION_TYPE_UNIT6 , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT6 ); REG64_FLD( EX_SCAN_REGION_TYPE_UNIT7 , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT7 ); REG64_FLD( EX_SCAN_REGION_TYPE_UNIT8 , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT8 ); REG64_FLD( EX_SCAN_REGION_TYPE_UNIT9 , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT9 ); REG64_FLD( EX_SCAN_REGION_TYPE_UNIT10 , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT10 ); REG64_FLD( EX_SCAN_REGION_TYPE_FUNC , 48 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FUNC ); REG64_FLD( EX_SCAN_REGION_TYPE_CFG , 49 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CFG ); REG64_FLD( EX_SCAN_REGION_TYPE_CCFG_GPTR , 50 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CCFG_GPTR ); REG64_FLD( EX_SCAN_REGION_TYPE_REGF , 51 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_REGF ); REG64_FLD( EX_SCAN_REGION_TYPE_LBIST , 52 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_LBIST ); REG64_FLD( EX_SCAN_REGION_TYPE_ABIST , 53 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ABIST ); REG64_FLD( EX_SCAN_REGION_TYPE_REPR , 54 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_REPR ); REG64_FLD( EX_SCAN_REGION_TYPE_TIME , 55 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TIME ); REG64_FLD( EX_SCAN_REGION_TYPE_BNDY , 56 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_BNDY ); REG64_FLD( EX_SCAN_REGION_TYPE_FARR , 57 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FARR ); REG64_FLD( EX_SCAN_REGION_TYPE_CMSK , 58 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CMSK ); REG64_FLD( EX_SCAN_REGION_TYPE_INEX , 59 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INEX ); REG64_FLD( C_SCAN_REGION_TYPE_SYSTEM_FAST_INIT , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SYSTEM_FAST_INIT ); REG64_FLD( C_SCAN_REGION_TYPE_VITL , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_VITL ); REG64_FLD( C_SCAN_REGION_TYPE_PERV , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PERV ); REG64_FLD( C_SCAN_REGION_TYPE_UNIT1 , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT1 ); REG64_FLD( C_SCAN_REGION_TYPE_UNIT2 , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT2 ); REG64_FLD( C_SCAN_REGION_TYPE_UNIT3 , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT3 ); REG64_FLD( C_SCAN_REGION_TYPE_UNIT4 , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT4 ); REG64_FLD( C_SCAN_REGION_TYPE_UNIT5 , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT5 ); REG64_FLD( C_SCAN_REGION_TYPE_UNIT6 , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT6 ); REG64_FLD( C_SCAN_REGION_TYPE_UNIT7 , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT7 ); REG64_FLD( C_SCAN_REGION_TYPE_UNIT8 , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT8 ); REG64_FLD( C_SCAN_REGION_TYPE_UNIT9 , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT9 ); REG64_FLD( C_SCAN_REGION_TYPE_UNIT10 , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT10 ); REG64_FLD( C_SCAN_REGION_TYPE_FUNC , 48 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FUNC ); REG64_FLD( C_SCAN_REGION_TYPE_CFG , 49 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CFG ); REG64_FLD( C_SCAN_REGION_TYPE_CCFG_GPTR , 50 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CCFG_GPTR ); REG64_FLD( C_SCAN_REGION_TYPE_REGF , 51 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_REGF ); REG64_FLD( C_SCAN_REGION_TYPE_LBIST , 52 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LBIST ); REG64_FLD( C_SCAN_REGION_TYPE_ABIST , 53 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ABIST ); REG64_FLD( C_SCAN_REGION_TYPE_REPR , 54 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_REPR ); REG64_FLD( C_SCAN_REGION_TYPE_TIME , 55 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TIME ); REG64_FLD( C_SCAN_REGION_TYPE_BNDY , 56 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_BNDY ); REG64_FLD( C_SCAN_REGION_TYPE_FARR , 57 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FARR ); REG64_FLD( C_SCAN_REGION_TYPE_CMSK , 58 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CMSK ); REG64_FLD( C_SCAN_REGION_TYPE_INEX , 59 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INEX ); REG64_FLD( EX_L2_SCOMC_MODE_CX , 54 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_MODE_CX ); REG64_FLD( EX_L2_SCOMC_MODE_CX_LEN , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_MODE_CX_LEN ); REG64_FLD( C_SCOMC_MODE_CX , 54 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_MODE_CX ); REG64_FLD( C_SCOMC_MODE_CX_LEN , 7 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_MODE_CX_LEN ); REG64_FLD( EX_L2_SHID0_TRIG2_TRACE_EN , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_TRIG2_TRACE_EN ); REG64_FLD( EX_L2_SHID0_DIS_TRACE_SPR , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_DIS_TRACE_SPR ); REG64_FLD( C_SHID0_TRIG2_TRACE_EN , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_TRIG2_TRACE_EN ); REG64_FLD( C_SHID0_DIS_TRACE_SPR , 1 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_DIS_TRACE_SPR ); REG64_FLD( EX_SIER_MASK_SIER_MASK_TBD , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SIER_MASK_TBD ); REG64_FLD( EX_SIER_MASK_SIER_MASK_TBD_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SIER_MASK_TBD_LEN ); REG64_FLD( C_SIER_MASK_SIER_MASK_TBD , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SIER_MASK_TBD ); REG64_FLD( C_SIER_MASK_SIER_MASK_TBD_LEN , 64 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SIER_MASK_TBD_LEN ); REG64_FLD( EQ_SKITTER_CLKSRC_REG_SKITTER0 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SKITTER0 ); REG64_FLD( EQ_SKITTER_CLKSRC_REG_SKITTER0_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SKITTER0_LEN ); REG64_FLD( EQ_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT , 36 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SKITTER0_DELAY_SELECT ); REG64_FLD( EQ_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SKITTER0_DELAY_SELECT_LEN ); REG64_FLD( EX_SKITTER_CLKSRC_REG_SKITTER0 , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SKITTER0 ); REG64_FLD( EX_SKITTER_CLKSRC_REG_SKITTER0_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SKITTER0_LEN ); REG64_FLD( EX_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT , 36 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SKITTER0_DELAY_SELECT ); REG64_FLD( EX_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SKITTER0_DELAY_SELECT_LEN ); REG64_FLD( C_SKITTER_CLKSRC_REG_SKITTER0 , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SKITTER0 ); REG64_FLD( C_SKITTER_CLKSRC_REG_SKITTER0_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SKITTER0_LEN ); REG64_FLD( C_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT , 36 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SKITTER0_DELAY_SELECT ); REG64_FLD( C_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SKITTER0_DELAY_SELECT_LEN ); REG64_FLD( EQ_SKITTER_FORCE_REG_F_READ , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_F_READ ); REG64_FLD( EX_SKITTER_FORCE_REG_F_READ , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_F_READ ); REG64_FLD( C_SKITTER_FORCE_REG_F_READ , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_F_READ ); REG64_FLD( EQ_SKITTER_MODE_REG_HOLD_SAMPLE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_HOLD_SAMPLE ); REG64_FLD( EQ_SKITTER_MODE_REG_DISABLE_STICKINESS , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DISABLE_STICKINESS ); REG64_FLD( EQ_SKITTER_MODE_REG_UNUSED1 , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED1 ); REG64_FLD( EQ_SKITTER_MODE_REG_UNUSED1_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED1_LEN ); REG64_FLD( EQ_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_HOLD_DBGTRIG_SEL ); REG64_FLD( EQ_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_HOLD_DBGTRIG_SEL_LEN ); REG64_FLD( EQ_SKITTER_MODE_REG_RESET_TRIG_SEL , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RESET_TRIG_SEL ); REG64_FLD( EQ_SKITTER_MODE_REG_RESET_TRIG_SEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RESET_TRIG_SEL_LEN ); REG64_FLD( EQ_SKITTER_MODE_REG_SAMPLE_GUTS , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SAMPLE_GUTS ); REG64_FLD( EQ_SKITTER_MODE_REG_SAMPLE_GUTS_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SAMPLE_GUTS_LEN ); REG64_FLD( EQ_SKITTER_MODE_REG_HOLD_SAMPLE_WITH_TRIGGER , 44 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_HOLD_SAMPLE_WITH_TRIGGER ); REG64_FLD( EQ_SKITTER_MODE_REG_DATA_V_LT , 45 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DATA_V_LT ); REG64_FLD( EX_SKITTER_MODE_REG_HOLD_SAMPLE , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_HOLD_SAMPLE ); REG64_FLD( EX_SKITTER_MODE_REG_DISABLE_STICKINESS , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DISABLE_STICKINESS ); REG64_FLD( EX_SKITTER_MODE_REG_UNUSED1 , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED1 ); REG64_FLD( EX_SKITTER_MODE_REG_UNUSED1_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED1_LEN ); REG64_FLD( EX_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_HOLD_DBGTRIG_SEL ); REG64_FLD( EX_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_HOLD_DBGTRIG_SEL_LEN ); REG64_FLD( EX_SKITTER_MODE_REG_RESET_TRIG_SEL , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESET_TRIG_SEL ); REG64_FLD( EX_SKITTER_MODE_REG_RESET_TRIG_SEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESET_TRIG_SEL_LEN ); REG64_FLD( EX_SKITTER_MODE_REG_SAMPLE_GUTS , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SAMPLE_GUTS ); REG64_FLD( EX_SKITTER_MODE_REG_SAMPLE_GUTS_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SAMPLE_GUTS_LEN ); REG64_FLD( EX_SKITTER_MODE_REG_HOLD_SAMPLE_WITH_TRIGGER , 44 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_HOLD_SAMPLE_WITH_TRIGGER ); REG64_FLD( EX_SKITTER_MODE_REG_DATA_V_LT , 45 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DATA_V_LT ); REG64_FLD( C_SKITTER_MODE_REG_HOLD_SAMPLE , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_HOLD_SAMPLE ); REG64_FLD( C_SKITTER_MODE_REG_DISABLE_STICKINESS , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DISABLE_STICKINESS ); REG64_FLD( C_SKITTER_MODE_REG_UNUSED1 , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED1 ); REG64_FLD( C_SKITTER_MODE_REG_UNUSED1_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED1_LEN ); REG64_FLD( C_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_HOLD_DBGTRIG_SEL ); REG64_FLD( C_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_HOLD_DBGTRIG_SEL_LEN ); REG64_FLD( C_SKITTER_MODE_REG_RESET_TRIG_SEL , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESET_TRIG_SEL ); REG64_FLD( C_SKITTER_MODE_REG_RESET_TRIG_SEL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESET_TRIG_SEL_LEN ); REG64_FLD( C_SKITTER_MODE_REG_SAMPLE_GUTS , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SAMPLE_GUTS ); REG64_FLD( C_SKITTER_MODE_REG_SAMPLE_GUTS_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SAMPLE_GUTS_LEN ); REG64_FLD( C_SKITTER_MODE_REG_HOLD_SAMPLE_WITH_TRIGGER , 44 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_HOLD_SAMPLE_WITH_TRIGGER ); REG64_FLD( C_SKITTER_MODE_REG_DATA_V_LT , 45 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DATA_V_LT ); REG64_FLD( EQ_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CFG_DISABLE_PERV_THOLD_CHECK ); REG64_FLD( EQ_SLAVE_CONFIG_REG_CFG_DISABLE_MALF_PULSE_GEN , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CFG_DISABLE_MALF_PULSE_GEN ); REG64_FLD( EQ_SLAVE_CONFIG_REG_CFG_STOP_HANG_CNT_SYS_XSTP , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CFG_STOP_HANG_CNT_SYS_XSTP ); REG64_FLD( EQ_SLAVE_CONFIG_REG_CFG_DISABLE_CL_ATOMIC_LOCK , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CFG_DISABLE_CL_ATOMIC_LOCK ); REG64_FLD( EQ_SLAVE_CONFIG_REG_CFG_DISABLE_HEARTBEAT , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CFG_DISABLE_HEARTBEAT ); REG64_FLD( EQ_SLAVE_CONFIG_REG_CFG_DISABLE_FORCE_TO_ZERO , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CFG_DISABLE_FORCE_TO_ZERO ); REG64_FLD( EQ_SLAVE_CONFIG_REG_CFG_PM_DISABLE , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CFG_PM_DISABLE ); REG64_FLD( EQ_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CFG_PM_MUX_DISABLE ); REG64_FLD( EQ_SLAVE_CONFIG_REG_ERROR_MASK , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_MASK ); REG64_FLD( EQ_SLAVE_CONFIG_REG_ERROR_MASK_LEN , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_MASK_LEN ); REG64_FLD( EX_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CFG_DISABLE_PERV_THOLD_CHECK ); REG64_FLD( EX_SLAVE_CONFIG_REG_CFG_DISABLE_MALF_PULSE_GEN , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CFG_DISABLE_MALF_PULSE_GEN ); REG64_FLD( EX_SLAVE_CONFIG_REG_CFG_STOP_HANG_CNT_SYS_XSTP , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CFG_STOP_HANG_CNT_SYS_XSTP ); REG64_FLD( EX_SLAVE_CONFIG_REG_CFG_DISABLE_CL_ATOMIC_LOCK , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CFG_DISABLE_CL_ATOMIC_LOCK ); REG64_FLD( EX_SLAVE_CONFIG_REG_CFG_DISABLE_HEARTBEAT , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CFG_DISABLE_HEARTBEAT ); REG64_FLD( EX_SLAVE_CONFIG_REG_CFG_DISABLE_FORCE_TO_ZERO , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CFG_DISABLE_FORCE_TO_ZERO ); REG64_FLD( EX_SLAVE_CONFIG_REG_CFG_PM_DISABLE , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CFG_PM_DISABLE ); REG64_FLD( EX_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CFG_PM_MUX_DISABLE ); REG64_FLD( EX_SLAVE_CONFIG_REG_ERROR_MASK , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ERROR_MASK ); REG64_FLD( EX_SLAVE_CONFIG_REG_ERROR_MASK_LEN , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ERROR_MASK_LEN ); REG64_FLD( C_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CFG_DISABLE_PERV_THOLD_CHECK ); REG64_FLD( C_SLAVE_CONFIG_REG_CFG_DISABLE_MALF_PULSE_GEN , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CFG_DISABLE_MALF_PULSE_GEN ); REG64_FLD( C_SLAVE_CONFIG_REG_CFG_STOP_HANG_CNT_SYS_XSTP , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CFG_STOP_HANG_CNT_SYS_XSTP ); REG64_FLD( C_SLAVE_CONFIG_REG_CFG_DISABLE_CL_ATOMIC_LOCK , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CFG_DISABLE_CL_ATOMIC_LOCK ); REG64_FLD( C_SLAVE_CONFIG_REG_CFG_DISABLE_HEARTBEAT , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CFG_DISABLE_HEARTBEAT ); REG64_FLD( C_SLAVE_CONFIG_REG_CFG_DISABLE_FORCE_TO_ZERO , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CFG_DISABLE_FORCE_TO_ZERO ); REG64_FLD( C_SLAVE_CONFIG_REG_CFG_PM_DISABLE , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CFG_PM_DISABLE ); REG64_FLD( C_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CFG_PM_MUX_DISABLE ); REG64_FLD( C_SLAVE_CONFIG_REG_ERROR_MASK , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ERROR_MASK ); REG64_FLD( C_SLAVE_CONFIG_REG_ERROR_MASK_LEN , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ERROR_MASK_LEN ); REG64_FLD( EQ_SPATTN_IN0 , 0 , SH_UNT_EQ , SH_ACS_SCOM2_NC , SH_FLD_IN0 ); REG64_FLD( EQ_SPATTN_IN1 , 1 , SH_UNT_EQ , SH_ACS_SCOM2_NC , SH_FLD_IN1 ); REG64_FLD( EQ_SPATTN_IN2 , 2 , SH_UNT_EQ , SH_ACS_SCOM2_NC , SH_FLD_IN2 ); REG64_FLD( EQ_SPATTN_IN3 , 3 , SH_UNT_EQ , SH_ACS_SCOM2_NC , SH_FLD_IN3 ); REG64_FLD( EQ_SPATTN_IN4 , 4 , SH_UNT_EQ , SH_ACS_SCOM2_NC , SH_FLD_IN4 ); REG64_FLD( EQ_SPATTN_IN5 , 5 , SH_UNT_EQ , SH_ACS_SCOM2_NC , SH_FLD_IN5 ); REG64_FLD( EQ_SPATTN_IN6 , 6 , SH_UNT_EQ , SH_ACS_SCOM2_NC , SH_FLD_IN6 ); REG64_FLD( EQ_SPATTN_IN7 , 7 , SH_UNT_EQ , SH_ACS_SCOM2_NC , SH_FLD_IN7 ); REG64_FLD( EQ_SPATTN_IN8 , 8 , SH_UNT_EQ , SH_ACS_SCOM2_NC , SH_FLD_IN8 ); REG64_FLD( EQ_SPATTN_IN9 , 9 , SH_UNT_EQ , SH_ACS_SCOM2_NC , SH_FLD_IN9 ); REG64_FLD( EX_SPATTN_LT0_SPR_INSTR_STOP , 0 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT0_SPR_INSTR_STOP ); REG64_FLD( EX_SPATTN_LT0_ATTN_COMPLETE , 1 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT0_ATTN_COMPLETE ); REG64_FLD( EX_SPATTN_LT0_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 2 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT0_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( EX_SPATTN_LT0_CORE_CODE_TO_SP , 3 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT0_CORE_CODE_TO_SP ); REG64_FLD( EX_SPATTN_LT1_SPR_INSTR_STOP , 4 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT1_SPR_INSTR_STOP ); REG64_FLD( EX_SPATTN_LT1_ATTN_COMPLETE , 5 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT1_ATTN_COMPLETE ); REG64_FLD( EX_SPATTN_LT1_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 6 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT1_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( EX_SPATTN_LT1_CORE_CODE_TO_SP , 7 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT1_CORE_CODE_TO_SP ); REG64_FLD( EX_SPATTN_LT2_SPR_INSTR_STOP , 8 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT2_SPR_INSTR_STOP ); REG64_FLD( EX_SPATTN_LT2_ATTN_COMPLETE , 9 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT2_ATTN_COMPLETE ); REG64_FLD( EX_SPATTN_LT2_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 10 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT2_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( EX_SPATTN_LT2_CORE_CODE_TO_SP , 11 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT2_CORE_CODE_TO_SP ); REG64_FLD( EX_SPATTN_LT3_SPR_INSTR_STOP , 12 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT3_SPR_INSTR_STOP ); REG64_FLD( EX_SPATTN_LT3_ATTN_COMPLETE , 13 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT3_ATTN_COMPLETE ); REG64_FLD( EX_SPATTN_LT3_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 14 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT3_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( EX_SPATTN_LT3_CORE_CODE_TO_SP , 15 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT3_CORE_CODE_TO_SP ); REG64_FLD( EX_SPATTN_LT4_SPR_INSTR_STOP , 16 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT4_SPR_INSTR_STOP ); REG64_FLD( EX_SPATTN_LT4_ATTN_COMPLETE , 17 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT4_ATTN_COMPLETE ); REG64_FLD( EX_SPATTN_LT4_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 18 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT4_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( EX_SPATTN_LT4_CORE_CODE_TO_SP , 19 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT4_CORE_CODE_TO_SP ); REG64_FLD( EX_SPATTN_LT5_SPR_INSTR_STOP , 20 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT5_SPR_INSTR_STOP ); REG64_FLD( EX_SPATTN_LT5_ATTN_COMPLETE , 21 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT5_ATTN_COMPLETE ); REG64_FLD( EX_SPATTN_LT5_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 22 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT5_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( EX_SPATTN_LT5_CORE_CODE_TO_SP , 23 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT5_CORE_CODE_TO_SP ); REG64_FLD( EX_SPATTN_LT6_SPR_INSTR_STOP , 24 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT6_SPR_INSTR_STOP ); REG64_FLD( EX_SPATTN_LT6_ATTN_COMPLETE , 25 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT6_ATTN_COMPLETE ); REG64_FLD( EX_SPATTN_LT6_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 26 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT6_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( EX_SPATTN_LT6_CORE_CODE_TO_SP , 27 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT6_CORE_CODE_TO_SP ); REG64_FLD( EX_SPATTN_LT7_SPR_INSTR_STOP , 28 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT7_SPR_INSTR_STOP ); REG64_FLD( EX_SPATTN_LT7_ATTN_COMPLETE , 29 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT7_ATTN_COMPLETE ); REG64_FLD( EX_SPATTN_LT7_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 30 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT7_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( EX_SPATTN_LT7_CORE_CODE_TO_SP , 31 , SH_UNT_EX , SH_ACS_SCOM2_NC , SH_FLD_LT7_CORE_CODE_TO_SP ); REG64_FLD( EX_L2_SPATTN_LT0_SPR_INSTR_STOP , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT0_SPR_INSTR_STOP ); REG64_FLD( EX_L2_SPATTN_LT0_ATTN_COMPLETE , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT0_ATTN_COMPLETE ); REG64_FLD( EX_L2_SPATTN_LT0_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT0_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( EX_L2_SPATTN_LT0_CORE_CODE_TO_SP , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT0_CORE_CODE_TO_SP ); REG64_FLD( EX_L2_SPATTN_LT1_SPR_INSTR_STOP , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT1_SPR_INSTR_STOP ); REG64_FLD( EX_L2_SPATTN_LT1_ATTN_COMPLETE , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT1_ATTN_COMPLETE ); REG64_FLD( EX_L2_SPATTN_LT1_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT1_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( EX_L2_SPATTN_LT1_CORE_CODE_TO_SP , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT1_CORE_CODE_TO_SP ); REG64_FLD( EX_L2_SPATTN_LT2_SPR_INSTR_STOP , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT2_SPR_INSTR_STOP ); REG64_FLD( EX_L2_SPATTN_LT2_ATTN_COMPLETE , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT2_ATTN_COMPLETE ); REG64_FLD( EX_L2_SPATTN_LT2_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT2_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( EX_L2_SPATTN_LT2_CORE_CODE_TO_SP , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT2_CORE_CODE_TO_SP ); REG64_FLD( EX_L2_SPATTN_LT3_SPR_INSTR_STOP , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT3_SPR_INSTR_STOP ); REG64_FLD( EX_L2_SPATTN_LT3_ATTN_COMPLETE , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT3_ATTN_COMPLETE ); REG64_FLD( EX_L2_SPATTN_LT3_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT3_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( EX_L2_SPATTN_LT3_CORE_CODE_TO_SP , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT3_CORE_CODE_TO_SP ); REG64_FLD( EX_L2_SPATTN_LT4_SPR_INSTR_STOP , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT4_SPR_INSTR_STOP ); REG64_FLD( EX_L2_SPATTN_LT4_ATTN_COMPLETE , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT4_ATTN_COMPLETE ); REG64_FLD( EX_L2_SPATTN_LT4_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT4_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( EX_L2_SPATTN_LT4_CORE_CODE_TO_SP , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT4_CORE_CODE_TO_SP ); REG64_FLD( EX_L2_SPATTN_LT5_SPR_INSTR_STOP , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT5_SPR_INSTR_STOP ); REG64_FLD( EX_L2_SPATTN_LT5_ATTN_COMPLETE , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT5_ATTN_COMPLETE ); REG64_FLD( EX_L2_SPATTN_LT5_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 22 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT5_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( EX_L2_SPATTN_LT5_CORE_CODE_TO_SP , 23 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT5_CORE_CODE_TO_SP ); REG64_FLD( EX_L2_SPATTN_LT6_SPR_INSTR_STOP , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT6_SPR_INSTR_STOP ); REG64_FLD( EX_L2_SPATTN_LT6_ATTN_COMPLETE , 25 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT6_ATTN_COMPLETE ); REG64_FLD( EX_L2_SPATTN_LT6_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 26 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT6_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( EX_L2_SPATTN_LT6_CORE_CODE_TO_SP , 27 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT6_CORE_CODE_TO_SP ); REG64_FLD( EX_L2_SPATTN_LT7_SPR_INSTR_STOP , 28 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT7_SPR_INSTR_STOP ); REG64_FLD( EX_L2_SPATTN_LT7_ATTN_COMPLETE , 29 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT7_ATTN_COMPLETE ); REG64_FLD( EX_L2_SPATTN_LT7_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 30 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT7_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( EX_L2_SPATTN_LT7_CORE_CODE_TO_SP , 31 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_LT7_CORE_CODE_TO_SP ); REG64_FLD( C_SPATTN_LT0_SPR_INSTR_STOP , 0 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT0_SPR_INSTR_STOP ); REG64_FLD( C_SPATTN_LT0_ATTN_COMPLETE , 1 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT0_ATTN_COMPLETE ); REG64_FLD( C_SPATTN_LT0_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 2 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT0_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( C_SPATTN_LT0_CORE_CODE_TO_SP , 3 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT0_CORE_CODE_TO_SP ); REG64_FLD( C_SPATTN_LT1_SPR_INSTR_STOP , 4 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT1_SPR_INSTR_STOP ); REG64_FLD( C_SPATTN_LT1_ATTN_COMPLETE , 5 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT1_ATTN_COMPLETE ); REG64_FLD( C_SPATTN_LT1_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 6 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT1_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( C_SPATTN_LT1_CORE_CODE_TO_SP , 7 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT1_CORE_CODE_TO_SP ); REG64_FLD( C_SPATTN_LT2_SPR_INSTR_STOP , 8 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT2_SPR_INSTR_STOP ); REG64_FLD( C_SPATTN_LT2_ATTN_COMPLETE , 9 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT2_ATTN_COMPLETE ); REG64_FLD( C_SPATTN_LT2_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 10 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT2_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( C_SPATTN_LT2_CORE_CODE_TO_SP , 11 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT2_CORE_CODE_TO_SP ); REG64_FLD( C_SPATTN_LT3_SPR_INSTR_STOP , 12 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT3_SPR_INSTR_STOP ); REG64_FLD( C_SPATTN_LT3_ATTN_COMPLETE , 13 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT3_ATTN_COMPLETE ); REG64_FLD( C_SPATTN_LT3_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 14 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT3_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( C_SPATTN_LT3_CORE_CODE_TO_SP , 15 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT3_CORE_CODE_TO_SP ); REG64_FLD( C_SPATTN_LT4_SPR_INSTR_STOP , 16 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT4_SPR_INSTR_STOP ); REG64_FLD( C_SPATTN_LT4_ATTN_COMPLETE , 17 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT4_ATTN_COMPLETE ); REG64_FLD( C_SPATTN_LT4_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 18 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT4_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( C_SPATTN_LT4_CORE_CODE_TO_SP , 19 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT4_CORE_CODE_TO_SP ); REG64_FLD( C_SPATTN_LT5_SPR_INSTR_STOP , 20 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT5_SPR_INSTR_STOP ); REG64_FLD( C_SPATTN_LT5_ATTN_COMPLETE , 21 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT5_ATTN_COMPLETE ); REG64_FLD( C_SPATTN_LT5_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 22 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT5_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( C_SPATTN_LT5_CORE_CODE_TO_SP , 23 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT5_CORE_CODE_TO_SP ); REG64_FLD( C_SPATTN_LT6_SPR_INSTR_STOP , 24 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT6_SPR_INSTR_STOP ); REG64_FLD( C_SPATTN_LT6_ATTN_COMPLETE , 25 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT6_ATTN_COMPLETE ); REG64_FLD( C_SPATTN_LT6_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 26 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT6_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( C_SPATTN_LT6_CORE_CODE_TO_SP , 27 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT6_CORE_CODE_TO_SP ); REG64_FLD( C_SPATTN_LT7_SPR_INSTR_STOP , 28 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT7_SPR_INSTR_STOP ); REG64_FLD( C_SPATTN_LT7_ATTN_COMPLETE , 29 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT7_ATTN_COMPLETE ); REG64_FLD( C_SPATTN_LT7_CORE_CHECKSTOP_RECOVERY_HANDSHAKE , 30 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT7_CORE_CHECKSTOP_RECOVERY_HANDSHAKE ); REG64_FLD( C_SPATTN_LT7_CORE_CODE_TO_SP , 31 , SH_UNT_C , SH_ACS_SCOM2_NC , SH_FLD_LT7_CORE_CODE_TO_SP ); REG64_FLD( EX_L2_SPATTN_MASK_LT0_SPATTN_MASK , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_LT0_SPATTN_MASK ); REG64_FLD( EX_L2_SPATTN_MASK_LT0_SPATTN_MASK_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_LT0_SPATTN_MASK_LEN ); REG64_FLD( EX_L2_SPATTN_MASK_LT1_SPATTN_MASK , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_LT1_SPATTN_MASK ); REG64_FLD( EX_L2_SPATTN_MASK_LT1_SPATTN_MASK_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_LT1_SPATTN_MASK_LEN ); REG64_FLD( EX_L2_SPATTN_MASK_LT2_SPATTN_MASK , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_LT2_SPATTN_MASK ); REG64_FLD( EX_L2_SPATTN_MASK_LT2_SPATTN_MASK_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_LT2_SPATTN_MASK_LEN ); REG64_FLD( EX_L2_SPATTN_MASK_LT3_SPATTN_MASK , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_LT3_SPATTN_MASK ); REG64_FLD( EX_L2_SPATTN_MASK_LT3_SPATTN_MASK_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_LT3_SPATTN_MASK_LEN ); REG64_FLD( EX_L2_SPATTN_MASK_LT4_SPATTN_MASK , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_LT4_SPATTN_MASK ); REG64_FLD( EX_L2_SPATTN_MASK_LT4_SPATTN_MASK_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_LT4_SPATTN_MASK_LEN ); REG64_FLD( EX_L2_SPATTN_MASK_LT5_SPATTN_MASK , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_LT5_SPATTN_MASK ); REG64_FLD( EX_L2_SPATTN_MASK_LT5_SPATTN_MASK_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_LT5_SPATTN_MASK_LEN ); REG64_FLD( EX_L2_SPATTN_MASK_LT6_SPATTN_MASK , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_LT6_SPATTN_MASK ); REG64_FLD( EX_L2_SPATTN_MASK_LT6_SPATTN_MASK_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_LT6_SPATTN_MASK_LEN ); REG64_FLD( EX_L2_SPATTN_MASK_LT7_SPATTN_MASK , 28 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_LT7_SPATTN_MASK ); REG64_FLD( EX_L2_SPATTN_MASK_LT7_SPATTN_MASK_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_LT7_SPATTN_MASK_LEN ); REG64_FLD( C_SPATTN_MASK_LT0_SPATTN_MASK , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LT0_SPATTN_MASK ); REG64_FLD( C_SPATTN_MASK_LT0_SPATTN_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LT0_SPATTN_MASK_LEN ); REG64_FLD( C_SPATTN_MASK_LT1_SPATTN_MASK , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LT1_SPATTN_MASK ); REG64_FLD( C_SPATTN_MASK_LT1_SPATTN_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LT1_SPATTN_MASK_LEN ); REG64_FLD( C_SPATTN_MASK_LT2_SPATTN_MASK , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LT2_SPATTN_MASK ); REG64_FLD( C_SPATTN_MASK_LT2_SPATTN_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LT2_SPATTN_MASK_LEN ); REG64_FLD( C_SPATTN_MASK_LT3_SPATTN_MASK , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LT3_SPATTN_MASK ); REG64_FLD( C_SPATTN_MASK_LT3_SPATTN_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LT3_SPATTN_MASK_LEN ); REG64_FLD( C_SPATTN_MASK_LT4_SPATTN_MASK , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LT4_SPATTN_MASK ); REG64_FLD( C_SPATTN_MASK_LT4_SPATTN_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LT4_SPATTN_MASK_LEN ); REG64_FLD( C_SPATTN_MASK_LT5_SPATTN_MASK , 20 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LT5_SPATTN_MASK ); REG64_FLD( C_SPATTN_MASK_LT5_SPATTN_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LT5_SPATTN_MASK_LEN ); REG64_FLD( C_SPATTN_MASK_LT6_SPATTN_MASK , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LT6_SPATTN_MASK ); REG64_FLD( C_SPATTN_MASK_LT6_SPATTN_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LT6_SPATTN_MASK_LEN ); REG64_FLD( C_SPATTN_MASK_LT7_SPATTN_MASK , 28 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LT7_SPATTN_MASK ); REG64_FLD( C_SPATTN_MASK_LT7_SPATTN_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LT7_SPATTN_MASK_LEN ); REG64_FLD( EQ_SPA_MASK_IN , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( EQ_SPA_MASK_IN_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( EX_SPA_MASK_IN , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( EX_SPA_MASK_IN_LEN , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( C_SPA_MASK_IN , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( C_SPA_MASK_IN_LEN , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( EX_L2_SPR_CORE_HOLD_OUT_IMA_HOLD_OUT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_IMA_HOLD_OUT ); REG64_FLD( EX_L2_SPR_CORE_HOLD_OUT_PTID_RECONFIG_SM_HOLD_OUT , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_PTID_RECONFIG_SM_HOLD_OUT ); REG64_FLD( EX_L2_SPR_CORE_HOLD_OUT_VS_ERR_HOLD_OUT , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VS_ERR_HOLD_OUT ); REG64_FLD( EX_L2_SPR_CORE_HOLD_OUT_VS_ERR_HOLD_OUT_LEN , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VS_ERR_HOLD_OUT_LEN ); REG64_FLD( EX_L2_SPR_CORE_HOLD_OUT_VT0_LPCR_ONL_PAR_HOLD_OUT , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT0_LPCR_ONL_PAR_HOLD_OUT ); REG64_FLD( EX_L2_SPR_CORE_HOLD_OUT_VT1_LPCR_ONL_PAR_HOLD_OUT , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT1_LPCR_ONL_PAR_HOLD_OUT ); REG64_FLD( EX_L2_SPR_CORE_HOLD_OUT_VT2_LPCR_ONL_PAR_HOLD_OUT , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT2_LPCR_ONL_PAR_HOLD_OUT ); REG64_FLD( EX_L2_SPR_CORE_HOLD_OUT_VT3_LPCR_ONL_PAR_HOLD_OUT , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_VT3_LPCR_ONL_PAR_HOLD_OUT ); REG64_FLD( C_SPR_CORE_HOLD_OUT_IMA_HOLD_OUT , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_IMA_HOLD_OUT ); REG64_FLD( C_SPR_CORE_HOLD_OUT_PTID_RECONFIG_SM_HOLD_OUT , 1 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_PTID_RECONFIG_SM_HOLD_OUT ); REG64_FLD( C_SPR_CORE_HOLD_OUT_VS_ERR_HOLD_OUT , 2 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VS_ERR_HOLD_OUT ); REG64_FLD( C_SPR_CORE_HOLD_OUT_VS_ERR_HOLD_OUT_LEN , 6 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VS_ERR_HOLD_OUT_LEN ); REG64_FLD( C_SPR_CORE_HOLD_OUT_VT0_LPCR_ONL_PAR_HOLD_OUT , 8 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT0_LPCR_ONL_PAR_HOLD_OUT ); REG64_FLD( C_SPR_CORE_HOLD_OUT_VT1_LPCR_ONL_PAR_HOLD_OUT , 9 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT1_LPCR_ONL_PAR_HOLD_OUT ); REG64_FLD( C_SPR_CORE_HOLD_OUT_VT2_LPCR_ONL_PAR_HOLD_OUT , 10 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT2_LPCR_ONL_PAR_HOLD_OUT ); REG64_FLD( C_SPR_CORE_HOLD_OUT_VT3_LPCR_ONL_PAR_HOLD_OUT , 11 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VT3_LPCR_ONL_PAR_HOLD_OUT ); REG64_FLD( EX_L2_SPR_MODE_MODEREG_TFAC_ERR_INJ , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_MODEREG_TFAC_ERR_INJ ); REG64_FLD( EX_L2_SPR_MODE_MODEREG_TFAC_ERR_INJ_LEN , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_MODEREG_TFAC_ERR_INJ_LEN ); REG64_FLD( EX_L2_SPR_MODE_MODEREG_SPRC_LT0_SEL , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_MODEREG_SPRC_LT0_SEL ); REG64_FLD( EX_L2_SPR_MODE_MODEREG_SPRC_LT1_SEL , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_MODEREG_SPRC_LT1_SEL ); REG64_FLD( EX_L2_SPR_MODE_MODEREG_SPRC_LT2_SEL , 22 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_MODEREG_SPRC_LT2_SEL ); REG64_FLD( EX_L2_SPR_MODE_MODEREG_SPRC_LT3_SEL , 23 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_MODEREG_SPRC_LT3_SEL ); REG64_FLD( EX_L2_SPR_MODE_MODEREG_SPRC_LT4_SEL , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_MODEREG_SPRC_LT4_SEL ); REG64_FLD( EX_L2_SPR_MODE_MODEREG_SPRC_LT5_SEL , 25 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_MODEREG_SPRC_LT5_SEL ); REG64_FLD( EX_L2_SPR_MODE_MODEREG_SPRC_LT6_SEL , 26 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_MODEREG_SPRC_LT6_SEL ); REG64_FLD( EX_L2_SPR_MODE_MODEREG_SPRC_LT7_SEL , 27 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_MODEREG_SPRC_LT7_SEL ); REG64_FLD( C_SPR_MODE_MODEREG_TFAC_ERR_INJ , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MODEREG_TFAC_ERR_INJ ); REG64_FLD( C_SPR_MODE_MODEREG_TFAC_ERR_INJ_LEN , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MODEREG_TFAC_ERR_INJ_LEN ); REG64_FLD( C_SPR_MODE_MODEREG_SPRC_LT0_SEL , 20 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MODEREG_SPRC_LT0_SEL ); REG64_FLD( C_SPR_MODE_MODEREG_SPRC_LT1_SEL , 21 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MODEREG_SPRC_LT1_SEL ); REG64_FLD( C_SPR_MODE_MODEREG_SPRC_LT2_SEL , 22 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MODEREG_SPRC_LT2_SEL ); REG64_FLD( C_SPR_MODE_MODEREG_SPRC_LT3_SEL , 23 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MODEREG_SPRC_LT3_SEL ); REG64_FLD( C_SPR_MODE_MODEREG_SPRC_LT4_SEL , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MODEREG_SPRC_LT4_SEL ); REG64_FLD( C_SPR_MODE_MODEREG_SPRC_LT5_SEL , 25 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MODEREG_SPRC_LT5_SEL ); REG64_FLD( C_SPR_MODE_MODEREG_SPRC_LT6_SEL , 26 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MODEREG_SPRC_LT6_SEL ); REG64_FLD( C_SPR_MODE_MODEREG_SPRC_LT7_SEL , 27 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MODEREG_SPRC_LT7_SEL ); REG64_FLD( EX_SPURR_FREQ_DETECT_CYC_CNT_CYCLE_COUNT , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_CYCLE_COUNT ); REG64_FLD( EX_SPURR_FREQ_DETECT_CYC_CNT_CYCLE_COUNT_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_CYCLE_COUNT_LEN ); REG64_FLD( C_SPURR_FREQ_DETECT_CYC_CNT_CYCLE_COUNT , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_CYCLE_COUNT ); REG64_FLD( C_SPURR_FREQ_DETECT_CYC_CNT_CYCLE_COUNT_LEN , 8 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_CYCLE_COUNT_LEN ); REG64_FLD( EX_L2_SPURR_FREQ_REF_FREQUENCY_REFERENCE , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_FREQUENCY_REFERENCE ); REG64_FLD( EX_L2_SPURR_FREQ_REF_FREQUENCY_REFERENCE_LEN , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_FREQUENCY_REFERENCE_LEN ); REG64_FLD( C_SPURR_FREQ_REF_FREQUENCY_REFERENCE , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_FREQUENCY_REFERENCE ); REG64_FLD( C_SPURR_FREQ_REF_FREQUENCY_REFERENCE_LEN , 8 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_FREQUENCY_REFERENCE_LEN ); REG64_FLD( EX_L2_SPURR_FREQ_SCALE_OVERRIDE_EN , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_OVERRIDE_EN ); REG64_FLD( EX_L2_SPURR_FREQ_SCALE_FACTOR , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_FACTOR ); REG64_FLD( EX_L2_SPURR_FREQ_SCALE_FACTOR_LEN , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM_RW , SH_FLD_FACTOR_LEN ); REG64_FLD( C_SPURR_FREQ_SCALE_OVERRIDE_EN , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_OVERRIDE_EN ); REG64_FLD( C_SPURR_FREQ_SCALE_FACTOR , 1 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_FACTOR ); REG64_FLD( C_SPURR_FREQ_SCALE_FACTOR_LEN , 7 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_FACTOR_LEN ); REG64_FLD( EX_SRC_MASK_SRC_MASK_TBD , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SRC_MASK_TBD ); REG64_FLD( EX_SRC_MASK_SRC_MASK_TBD_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SRC_MASK_TBD_LEN ); REG64_FLD( C_SRC_MASK_SRC_MASK_TBD , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SRC_MASK_TBD ); REG64_FLD( C_SRC_MASK_SRC_MASK_TBD_LEN , 64 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SRC_MASK_TBD_LEN ); REG64_FLD( EQ_SUM_MASK_REG_SMASK_IN0 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SMASK_IN0 ); REG64_FLD( EQ_SUM_MASK_REG_SMASK_IN1 , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SMASK_IN1 ); REG64_FLD( EQ_SUM_MASK_REG_SMASK_IN2 , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SMASK_IN2 ); REG64_FLD( EQ_SUM_MASK_REG_SMASK_IN3 , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SMASK_IN3 ); REG64_FLD( EQ_SUM_MASK_REG_SMASK_IN4 , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SMASK_IN4 ); REG64_FLD( EX_SUM_MASK_REG_SMASK_IN0 , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SMASK_IN0 ); REG64_FLD( EX_SUM_MASK_REG_SMASK_IN1 , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SMASK_IN1 ); REG64_FLD( EX_SUM_MASK_REG_SMASK_IN2 , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SMASK_IN2 ); REG64_FLD( EX_SUM_MASK_REG_SMASK_IN3 , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SMASK_IN3 ); REG64_FLD( EX_SUM_MASK_REG_SMASK_IN4 , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SMASK_IN4 ); REG64_FLD( C_SUM_MASK_REG_SMASK_IN0 , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SMASK_IN0 ); REG64_FLD( C_SUM_MASK_REG_SMASK_IN1 , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SMASK_IN1 ); REG64_FLD( C_SUM_MASK_REG_SMASK_IN2 , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SMASK_IN2 ); REG64_FLD( C_SUM_MASK_REG_SMASK_IN3 , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SMASK_IN3 ); REG64_FLD( C_SUM_MASK_REG_SMASK_IN4 , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SMASK_IN4 ); REG64_FLD( EQ_SYNC_CONFIG_PULSE_DELAY , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PULSE_DELAY ); REG64_FLD( EQ_SYNC_CONFIG_PULSE_DELAY_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PULSE_DELAY_LEN ); REG64_FLD( EQ_SYNC_CONFIG_LISTEN_TO_PULSE_DIS , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LISTEN_TO_PULSE_DIS ); REG64_FLD( EQ_SYNC_CONFIG_PULSE_INPUT_SEL , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PULSE_INPUT_SEL ); REG64_FLD( EQ_SYNC_CONFIG_USE_FOR_SCAN , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_USE_FOR_SCAN ); REG64_FLD( EQ_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CLEAR_CHIPLET_IS_ALIGNED ); REG64_FLD( EQ_SYNC_CONFIG_UNIT_REGION_CLKCMD_ENABLE , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT_REGION_CLKCMD_ENABLE ); REG64_FLD( EQ_SYNC_CONFIG_DISABLE_PCB_ITR , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DISABLE_PCB_ITR ); REG64_FLD( EQ_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENABLE_VITL_ALIGN_CHECK ); REG64_FLD( EQ_SYNC_CONFIG_PULSE_OUT_DIS , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PULSE_OUT_DIS ); REG64_FLD( EQ_SYNC_CONFIG_UNUSED1219 , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED1219 ); REG64_FLD( EQ_SYNC_CONFIG_UNUSED1219_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED1219_LEN ); REG64_FLD( EX_SYNC_CONFIG_PULSE_DELAY , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PULSE_DELAY ); REG64_FLD( EX_SYNC_CONFIG_PULSE_DELAY_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PULSE_DELAY_LEN ); REG64_FLD( EX_SYNC_CONFIG_LISTEN_TO_PULSE_DIS , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_LISTEN_TO_PULSE_DIS ); REG64_FLD( EX_SYNC_CONFIG_PULSE_INPUT_SEL , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PULSE_INPUT_SEL ); REG64_FLD( EX_SYNC_CONFIG_USE_FOR_SCAN , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_USE_FOR_SCAN ); REG64_FLD( EX_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CLEAR_CHIPLET_IS_ALIGNED ); REG64_FLD( EX_SYNC_CONFIG_UNIT_REGION_CLKCMD_ENABLE , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT_REGION_CLKCMD_ENABLE ); REG64_FLD( EX_SYNC_CONFIG_DISABLE_PCB_ITR , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DISABLE_PCB_ITR ); REG64_FLD( EX_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ENABLE_VITL_ALIGN_CHECK ); REG64_FLD( EX_SYNC_CONFIG_PULSE_OUT_DIS , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PULSE_OUT_DIS ); REG64_FLD( EX_SYNC_CONFIG_UNUSED1219 , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED1219 ); REG64_FLD( EX_SYNC_CONFIG_UNUSED1219_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED1219_LEN ); REG64_FLD( C_SYNC_CONFIG_PULSE_DELAY , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PULSE_DELAY ); REG64_FLD( C_SYNC_CONFIG_PULSE_DELAY_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PULSE_DELAY_LEN ); REG64_FLD( C_SYNC_CONFIG_LISTEN_TO_PULSE_DIS , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LISTEN_TO_PULSE_DIS ); REG64_FLD( C_SYNC_CONFIG_PULSE_INPUT_SEL , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PULSE_INPUT_SEL ); REG64_FLD( C_SYNC_CONFIG_USE_FOR_SCAN , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_USE_FOR_SCAN ); REG64_FLD( C_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CLEAR_CHIPLET_IS_ALIGNED ); REG64_FLD( C_SYNC_CONFIG_UNIT_REGION_CLKCMD_ENABLE , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT_REGION_CLKCMD_ENABLE ); REG64_FLD( C_SYNC_CONFIG_DISABLE_PCB_ITR , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DISABLE_PCB_ITR ); REG64_FLD( C_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ENABLE_VITL_ALIGN_CHECK ); REG64_FLD( C_SYNC_CONFIG_PULSE_OUT_DIS , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PULSE_OUT_DIS ); REG64_FLD( C_SYNC_CONFIG_UNUSED1219 , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED1219 ); REG64_FLD( C_SYNC_CONFIG_UNUSED1219_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED1219_LEN ); REG64_FLD( EX_L2_T0_PMU_SCOM_IDLE_DELAY , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_IDLE_DELAY ); REG64_FLD( EX_L2_T0_PMU_SCOM_IDLE_DELAY_LEN , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_IDLE_DELAY_LEN ); REG64_FLD( EX_L2_T0_PMU_SCOM_COMPLETION_DELAY , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_COMPLETION_DELAY ); REG64_FLD( EX_L2_T0_PMU_SCOM_COMPLETION_DELAY_LEN , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_COMPLETION_DELAY_LEN ); REG64_FLD( EX_L2_T0_PMU_SCOM_SAMPLE_OVERRIDE , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SAMPLE_OVERRIDE ); REG64_FLD( EX_L2_T0_PMU_SCOM_SPARE_CTRL , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SPARE_CTRL ); REG64_FLD( EX_L2_T0_PMU_SCOM_SPARE_CTRL_LEN , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SPARE_CTRL_LEN ); REG64_FLD( C_T0_PMU_SCOM_IDLE_DELAY , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IDLE_DELAY ); REG64_FLD( C_T0_PMU_SCOM_IDLE_DELAY_LEN , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IDLE_DELAY_LEN ); REG64_FLD( C_T0_PMU_SCOM_COMPLETION_DELAY , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COMPLETION_DELAY ); REG64_FLD( C_T0_PMU_SCOM_COMPLETION_DELAY_LEN , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COMPLETION_DELAY_LEN ); REG64_FLD( C_T0_PMU_SCOM_SAMPLE_OVERRIDE , 18 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SAMPLE_OVERRIDE ); REG64_FLD( C_T0_PMU_SCOM_SPARE_CTRL , 19 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SPARE_CTRL ); REG64_FLD( C_T0_PMU_SCOM_SPARE_CTRL_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SPARE_CTRL_LEN ); REG64_FLD( EX_L2_T1_PMU_SCOM_IDLE_DELAY , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_IDLE_DELAY ); REG64_FLD( EX_L2_T1_PMU_SCOM_IDLE_DELAY_LEN , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_IDLE_DELAY_LEN ); REG64_FLD( EX_L2_T1_PMU_SCOM_COMPLETION_DELAY , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_COMPLETION_DELAY ); REG64_FLD( EX_L2_T1_PMU_SCOM_COMPLETION_DELAY_LEN , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_COMPLETION_DELAY_LEN ); REG64_FLD( EX_L2_T1_PMU_SCOM_SAMPLE_OVERRIDE , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SAMPLE_OVERRIDE ); REG64_FLD( EX_L2_T1_PMU_SCOM_SPARE_CTRL , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SPARE_CTRL ); REG64_FLD( EX_L2_T1_PMU_SCOM_SPARE_CTRL_LEN , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SPARE_CTRL_LEN ); REG64_FLD( C_T1_PMU_SCOM_IDLE_DELAY , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IDLE_DELAY ); REG64_FLD( C_T1_PMU_SCOM_IDLE_DELAY_LEN , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IDLE_DELAY_LEN ); REG64_FLD( C_T1_PMU_SCOM_COMPLETION_DELAY , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COMPLETION_DELAY ); REG64_FLD( C_T1_PMU_SCOM_COMPLETION_DELAY_LEN , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COMPLETION_DELAY_LEN ); REG64_FLD( C_T1_PMU_SCOM_SAMPLE_OVERRIDE , 18 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SAMPLE_OVERRIDE ); REG64_FLD( C_T1_PMU_SCOM_SPARE_CTRL , 19 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SPARE_CTRL ); REG64_FLD( C_T1_PMU_SCOM_SPARE_CTRL_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SPARE_CTRL_LEN ); REG64_FLD( EX_L2_T2_PMU_SCOM_IDLE_DELAY , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_IDLE_DELAY ); REG64_FLD( EX_L2_T2_PMU_SCOM_IDLE_DELAY_LEN , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_IDLE_DELAY_LEN ); REG64_FLD( EX_L2_T2_PMU_SCOM_COMPLETION_DELAY , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_COMPLETION_DELAY ); REG64_FLD( EX_L2_T2_PMU_SCOM_COMPLETION_DELAY_LEN , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_COMPLETION_DELAY_LEN ); REG64_FLD( EX_L2_T2_PMU_SCOM_SAMPLE_OVERRIDE , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SAMPLE_OVERRIDE ); REG64_FLD( EX_L2_T2_PMU_SCOM_SPARE_CTRL , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SPARE_CTRL ); REG64_FLD( EX_L2_T2_PMU_SCOM_SPARE_CTRL_LEN , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SPARE_CTRL_LEN ); REG64_FLD( C_T2_PMU_SCOM_IDLE_DELAY , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IDLE_DELAY ); REG64_FLD( C_T2_PMU_SCOM_IDLE_DELAY_LEN , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IDLE_DELAY_LEN ); REG64_FLD( C_T2_PMU_SCOM_COMPLETION_DELAY , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COMPLETION_DELAY ); REG64_FLD( C_T2_PMU_SCOM_COMPLETION_DELAY_LEN , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COMPLETION_DELAY_LEN ); REG64_FLD( C_T2_PMU_SCOM_SAMPLE_OVERRIDE , 18 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SAMPLE_OVERRIDE ); REG64_FLD( C_T2_PMU_SCOM_SPARE_CTRL , 19 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SPARE_CTRL ); REG64_FLD( C_T2_PMU_SCOM_SPARE_CTRL_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SPARE_CTRL_LEN ); REG64_FLD( EX_L2_T3_PMU_SCOM_IDLE_DELAY , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_IDLE_DELAY ); REG64_FLD( EX_L2_T3_PMU_SCOM_IDLE_DELAY_LEN , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_IDLE_DELAY_LEN ); REG64_FLD( EX_L2_T3_PMU_SCOM_COMPLETION_DELAY , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_COMPLETION_DELAY ); REG64_FLD( EX_L2_T3_PMU_SCOM_COMPLETION_DELAY_LEN , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_COMPLETION_DELAY_LEN ); REG64_FLD( EX_L2_T3_PMU_SCOM_SAMPLE_OVERRIDE , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SAMPLE_OVERRIDE ); REG64_FLD( EX_L2_T3_PMU_SCOM_SPARE_CTRL , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SPARE_CTRL ); REG64_FLD( EX_L2_T3_PMU_SCOM_SPARE_CTRL_LEN , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SPARE_CTRL_LEN ); REG64_FLD( C_T3_PMU_SCOM_IDLE_DELAY , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IDLE_DELAY ); REG64_FLD( C_T3_PMU_SCOM_IDLE_DELAY_LEN , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IDLE_DELAY_LEN ); REG64_FLD( C_T3_PMU_SCOM_COMPLETION_DELAY , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COMPLETION_DELAY ); REG64_FLD( C_T3_PMU_SCOM_COMPLETION_DELAY_LEN , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_COMPLETION_DELAY_LEN ); REG64_FLD( C_T3_PMU_SCOM_SAMPLE_OVERRIDE , 18 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SAMPLE_OVERRIDE ); REG64_FLD( C_T3_PMU_SCOM_SPARE_CTRL , 19 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SPARE_CTRL ); REG64_FLD( C_T3_PMU_SCOM_SPARE_CTRL_LEN , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SPARE_CTRL_LEN ); REG64_FLD( EQ_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DIS_CPM_BUBBLE_CORR ); REG64_FLD( EQ_THERM_MODE_REG_FORCE_THRES_ACT , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_FORCE_THRES_ACT ); REG64_FLD( EQ_THERM_MODE_REG_THRES_TRIP_ENA , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_THRES_TRIP_ENA ); REG64_FLD( EQ_THERM_MODE_REG_THRES_TRIP_ENA_LEN , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_THRES_TRIP_ENA_LEN ); REG64_FLD( EQ_THERM_MODE_REG_DTS_SAMPLE_ENA , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DTS_SAMPLE_ENA ); REG64_FLD( EQ_THERM_MODE_REG_SAMPLE_PULSE_CNT , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SAMPLE_PULSE_CNT ); REG64_FLD( EQ_THERM_MODE_REG_SAMPLE_PULSE_CNT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SAMPLE_PULSE_CNT_LEN ); REG64_FLD( EQ_THERM_MODE_REG_THRES_ENA , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_THRES_ENA ); REG64_FLD( EQ_THERM_MODE_REG_THRES_ENA_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_THRES_ENA_LEN ); REG64_FLD( EQ_THERM_MODE_REG_DTS_TRIGGER , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DTS_TRIGGER ); REG64_FLD( EQ_THERM_MODE_REG_DTS_TRIGGER_SEL , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DTS_TRIGGER_SEL ); REG64_FLD( EQ_THERM_MODE_REG_THRES_OVERFLOW_MASK , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_THRES_OVERFLOW_MASK ); REG64_FLD( EQ_THERM_MODE_REG_UNUSED , 15 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( EQ_THERM_MODE_REG_DTS_READ_SEL , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DTS_READ_SEL ); REG64_FLD( EQ_THERM_MODE_REG_DTS_READ_SEL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DTS_READ_SEL_LEN ); REG64_FLD( EQ_THERM_MODE_REG_DTS_ENABLE_L1 , 20 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DTS_ENABLE_L1 ); REG64_FLD( EQ_THERM_MODE_REG_DTS_ENABLE_L1_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DTS_ENABLE_L1_LEN ); REG64_FLD( EQ_THERM_MODE_REG_THERM_CPM_ENABLE_L1 , 35 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_THERM_CPM_ENABLE_L1 ); REG64_FLD( EQ_THERM_MODE_REG_THERM_CPM_ENABLE_L1_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_THERM_CPM_ENABLE_L1_LEN ); REG64_FLD( EX_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DIS_CPM_BUBBLE_CORR ); REG64_FLD( EX_THERM_MODE_REG_FORCE_THRES_ACT , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_FORCE_THRES_ACT ); REG64_FLD( EX_THERM_MODE_REG_THRES_TRIP_ENA , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_THRES_TRIP_ENA ); REG64_FLD( EX_THERM_MODE_REG_THRES_TRIP_ENA_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_THRES_TRIP_ENA_LEN ); REG64_FLD( EX_THERM_MODE_REG_DTS_SAMPLE_ENA , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DTS_SAMPLE_ENA ); REG64_FLD( EX_THERM_MODE_REG_SAMPLE_PULSE_CNT , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SAMPLE_PULSE_CNT ); REG64_FLD( EX_THERM_MODE_REG_SAMPLE_PULSE_CNT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SAMPLE_PULSE_CNT_LEN ); REG64_FLD( EX_THERM_MODE_REG_THRES_ENA , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_THRES_ENA ); REG64_FLD( EX_THERM_MODE_REG_THRES_ENA_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_THRES_ENA_LEN ); REG64_FLD( EX_THERM_MODE_REG_DTS_TRIGGER , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DTS_TRIGGER ); REG64_FLD( EX_THERM_MODE_REG_DTS_TRIGGER_SEL , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DTS_TRIGGER_SEL ); REG64_FLD( EX_THERM_MODE_REG_THRES_OVERFLOW_MASK , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_THRES_OVERFLOW_MASK ); REG64_FLD( EX_THERM_MODE_REG_UNUSED , 15 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( EX_THERM_MODE_REG_DTS_READ_SEL , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DTS_READ_SEL ); REG64_FLD( EX_THERM_MODE_REG_DTS_READ_SEL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DTS_READ_SEL_LEN ); REG64_FLD( EX_THERM_MODE_REG_DTS_ENABLE_L1 , 20 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DTS_ENABLE_L1 ); REG64_FLD( EX_THERM_MODE_REG_DTS_ENABLE_L1_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DTS_ENABLE_L1_LEN ); REG64_FLD( EX_THERM_MODE_REG_THERM_CPM_ENABLE_L1 , 35 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_THERM_CPM_ENABLE_L1 ); REG64_FLD( EX_THERM_MODE_REG_THERM_CPM_ENABLE_L1_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_THERM_CPM_ENABLE_L1_LEN ); REG64_FLD( C_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DIS_CPM_BUBBLE_CORR ); REG64_FLD( C_THERM_MODE_REG_FORCE_THRES_ACT , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_FORCE_THRES_ACT ); REG64_FLD( C_THERM_MODE_REG_THRES_TRIP_ENA , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_THRES_TRIP_ENA ); REG64_FLD( C_THERM_MODE_REG_THRES_TRIP_ENA_LEN , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_THRES_TRIP_ENA_LEN ); REG64_FLD( C_THERM_MODE_REG_DTS_SAMPLE_ENA , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DTS_SAMPLE_ENA ); REG64_FLD( C_THERM_MODE_REG_SAMPLE_PULSE_CNT , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SAMPLE_PULSE_CNT ); REG64_FLD( C_THERM_MODE_REG_SAMPLE_PULSE_CNT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SAMPLE_PULSE_CNT_LEN ); REG64_FLD( C_THERM_MODE_REG_THRES_ENA , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_THRES_ENA ); REG64_FLD( C_THERM_MODE_REG_THRES_ENA_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_THRES_ENA_LEN ); REG64_FLD( C_THERM_MODE_REG_DTS_TRIGGER , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DTS_TRIGGER ); REG64_FLD( C_THERM_MODE_REG_DTS_TRIGGER_SEL , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DTS_TRIGGER_SEL ); REG64_FLD( C_THERM_MODE_REG_THRES_OVERFLOW_MASK , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_THRES_OVERFLOW_MASK ); REG64_FLD( C_THERM_MODE_REG_UNUSED , 15 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( C_THERM_MODE_REG_DTS_READ_SEL , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DTS_READ_SEL ); REG64_FLD( C_THERM_MODE_REG_DTS_READ_SEL_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DTS_READ_SEL_LEN ); REG64_FLD( C_THERM_MODE_REG_DTS_ENABLE_L1 , 20 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DTS_ENABLE_L1 ); REG64_FLD( C_THERM_MODE_REG_DTS_ENABLE_L1_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DTS_ENABLE_L1_LEN ); REG64_FLD( C_THERM_MODE_REG_THERM_CPM_ENABLE_L1 , 35 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_THERM_CPM_ENABLE_L1 ); REG64_FLD( C_THERM_MODE_REG_THERM_CPM_ENABLE_L1_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_THERM_CPM_ENABLE_L1_LEN ); REG64_FLD( EX_L2_THREAD_INFO_VTID0_V , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_VTID0_V ); REG64_FLD( EX_L2_THREAD_INFO_VTID1_V , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_VTID1_V ); REG64_FLD( EX_L2_THREAD_INFO_VTID2_V , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_VTID2_V ); REG64_FLD( EX_L2_THREAD_INFO_VTID3_V , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_VTID3_V ); REG64_FLD( EX_L2_THREAD_INFO_PTID0_V , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PTID0_V ); REG64_FLD( EX_L2_THREAD_INFO_PTID1_V , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PTID1_V ); REG64_FLD( EX_L2_THREAD_INFO_PTID2_V , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PTID2_V ); REG64_FLD( EX_L2_THREAD_INFO_PTID3_V , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PTID3_V ); REG64_FLD( EX_L2_THREAD_INFO_SMT_MODE , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SMT_MODE ); REG64_FLD( EX_L2_THREAD_INFO_SMT_MODE_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_SMT_MODE_LEN ); REG64_FLD( EX_L2_THREAD_INFO_VTID0_TO_PTID_MAP , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_VTID0_TO_PTID_MAP ); REG64_FLD( EX_L2_THREAD_INFO_VTID0_TO_PTID_MAP_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_VTID0_TO_PTID_MAP_LEN ); REG64_FLD( EX_L2_THREAD_INFO_VTID1_TO_PTID_MAP , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_VTID1_TO_PTID_MAP ); REG64_FLD( EX_L2_THREAD_INFO_VTID1_TO_PTID_MAP_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_VTID1_TO_PTID_MAP_LEN ); REG64_FLD( EX_L2_THREAD_INFO_VTID2_TO_PTID_MAP , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_VTID2_TO_PTID_MAP ); REG64_FLD( EX_L2_THREAD_INFO_VTID2_TO_PTID_MAP_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_VTID2_TO_PTID_MAP_LEN ); REG64_FLD( EX_L2_THREAD_INFO_VTID3_TO_PTID_MAP , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_VTID3_TO_PTID_MAP ); REG64_FLD( EX_L2_THREAD_INFO_VTID3_TO_PTID_MAP_LEN , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_VTID3_TO_PTID_MAP_LEN ); REG64_FLD( EX_L2_THREAD_INFO_RAM_THREAD_ACTIVE , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_RAM_THREAD_ACTIVE ); REG64_FLD( EX_L2_THREAD_INFO_RAM_THREAD_ACTIVE_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_RAM_THREAD_ACTIVE_LEN ); REG64_FLD( EX_L2_THREAD_INFO_PSCOM_PURGE , 22 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_PSCOM_PURGE ); REG64_FLD( C_THREAD_INFO_VTID0_V , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_VTID0_V ); REG64_FLD( C_THREAD_INFO_VTID1_V , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_VTID1_V ); REG64_FLD( C_THREAD_INFO_VTID2_V , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_VTID2_V ); REG64_FLD( C_THREAD_INFO_VTID3_V , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_VTID3_V ); REG64_FLD( C_THREAD_INFO_PTID0_V , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PTID0_V ); REG64_FLD( C_THREAD_INFO_PTID1_V , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PTID1_V ); REG64_FLD( C_THREAD_INFO_PTID2_V , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PTID2_V ); REG64_FLD( C_THREAD_INFO_PTID3_V , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PTID3_V ); REG64_FLD( C_THREAD_INFO_SMT_MODE , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SMT_MODE ); REG64_FLD( C_THREAD_INFO_SMT_MODE_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SMT_MODE_LEN ); REG64_FLD( C_THREAD_INFO_VTID0_TO_PTID_MAP , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_VTID0_TO_PTID_MAP ); REG64_FLD( C_THREAD_INFO_VTID0_TO_PTID_MAP_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_VTID0_TO_PTID_MAP_LEN ); REG64_FLD( C_THREAD_INFO_VTID1_TO_PTID_MAP , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_VTID1_TO_PTID_MAP ); REG64_FLD( C_THREAD_INFO_VTID1_TO_PTID_MAP_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_VTID1_TO_PTID_MAP_LEN ); REG64_FLD( C_THREAD_INFO_VTID2_TO_PTID_MAP , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_VTID2_TO_PTID_MAP ); REG64_FLD( C_THREAD_INFO_VTID2_TO_PTID_MAP_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_VTID2_TO_PTID_MAP_LEN ); REG64_FLD( C_THREAD_INFO_VTID3_TO_PTID_MAP , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_VTID3_TO_PTID_MAP ); REG64_FLD( C_THREAD_INFO_VTID3_TO_PTID_MAP_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_VTID3_TO_PTID_MAP_LEN ); REG64_FLD( C_THREAD_INFO_RAM_THREAD_ACTIVE , 18 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RAM_THREAD_ACTIVE ); REG64_FLD( C_THREAD_INFO_RAM_THREAD_ACTIVE_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RAM_THREAD_ACTIVE_LEN ); REG64_FLD( C_THREAD_INFO_PSCOM_PURGE , 22 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PSCOM_PURGE ); REG64_FLD( EX_THROTTLE_CONTROL_SCOM_DIDT_THROTTLE , 0 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SCOM_DIDT_THROTTLE ); REG64_FLD( EX_THROTTLE_CONTROL_SCOM_DIDT_THROTTLE_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SCOM_DIDT_THROTTLE_LEN ); REG64_FLD( EX_THROTTLE_CONTROL_SCOM_DIDT_TRIGGER_ENABLE , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SCOM_DIDT_TRIGGER_ENABLE ); REG64_FLD( EX_THROTTLE_CONTROL_SCOM_CORE_SLOWDOWN , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SCOM_CORE_SLOWDOWN ); REG64_FLD( EX_THROTTLE_CONTROL_SCOM_FORCE_DYN_SUPPRESS , 4 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SCOM_FORCE_DYN_SUPPRESS ); REG64_FLD( EX_THROTTLE_CONTROL_SCOM_DYN_SUPPRESS_ON_THROTTLE , 5 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SCOM_DYN_SUPPRESS_ON_THROTTLE ); REG64_FLD( EX_THROTTLE_CONTROL_SCOM_DISABLE_DROOP , 6 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SCOM_DISABLE_DROOP ); REG64_FLD( EX_THROTTLE_CONTROL_SCOM_DISABLE_DROOP_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SCOM_DISABLE_DROOP_LEN ); REG64_FLD( EX_THROTTLE_CONTROL_SCOM_DROOP_MODE_DISABLE , 9 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SCOM_DROOP_MODE_DISABLE ); REG64_FLD( EX_THROTTLE_CONTROL_SCOM_DROOP_MODE_DISABLE_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM_RW , SH_FLD_SCOM_DROOP_MODE_DISABLE_LEN ); REG64_FLD( C_THROTTLE_CONTROL_SCOM_DIDT_THROTTLE , 0 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SCOM_DIDT_THROTTLE ); REG64_FLD( C_THROTTLE_CONTROL_SCOM_DIDT_THROTTLE_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SCOM_DIDT_THROTTLE_LEN ); REG64_FLD( C_THROTTLE_CONTROL_SCOM_DIDT_TRIGGER_ENABLE , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SCOM_DIDT_TRIGGER_ENABLE ); REG64_FLD( C_THROTTLE_CONTROL_SCOM_CORE_SLOWDOWN , 3 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SCOM_CORE_SLOWDOWN ); REG64_FLD( C_THROTTLE_CONTROL_SCOM_FORCE_DYN_SUPPRESS , 4 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SCOM_FORCE_DYN_SUPPRESS ); REG64_FLD( C_THROTTLE_CONTROL_SCOM_DYN_SUPPRESS_ON_THROTTLE , 5 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SCOM_DYN_SUPPRESS_ON_THROTTLE ); REG64_FLD( C_THROTTLE_CONTROL_SCOM_DISABLE_DROOP , 6 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SCOM_DISABLE_DROOP ); REG64_FLD( C_THROTTLE_CONTROL_SCOM_DISABLE_DROOP_LEN , 3 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SCOM_DISABLE_DROOP_LEN ); REG64_FLD( C_THROTTLE_CONTROL_SCOM_DROOP_MODE_DISABLE , 9 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SCOM_DROOP_MODE_DISABLE ); REG64_FLD( C_THROTTLE_CONTROL_SCOM_DROOP_MODE_DISABLE_LEN , 2 , SH_UNT_C , SH_ACS_SCOM_RW , SH_FLD_SCOM_DROOP_MODE_DISABLE_LEN ); REG64_FLD( EQ_TIMEOUT_REG_INT_TIMEOUT , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INT_TIMEOUT ); REG64_FLD( EQ_TIMEOUT_REG_INT_TIMEOUT_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_INT_TIMEOUT_LEN ); REG64_FLD( EX_TIMEOUT_REG_INT_TIMEOUT , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INT_TIMEOUT ); REG64_FLD( EX_TIMEOUT_REG_INT_TIMEOUT_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_INT_TIMEOUT_LEN ); REG64_FLD( C_TIMEOUT_REG_INT_TIMEOUT , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INT_TIMEOUT ); REG64_FLD( C_TIMEOUT_REG_INT_TIMEOUT_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_INT_TIMEOUT_LEN ); REG64_FLD( EQ_TIMESTAMP_COUNTER_READ_VALUE , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VALUE ); REG64_FLD( EQ_TIMESTAMP_COUNTER_READ_VALUE_LEN , 44 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_VALUE_LEN ); REG64_FLD( EQ_TIMESTAMP_COUNTER_READ_OVERFLOW_ERR , 44 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_OVERFLOW_ERR ); REG64_FLD( EX_TIMESTAMP_COUNTER_READ_VALUE , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VALUE ); REG64_FLD( EX_TIMESTAMP_COUNTER_READ_VALUE_LEN , 44 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_VALUE_LEN ); REG64_FLD( EX_TIMESTAMP_COUNTER_READ_OVERFLOW_ERR , 44 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_OVERFLOW_ERR ); REG64_FLD( C_TIMESTAMP_COUNTER_READ_VALUE , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VALUE ); REG64_FLD( C_TIMESTAMP_COUNTER_READ_VALUE_LEN , 44 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_VALUE_LEN ); REG64_FLD( C_TIMESTAMP_COUNTER_READ_OVERFLOW_ERR , 44 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_OVERFLOW_ERR ); REG64_FLD( EX_L2_TOD_READ_TIMEBASE , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_TIMEBASE ); REG64_FLD( EX_L2_TOD_READ_TIMEBASE_LEN , 60 , SH_UNT_EX_L2 , SH_ACS_SCOM_RO , SH_FLD_TIMEBASE_LEN ); REG64_FLD( C_TOD_READ_TIMEBASE , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_TIMEBASE ); REG64_FLD( C_TOD_READ_TIMEBASE_LEN , 60 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_TIMEBASE_LEN ); REG64_FLD( EX_L2_TOD_SYNC000_TIMEBASE , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE ); REG64_FLD( EX_L2_TOD_SYNC000_TIMEBASE_LEN , 55 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE_LEN ); REG64_FLD( EX_L2_TOD_SYNC000_CHIP_STATUS , 60 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS ); REG64_FLD( EX_L2_TOD_SYNC000_CHIP_STATUS_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS_LEN ); REG64_FLD( C_TOD_SYNC000_TIMEBASE , 0 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE ); REG64_FLD( C_TOD_SYNC000_TIMEBASE_LEN , 55 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE_LEN ); REG64_FLD( C_TOD_SYNC000_CHIP_STATUS , 60 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS ); REG64_FLD( C_TOD_SYNC000_CHIP_STATUS_LEN , 4 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS_LEN ); REG64_FLD( EX_L2_TOD_SYNC001_TIMEBASE , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE ); REG64_FLD( EX_L2_TOD_SYNC001_TIMEBASE_LEN , 54 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE_LEN ); REG64_FLD( EX_L2_TOD_SYNC001_CHIP_STATUS , 60 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS ); REG64_FLD( EX_L2_TOD_SYNC001_CHIP_STATUS_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS_LEN ); REG64_FLD( C_TOD_SYNC001_TIMEBASE , 0 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE ); REG64_FLD( C_TOD_SYNC001_TIMEBASE_LEN , 54 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE_LEN ); REG64_FLD( C_TOD_SYNC001_CHIP_STATUS , 60 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS ); REG64_FLD( C_TOD_SYNC001_CHIP_STATUS_LEN , 4 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS_LEN ); REG64_FLD( EX_L2_TOD_SYNC010_TIMEBASE , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE ); REG64_FLD( EX_L2_TOD_SYNC010_TIMEBASE_LEN , 53 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE_LEN ); REG64_FLD( EX_L2_TOD_SYNC010_CHIP_STATUS , 60 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS ); REG64_FLD( EX_L2_TOD_SYNC010_CHIP_STATUS_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS_LEN ); REG64_FLD( C_TOD_SYNC010_TIMEBASE , 0 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE ); REG64_FLD( C_TOD_SYNC010_TIMEBASE_LEN , 53 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE_LEN ); REG64_FLD( C_TOD_SYNC010_CHIP_STATUS , 60 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS ); REG64_FLD( C_TOD_SYNC010_CHIP_STATUS_LEN , 4 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS_LEN ); REG64_FLD( EX_L2_TOD_SYNC011_TIMEBASE , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE ); REG64_FLD( EX_L2_TOD_SYNC011_TIMEBASE_LEN , 52 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE_LEN ); REG64_FLD( EX_L2_TOD_SYNC011_CHIP_STATUS , 60 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS ); REG64_FLD( EX_L2_TOD_SYNC011_CHIP_STATUS_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS_LEN ); REG64_FLD( C_TOD_SYNC011_TIMEBASE , 0 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE ); REG64_FLD( C_TOD_SYNC011_TIMEBASE_LEN , 52 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE_LEN ); REG64_FLD( C_TOD_SYNC011_CHIP_STATUS , 60 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS ); REG64_FLD( C_TOD_SYNC011_CHIP_STATUS_LEN , 4 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS_LEN ); REG64_FLD( EX_L2_TOD_SYNC100_TIMEBASE , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE ); REG64_FLD( EX_L2_TOD_SYNC100_TIMEBASE_LEN , 51 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE_LEN ); REG64_FLD( EX_L2_TOD_SYNC100_CHIP_STATUS , 60 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS ); REG64_FLD( EX_L2_TOD_SYNC100_CHIP_STATUS_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS_LEN ); REG64_FLD( C_TOD_SYNC100_TIMEBASE , 0 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE ); REG64_FLD( C_TOD_SYNC100_TIMEBASE_LEN , 51 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE_LEN ); REG64_FLD( C_TOD_SYNC100_CHIP_STATUS , 60 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS ); REG64_FLD( C_TOD_SYNC100_CHIP_STATUS_LEN , 4 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS_LEN ); REG64_FLD( EX_L2_TOD_SYNC101_TIMEBASE , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE ); REG64_FLD( EX_L2_TOD_SYNC101_TIMEBASE_LEN , 50 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE_LEN ); REG64_FLD( EX_L2_TOD_SYNC101_CHIP_STATUS , 60 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS ); REG64_FLD( EX_L2_TOD_SYNC101_CHIP_STATUS_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS_LEN ); REG64_FLD( C_TOD_SYNC101_TIMEBASE , 0 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE ); REG64_FLD( C_TOD_SYNC101_TIMEBASE_LEN , 50 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE_LEN ); REG64_FLD( C_TOD_SYNC101_CHIP_STATUS , 60 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS ); REG64_FLD( C_TOD_SYNC101_CHIP_STATUS_LEN , 4 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS_LEN ); REG64_FLD( EX_L2_TOD_SYNC110_TIMEBASE , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE ); REG64_FLD( EX_L2_TOD_SYNC110_TIMEBASE_LEN , 49 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE_LEN ); REG64_FLD( EX_L2_TOD_SYNC110_CHIP_STATUS , 60 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS ); REG64_FLD( EX_L2_TOD_SYNC110_CHIP_STATUS_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS_LEN ); REG64_FLD( C_TOD_SYNC110_TIMEBASE , 0 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE ); REG64_FLD( C_TOD_SYNC110_TIMEBASE_LEN , 49 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE_LEN ); REG64_FLD( C_TOD_SYNC110_CHIP_STATUS , 60 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS ); REG64_FLD( C_TOD_SYNC110_CHIP_STATUS_LEN , 4 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS_LEN ); REG64_FLD( EX_L2_TOD_SYNC111_TIMEBASE , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE ); REG64_FLD( EX_L2_TOD_SYNC111_TIMEBASE_LEN , 48 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE_LEN ); REG64_FLD( EX_L2_TOD_SYNC111_CHIP_STATUS , 60 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS ); REG64_FLD( EX_L2_TOD_SYNC111_CHIP_STATUS_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS_LEN ); REG64_FLD( C_TOD_SYNC111_TIMEBASE , 0 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE ); REG64_FLD( C_TOD_SYNC111_TIMEBASE_LEN , 48 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_TIMEBASE_LEN ); REG64_FLD( C_TOD_SYNC111_CHIP_STATUS , 60 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS ); REG64_FLD( C_TOD_SYNC111_CHIP_STATUS_LEN , 4 , SH_UNT_C , SH_ACS_SCOM1_WO , SH_FLD_CHIP_STATUS_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EQ_TPLC20_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EX_TPLC20_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( EQ_TPLC20_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( EX_TPLC20_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WRITE_ON_RUN_MODE ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXTEND_TRIG_MODE ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXTEND_TRIG_MODE_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_BANK_MODE ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENH_MODE ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SELCT_CONTROL ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SELCT_CONTROL_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_CONTROL ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WRITE_ON_RUN_MODE ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EXTEND_TRIG_MODE ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EXTEND_TRIG_MODE_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_BANK_MODE ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ENH_MODE ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SELCT_CONTROL ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SELCT_CONTROL_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SPARE_CONTROL ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT_LEN ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); REG64_FLD( EQ_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_LT ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT_LEN ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); REG64_FLD( EX_TPLC20_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SPARE_LT ); REG64_FLD( EQ_TPLC20_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EQ_TPLC20_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EX_TPLC20_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( EQ_TPLC20_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( EX_TPLC20_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WRITE_ON_RUN_MODE ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXTEND_TRIG_MODE ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXTEND_TRIG_MODE_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_BANK_MODE ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENH_MODE ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SELCT_CONTROL ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SELCT_CONTROL_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_CONTROL ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WRITE_ON_RUN_MODE ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EXTEND_TRIG_MODE ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EXTEND_TRIG_MODE_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_BANK_MODE ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ENH_MODE ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SELCT_CONTROL ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SELCT_CONTROL_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SPARE_CONTROL ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT_LEN ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); REG64_FLD( EQ_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_LT ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT_LEN ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); REG64_FLD( EX_TPLC20_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SPARE_LT ); REG64_FLD( EQ_TPLC21_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EQ_TPLC21_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( EQ_TPLC21_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WRITE_ON_RUN_MODE ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXTEND_TRIG_MODE ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXTEND_TRIG_MODE_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_BANK_MODE ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENH_MODE ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SELCT_CONTROL ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SELCT_CONTROL_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_CONTROL ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT_LEN ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); REG64_FLD( EQ_TPLC21_TR0_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_LT ); REG64_FLD( EQ_TPLC21_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EQ_TPLC21_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( EQ_TPLC21_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_EQ , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WRITE_ON_RUN_MODE ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXTEND_TRIG_MODE ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_EXTEND_TRIG_MODE_LEN , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_EXTEND_TRIG_MODE_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_BANK_MODE ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ENH_MODE ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_LOCAL_CLOCK_GATE_CONTROL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_LOCAL_CLOCK_GATE_CONTROL_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SELCT_CONTROL ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_SELCT_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SELCT_CONTROL_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_CONTROL ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRCTRL_CONFIG_SPARE_CONTROL_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_CONTROL_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT_LEN ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_DD1_STRETCH_TRIGGER_PULSES , 36 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DD1_STRETCH_TRIGGER_PULSES ); REG64_FLD( EQ_TPLC21_TR1_TRACE_TRDATA_CONFIG_9_SPARE_LT , 37 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_SPARE_LT ); REG64_FLD( EX_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EX_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( C_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( C_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EX_L3_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EX_L3_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EX_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EX_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EX_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( EX_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( EX_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( EX_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( EX_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( EX_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( EX_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( EX_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( EX_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_EX , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( C_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( C_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( C_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( C_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( C_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( C_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( C_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( C_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( C_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( C_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( C_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_C , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( EX_L3_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( EX_L3_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( EX_L3_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( EX_L3_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( EX_L3_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( EX_L3_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( EX_L3_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( EX_L3_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( EX_L3_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( EX_L3_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( EX_L3_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_EX_L3 , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( EX_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WRITE_ON_RUN_MODE ); REG64_FLD( EX_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EXTENDED_STORE_ON_TRIG_MODE ); REG64_FLD( EX_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_EXTENDED_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( EX_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_BANK_MODE ); REG64_FLD( EX_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ENH_MODE ); REG64_FLD( EX_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_LCL_CLK_GATE_CTRL ); REG64_FLD( EX_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_LCL_CLK_GATE_CTRL_LEN ); REG64_FLD( EX_TRACE_TRCTRL_CONFIG_TRCTRL_CONFIG_D , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRCTRL_CONFIG_D ); REG64_FLD( EX_TRACE_TRCTRL_CONFIG_TRCTRL_CONFIG_D_LEN , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRCTRL_CONFIG_D_LEN ); REG64_FLD( C_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WRITE_ON_RUN_MODE ); REG64_FLD( C_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_EXTENDED_STORE_ON_TRIG_MODE ); REG64_FLD( C_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_EXTENDED_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( C_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_BANK_MODE ); REG64_FLD( C_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ENH_MODE ); REG64_FLD( C_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LCL_CLK_GATE_CTRL ); REG64_FLD( C_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_LCL_CLK_GATE_CTRL_LEN ); REG64_FLD( C_TRACE_TRCTRL_CONFIG_TRCTRL_CONFIG_D , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRCTRL_CONFIG_D ); REG64_FLD( C_TRACE_TRCTRL_CONFIG_TRCTRL_CONFIG_D_LEN , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRCTRL_CONFIG_D_LEN ); REG64_FLD( EX_L3_TRACE_TRCTRL_CONFIG_WRITE_ON_RUN_MODE , 1 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_WRITE_ON_RUN_MODE ); REG64_FLD( EX_L3_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_EXTENDED_STORE_ON_TRIG_MODE ); REG64_FLD( EX_L3_TRACE_TRCTRL_CONFIG_EXTENDED_STORE_ON_TRIG_MODE_LEN , 8 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_EXTENDED_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( EX_L3_TRACE_TRCTRL_CONFIG_BANK_MODE , 10 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_BANK_MODE ); REG64_FLD( EX_L3_TRACE_TRCTRL_CONFIG_ENH_MODE , 11 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_ENH_MODE ); REG64_FLD( EX_L3_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL , 12 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_LCL_CLK_GATE_CTRL ); REG64_FLD( EX_L3_TRACE_TRCTRL_CONFIG_LCL_CLK_GATE_CTRL_LEN , 2 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_LCL_CLK_GATE_CTRL_LEN ); REG64_FLD( EX_L3_TRACE_TRCTRL_CONFIG_TRCTRL_CONFIG_D , 14 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_TRCTRL_CONFIG_D ); REG64_FLD( EX_L3_TRACE_TRCTRL_CONFIG_TRCTRL_CONFIG_D_LEN , 8 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_TRCTRL_CONFIG_D_LEN ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( C_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( C_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( C_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( C_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( C_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( C_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( C_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( C_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( C_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( C_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( C_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( C_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( C_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( C_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( C_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( C_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( EX_L3_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_EX_L3 , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( C_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( C_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( C_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( C_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT_LEN ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_SPARE_LT , 36 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SPARE_LT ); REG64_FLD( EX_TRACE_TRDATA_CONFIG_9_SPARE_LT_LEN , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_SPARE_LT_LEN ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT , 32 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_ERROR_MODE_LT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_ERROR_MODE_LT_LEN ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_SPARE_LT , 36 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SPARE_LT ); REG64_FLD( C_TRACE_TRDATA_CONFIG_9_SPARE_LT_LEN , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_SPARE_LT_LEN ); REG64_FLD( EX_V0_HMER_MALFUNCTION_ALERT , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_MALFUNCTION_ALERT ); REG64_FLD( EX_V0_HMER_CME_REQUEST , 1 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CME_REQUEST ); REG64_FLD( EX_V0_HMER_PROC_RCVY_DONE , 2 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_DONE ); REG64_FLD( EX_V0_HMER_SPARE_3 , 3 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_3 ); REG64_FLD( EX_V0_HMER_TFAC_ERR , 4 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_TFAC_ERR ); REG64_FLD( EX_V0_HMER_TFMR_PARITY_ERR , 5 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_TFMR_PARITY_ERR ); REG64_FLD( EX_V0_HMER_SPARE_6 , 6 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_6 ); REG64_FLD( EX_V0_HMER_SPARE_7 , 7 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_7 ); REG64_FLD( EX_V0_HMER_XSCOM_FAIL , 8 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_FAIL ); REG64_FLD( EX_V0_HMER_XSCOM_DONE , 9 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_DONE ); REG64_FLD( EX_V0_HMER_SPARE_10 , 10 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_10 ); REG64_FLD( EX_V0_HMER_PROC_RCVY_AGAIN , 11 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_AGAIN ); REG64_FLD( EX_V0_HMER_SPARE_12 , 12 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_12 ); REG64_FLD( EX_V0_HMER_SPARE_13 , 13 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_13 ); REG64_FLD( EX_V0_HMER_SPARE_14 , 14 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_14 ); REG64_FLD( EX_V0_HMER_SPARE_15 , 15 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_15 ); REG64_FLD( EX_V0_HMER_SCOM_FIR_HMI , 16 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SCOM_FIR_HMI ); REG64_FLD( EX_V0_HMER_TRIG_FIR_HMI , 17 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_TRIG_FIR_HMI ); REG64_FLD( EX_V0_HMER_SPARE_18 , 18 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_18 ); REG64_FLD( EX_V0_HMER_SPARE_19 , 19 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_19 ); REG64_FLD( EX_V0_HMER_HYP_RECOURCE_ERR , 20 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_HYP_RECOURCE_ERR ); REG64_FLD( EX_V0_HMER_XSCOM_STATUS , 21 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_STATUS ); REG64_FLD( EX_V0_HMER_XSCOM_STATUS_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_STATUS_LEN ); REG64_FLD( EX_L2_V0_HMER_MALFUNCTION_ALERT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_MALFUNCTION_ALERT ); REG64_FLD( EX_L2_V0_HMER_CME_REQUEST , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_CME_REQUEST ); REG64_FLD( EX_L2_V0_HMER_PROC_RCVY_DONE , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_PROC_RCVY_DONE ); REG64_FLD( EX_L2_V0_HMER_SPARE_3 , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SPARE_3 ); REG64_FLD( EX_L2_V0_HMER_TFAC_ERR , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_TFAC_ERR ); REG64_FLD( EX_L2_V0_HMER_TFMR_PARITY_ERR , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_TFMR_PARITY_ERR ); REG64_FLD( EX_L2_V0_HMER_SPARE_6 , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SPARE_6 ); REG64_FLD( EX_L2_V0_HMER_SPARE_7 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SPARE_7 ); REG64_FLD( EX_L2_V0_HMER_XSCOM_FAIL , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_XSCOM_FAIL ); REG64_FLD( EX_L2_V0_HMER_XSCOM_DONE , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_XSCOM_DONE ); REG64_FLD( EX_L2_V0_HMER_SPARE_10 , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SPARE_10 ); REG64_FLD( EX_L2_V0_HMER_PROC_RCVY_AGAIN , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_PROC_RCVY_AGAIN ); REG64_FLD( EX_L2_V0_HMER_SPARE_12 , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SPARE_12 ); REG64_FLD( EX_L2_V0_HMER_SPARE_13 , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SPARE_13 ); REG64_FLD( EX_L2_V0_HMER_SPARE_14 , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SPARE_14 ); REG64_FLD( EX_L2_V0_HMER_SPARE_15 , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SPARE_15 ); REG64_FLD( EX_L2_V0_HMER_SCOM_FIR_HMI , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SCOM_FIR_HMI ); REG64_FLD( EX_L2_V0_HMER_TRIG_FIR_HMI , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_TRIG_FIR_HMI ); REG64_FLD( EX_L2_V0_HMER_SPARE_18 , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SPARE_18 ); REG64_FLD( EX_L2_V0_HMER_SPARE_19 , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SPARE_19 ); REG64_FLD( EX_L2_V0_HMER_HYP_RECOURCE_ERR , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_HYP_RECOURCE_ERR ); REG64_FLD( EX_L2_V0_HMER_XSCOM_STATUS , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_XSCOM_STATUS ); REG64_FLD( EX_L2_V0_HMER_XSCOM_STATUS_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_XSCOM_STATUS_LEN ); REG64_FLD( C_V0_HMER_MALFUNCTION_ALERT , 0 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MALFUNCTION_ALERT ); REG64_FLD( C_V0_HMER_CME_REQUEST , 1 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CME_REQUEST ); REG64_FLD( C_V0_HMER_PROC_RCVY_DONE , 2 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_DONE ); REG64_FLD( C_V0_HMER_SPARE_3 , 3 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_3 ); REG64_FLD( C_V0_HMER_TFAC_ERR , 4 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TFAC_ERR ); REG64_FLD( C_V0_HMER_TFMR_PARITY_ERR , 5 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TFMR_PARITY_ERR ); REG64_FLD( C_V0_HMER_SPARE_6 , 6 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_6 ); REG64_FLD( C_V0_HMER_SPARE_7 , 7 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_7 ); REG64_FLD( C_V0_HMER_XSCOM_FAIL , 8 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_FAIL ); REG64_FLD( C_V0_HMER_XSCOM_DONE , 9 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_DONE ); REG64_FLD( C_V0_HMER_SPARE_10 , 10 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_10 ); REG64_FLD( C_V0_HMER_PROC_RCVY_AGAIN , 11 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_AGAIN ); REG64_FLD( C_V0_HMER_SPARE_12 , 12 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_12 ); REG64_FLD( C_V0_HMER_SPARE_13 , 13 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_13 ); REG64_FLD( C_V0_HMER_SPARE_14 , 14 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_14 ); REG64_FLD( C_V0_HMER_SPARE_15 , 15 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_15 ); REG64_FLD( C_V0_HMER_SCOM_FIR_HMI , 16 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SCOM_FIR_HMI ); REG64_FLD( C_V0_HMER_TRIG_FIR_HMI , 17 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TRIG_FIR_HMI ); REG64_FLD( C_V0_HMER_SPARE_18 , 18 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_18 ); REG64_FLD( C_V0_HMER_SPARE_19 , 19 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_19 ); REG64_FLD( C_V0_HMER_HYP_RECOURCE_ERR , 20 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_HYP_RECOURCE_ERR ); REG64_FLD( C_V0_HMER_XSCOM_STATUS , 21 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_STATUS ); REG64_FLD( C_V0_HMER_XSCOM_STATUS_LEN , 3 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_STATUS_LEN ); REG64_FLD( EX_V1_HMER_MALFUNCTION_ALERT , 0 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_MALFUNCTION_ALERT ); REG64_FLD( EX_V1_HMER_CME_REQUEST , 1 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_CME_REQUEST ); REG64_FLD( EX_V1_HMER_PROC_RCVY_DONE , 2 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_DONE ); REG64_FLD( EX_V1_HMER_SPARE_3 , 3 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_3 ); REG64_FLD( EX_V1_HMER_TFAC_ERR , 4 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_TFAC_ERR ); REG64_FLD( EX_V1_HMER_TFMR_PARITY_ERR , 5 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_TFMR_PARITY_ERR ); REG64_FLD( EX_V1_HMER_SPARE_6 , 6 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_6 ); REG64_FLD( EX_V1_HMER_SPARE_7 , 7 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_7 ); REG64_FLD( EX_V1_HMER_XSCOM_FAIL , 8 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_FAIL ); REG64_FLD( EX_V1_HMER_XSCOM_DONE , 9 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_DONE ); REG64_FLD( EX_V1_HMER_SPARE_10 , 10 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_10 ); REG64_FLD( EX_V1_HMER_PROC_RCVY_AGAIN , 11 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_AGAIN ); REG64_FLD( EX_V1_HMER_SPARE_12 , 12 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_12 ); REG64_FLD( EX_V1_HMER_SPARE_13 , 13 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_13 ); REG64_FLD( EX_V1_HMER_SPARE_14 , 14 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_14 ); REG64_FLD( EX_V1_HMER_SPARE_15 , 15 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_15 ); REG64_FLD( EX_V1_HMER_SCOM_FIR_HMI , 16 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SCOM_FIR_HMI ); REG64_FLD( EX_V1_HMER_TRIG_FIR_HMI , 17 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_TRIG_FIR_HMI ); REG64_FLD( EX_V1_HMER_SPARE_18 , 18 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_18 ); REG64_FLD( EX_V1_HMER_SPARE_19 , 19 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_SPARE_19 ); REG64_FLD( EX_V1_HMER_HYP_RECOURCE_ERR , 20 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_HYP_RECOURCE_ERR ); REG64_FLD( EX_V1_HMER_XSCOM_STATUS , 21 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_STATUS ); REG64_FLD( EX_V1_HMER_XSCOM_STATUS_LEN , 3 , SH_UNT_EX , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_STATUS_LEN ); REG64_FLD( EX_L2_V1_HMER_MALFUNCTION_ALERT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_MALFUNCTION_ALERT ); REG64_FLD( EX_L2_V1_HMER_CME_REQUEST , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_CME_REQUEST ); REG64_FLD( EX_L2_V1_HMER_PROC_RCVY_DONE , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_PROC_RCVY_DONE ); REG64_FLD( EX_L2_V1_HMER_SPARE_3 , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SPARE_3 ); REG64_FLD( EX_L2_V1_HMER_TFAC_ERR , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_TFAC_ERR ); REG64_FLD( EX_L2_V1_HMER_TFMR_PARITY_ERR , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_TFMR_PARITY_ERR ); REG64_FLD( EX_L2_V1_HMER_SPARE_6 , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SPARE_6 ); REG64_FLD( EX_L2_V1_HMER_SPARE_7 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SPARE_7 ); REG64_FLD( EX_L2_V1_HMER_XSCOM_FAIL , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_XSCOM_FAIL ); REG64_FLD( EX_L2_V1_HMER_XSCOM_DONE , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_XSCOM_DONE ); REG64_FLD( EX_L2_V1_HMER_SPARE_10 , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SPARE_10 ); REG64_FLD( EX_L2_V1_HMER_PROC_RCVY_AGAIN , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_PROC_RCVY_AGAIN ); REG64_FLD( EX_L2_V1_HMER_SPARE_12 , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SPARE_12 ); REG64_FLD( EX_L2_V1_HMER_SPARE_13 , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SPARE_13 ); REG64_FLD( EX_L2_V1_HMER_SPARE_14 , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SPARE_14 ); REG64_FLD( EX_L2_V1_HMER_SPARE_15 , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SPARE_15 ); REG64_FLD( EX_L2_V1_HMER_SCOM_FIR_HMI , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SCOM_FIR_HMI ); REG64_FLD( EX_L2_V1_HMER_TRIG_FIR_HMI , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_TRIG_FIR_HMI ); REG64_FLD( EX_L2_V1_HMER_SPARE_18 , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SPARE_18 ); REG64_FLD( EX_L2_V1_HMER_SPARE_19 , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_SPARE_19 ); REG64_FLD( EX_L2_V1_HMER_HYP_RECOURCE_ERR , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_HYP_RECOURCE_ERR ); REG64_FLD( EX_L2_V1_HMER_XSCOM_STATUS , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_XSCOM_STATUS ); REG64_FLD( EX_L2_V1_HMER_XSCOM_STATUS_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM1_WAND, SH_FLD_XSCOM_STATUS_LEN ); REG64_FLD( C_V1_HMER_MALFUNCTION_ALERT , 0 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MALFUNCTION_ALERT ); REG64_FLD( C_V1_HMER_CME_REQUEST , 1 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CME_REQUEST ); REG64_FLD( C_V1_HMER_PROC_RCVY_DONE , 2 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_DONE ); REG64_FLD( C_V1_HMER_SPARE_3 , 3 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_3 ); REG64_FLD( C_V1_HMER_TFAC_ERR , 4 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TFAC_ERR ); REG64_FLD( C_V1_HMER_TFMR_PARITY_ERR , 5 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TFMR_PARITY_ERR ); REG64_FLD( C_V1_HMER_SPARE_6 , 6 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_6 ); REG64_FLD( C_V1_HMER_SPARE_7 , 7 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_7 ); REG64_FLD( C_V1_HMER_XSCOM_FAIL , 8 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_FAIL ); REG64_FLD( C_V1_HMER_XSCOM_DONE , 9 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_DONE ); REG64_FLD( C_V1_HMER_SPARE_10 , 10 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_10 ); REG64_FLD( C_V1_HMER_PROC_RCVY_AGAIN , 11 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_AGAIN ); REG64_FLD( C_V1_HMER_SPARE_12 , 12 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_12 ); REG64_FLD( C_V1_HMER_SPARE_13 , 13 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_13 ); REG64_FLD( C_V1_HMER_SPARE_14 , 14 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_14 ); REG64_FLD( C_V1_HMER_SPARE_15 , 15 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_15 ); REG64_FLD( C_V1_HMER_SCOM_FIR_HMI , 16 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SCOM_FIR_HMI ); REG64_FLD( C_V1_HMER_TRIG_FIR_HMI , 17 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TRIG_FIR_HMI ); REG64_FLD( C_V1_HMER_SPARE_18 , 18 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_18 ); REG64_FLD( C_V1_HMER_SPARE_19 , 19 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_19 ); REG64_FLD( C_V1_HMER_HYP_RECOURCE_ERR , 20 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_HYP_RECOURCE_ERR ); REG64_FLD( C_V1_HMER_XSCOM_STATUS , 21 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_STATUS ); REG64_FLD( C_V1_HMER_XSCOM_STATUS_LEN , 3 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_STATUS_LEN ); REG64_FLD( EX_L2_V2_HMER_MALFUNCTION_ALERT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MALFUNCTION_ALERT ); REG64_FLD( EX_L2_V2_HMER_CME_REQUEST , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_CME_REQUEST ); REG64_FLD( EX_L2_V2_HMER_PROC_RCVY_DONE , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_DONE ); REG64_FLD( EX_L2_V2_HMER_SPARE_3 , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE_3 ); REG64_FLD( EX_L2_V2_HMER_TFAC_ERR , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_TFAC_ERR ); REG64_FLD( EX_L2_V2_HMER_TFMR_PARITY_ERR , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_TFMR_PARITY_ERR ); REG64_FLD( EX_L2_V2_HMER_SPARE_6 , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE_6 ); REG64_FLD( EX_L2_V2_HMER_SPARE_7 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE_7 ); REG64_FLD( EX_L2_V2_HMER_XSCOM_FAIL , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_FAIL ); REG64_FLD( EX_L2_V2_HMER_XSCOM_DONE , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_DONE ); REG64_FLD( EX_L2_V2_HMER_SPARE_10 , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE_10 ); REG64_FLD( EX_L2_V2_HMER_PROC_RCVY_AGAIN , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_AGAIN ); REG64_FLD( EX_L2_V2_HMER_SPARE_12 , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE_12 ); REG64_FLD( EX_L2_V2_HMER_SPARE_13 , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE_13 ); REG64_FLD( EX_L2_V2_HMER_SPARE_14 , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE_14 ); REG64_FLD( EX_L2_V2_HMER_SPARE_15 , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE_15 ); REG64_FLD( EX_L2_V2_HMER_SCOM_FIR_HMI , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SCOM_FIR_HMI ); REG64_FLD( EX_L2_V2_HMER_TRIG_FIR_HMI , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_TRIG_FIR_HMI ); REG64_FLD( EX_L2_V2_HMER_SPARE_18 , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE_18 ); REG64_FLD( EX_L2_V2_HMER_SPARE_19 , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE_19 ); REG64_FLD( EX_L2_V2_HMER_HYP_RECOURCE_ERR , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_HYP_RECOURCE_ERR ); REG64_FLD( EX_L2_V2_HMER_XSCOM_STATUS , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_STATUS ); REG64_FLD( EX_L2_V2_HMER_XSCOM_STATUS_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_STATUS_LEN ); REG64_FLD( C_V2_HMER_MALFUNCTION_ALERT , 0 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MALFUNCTION_ALERT ); REG64_FLD( C_V2_HMER_CME_REQUEST , 1 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CME_REQUEST ); REG64_FLD( C_V2_HMER_PROC_RCVY_DONE , 2 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_DONE ); REG64_FLD( C_V2_HMER_SPARE_3 , 3 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_3 ); REG64_FLD( C_V2_HMER_TFAC_ERR , 4 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TFAC_ERR ); REG64_FLD( C_V2_HMER_TFMR_PARITY_ERR , 5 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TFMR_PARITY_ERR ); REG64_FLD( C_V2_HMER_SPARE_6 , 6 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_6 ); REG64_FLD( C_V2_HMER_SPARE_7 , 7 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_7 ); REG64_FLD( C_V2_HMER_XSCOM_FAIL , 8 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_FAIL ); REG64_FLD( C_V2_HMER_XSCOM_DONE , 9 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_DONE ); REG64_FLD( C_V2_HMER_SPARE_10 , 10 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_10 ); REG64_FLD( C_V2_HMER_PROC_RCVY_AGAIN , 11 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_AGAIN ); REG64_FLD( C_V2_HMER_SPARE_12 , 12 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_12 ); REG64_FLD( C_V2_HMER_SPARE_13 , 13 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_13 ); REG64_FLD( C_V2_HMER_SPARE_14 , 14 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_14 ); REG64_FLD( C_V2_HMER_SPARE_15 , 15 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_15 ); REG64_FLD( C_V2_HMER_SCOM_FIR_HMI , 16 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SCOM_FIR_HMI ); REG64_FLD( C_V2_HMER_TRIG_FIR_HMI , 17 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TRIG_FIR_HMI ); REG64_FLD( C_V2_HMER_SPARE_18 , 18 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_18 ); REG64_FLD( C_V2_HMER_SPARE_19 , 19 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_19 ); REG64_FLD( C_V2_HMER_HYP_RECOURCE_ERR , 20 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_HYP_RECOURCE_ERR ); REG64_FLD( C_V2_HMER_XSCOM_STATUS , 21 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_STATUS ); REG64_FLD( C_V2_HMER_XSCOM_STATUS_LEN , 3 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_STATUS_LEN ); REG64_FLD( EX_L2_V3_HMER_MALFUNCTION_ALERT , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_MALFUNCTION_ALERT ); REG64_FLD( EX_L2_V3_HMER_CME_REQUEST , 1 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_CME_REQUEST ); REG64_FLD( EX_L2_V3_HMER_PROC_RCVY_DONE , 2 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_DONE ); REG64_FLD( EX_L2_V3_HMER_SPARE_3 , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE_3 ); REG64_FLD( EX_L2_V3_HMER_TFAC_ERR , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_TFAC_ERR ); REG64_FLD( EX_L2_V3_HMER_TFMR_PARITY_ERR , 5 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_TFMR_PARITY_ERR ); REG64_FLD( EX_L2_V3_HMER_SPARE_6 , 6 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE_6 ); REG64_FLD( EX_L2_V3_HMER_SPARE_7 , 7 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE_7 ); REG64_FLD( EX_L2_V3_HMER_XSCOM_FAIL , 8 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_FAIL ); REG64_FLD( EX_L2_V3_HMER_XSCOM_DONE , 9 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_DONE ); REG64_FLD( EX_L2_V3_HMER_SPARE_10 , 10 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE_10 ); REG64_FLD( EX_L2_V3_HMER_PROC_RCVY_AGAIN , 11 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_AGAIN ); REG64_FLD( EX_L2_V3_HMER_SPARE_12 , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE_12 ); REG64_FLD( EX_L2_V3_HMER_SPARE_13 , 13 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE_13 ); REG64_FLD( EX_L2_V3_HMER_SPARE_14 , 14 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE_14 ); REG64_FLD( EX_L2_V3_HMER_SPARE_15 , 15 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE_15 ); REG64_FLD( EX_L2_V3_HMER_SCOM_FIR_HMI , 16 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SCOM_FIR_HMI ); REG64_FLD( EX_L2_V3_HMER_TRIG_FIR_HMI , 17 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_TRIG_FIR_HMI ); REG64_FLD( EX_L2_V3_HMER_SPARE_18 , 18 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE_18 ); REG64_FLD( EX_L2_V3_HMER_SPARE_19 , 19 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_SPARE_19 ); REG64_FLD( EX_L2_V3_HMER_HYP_RECOURCE_ERR , 20 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_HYP_RECOURCE_ERR ); REG64_FLD( EX_L2_V3_HMER_XSCOM_STATUS , 21 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_STATUS ); REG64_FLD( EX_L2_V3_HMER_XSCOM_STATUS_LEN , 3 , SH_UNT_EX_L2 , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_STATUS_LEN ); REG64_FLD( C_V3_HMER_MALFUNCTION_ALERT , 0 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_MALFUNCTION_ALERT ); REG64_FLD( C_V3_HMER_CME_REQUEST , 1 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_CME_REQUEST ); REG64_FLD( C_V3_HMER_PROC_RCVY_DONE , 2 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_DONE ); REG64_FLD( C_V3_HMER_SPARE_3 , 3 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_3 ); REG64_FLD( C_V3_HMER_TFAC_ERR , 4 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TFAC_ERR ); REG64_FLD( C_V3_HMER_TFMR_PARITY_ERR , 5 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TFMR_PARITY_ERR ); REG64_FLD( C_V3_HMER_SPARE_6 , 6 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_6 ); REG64_FLD( C_V3_HMER_SPARE_7 , 7 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_7 ); REG64_FLD( C_V3_HMER_XSCOM_FAIL , 8 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_FAIL ); REG64_FLD( C_V3_HMER_XSCOM_DONE , 9 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_DONE ); REG64_FLD( C_V3_HMER_SPARE_10 , 10 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_10 ); REG64_FLD( C_V3_HMER_PROC_RCVY_AGAIN , 11 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_PROC_RCVY_AGAIN ); REG64_FLD( C_V3_HMER_SPARE_12 , 12 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_12 ); REG64_FLD( C_V3_HMER_SPARE_13 , 13 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_13 ); REG64_FLD( C_V3_HMER_SPARE_14 , 14 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_14 ); REG64_FLD( C_V3_HMER_SPARE_15 , 15 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_15 ); REG64_FLD( C_V3_HMER_SCOM_FIR_HMI , 16 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SCOM_FIR_HMI ); REG64_FLD( C_V3_HMER_TRIG_FIR_HMI , 17 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_TRIG_FIR_HMI ); REG64_FLD( C_V3_HMER_SPARE_18 , 18 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_18 ); REG64_FLD( C_V3_HMER_SPARE_19 , 19 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_SPARE_19 ); REG64_FLD( C_V3_HMER_HYP_RECOURCE_ERR , 20 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_HYP_RECOURCE_ERR ); REG64_FLD( C_V3_HMER_XSCOM_STATUS , 21 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_STATUS ); REG64_FLD( C_V3_HMER_XSCOM_STATUS_LEN , 3 , SH_UNT_C , SH_ACS_SCOM2_OR , SH_FLD_XSCOM_STATUS_LEN ); REG64_FLD( EQ_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RING_LOCKING ); REG64_FLD( EQ_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RESERVED_RING_LOCKING ); REG64_FLD( EX_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RING_LOCKING ); REG64_FLD( EX_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RESERVED_RING_LOCKING ); REG64_FLD( C_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RING_LOCKING ); REG64_FLD( C_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RESERVED_RING_LOCKING ); REG64_FLD( EQ_WRITE_PROTECT_RINGS_REG_RINGS , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RINGS ); REG64_FLD( EQ_WRITE_PROTECT_RINGS_REG_RINGS_LEN , 16 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_RINGS_LEN ); REG64_FLD( EX_WRITE_PROTECT_RINGS_REG_RINGS , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RINGS ); REG64_FLD( EX_WRITE_PROTECT_RINGS_REG_RINGS_LEN , 16 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_RINGS_LEN ); REG64_FLD( C_WRITE_PROTECT_RINGS_REG_RINGS , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RINGS ); REG64_FLD( C_WRITE_PROTECT_RINGS_REG_RINGS_LEN , 16 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_RINGS_LEN ); REG64_FLD( EQ_WR_EPS_REG_TIER1_VALUE , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TIER1_VALUE ); REG64_FLD( EQ_WR_EPS_REG_TIER1_VALUE_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TIER1_VALUE_LEN ); REG64_FLD( EQ_WR_EPS_REG_TIER2_VALUE , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TIER2_VALUE ); REG64_FLD( EQ_WR_EPS_REG_TIER2_VALUE_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TIER2_VALUE_LEN ); REG64_FLD( EQ_WR_EPS_REG_DIVIDER_MODE , 24 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DIVIDER_MODE ); REG64_FLD( EQ_WR_EPS_REG_DIVIDER_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DIVIDER_MODE_LEN ); REG64_FLD( EQ_WR_EPS_REG_MODE_SEL , 28 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MODE_SEL ); REG64_FLD( EQ_WR_EPS_REG_CNT_USE_L2_DIVIDER_EN , 29 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_CNT_USE_L2_DIVIDER_EN ); REG64_FLD( EQ_WR_EPS_REG_L2_STEP_MODE , 30 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L2_STEP_MODE ); REG64_FLD( EQ_WR_EPS_REG_L2_STEP_MODE_LEN , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_L2_STEP_MODE_LEN ); REG64_FLD( EX_L2_WR_EPS_REG_TIER1_VALUE , 0 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_TIER1_VALUE ); REG64_FLD( EX_L2_WR_EPS_REG_TIER1_VALUE_LEN , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_TIER1_VALUE_LEN ); REG64_FLD( EX_L2_WR_EPS_REG_TIER2_VALUE , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_TIER2_VALUE ); REG64_FLD( EX_L2_WR_EPS_REG_TIER2_VALUE_LEN , 12 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_TIER2_VALUE_LEN ); REG64_FLD( EX_L2_WR_EPS_REG_DIVIDER_MODE , 24 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DIVIDER_MODE ); REG64_FLD( EX_L2_WR_EPS_REG_DIVIDER_MODE_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_DIVIDER_MODE_LEN ); REG64_FLD( EX_L2_WR_EPS_REG_MODE_SEL , 28 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_MODE_SEL ); REG64_FLD( EX_L2_WR_EPS_REG_CNT_USE_L2_DIVIDER_EN , 29 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_CNT_USE_L2_DIVIDER_EN ); REG64_FLD( EX_L2_WR_EPS_REG_L2_STEP_MODE , 30 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_L2_STEP_MODE ); REG64_FLD( EX_L2_WR_EPS_REG_L2_STEP_MODE_LEN , 4 , SH_UNT_EX_L2 , SH_ACS_SCOM , SH_FLD_L2_STEP_MODE_LEN ); REG64_FLD( EQ_XFIR_IN0 , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN0 ); REG64_FLD( EQ_XFIR_IN1 , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN1 ); REG64_FLD( EQ_XFIR_IN2 , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN2 ); REG64_FLD( EQ_XFIR_IN3 , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN3 ); REG64_FLD( EQ_XFIR_IN4 , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN4 ); REG64_FLD( EQ_XFIR_IN5 , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN5 ); REG64_FLD( EQ_XFIR_IN6 , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN6 ); REG64_FLD( EQ_XFIR_IN7 , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN7 ); REG64_FLD( EQ_XFIR_IN8 , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN8 ); REG64_FLD( EQ_XFIR_IN9 , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN9 ); REG64_FLD( EQ_XFIR_IN10 , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN10 ); REG64_FLD( EQ_XFIR_IN11 , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN11 ); REG64_FLD( EQ_XFIR_IN12 , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN12 ); REG64_FLD( EQ_XFIR_IN13 , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN13 ); REG64_FLD( EQ_XFIR_IN13_LEN , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN13_LEN ); REG64_FLD( EQ_XFIR_IN26 , 26 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_IN26 ); REG64_FLD( EX_XFIR_IN0 , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN0 ); REG64_FLD( EX_XFIR_IN1 , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN1 ); REG64_FLD( EX_XFIR_IN2 , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN2 ); REG64_FLD( EX_XFIR_IN3 , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN3 ); REG64_FLD( EX_XFIR_IN4 , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN4 ); REG64_FLD( EX_XFIR_IN5 , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN5 ); REG64_FLD( EX_XFIR_IN5_LEN , 21 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN5_LEN ); REG64_FLD( EX_XFIR_IN26 , 26 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_IN26 ); REG64_FLD( C_XFIR_IN0 , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN0 ); REG64_FLD( C_XFIR_IN1 , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN1 ); REG64_FLD( C_XFIR_IN2 , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN2 ); REG64_FLD( C_XFIR_IN3 , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN3 ); REG64_FLD( C_XFIR_IN4 , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN4 ); REG64_FLD( C_XFIR_IN5 , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN5 ); REG64_FLD( C_XFIR_IN5_LEN , 21 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN5_LEN ); REG64_FLD( C_XFIR_IN26 , 26 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_IN26 ); REG64_FLD( EQ_XSTOP1_MASK_B , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASK_B ); REG64_FLD( EQ_XSTOP1_UNUSED , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( EQ_XSTOP1_TRIGGER_OPCG_ON , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIGGER_OPCG_ON ); REG64_FLD( EQ_XSTOP1_WAIT_ALLWAYS , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WAIT_ALLWAYS ); REG64_FLD( EQ_XSTOP1_PERV , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PERV ); REG64_FLD( EQ_XSTOP1_UNIT1 , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT1 ); REG64_FLD( EQ_XSTOP1_UNIT2 , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT2 ); REG64_FLD( EQ_XSTOP1_UNIT3 , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT3 ); REG64_FLD( EQ_XSTOP1_UNIT4 , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT4 ); REG64_FLD( EQ_XSTOP1_UNIT5 , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT5 ); REG64_FLD( EQ_XSTOP1_UNIT6 , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT6 ); REG64_FLD( EQ_XSTOP1_UNIT7 , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT7 ); REG64_FLD( EQ_XSTOP1_UNIT8 , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT8 ); REG64_FLD( EQ_XSTOP1_UNIT9 , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT9 ); REG64_FLD( EQ_XSTOP1_UNIT10 , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT10 ); REG64_FLD( EQ_XSTOP1_WAIT_CYCLES , 48 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES ); REG64_FLD( EQ_XSTOP1_WAIT_CYCLES_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES_LEN ); REG64_FLD( EX_XSTOP1_MASK_B , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASK_B ); REG64_FLD( EX_XSTOP1_UNUSED , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( EX_XSTOP1_TRIGGER_OPCG_ON , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIGGER_OPCG_ON ); REG64_FLD( EX_XSTOP1_WAIT_ALLWAYS , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WAIT_ALLWAYS ); REG64_FLD( EX_XSTOP1_PERV , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PERV ); REG64_FLD( EX_XSTOP1_UNIT1 , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT1 ); REG64_FLD( EX_XSTOP1_UNIT2 , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT2 ); REG64_FLD( EX_XSTOP1_UNIT3 , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT3 ); REG64_FLD( EX_XSTOP1_UNIT4 , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT4 ); REG64_FLD( EX_XSTOP1_UNIT5 , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT5 ); REG64_FLD( EX_XSTOP1_UNIT6 , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT6 ); REG64_FLD( EX_XSTOP1_UNIT7 , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT7 ); REG64_FLD( EX_XSTOP1_UNIT8 , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT8 ); REG64_FLD( EX_XSTOP1_UNIT9 , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT9 ); REG64_FLD( EX_XSTOP1_UNIT10 , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT10 ); REG64_FLD( EX_XSTOP1_WAIT_CYCLES , 48 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES ); REG64_FLD( EX_XSTOP1_WAIT_CYCLES_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES_LEN ); REG64_FLD( C_XSTOP1_MASK_B , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MASK_B ); REG64_FLD( C_XSTOP1_UNUSED , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( C_XSTOP1_TRIGGER_OPCG_ON , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIGGER_OPCG_ON ); REG64_FLD( C_XSTOP1_WAIT_ALLWAYS , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WAIT_ALLWAYS ); REG64_FLD( C_XSTOP1_PERV , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PERV ); REG64_FLD( C_XSTOP1_UNIT1 , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT1 ); REG64_FLD( C_XSTOP1_UNIT2 , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT2 ); REG64_FLD( C_XSTOP1_UNIT3 , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT3 ); REG64_FLD( C_XSTOP1_UNIT4 , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT4 ); REG64_FLD( C_XSTOP1_UNIT5 , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT5 ); REG64_FLD( C_XSTOP1_UNIT6 , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT6 ); REG64_FLD( C_XSTOP1_UNIT7 , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT7 ); REG64_FLD( C_XSTOP1_UNIT8 , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT8 ); REG64_FLD( C_XSTOP1_UNIT9 , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT9 ); REG64_FLD( C_XSTOP1_UNIT10 , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT10 ); REG64_FLD( C_XSTOP1_WAIT_CYCLES , 48 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES ); REG64_FLD( C_XSTOP1_WAIT_CYCLES_LEN , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES_LEN ); REG64_FLD( EQ_XSTOP2_MASK_B , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASK_B ); REG64_FLD( EQ_XSTOP2_UNUSED , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( EQ_XSTOP2_TRIGGER_OPCG_ON , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIGGER_OPCG_ON ); REG64_FLD( EQ_XSTOP2_WAIT_ALLWAYS , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WAIT_ALLWAYS ); REG64_FLD( EQ_XSTOP2_PERV , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PERV ); REG64_FLD( EQ_XSTOP2_UNIT1 , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT1 ); REG64_FLD( EQ_XSTOP2_UNIT2 , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT2 ); REG64_FLD( EQ_XSTOP2_UNIT3 , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT3 ); REG64_FLD( EQ_XSTOP2_UNIT4 , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT4 ); REG64_FLD( EQ_XSTOP2_UNIT5 , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT5 ); REG64_FLD( EQ_XSTOP2_UNIT6 , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT6 ); REG64_FLD( EQ_XSTOP2_UNIT7 , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT7 ); REG64_FLD( EQ_XSTOP2_UNIT8 , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT8 ); REG64_FLD( EQ_XSTOP2_UNIT9 , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT9 ); REG64_FLD( EQ_XSTOP2_UNIT10 , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT10 ); REG64_FLD( EQ_XSTOP2_WAIT_CYCLES , 48 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES ); REG64_FLD( EQ_XSTOP2_WAIT_CYCLES_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES_LEN ); REG64_FLD( EX_XSTOP2_MASK_B , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASK_B ); REG64_FLD( EX_XSTOP2_UNUSED , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( EX_XSTOP2_TRIGGER_OPCG_ON , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIGGER_OPCG_ON ); REG64_FLD( EX_XSTOP2_WAIT_ALLWAYS , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WAIT_ALLWAYS ); REG64_FLD( EX_XSTOP2_PERV , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PERV ); REG64_FLD( EX_XSTOP2_UNIT1 , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT1 ); REG64_FLD( EX_XSTOP2_UNIT2 , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT2 ); REG64_FLD( EX_XSTOP2_UNIT3 , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT3 ); REG64_FLD( EX_XSTOP2_UNIT4 , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT4 ); REG64_FLD( EX_XSTOP2_UNIT5 , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT5 ); REG64_FLD( EX_XSTOP2_UNIT6 , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT6 ); REG64_FLD( EX_XSTOP2_UNIT7 , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT7 ); REG64_FLD( EX_XSTOP2_UNIT8 , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT8 ); REG64_FLD( EX_XSTOP2_UNIT9 , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT9 ); REG64_FLD( EX_XSTOP2_UNIT10 , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT10 ); REG64_FLD( EX_XSTOP2_WAIT_CYCLES , 48 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES ); REG64_FLD( EX_XSTOP2_WAIT_CYCLES_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES_LEN ); REG64_FLD( C_XSTOP2_MASK_B , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MASK_B ); REG64_FLD( C_XSTOP2_UNUSED , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( C_XSTOP2_TRIGGER_OPCG_ON , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIGGER_OPCG_ON ); REG64_FLD( C_XSTOP2_WAIT_ALLWAYS , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WAIT_ALLWAYS ); REG64_FLD( C_XSTOP2_PERV , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PERV ); REG64_FLD( C_XSTOP2_UNIT1 , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT1 ); REG64_FLD( C_XSTOP2_UNIT2 , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT2 ); REG64_FLD( C_XSTOP2_UNIT3 , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT3 ); REG64_FLD( C_XSTOP2_UNIT4 , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT4 ); REG64_FLD( C_XSTOP2_UNIT5 , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT5 ); REG64_FLD( C_XSTOP2_UNIT6 , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT6 ); REG64_FLD( C_XSTOP2_UNIT7 , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT7 ); REG64_FLD( C_XSTOP2_UNIT8 , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT8 ); REG64_FLD( C_XSTOP2_UNIT9 , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT9 ); REG64_FLD( C_XSTOP2_UNIT10 , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT10 ); REG64_FLD( C_XSTOP2_WAIT_CYCLES , 48 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES ); REG64_FLD( C_XSTOP2_WAIT_CYCLES_LEN , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES_LEN ); REG64_FLD( EQ_XSTOP3_MASK_B , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_MASK_B ); REG64_FLD( EQ_XSTOP3_UNUSED , 1 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( EQ_XSTOP3_TRIGGER_OPCG_ON , 2 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_TRIGGER_OPCG_ON ); REG64_FLD( EQ_XSTOP3_WAIT_ALLWAYS , 3 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WAIT_ALLWAYS ); REG64_FLD( EQ_XSTOP3_PERV , 4 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_PERV ); REG64_FLD( EQ_XSTOP3_UNIT1 , 5 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT1 ); REG64_FLD( EQ_XSTOP3_UNIT2 , 6 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT2 ); REG64_FLD( EQ_XSTOP3_UNIT3 , 7 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT3 ); REG64_FLD( EQ_XSTOP3_UNIT4 , 8 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT4 ); REG64_FLD( EQ_XSTOP3_UNIT5 , 9 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT5 ); REG64_FLD( EQ_XSTOP3_UNIT6 , 10 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT6 ); REG64_FLD( EQ_XSTOP3_UNIT7 , 11 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT7 ); REG64_FLD( EQ_XSTOP3_UNIT8 , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT8 ); REG64_FLD( EQ_XSTOP3_UNIT9 , 13 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT9 ); REG64_FLD( EQ_XSTOP3_UNIT10 , 14 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_UNIT10 ); REG64_FLD( EQ_XSTOP3_WAIT_CYCLES , 48 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES ); REG64_FLD( EQ_XSTOP3_WAIT_CYCLES_LEN , 12 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES_LEN ); REG64_FLD( EX_XSTOP3_MASK_B , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_MASK_B ); REG64_FLD( EX_XSTOP3_UNUSED , 1 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( EX_XSTOP3_TRIGGER_OPCG_ON , 2 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_TRIGGER_OPCG_ON ); REG64_FLD( EX_XSTOP3_WAIT_ALLWAYS , 3 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WAIT_ALLWAYS ); REG64_FLD( EX_XSTOP3_PERV , 4 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_PERV ); REG64_FLD( EX_XSTOP3_UNIT1 , 5 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT1 ); REG64_FLD( EX_XSTOP3_UNIT2 , 6 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT2 ); REG64_FLD( EX_XSTOP3_UNIT3 , 7 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT3 ); REG64_FLD( EX_XSTOP3_UNIT4 , 8 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT4 ); REG64_FLD( EX_XSTOP3_UNIT5 , 9 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT5 ); REG64_FLD( EX_XSTOP3_UNIT6 , 10 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT6 ); REG64_FLD( EX_XSTOP3_UNIT7 , 11 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT7 ); REG64_FLD( EX_XSTOP3_UNIT8 , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT8 ); REG64_FLD( EX_XSTOP3_UNIT9 , 13 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT9 ); REG64_FLD( EX_XSTOP3_UNIT10 , 14 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_UNIT10 ); REG64_FLD( EX_XSTOP3_WAIT_CYCLES , 48 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES ); REG64_FLD( EX_XSTOP3_WAIT_CYCLES_LEN , 12 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES_LEN ); REG64_FLD( C_XSTOP3_MASK_B , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_MASK_B ); REG64_FLD( C_XSTOP3_UNUSED , 1 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( C_XSTOP3_TRIGGER_OPCG_ON , 2 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_TRIGGER_OPCG_ON ); REG64_FLD( C_XSTOP3_WAIT_ALLWAYS , 3 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WAIT_ALLWAYS ); REG64_FLD( C_XSTOP3_PERV , 4 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_PERV ); REG64_FLD( C_XSTOP3_UNIT1 , 5 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT1 ); REG64_FLD( C_XSTOP3_UNIT2 , 6 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT2 ); REG64_FLD( C_XSTOP3_UNIT3 , 7 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT3 ); REG64_FLD( C_XSTOP3_UNIT4 , 8 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT4 ); REG64_FLD( C_XSTOP3_UNIT5 , 9 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT5 ); REG64_FLD( C_XSTOP3_UNIT6 , 10 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT6 ); REG64_FLD( C_XSTOP3_UNIT7 , 11 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT7 ); REG64_FLD( C_XSTOP3_UNIT8 , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT8 ); REG64_FLD( C_XSTOP3_UNIT9 , 13 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT9 ); REG64_FLD( C_XSTOP3_UNIT10 , 14 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_UNIT10 ); REG64_FLD( C_XSTOP3_WAIT_CYCLES , 48 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES ); REG64_FLD( C_XSTOP3_WAIT_CYCLES_LEN , 12 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES_LEN ); REG64_FLD( EQ_XSTOP_INTERRUPT_REG_XSTOP , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_XSTOP ); REG64_FLD( EX_XSTOP_INTERRUPT_REG_XSTOP , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_XSTOP ); REG64_FLD( C_XSTOP_INTERRUPT_REG_XSTOP , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_XSTOP ); REG64_FLD( EQ_XTRA_TRACE_MODE_DATA , 0 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DATA ); REG64_FLD( EQ_XTRA_TRACE_MODE_DATA_LEN , 38 , SH_UNT_EQ , SH_ACS_SCOM , SH_FLD_DATA_LEN ); REG64_FLD( EX_XTRA_TRACE_MODE_DATA , 0 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DATA ); REG64_FLD( EX_XTRA_TRACE_MODE_DATA_LEN , 38 , SH_UNT_EX , SH_ACS_SCOM , SH_FLD_DATA_LEN ); REG64_FLD( C_XTRA_TRACE_MODE_DATA , 0 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DATA ); REG64_FLD( C_XTRA_TRACE_MODE_DATA_LEN , 38 , SH_UNT_C , SH_ACS_SCOM , SH_FLD_DATA_LEN ); #endif