/* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ /* $Source: import/chips/p9/common/include/p9_misc_scom_addresses_fld.H $ */ /* */ /* OpenPOWER sbe Project */ /* */ /* Contributors Listed Below - COPYRIGHT 2015,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ /* You may obtain a copy of the License at */ /* */ /* http://www.apache.org/licenses/LICENSE-2.0 */ /* */ /* Unless required by applicable law or agreed to in writing, software */ /* distributed under the License is distributed on an "AS IS" BASIS, */ /* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ /* implied. See the License for the specific language governing */ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ /// /// @file p9_misc_scom_addresses_fld.H /// @brief Defines constants for scom addresses /// // *HWP HWP Owner: Ben Gass // *HWP FW Owner: Thi Tran // *HWP Team: SOA // *HWP Level: 1 // *HWP Consumed by: FSP:HB:HS:OCC:SBE:CME:SGPE:PGPE:FPPE:IPPE #include #ifndef __P9_MISC_SCOM_ADDRESSES_FLD_H #define __P9_MISC_SCOM_ADDRESSES_FLD_H #include #include REG64_FLD( PU_ADDR_0_HASH_FUNCTION_REG_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS ); REG64_FLD( PU_ADDR_0_HASH_FUNCTION_REG_ADDRESS_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_ADDR_10_HASH_FUNCTION_REG_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS ); REG64_FLD( PU_ADDR_10_HASH_FUNCTION_REG_ADDRESS_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_ADDR_1_HASH_FUNCTION_REG_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS ); REG64_FLD( PU_ADDR_1_HASH_FUNCTION_REG_ADDRESS_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_ADDR_2_HASH_FUNCTION_REG_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS ); REG64_FLD( PU_ADDR_2_HASH_FUNCTION_REG_ADDRESS_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_ADDR_3_HASH_FUNCTION_REG_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS ); REG64_FLD( PU_ADDR_3_HASH_FUNCTION_REG_ADDRESS_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_ADDR_4_HASH_FUNCTION_REG_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS ); REG64_FLD( PU_ADDR_4_HASH_FUNCTION_REG_ADDRESS_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_ADDR_5_HASH_FUNCTION_REG_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS ); REG64_FLD( PU_ADDR_5_HASH_FUNCTION_REG_ADDRESS_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_ADDR_6_HASH_FUNCTION_REG_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS ); REG64_FLD( PU_ADDR_6_HASH_FUNCTION_REG_ADDRESS_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_ADDR_7_HASH_FUNCTION_REG_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS ); REG64_FLD( PU_ADDR_7_HASH_FUNCTION_REG_ADDRESS_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_ADDR_8_HASH_FUNCTION_REG_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS ); REG64_FLD( PU_ADDR_8_HASH_FUNCTION_REG_ADDRESS_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_ADDR_9_HASH_FUNCTION_REG_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS ); REG64_FLD( PU_ADDR_9_HASH_FUNCTION_REG_ADDRESS_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_N3_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR ); REG64_FLD( PU_N3_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN ); REG64_FLD( PU_N3_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR ); REG64_FLD( PU_N3_ADDR_TRAP_REG_RESERVED_LAST_LT , 17 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RESERVED_LAST_LT ); REG64_FLD( PU_N3_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR ); REG64_FLD( PU_N3_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN ); REG64_FLD( PU_N3_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY ); REG64_FLD( PU_N3_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR ); REG64_FLD( PU_N3_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION ); REG64_FLD( PU_N3_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER ); REG64_FLD( PU_N1_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR ); REG64_FLD( PU_N1_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN ); REG64_FLD( PU_N1_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR ); REG64_FLD( PU_N1_ADDR_TRAP_REG_RESERVED_LAST_LT , 17 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESERVED_LAST_LT ); REG64_FLD( PU_N1_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR ); REG64_FLD( PU_N1_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN ); REG64_FLD( PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY ); REG64_FLD( PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR ); REG64_FLD( PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION ); REG64_FLD( PU_N1_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER ); REG64_FLD( PU_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR ); REG64_FLD( PU_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN ); REG64_FLD( PU_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR ); REG64_FLD( PU_ADDR_TRAP_REG_RESERVED_LAST_LT , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_LAST_LT ); REG64_FLD( PU_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR ); REG64_FLD( PU_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN ); REG64_FLD( PU_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY ); REG64_FLD( PU_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR ); REG64_FLD( PU_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33 , SH_UNT , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION ); REG64_FLD( PU_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34 , SH_UNT , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER ); REG64_FLD( PU_N2_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR ); REG64_FLD( PU_N2_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN ); REG64_FLD( PU_N2_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR ); REG64_FLD( PU_N2_ADDR_TRAP_REG_RESERVED_LAST_LT , 17 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RESERVED_LAST_LT ); REG64_FLD( PU_N2_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR ); REG64_FLD( PU_N2_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN ); REG64_FLD( PU_N2_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY ); REG64_FLD( PU_N2_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR ); REG64_FLD( PU_N2_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION ); REG64_FLD( PU_N2_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER ); REG64_FLD( PEC_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR ); REG64_FLD( PEC_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN ); REG64_FLD( PEC_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR ); REG64_FLD( PEC_ADDR_TRAP_REG_RESERVED_LAST_LT , 17 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESERVED_LAST_LT ); REG64_FLD( PEC_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR ); REG64_FLD( PEC_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN ); REG64_FLD( PEC_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY ); REG64_FLD( PEC_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR ); REG64_FLD( PEC_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION ); REG64_FLD( PEC_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER ); REG64_FLD( PU_N0_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR ); REG64_FLD( PU_N0_ADDR_TRAP_REG_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_OF_LAST_TRANSACTION_WITH_ERROR_LEN ); REG64_FLD( PU_N0_ADDR_TRAP_REG_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_PCB_READ_NOTWRITE_OF_LAST_TRANSACTION_WITH_ERROR ); REG64_FLD( PU_N0_ADDR_TRAP_REG_RESERVED_LAST_LT , 17 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RESERVED_LAST_LT ); REG64_FLD( PU_N0_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR , 18 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR ); REG64_FLD( PU_N0_ADDR_TRAP_REG_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN , 13 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_SERIAL2PARALLEL_STATE_MACHINE_AT_TIME_OF_ERROR_LEN ); REG64_FLD( PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY , 31 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_RETURN_PARITY ); REG64_FLD( PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR , 32 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_WRITE_PARITY_ERROR ); REG64_FLD( PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION , 33 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_ACCESS_VIOLATION ); REG64_FLD( PU_N0_ADDR_TRAP_REG_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER , 34 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_BIT_INVALID_REGISTER ); REG64_FLD( PU_ADS_XSCOM_CMD_REG_RNW , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RNW ); REG64_FLD( PU_ADS_XSCOM_CMD_REG_SIZE , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_SIZE ); REG64_FLD( PU_ADS_XSCOM_CMD_REG_SIZE_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_SIZE_LEN ); REG64_FLD( PU_ADS_XSCOM_CMD_REG_ADR , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADR ); REG64_FLD( PU_ADS_XSCOM_CMD_REG_ADR_LEN , 34 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADR_LEN ); REG64_FLD( PU_ADU_HANG_DIV_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( PU_ADU_HANG_DIV_REG_DATA_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( PU_ADU_HANG_DIV_REG_OPER , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OPER ); REG64_FLD( PU_ADU_HANG_DIV_REG_OPER_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OPER_LEN ); REG64_FLD( PU_ALTD_ADDR_REG_FBC_ADDRESS , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_ADDRESS ); REG64_FLD( PU_ALTD_ADDR_REG_FBC_ADDRESS_LEN , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_ADDRESS_LEN ); REG64_FLD( PU_ALTD_CMD_REG_FBC_START_OP , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_START_OP ); REG64_FLD( PU_ALTD_CMD_REG_FBC_CLEAR_STATUS , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_CLEAR_STATUS ); REG64_FLD( PU_ALTD_CMD_REG_FBC_RESET_FSM , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_RESET_FSM ); REG64_FLD( PU_ALTD_CMD_REG_FBC_RNW , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_RNW ); REG64_FLD( PU_ALTD_CMD_REG_FBC_AXTYPE , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_AXTYPE ); REG64_FLD( PU_ALTD_CMD_REG_FBC_DATA_ONLY , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_DATA_ONLY ); REG64_FLD( PU_ALTD_CMD_REG_FBC_LOCKED , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_LOCKED ); REG64_FLD( PU_ALTD_CMD_REG_FBC_LOCK_ID , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_LOCK_ID ); REG64_FLD( PU_ALTD_CMD_REG_FBC_LOCK_ID_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_LOCK_ID_LEN ); REG64_FLD( PU_ALTD_CMD_REG_FBC_SCOPE , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_SCOPE ); REG64_FLD( PU_ALTD_CMD_REG_FBC_SCOPE_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_SCOPE_LEN ); REG64_FLD( PU_ALTD_CMD_REG_FBC_AUTO_INC , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_AUTO_INC ); REG64_FLD( PU_ALTD_CMD_REG_FBC_DROP_PRIORITY , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_DROP_PRIORITY ); REG64_FLD( PU_ALTD_CMD_REG_FBC_DROP_PRIORITY_MAX , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_DROP_PRIORITY_MAX ); REG64_FLD( PU_ALTD_CMD_REG_FBC_OVERWRITE_PBINIT , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_OVERWRITE_PBINIT ); REG64_FLD( PU_ALTD_CMD_REG_FBC_PIB_DIRECT , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_PIB_DIRECT ); REG64_FLD( PU_ALTD_CMD_REG_FBC_WITH_TM_QUIESCE , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_WITH_TM_QUIESCE ); REG64_FLD( PU_ALTD_CMD_REG_FBC_TTYPE , 25 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_TTYPE ); REG64_FLD( PU_ALTD_CMD_REG_FBC_TTYPE_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_TTYPE_LEN ); REG64_FLD( PU_ALTD_CMD_REG_FBC_TSIZE , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_TSIZE ); REG64_FLD( PU_ALTD_CMD_REG_FBC_TSIZE_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_TSIZE_LEN ); REG64_FLD( PU_ALTD_DATA_REG_FBC , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FBC ); REG64_FLD( PU_ALTD_DATA_REG_FBC_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FBC_LEN ); REG64_FLD( PU_ALTD_OPTION_REG_FBC_WITH_PRE_QUIESCE , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_WITH_PRE_QUIESCE ); REG64_FLD( PU_ALTD_OPTION_REG_FBC_WITH_PBINIT_LOW_WAIT , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_WITH_PBINIT_LOW_WAIT ); REG64_FLD( PU_ALTD_OPTION_REG_FBC_AFTER_QUIESCE_WAIT_COUNT , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT ); REG64_FLD( PU_ALTD_OPTION_REG_FBC_AFTER_QUIESCE_WAIT_COUNT_LEN , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_AFTER_QUIESCE_WAIT_COUNT_LEN ); REG64_FLD( PU_ALTD_OPTION_REG_FBC_WITH_POST_INIT , 51 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_WITH_POST_INIT ); REG64_FLD( PU_ALTD_OPTION_REG_FBC_BEFORE_INIT_WAIT_COUNT , 54 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT ); REG64_FLD( PU_ALTD_OPTION_REG_FBC_BEFORE_INIT_WAIT_COUNT_LEN , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_BEFORE_INIT_WAIT_COUNT_LEN ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_WAIT_CMD_ARBIT , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_WAIT_CMD_ARBIT ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_ADDR_DONE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_ADDR_DONE ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_DATA_DONE , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_DATA_DONE ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_WAIT_RESP , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_WAIT_RESP ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_OVERRUN_ERROR , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_OVERRUN_ERROR ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_AUTOINC_ERROR , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_AUTOINC_ERROR ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_COMMAND_ERROR , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_COMMAND_ERROR ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_ADDRESS_ERROR , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_ADDRESS_ERROR ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_PB_OP_HANG_ERR , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_PB_OP_HANG_ERR ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_PB_DATA_HANG_ERR , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_PB_DATA_HANG_ERR ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_PB_UNEXPECT_CRESP_ERR , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_PB_UNEXPECT_CRESP_ERR ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_PB_UNEXPECT_DATA_ERR , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_PB_UNEXPECT_DATA_ERR ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_WAIT_PIB_DIRECT , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_WAIT_PIB_DIRECT ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_PIB_DIRECT_DONE , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_PIB_DIRECT_DONE ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_PBINIT_MISSING , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_PBINIT_MISSING ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_PIB_ERROR , 33 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_PIB_ERROR ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_PIB_ERROR_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_PIB_ERROR_LEN ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_ECC_CE , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_ECC_CE ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_ECC_UE , 49 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_ECC_UE ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_ECC_SUE , 50 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_ECC_SUE ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_CRESP_VALUE , 59 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_CRESP_VALUE ); REG64_FLD( PU_ALTD_STATUS_REG_FBC_CRESP_VALUE_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_CRESP_VALUE_LEN ); REG64_FLD( CAPP_APCFG_APCCTL_PHB_SEL , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_PHB_SEL ); REG64_FLD( CAPP_APCFG_APCCTL_PHB_SEL_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_PHB_SEL_LEN ); REG64_FLD( CAPP_APCFG_HANG_POLL_SCALE , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_HANG_POLL_SCALE ); REG64_FLD( CAPP_APCFG_HANG_POLL_SCALE_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_HANG_POLL_SCALE_LEN ); REG64_FLD( CAPP_APCFG_SPEC_HPC_DIR_STATE , 8 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SPEC_HPC_DIR_STATE ); REG64_FLD( CAPP_APCFG_SPEC_HPC_DIR_STATE_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SPEC_HPC_DIR_STATE_LEN ); REG64_FLD( CAPP_APCFG_APCCTL_P9_MODE , 14 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_P9_MODE ); REG64_FLD( CAPP_APCFG_APCCTL_SYSADDR , 15 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_SYSADDR ); REG64_FLD( CAPP_APCFG_APCCTL_SYSADDR_LEN , 6 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_SYSADDR_LEN ); REG64_FLD( CAPP_APCFG_APCCTL_MEM_SEL_MODE , 21 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_MEM_SEL_MODE ); REG64_FLD( CAPP_APCFG_APCCTL_ENB_FRC_ADDR13 , 22 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_ENB_FRC_ADDR13 ); REG64_FLD( CAPP_APCLCO_TARGET_VALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TARGET_VALID ); REG64_FLD( CAPP_APCLCO_TARGET_VALID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TARGET_VALID_LEN ); REG64_FLD( CAPP_APCLCO_TARGET_ID0 , 12 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TARGET_ID0 ); REG64_FLD( CAPP_APCLCO_TARGET_MIN , 13 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TARGET_MIN ); REG64_FLD( CAPP_APCLCO_TARGET_MIN_LEN , 3 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TARGET_MIN_LEN ); REG64_FLD( CAPP_APCRDFSMMASK_APC_RDFSM_MASK , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APC_RDFSM_MASK ); REG64_FLD( CAPP_APCRDFSMMASK_APC_RDFSM_MASK_LEN , 48 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APC_RDFSM_MASK_LEN ); REG64_FLD( CAPP_APCTL_APCCTL_ENB_CRESP_EXAM , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_ENB_CRESP_EXAM ); REG64_FLD( CAPP_APCTL_APCCTL_ADR_BAR_MODE , 1 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_ADR_BAR_MODE ); REG64_FLD( CAPP_APCTL_APCCTL_DISABLE_NN_RN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_DISABLE_NN_RN ); REG64_FLD( CAPP_APCTL_APCCTL_DISABLE_VG_NOT_SYS , 3 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_DISABLE_VG_NOT_SYS ); REG64_FLD( CAPP_APCTL_APCCTL_DISABLE_G , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_DISABLE_G ); REG64_FLD( CAPP_APCTL_APCCTL_DISABLE_LN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_DISABLE_LN ); REG64_FLD( CAPP_APCTL_APCCTL_SKIP_G , 6 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_SKIP_G ); REG64_FLD( CAPP_APCTL_APCCTL_HANG_ARE , 7 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_HANG_ARE ); REG64_FLD( CAPP_APCTL_APCCTL_HANG_DEAD , 8 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_HANG_DEAD ); REG64_FLD( CAPP_APCTL_APCCTL_CFG_BKILL_INC , 9 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_CFG_BKILL_INC ); REG64_FLD( CAPP_APCTL_APCCTL_DISABLE_PSL_CMDQUEUE , 12 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_DISABLE_PSL_CMDQUEUE ); REG64_FLD( CAPP_APCTL_APCCTL_ENABLE_MASTER_RETRY_BACKOFF , 13 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_ENABLE_MASTER_RETRY_BACKOFF ); REG64_FLD( CAPP_APCTL_SCPTGT_LFSR_MODE , 14 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SCPTGT_LFSR_MODE ); REG64_FLD( CAPP_APCTL_SCPTGT_LFSR_MODE_LEN , 3 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SCPTGT_LFSR_MODE_LEN ); REG64_FLD( CAPP_APCTL_APCCTL_ENABLE_RD_VG_SCOPE_PREDICT , 17 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_ENABLE_RD_VG_SCOPE_PREDICT ); REG64_FLD( CAPP_APCTL_WR_EPSILON_VALUE , 39 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_WR_EPSILON_VALUE ); REG64_FLD( CAPP_APCTL_WR_EPSILON_VALUE_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_WR_EPSILON_VALUE_LEN ); REG64_FLD( CAPP_APCTL_APCCTL_MAX_RETRY , 56 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_MAX_RETRY ); REG64_FLD( CAPP_APCTL_APCCTL_MAX_RETRY_LEN , 8 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCCTL_MAX_RETRY_LEN ); REG64_FLD( CAPP_APC_ARRY_ADDR_APCARY_ADDRESS , 3 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCARY_ADDRESS ); REG64_FLD( CAPP_APC_ARRY_ADDR_APCARY_ADDRESS_LEN , 9 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCARY_ADDRESS_LEN ); REG64_FLD( CAPP_APC_ARRY_RDDATA_APCARY , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCARY ); REG64_FLD( CAPP_APC_ARRY_RDDATA_APCARY_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCARY_LEN ); REG64_FLD( CAPP_APC_ARRY_WRDATA_APCARY , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCARY ); REG64_FLD( CAPP_APC_ARRY_WRDATA_APCARY_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APCARY_LEN ); REG64_FLD( CAPP_APC_ERRINJ_ENABLE , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( CAPP_APC_ERRINJ_DBLERR , 1 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_DBLERR ); REG64_FLD( CAPP_APC_ERRINJ_CONTINUOUS , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_CONTINUOUS ); REG64_FLD( CAPP_APC_ERRINJ_TARGET , 7 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TARGET ); REG64_FLD( CAPP_APC_ERRINJ_TARGET_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TARGET_LEN ); REG64_FLD( CAPP_APC_ERRINJ_SNP_ERROR_INJECT_ENABLE , 12 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SNP_ERROR_INJECT_ENABLE ); REG64_FLD( CAPP_APC_ERRINJ_SNP_INJECT_DBL_ECC_ERROR , 13 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SNP_INJECT_DBL_ECC_ERROR ); REG64_FLD( CAPP_APC_ERRINJ_SNP_INJECT_CONTINOUS_ERROR , 14 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SNP_INJECT_CONTINOUS_ERROR ); REG64_FLD( CAPP_APC_ERRINJ_SNP_ERROR_INJECT_TARGET , 17 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SNP_ERROR_INJECT_TARGET ); REG64_FLD( CAPP_APC_ERRINJ_SNP_ERROR_INJECT_TARGET_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SNP_ERROR_INJECT_TARGET_LEN ); REG64_FLD( CAPP_APC_ERRINJ_XPT_ERROR_INJECT_ENABLE , 32 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_XPT_ERROR_INJECT_ENABLE ); REG64_FLD( CAPP_APC_ERRINJ_XPT_ERROR_TYPE , 33 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_XPT_ERROR_TYPE ); REG64_FLD( CAPP_APC_ERRINJ_XPT_ERROR_TYPE_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_XPT_ERROR_TYPE_LEN ); REG64_FLD( CAPP_APC_ERRINJ_XPT_INJECT_CONTINUOUS_ERROR , 35 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_XPT_INJECT_CONTINUOUS_ERROR ); REG64_FLD( CAPP_APC_ERRINJ_XPT_ERROR_INJECT_TARGET , 36 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_XPT_ERROR_INJECT_TARGET ); REG64_FLD( CAPP_APC_ERRINJ_XPT_ERROR_INJECT_TARGET_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_XPT_ERROR_INJECT_TARGET_LEN ); REG64_FLD( CAPP_APC_PMUSEL_GRPSEL , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_GRPSEL ); REG64_FLD( CAPP_APC_PMUSEL_GRPSEL_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_GRPSEL_LEN ); REG64_FLD( CAPP_APC_PMUSEL_FSMJ_EVENT_SEL , 6 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_FSMJ_EVENT_SEL ); REG64_FLD( CAPP_APC_PMUSEL_FSMJ_EVENT_SEL_LEN , 6 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_FSMJ_EVENT_SEL_LEN ); REG64_FLD( CAPP_APC_PMUSEL_FSMJ_FSM_SEL , 13 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_FSMJ_FSM_SEL ); REG64_FLD( CAPP_APC_PMUSEL_FSMJ_FSM_SEL_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_FSMJ_FSM_SEL_LEN ); REG64_FLD( CAPP_ASE_TUPLE0_LPID , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_LPID ); REG64_FLD( CAPP_ASE_TUPLE0_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_LPID_LEN ); REG64_FLD( CAPP_ASE_TUPLE0_PID , 20 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PID ); REG64_FLD( CAPP_ASE_TUPLE0_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PID_LEN ); REG64_FLD( CAPP_ASE_TUPLE0_TID , 44 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TID ); REG64_FLD( CAPP_ASE_TUPLE0_TID_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TID_LEN ); REG64_FLD( CAPP_ASE_TUPLE0_VALID , 63 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_VALID ); REG64_FLD( CAPP_ASE_TUPLE1_LPID , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_LPID ); REG64_FLD( CAPP_ASE_TUPLE1_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_LPID_LEN ); REG64_FLD( CAPP_ASE_TUPLE1_PID , 20 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PID ); REG64_FLD( CAPP_ASE_TUPLE1_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PID_LEN ); REG64_FLD( CAPP_ASE_TUPLE1_TID , 44 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TID ); REG64_FLD( CAPP_ASE_TUPLE1_TID_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TID_LEN ); REG64_FLD( CAPP_ASE_TUPLE1_VALID , 63 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_VALID ); REG64_FLD( CAPP_ASE_TUPLE2_LPID , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_LPID ); REG64_FLD( CAPP_ASE_TUPLE2_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_LPID_LEN ); REG64_FLD( CAPP_ASE_TUPLE2_PID , 20 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PID ); REG64_FLD( CAPP_ASE_TUPLE2_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PID_LEN ); REG64_FLD( CAPP_ASE_TUPLE2_TID , 44 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TID ); REG64_FLD( CAPP_ASE_TUPLE2_TID_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TID_LEN ); REG64_FLD( CAPP_ASE_TUPLE2_VALID , 63 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_VALID ); REG64_FLD( CAPP_ASE_TUPLE3_LPID , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_LPID ); REG64_FLD( CAPP_ASE_TUPLE3_LPID_LEN , 12 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_LPID_LEN ); REG64_FLD( CAPP_ASE_TUPLE3_PID , 20 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PID ); REG64_FLD( CAPP_ASE_TUPLE3_PID_LEN , 20 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PID_LEN ); REG64_FLD( CAPP_ASE_TUPLE3_TID , 44 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TID ); REG64_FLD( CAPP_ASE_TUPLE3_TID_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TID_LEN ); REG64_FLD( CAPP_ASE_TUPLE3_VALID , 63 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_VALID ); REG64_FLD( PU_N3_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_MASK ); REG64_FLD( PU_N3_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_MASK_LEN ); REG64_FLD( PU_N1_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_MASK ); REG64_FLD( PU_N1_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_MASK_LEN ); REG64_FLD( PU_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASK ); REG64_FLD( PU_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASK_LEN ); REG64_FLD( PU_N2_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_MASK ); REG64_FLD( PU_N2_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_MASK_LEN ); REG64_FLD( PEC_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MASK ); REG64_FLD( PEC_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MASK_LEN ); REG64_FLD( PU_N0_ATOMIC_LOCK_MASK_LATCH_REG_MASK , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_MASK ); REG64_FLD( PU_N0_ATOMIC_LOCK_MASK_LATCH_REG_MASK_LEN , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_MASK_LEN ); REG64_FLD( PEC_ATOMIC_LOCK_REG_ENABLE , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PEC_ATOMIC_LOCK_REG_ID , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ID ); REG64_FLD( PEC_ATOMIC_LOCK_REG_ID_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ID_LEN ); REG64_FLD( PEC_ATOMIC_LOCK_REG_ACTIVITY , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACTIVITY ); REG64_FLD( PEC_ATOMIC_LOCK_REG_ACTIVITY_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACTIVITY_LEN ); REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_START , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_START ); REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_START_LEN , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_START_LEN ); REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_END , 17 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_END ); REG64_FLD( PU_NPU2_NTL0_ATR_HA_PTR_END_LEN , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_END_LEN ); REG64_FLD( NV_ATR_HA_PTR_RESERVED1 , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( NV_ATR_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( NV_ATR_HA_PTR_START , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_START ); REG64_FLD( NV_ATR_HA_PTR_START_LEN , 7 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_START_LEN ); REG64_FLD( NV_ATR_HA_PTR_RESERVED2 , 12 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( NV_ATR_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( NV_ATR_HA_PTR_END , 17 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_END ); REG64_FLD( NV_ATR_HA_PTR_END_LEN , 7 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_END_LEN ); REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_START , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_START ); REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_START_LEN , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_START_LEN ); REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_END , 17 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_END ); REG64_FLD( PU_NPU2_NTL1_ATR_HA_PTR_END_LEN , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_END_LEN ); REG64_FLD( PU_NPU_SM0_ATS_CKSW_SPARE , 0 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_SPARE ); REG64_FLD( PU_NPU_SM0_ATS_CKSW_SPARE_LEN , 64 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_SPARE_LEN ); REG64_FLD( PU_NPU_SM1_ATS_CTRL_ARB_STOP , 0 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_ARB_STOP ); REG64_FLD( PU_NPU_SM1_ATS_CTRL_ARB_STALL , 1 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_ARB_STALL ); REG64_FLD( PU_NPU_SM1_ATS_CTRL_TCE_CACHE_DISABLE , 2 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_TCE_CACHE_DISABLE ); REG64_FLD( PU_NPU_SM1_ATS_CTRL_TCE_CACHE_1W , 3 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_TCE_CACHE_1W ); REG64_FLD( PU_NPU_SM1_ATS_CTRL_CONFIG_BRAZOS , 4 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_CONFIG_BRAZOS ); REG64_FLD( PU_NPU_SM1_ATS_CTRL_CONFIG_SYNC_WAIT , 5 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_CONFIG_SYNC_WAIT ); REG64_FLD( PU_NPU_SM1_ATS_CTRL_CONFIG_SYNC_WAIT_LEN , 5 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_CONFIG_SYNC_WAIT_LEN ); REG64_FLD( PU_NPU_SM1_ATS_CTRL_SPARE , 10 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_SPARE ); REG64_FLD( PU_NPU_SM1_ATS_CTRL_SPARE_LEN , 54 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_SPARE_LEN ); REG64_FLD( PU_NPU_SM0_ATS_HOLD_TVT_ENTRY_INVALID_ESR , 0 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_TVT_ENTRY_INVALID_ESR ); REG64_FLD( PU_NPU_SM0_ATS_HOLD_TVT_ADDR_RANGE_ERR_ESR , 1 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_TVT_ADDR_RANGE_ERR_ESR ); REG64_FLD( PU_NPU_SM0_ATS_HOLD_TCE_PAGE_ACCESS_ERR_ESR , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_TCE_PAGE_ACCESS_ERR_ESR ); REG64_FLD( PU_NPU_SM0_ATS_HOLD_TCE_CACHE_MULT_HIT_ERR_ESR , 3 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_TCE_CACHE_MULT_HIT_ERR_ESR ); REG64_FLD( PU_NPU_SM0_ATS_HOLD_MLC_ACCESS_ERR_ESR , 4 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_MLC_ACCESS_ERR_ESR ); REG64_FLD( PU_NPU_SM0_ATS_HOLD_TCE_REQ_TO_ERR_ESR , 5 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_TCE_REQ_TO_ERR_ESR ); REG64_FLD( PU_NPU_SM0_ATS_HOLD_TCD_PERR_ESR , 6 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_TCD_PERR_ESR ); REG64_FLD( PU_NPU_SM0_ATS_HOLD_TDR_PERR_ESR , 7 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_TDR_PERR_ESR ); REG64_FLD( PU_NPU_SM0_ATS_HOLD_AT_EA_UE_ESR , 8 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_AT_EA_UE_ESR ); REG64_FLD( PU_NPU_SM0_ATS_HOLD_AT_EA_CE_ESR , 9 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_AT_EA_CE_ESR ); REG64_FLD( PU_NPU_SM0_ATS_HOLD_AT_TDRMEM_UE_ESR , 10 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_AT_TDRMEM_UE_ESR ); REG64_FLD( PU_NPU_SM0_ATS_HOLD_AT_TDRMEM_CE_ESR , 11 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_AT_TDRMEM_CE_ESR ); REG64_FLD( PU_NPU_SM0_ATS_HOLD_RSPOUT_UE_ESR , 12 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_RSPOUT_UE_ESR ); REG64_FLD( PU_NPU_SM0_ATS_HOLD_RSPOUT_CE_ESR , 13 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_RSPOUT_CE_ESR ); REG64_FLD( PU_NPU_SM0_ATS_HOLD_TVT_PERR_ESR , 14 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_TVT_PERR_ESR ); REG64_FLD( PU_NPU_SM0_ATS_HOLD_IODA_ADDR_PERR_ESR , 15 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_IODA_ADDR_PERR_ESR ); REG64_FLD( PU_NPU_SM0_ATS_HOLD_CTRLR_PERR_ESR , 16 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_CTRLR_PERR_ESR ); REG64_FLD( PU_NPU_SM0_ATS_HOLD_TOR_PERR_ESR , 17 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_TOR_PERR_ESR ); REG64_FLD( PU_NPU_SM0_ATS_HOLD_INVAL_IODA_TBL_SEL_ESR , 18 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_INVAL_IODA_TBL_SEL_ESR ); REG64_FLD( PU_NPU_SM0_ATS_HOLD_ESR_RSVD_19 , 19 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_ESR_RSVD_19 ); REG64_FLD( PU_NPU_SM0_ATS_MASK_IDIAL , 0 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO , SH_FLD_IDIAL ); REG64_FLD( PU_NPU_SM0_ATS_MASK_IDIAL_LEN , 20 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_NPU_SM1_ATS_TCR_TCE_TIMEOUT , 10 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_TCE_TIMEOUT ); REG64_FLD( PU_NPU_SM1_ATS_TCR_TCE_TIMEOUT_LEN , 6 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_TCE_TIMEOUT_LEN ); REG64_FLD( PU_BANK0_MCD_BOT_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_BANK0_MCD_BOT_CPG , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CPG ); REG64_FLD( PU_BANK0_MCD_BOT_GRP_MBR_ID , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GRP_MBR_ID ); REG64_FLD( PU_BANK0_MCD_BOT_ALWAYS_RTY , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ALWAYS_RTY ); REG64_FLD( PU_BANK0_MCD_BOT_GRP_SIZE , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GRP_SIZE ); REG64_FLD( PU_BANK0_MCD_BOT_GRP_SIZE_LEN , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GRP_SIZE_LEN ); REG64_FLD( PU_BANK0_MCD_BOT_GRP_BASE , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GRP_BASE ); REG64_FLD( PU_BANK0_MCD_BOT_GRP_BASE_LEN , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GRP_BASE_LEN ); REG64_FLD( PU_MCD1_BANK0_MCD_BOT_VALID , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_MCD1_BANK0_MCD_BOT_CPG , 1 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_CPG ); REG64_FLD( PU_MCD1_BANK0_MCD_BOT_GRP_MBR_ID , 2 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_GRP_MBR_ID ); REG64_FLD( PU_MCD1_BANK0_MCD_BOT_ALWAYS_RTY , 3 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_ALWAYS_RTY ); REG64_FLD( PU_MCD1_BANK0_MCD_BOT_GRP_SIZE , 13 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_GRP_SIZE ); REG64_FLD( PU_MCD1_BANK0_MCD_BOT_GRP_SIZE_LEN , 17 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_GRP_SIZE_LEN ); REG64_FLD( PU_MCD1_BANK0_MCD_BOT_GRP_BASE , 33 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_GRP_BASE ); REG64_FLD( PU_MCD1_BANK0_MCD_BOT_GRP_BASE_LEN , 31 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_GRP_BASE_LEN ); REG64_FLD( PU_BANK0_MCD_CHA_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_BANK0_MCD_CHA_CPG , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CPG ); REG64_FLD( PU_BANK0_MCD_CHA_GRP_MBR_ID , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GRP_MBR_ID ); REG64_FLD( PU_BANK0_MCD_CHA_ALWAYS_RTY , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ALWAYS_RTY ); REG64_FLD( PU_BANK0_MCD_CHA_GRP_SIZE , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GRP_SIZE ); REG64_FLD( PU_BANK0_MCD_CHA_GRP_SIZE_LEN , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GRP_SIZE_LEN ); REG64_FLD( PU_BANK0_MCD_CHA_GRP_BASE , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GRP_BASE ); REG64_FLD( PU_BANK0_MCD_CHA_GRP_BASE_LEN , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GRP_BASE_LEN ); REG64_FLD( PU_MCD1_BANK0_MCD_CHA_VALID , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_MCD1_BANK0_MCD_CHA_CPG , 1 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_CPG ); REG64_FLD( PU_MCD1_BANK0_MCD_CHA_GRP_MBR_ID , 2 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_GRP_MBR_ID ); REG64_FLD( PU_MCD1_BANK0_MCD_CHA_ALWAYS_RTY , 3 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_ALWAYS_RTY ); REG64_FLD( PU_MCD1_BANK0_MCD_CHA_GRP_SIZE , 13 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_GRP_SIZE ); REG64_FLD( PU_MCD1_BANK0_MCD_CHA_GRP_SIZE_LEN , 17 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_GRP_SIZE_LEN ); REG64_FLD( PU_MCD1_BANK0_MCD_CHA_GRP_BASE , 33 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_GRP_BASE ); REG64_FLD( PU_MCD1_BANK0_MCD_CHA_GRP_BASE_LEN , 31 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_GRP_BASE_LEN ); REG64_FLD( PU_BANK0_MCD_CMD_CHECK_CMDS , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHECK_CMDS ); REG64_FLD( PU_BANK0_MCD_CMD_CHECK_CMDS_LEN , 19 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHECK_CMDS_LEN ); REG64_FLD( PU_BANK0_MCD_CMD_CHECK_CMDS_EN , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHECK_CMDS_EN ); REG64_FLD( PU_BANK0_MCD_CMD_SET_CMDS , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SET_CMDS ); REG64_FLD( PU_BANK0_MCD_CMD_SET_CMDS_LEN , 19 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SET_CMDS_LEN ); REG64_FLD( PU_BANK0_MCD_CMD_SET_CMDS_EN , 63 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SET_CMDS_EN ); REG64_FLD( PU_MCD1_BANK0_MCD_CMD_CHECK_CMDS , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_CHECK_CMDS ); REG64_FLD( PU_MCD1_BANK0_MCD_CMD_CHECK_CMDS_LEN , 19 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_CHECK_CMDS_LEN ); REG64_FLD( PU_MCD1_BANK0_MCD_CMD_CHECK_CMDS_EN , 31 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_CHECK_CMDS_EN ); REG64_FLD( PU_MCD1_BANK0_MCD_CMD_SET_CMDS , 32 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_SET_CMDS ); REG64_FLD( PU_MCD1_BANK0_MCD_CMD_SET_CMDS_LEN , 19 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_SET_CMDS_LEN ); REG64_FLD( PU_MCD1_BANK0_MCD_CMD_SET_CMDS_EN , 63 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_SET_CMDS_EN ); REG64_FLD( PU_BANK0_MCD_REC_ENABLE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_BANK0_MCD_REC_DONE , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_DONE ); REG64_FLD( PU_BANK0_MCD_REC_CONTINUOUS , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CONTINUOUS ); REG64_FLD( PU_BANK0_MCD_REC_STATUS , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_STATUS ); REG64_FLD( PU_BANK0_MCD_REC_PACE , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PACE ); REG64_FLD( PU_BANK0_MCD_REC_PACE_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_PACE_LEN ); REG64_FLD( PU_BANK0_MCD_REC_ADDR_ERROR , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDR_ERROR ); REG64_FLD( PU_BANK0_MCD_REC_ADDR , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDR ); REG64_FLD( PU_BANK0_MCD_REC_ADDR_LEN , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDR_LEN ); REG64_FLD( PU_BANK0_MCD_REC_RTY_COUNT , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_RTY_COUNT ); REG64_FLD( PU_BANK0_MCD_REC_RTY_COUNT_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_RTY_COUNT_LEN ); REG64_FLD( PU_BANK0_MCD_REC_VG_COUNT , 49 , SH_UNT , SH_ACS_SCOM , SH_FLD_VG_COUNT ); REG64_FLD( PU_BANK0_MCD_REC_VG_COUNT_LEN , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_VG_COUNT_LEN ); REG64_FLD( PU_MCD1_BANK0_MCD_REC_ENABLE , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_MCD1_BANK0_MCD_REC_DONE , 1 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_DONE ); REG64_FLD( PU_MCD1_BANK0_MCD_REC_CONTINUOUS , 2 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_CONTINUOUS ); REG64_FLD( PU_MCD1_BANK0_MCD_REC_STATUS , 5 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_STATUS ); REG64_FLD( PU_MCD1_BANK0_MCD_REC_PACE , 8 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_PACE ); REG64_FLD( PU_MCD1_BANK0_MCD_REC_PACE_LEN , 12 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_PACE_LEN ); REG64_FLD( PU_MCD1_BANK0_MCD_REC_ADDR_ERROR , 20 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_ADDR_ERROR ); REG64_FLD( PU_MCD1_BANK0_MCD_REC_ADDR , 21 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_ADDR ); REG64_FLD( PU_MCD1_BANK0_MCD_REC_ADDR_LEN , 15 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_ADDR_LEN ); REG64_FLD( PU_MCD1_BANK0_MCD_REC_RTY_COUNT , 40 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_RTY_COUNT ); REG64_FLD( PU_MCD1_BANK0_MCD_REC_RTY_COUNT_LEN , 4 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_RTY_COUNT_LEN ); REG64_FLD( PU_MCD1_BANK0_MCD_REC_VG_COUNT , 49 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_VG_COUNT ); REG64_FLD( PU_MCD1_BANK0_MCD_REC_VG_COUNT_LEN , 15 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_VG_COUNT_LEN ); REG64_FLD( PU_BANK0_MCD_RW_RDWR_ACCESS_EN , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RDWR_ACCESS_EN ); REG64_FLD( PU_BANK0_MCD_RW_RDWR_WR_ENABLE , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_RDWR_WR_ENABLE ); REG64_FLD( PU_BANK0_MCD_RW_RDWR_REQ_PEND , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_RDWR_REQ_PEND ); REG64_FLD( PU_BANK0_MCD_RW_RDWR_READ_STATUS , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_RDWR_READ_STATUS ); REG64_FLD( PU_BANK0_MCD_RW_RDWR_WRITE_MODE , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_RDWR_WRITE_MODE ); REG64_FLD( PU_BANK0_MCD_RW_RDWR_WRITE_STATUS , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_RDWR_WRITE_STATUS ); REG64_FLD( PU_BANK0_MCD_RW_RDWR_ADDR , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_RDWR_ADDR ); REG64_FLD( PU_BANK0_MCD_RW_RDWR_ADDR_LEN , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_RDWR_ADDR_LEN ); REG64_FLD( PU_BANK0_MCD_RW_RDWR_RDWR_DATA , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_RDWR_RDWR_DATA ); REG64_FLD( PU_BANK0_MCD_RW_RDWR_RDWR_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_RDWR_RDWR_DATA_LEN ); REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_ACCESS_EN , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_RDWR_ACCESS_EN ); REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_WR_ENABLE , 1 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_RDWR_WR_ENABLE ); REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_REQ_PEND , 3 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_RDWR_REQ_PEND ); REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_READ_STATUS , 4 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_RDWR_READ_STATUS ); REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_WRITE_MODE , 5 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_RDWR_WRITE_MODE ); REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_WRITE_STATUS , 6 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_RDWR_WRITE_STATUS ); REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_ADDR , 17 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_RDWR_ADDR ); REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_ADDR_LEN , 15 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_RDWR_ADDR_LEN ); REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_RDWR_DATA , 32 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_RDWR_RDWR_DATA ); REG64_FLD( PU_MCD1_BANK0_MCD_RW_RDWR_RDWR_DATA_LEN , 32 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_RDWR_RDWR_DATA_LEN ); REG64_FLD( PU_BANK0_MCD_STR_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_BANK0_MCD_STR_CPG , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CPG ); REG64_FLD( PU_BANK0_MCD_STR_GRP_MBR_ID , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GRP_MBR_ID ); REG64_FLD( PU_BANK0_MCD_STR_ALWAYS_RTY , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ALWAYS_RTY ); REG64_FLD( PU_BANK0_MCD_STR_GRP_SIZE , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GRP_SIZE ); REG64_FLD( PU_BANK0_MCD_STR_GRP_SIZE_LEN , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GRP_SIZE_LEN ); REG64_FLD( PU_BANK0_MCD_STR_GRP_BASE , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GRP_BASE ); REG64_FLD( PU_BANK0_MCD_STR_GRP_BASE_LEN , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GRP_BASE_LEN ); REG64_FLD( PU_MCD1_BANK0_MCD_STR_VALID , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_MCD1_BANK0_MCD_STR_CPG , 1 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_CPG ); REG64_FLD( PU_MCD1_BANK0_MCD_STR_GRP_MBR_ID , 2 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_GRP_MBR_ID ); REG64_FLD( PU_MCD1_BANK0_MCD_STR_ALWAYS_RTY , 3 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_ALWAYS_RTY ); REG64_FLD( PU_MCD1_BANK0_MCD_STR_GRP_SIZE , 13 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_GRP_SIZE ); REG64_FLD( PU_MCD1_BANK0_MCD_STR_GRP_SIZE_LEN , 17 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_GRP_SIZE_LEN ); REG64_FLD( PU_MCD1_BANK0_MCD_STR_GRP_BASE , 33 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_GRP_BASE ); REG64_FLD( PU_MCD1_BANK0_MCD_STR_GRP_BASE_LEN , 31 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_GRP_BASE_LEN ); REG64_FLD( PU_BANK0_MCD_TOP_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_BANK0_MCD_TOP_CPG , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CPG ); REG64_FLD( PU_BANK0_MCD_TOP_GRP_MBR_ID , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GRP_MBR_ID ); REG64_FLD( PU_BANK0_MCD_TOP_ALWAYS_RTY , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ALWAYS_RTY ); REG64_FLD( PU_BANK0_MCD_TOP_GRP_SIZE , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GRP_SIZE ); REG64_FLD( PU_BANK0_MCD_TOP_GRP_SIZE_LEN , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GRP_SIZE_LEN ); REG64_FLD( PU_BANK0_MCD_TOP_GRP_BASE , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GRP_BASE ); REG64_FLD( PU_BANK0_MCD_TOP_GRP_BASE_LEN , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GRP_BASE_LEN ); REG64_FLD( PU_MCD1_BANK0_MCD_TOP_VALID , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_MCD1_BANK0_MCD_TOP_CPG , 1 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_CPG ); REG64_FLD( PU_MCD1_BANK0_MCD_TOP_GRP_MBR_ID , 2 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_GRP_MBR_ID ); REG64_FLD( PU_MCD1_BANK0_MCD_TOP_ALWAYS_RTY , 3 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_ALWAYS_RTY ); REG64_FLD( PU_MCD1_BANK0_MCD_TOP_GRP_SIZE , 13 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_GRP_SIZE ); REG64_FLD( PU_MCD1_BANK0_MCD_TOP_GRP_SIZE_LEN , 17 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_GRP_SIZE_LEN ); REG64_FLD( PU_MCD1_BANK0_MCD_TOP_GRP_BASE , 33 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_GRP_BASE ); REG64_FLD( PU_MCD1_BANK0_MCD_TOP_GRP_BASE_LEN , 31 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_GRP_BASE_LEN ); REG64_FLD( PU_BANK0_MCD_VGC_AVAIL_GROUPS , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_AVAIL_GROUPS ); REG64_FLD( PU_BANK0_MCD_VGC_AVAIL_GROUPS_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_AVAIL_GROUPS_LEN ); REG64_FLD( PU_BANK0_MCD_VGC_4X4_MODE , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_4X4_MODE ); REG64_FLD( PU_BANK0_MCD_VGC_HANG_POLL_ENABLE , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HANG_POLL_ENABLE ); REG64_FLD( PU_BANK0_MCD_VGC_RND_BACKOFF_ENABLE , 34 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RND_BACKOFF_ENABLE ); REG64_FLD( PU_BANK0_MCD_VGC_DROP_PRIORITY_MODE , 35 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DROP_PRIORITY_MODE ); REG64_FLD( PU_BANK0_MCD_VGC_MASK_AGV_DISABLE_MODE , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MASK_AGV_DISABLE_MODE ); REG64_FLD( PU_BANK0_MCD_VGC_XLATE_TO_ADDR_ID_ENABLE , 37 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_XLATE_TO_ADDR_ID_ENABLE ); REG64_FLD( PU_MCD1_BANK0_MCD_VGC_AVAIL_GROUPS , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_AVAIL_GROUPS ); REG64_FLD( PU_MCD1_BANK0_MCD_VGC_AVAIL_GROUPS_LEN , 16 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_AVAIL_GROUPS_LEN ); REG64_FLD( PU_MCD1_BANK0_MCD_VGC_4X4_MODE , 32 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_4X4_MODE ); REG64_FLD( PU_MCD1_BANK0_MCD_VGC_HANG_POLL_ENABLE , 33 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_HANG_POLL_ENABLE ); REG64_FLD( PU_MCD1_BANK0_MCD_VGC_RND_BACKOFF_ENABLE , 34 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_RND_BACKOFF_ENABLE ); REG64_FLD( PU_MCD1_BANK0_MCD_VGC_DROP_PRIORITY_MODE , 35 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_DROP_PRIORITY_MODE ); REG64_FLD( PU_MCD1_BANK0_MCD_VGC_MASK_AGV_DISABLE_MODE , 36 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_MASK_AGV_DISABLE_MODE ); REG64_FLD( PU_MCD1_BANK0_MCD_VGC_XLATE_TO_ADDR_ID_ENABLE , 37 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_XLATE_TO_ADDR_ID_ENABLE ); REG64_FLD( PEC_STACK2_BARE_REG_PE_MMIO_BAR0_EN , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , SH_FLD_PE_MMIO_BAR0_EN ); REG64_FLD( PEC_STACK2_BARE_REG_PE_MMIO_BAR1_EN , 1 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , SH_FLD_PE_MMIO_BAR1_EN ); REG64_FLD( PEC_STACK2_BARE_REG_PE_PHB_BAR_EN , 2 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , SH_FLD_PE_PHB_BAR_EN ); REG64_FLD( PEC_STACK2_BARE_REG_PE_INT_BAR_EN , 3 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , SH_FLD_PE_INT_BAR_EN ); REG64_FLD( PEC_STACK1_BARE_REG_PE_MMIO_BAR0_EN , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , SH_FLD_PE_MMIO_BAR0_EN ); REG64_FLD( PEC_STACK1_BARE_REG_PE_MMIO_BAR1_EN , 1 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , SH_FLD_PE_MMIO_BAR1_EN ); REG64_FLD( PEC_STACK1_BARE_REG_PE_PHB_BAR_EN , 2 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , SH_FLD_PE_PHB_BAR_EN ); REG64_FLD( PEC_STACK1_BARE_REG_PE_INT_BAR_EN , 3 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , SH_FLD_PE_INT_BAR_EN ); REG64_FLD( PHB_BARE_REG_PE_MMIO_BAR0_EN , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_PE_MMIO_BAR0_EN ); REG64_FLD( PHB_BARE_REG_PE_MMIO_BAR1_EN , 1 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_PE_MMIO_BAR1_EN ); REG64_FLD( PHB_BARE_REG_PE_PHB_BAR_EN , 2 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_PE_PHB_BAR_EN ); REG64_FLD( PHB_BARE_REG_PE_INT_BAR_EN , 3 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_PE_INT_BAR_EN ); REG64_FLD( PEC_STACK0_BARE_REG_PE_MMIO_BAR0_EN , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , SH_FLD_PE_MMIO_BAR0_EN ); REG64_FLD( PEC_STACK0_BARE_REG_PE_MMIO_BAR1_EN , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , SH_FLD_PE_MMIO_BAR1_EN ); REG64_FLD( PEC_STACK0_BARE_REG_PE_PHB_BAR_EN , 2 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , SH_FLD_PE_PHB_BAR_EN ); REG64_FLD( PEC_STACK0_BARE_REG_PE_INT_BAR_EN , 3 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , SH_FLD_PE_INT_BAR_EN ); REG64_FLD( PU_BCDE_CTL_STOP , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_STOP ); REG64_FLD( PU_BCDE_CTL_START , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_START ); REG64_FLD( PU_BCDE_OCIBAR_ADDR , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_ADDR ); REG64_FLD( PU_BCDE_OCIBAR_ADDR_LEN , 25 , SH_UNT , SH_ACS_PIB , SH_FLD_ADDR_LEN ); REG64_FLD( PU_BCDE_PBADR_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_1 ); REG64_FLD( PU_BCDE_PBADR_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_1_LEN ); REG64_FLD( PU_BCDE_PBADR_PB_OFFSET , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_PB_OFFSET ); REG64_FLD( PU_BCDE_PBADR_PB_OFFSET_LEN , 23 , SH_UNT , SH_ACS_PIB , SH_FLD_PB_OFFSET_LEN ); REG64_FLD( PU_BCDE_PBADR_RESERVED_25_26 , 25 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_25_26 ); REG64_FLD( PU_BCDE_PBADR_RESERVED_25_26_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_25_26_LEN ); REG64_FLD( PU_BCDE_PBADR_EXTADDR , 27 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR ); REG64_FLD( PU_BCDE_PBADR_EXTADDR_LEN , 14 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR_LEN ); REG64_FLD( PU_BCDE_PBADR_RESERVED_41_42 , 41 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_41_42 ); REG64_FLD( PU_BCDE_PBADR_RESERVED_41_42_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_41_42_LEN ); REG64_FLD( PU_BCDE_SET_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_1 ); REG64_FLD( PU_BCDE_SET_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_1_LEN ); REG64_FLD( PU_BCDE_SET_COPY_LENGTH , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_COPY_LENGTH ); REG64_FLD( PU_BCDE_SET_COPY_LENGTH_LEN , 6 , SH_UNT , SH_ACS_PIB , SH_FLD_COPY_LENGTH_LEN ); REG64_FLD( PU_BCDE_STAT_RUNNING , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_RUNNING ); REG64_FLD( PU_BCDE_STAT_WAITING , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_WAITING ); REG64_FLD( PU_BCDE_STAT_WRCMP , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_WRCMP ); REG64_FLD( PU_BCDE_STAT_WRCMP_LEN , 6 , SH_UNT , SH_ACS_PIB , SH_FLD_WRCMP_LEN ); REG64_FLD( PU_BCDE_STAT_RDCMP , 14 , SH_UNT , SH_ACS_PIB , SH_FLD_RDCMP ); REG64_FLD( PU_BCDE_STAT_RDCMP_LEN , 6 , SH_UNT , SH_ACS_PIB , SH_FLD_RDCMP_LEN ); REG64_FLD( PU_BCDE_STAT_DEBUG , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_DEBUG ); REG64_FLD( PU_BCDE_STAT_DEBUG_LEN , 9 , SH_UNT , SH_ACS_PIB , SH_FLD_DEBUG_LEN ); REG64_FLD( PU_BCDE_STAT_STOPPED , 29 , SH_UNT , SH_ACS_PIB , SH_FLD_STOPPED ); REG64_FLD( PU_BCDE_STAT_ERROR , 30 , SH_UNT , SH_ACS_PIB , SH_FLD_ERROR ); REG64_FLD( PU_BCDE_STAT_DONE , 31 , SH_UNT , SH_ACS_PIB , SH_FLD_DONE ); REG64_FLD( PU_BCUE_CTL_STOP , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_STOP ); REG64_FLD( PU_BCUE_CTL_START , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_START ); REG64_FLD( PU_BCUE_OCIBAR_ADDR , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_ADDR ); REG64_FLD( PU_BCUE_OCIBAR_ADDR_LEN , 25 , SH_UNT , SH_ACS_PIB , SH_FLD_ADDR_LEN ); REG64_FLD( PU_BCUE_PBADR_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_1 ); REG64_FLD( PU_BCUE_PBADR_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_1_LEN ); REG64_FLD( PU_BCUE_PBADR_PB_OFFSET , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_PB_OFFSET ); REG64_FLD( PU_BCUE_PBADR_PB_OFFSET_LEN , 23 , SH_UNT , SH_ACS_PIB , SH_FLD_PB_OFFSET_LEN ); REG64_FLD( PU_BCUE_PBADR_RESERVED_25_26 , 25 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_25_26 ); REG64_FLD( PU_BCUE_PBADR_RESERVED_25_26_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_25_26_LEN ); REG64_FLD( PU_BCUE_PBADR_EXTADDR , 27 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR ); REG64_FLD( PU_BCUE_PBADR_EXTADDR_LEN , 14 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR_LEN ); REG64_FLD( PU_BCUE_PBADR_RESERVED_41_42 , 41 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_41_42 ); REG64_FLD( PU_BCUE_PBADR_RESERVED_41_42_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_41_42_LEN ); REG64_FLD( PU_BCUE_SET_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_1 ); REG64_FLD( PU_BCUE_SET_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_1_LEN ); REG64_FLD( PU_BCUE_SET_COPY_LENGTH , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_COPY_LENGTH ); REG64_FLD( PU_BCUE_SET_COPY_LENGTH_LEN , 6 , SH_UNT , SH_ACS_PIB , SH_FLD_COPY_LENGTH_LEN ); REG64_FLD( PU_BCUE_STAT_RUNNING , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_RUNNING ); REG64_FLD( PU_BCUE_STAT_WAITING , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_WAITING ); REG64_FLD( PU_BCUE_STAT_WRCMP , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_WRCMP ); REG64_FLD( PU_BCUE_STAT_WRCMP_LEN , 6 , SH_UNT , SH_ACS_PIB , SH_FLD_WRCMP_LEN ); REG64_FLD( PU_BCUE_STAT_RDCMP , 14 , SH_UNT , SH_ACS_PIB , SH_FLD_RDCMP ); REG64_FLD( PU_BCUE_STAT_RDCMP_LEN , 6 , SH_UNT , SH_ACS_PIB , SH_FLD_RDCMP_LEN ); REG64_FLD( PU_BCUE_STAT_DEBUG , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_DEBUG ); REG64_FLD( PU_BCUE_STAT_DEBUG_LEN , 9 , SH_UNT , SH_ACS_PIB , SH_FLD_DEBUG_LEN ); REG64_FLD( PU_BCUE_STAT_STOPPED , 29 , SH_UNT , SH_ACS_PIB , SH_FLD_STOPPED ); REG64_FLD( PU_BCUE_STAT_ERROR , 30 , SH_UNT , SH_ACS_PIB , SH_FLD_ERROR ); REG64_FLD( PU_BCUE_STAT_DONE , 31 , SH_UNT , SH_ACS_PIB , SH_FLD_DONE ); REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_WILDCARD , 1 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_WILDCARD ); REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_RESERVED , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_RESERVED_LEN , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_PE , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_BDF , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU1_CTL_BDF2PE_00_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU_BDF2PE_00_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU_BDF2PE_00_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU_BDF2PE_00_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU_BDF2PE_00_CONFIG_PE , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU_BDF2PE_00_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU_BDF2PE_00_CONFIG_BDF , 8 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU_BDF2PE_00_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_WILDCARD , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_WILDCARD ); REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_RESERVED , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_RESERVED_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_PE , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_BDF , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU0_CTL_BDF2PE_00_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_WILDCARD , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_WILDCARD ); REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_RESERVED , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_RESERVED_LEN , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_PE , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_BDF , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU2_CTL_BDF2PE_00_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU1_CTL_BDF2PE_01_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU1_CTL_BDF2PE_01_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU1_CTL_BDF2PE_01_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU1_CTL_BDF2PE_01_CONFIG_PE , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU1_CTL_BDF2PE_01_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU1_CTL_BDF2PE_01_CONFIG_BDF , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU1_CTL_BDF2PE_01_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU_BDF2PE_01_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU_BDF2PE_01_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU_BDF2PE_01_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU_BDF2PE_01_CONFIG_PE , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU_BDF2PE_01_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU_BDF2PE_01_CONFIG_BDF , 8 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU_BDF2PE_01_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU0_CTL_BDF2PE_01_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU0_CTL_BDF2PE_01_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU0_CTL_BDF2PE_01_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_CTL_BDF2PE_01_CONFIG_PE , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU0_CTL_BDF2PE_01_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU0_CTL_BDF2PE_01_CONFIG_BDF , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU0_CTL_BDF2PE_01_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU2_CTL_BDF2PE_01_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU2_CTL_BDF2PE_01_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU2_CTL_BDF2PE_01_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_CTL_BDF2PE_01_CONFIG_PE , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU2_CTL_BDF2PE_01_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU2_CTL_BDF2PE_01_CONFIG_BDF , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU2_CTL_BDF2PE_01_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU1_CTL_BDF2PE_02_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU1_CTL_BDF2PE_02_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU1_CTL_BDF2PE_02_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU1_CTL_BDF2PE_02_CONFIG_PE , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU1_CTL_BDF2PE_02_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU1_CTL_BDF2PE_02_CONFIG_BDF , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU1_CTL_BDF2PE_02_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU_BDF2PE_02_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU_BDF2PE_02_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU_BDF2PE_02_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU_BDF2PE_02_CONFIG_PE , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU_BDF2PE_02_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU_BDF2PE_02_CONFIG_BDF , 8 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU_BDF2PE_02_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU0_CTL_BDF2PE_02_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU0_CTL_BDF2PE_02_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU0_CTL_BDF2PE_02_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_CTL_BDF2PE_02_CONFIG_PE , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU0_CTL_BDF2PE_02_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU0_CTL_BDF2PE_02_CONFIG_BDF , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU0_CTL_BDF2PE_02_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_PE , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_BDF , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU2_CTL_BDF2PE_02_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_WILDCARD , 1 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_WILDCARD ); REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_RESERVED , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_RESERVED_LEN , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_PE , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_BDF , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU1_CTL_BDF2PE_10_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU_BDF2PE_10_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU_BDF2PE_10_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU_BDF2PE_10_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU_BDF2PE_10_CONFIG_PE , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU_BDF2PE_10_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU_BDF2PE_10_CONFIG_BDF , 8 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU_BDF2PE_10_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_WILDCARD , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_WILDCARD ); REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_RESERVED , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_RESERVED_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_PE , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_BDF , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU0_CTL_BDF2PE_10_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_WILDCARD , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_WILDCARD ); REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_RESERVED , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_RESERVED_LEN , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_PE , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_BDF , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU2_CTL_BDF2PE_10_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU1_CTL_BDF2PE_11_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU1_CTL_BDF2PE_11_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU1_CTL_BDF2PE_11_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU1_CTL_BDF2PE_11_CONFIG_PE , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU1_CTL_BDF2PE_11_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU1_CTL_BDF2PE_11_CONFIG_BDF , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU1_CTL_BDF2PE_11_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU_BDF2PE_11_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU_BDF2PE_11_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU_BDF2PE_11_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU_BDF2PE_11_CONFIG_PE , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU_BDF2PE_11_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU_BDF2PE_11_CONFIG_BDF , 8 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU_BDF2PE_11_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU0_CTL_BDF2PE_11_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU0_CTL_BDF2PE_11_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU0_CTL_BDF2PE_11_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_CTL_BDF2PE_11_CONFIG_PE , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU0_CTL_BDF2PE_11_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU0_CTL_BDF2PE_11_CONFIG_BDF , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU0_CTL_BDF2PE_11_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU2_CTL_BDF2PE_11_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU2_CTL_BDF2PE_11_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU2_CTL_BDF2PE_11_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_CTL_BDF2PE_11_CONFIG_PE , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU2_CTL_BDF2PE_11_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU2_CTL_BDF2PE_11_CONFIG_BDF , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU2_CTL_BDF2PE_11_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU1_CTL_BDF2PE_12_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU1_CTL_BDF2PE_12_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU1_CTL_BDF2PE_12_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU1_CTL_BDF2PE_12_CONFIG_PE , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU1_CTL_BDF2PE_12_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU1_CTL_BDF2PE_12_CONFIG_BDF , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU1_CTL_BDF2PE_12_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU_BDF2PE_12_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU_BDF2PE_12_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU_BDF2PE_12_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU_BDF2PE_12_CONFIG_PE , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU_BDF2PE_12_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU_BDF2PE_12_CONFIG_BDF , 8 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU_BDF2PE_12_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU0_CTL_BDF2PE_12_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU0_CTL_BDF2PE_12_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU0_CTL_BDF2PE_12_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_CTL_BDF2PE_12_CONFIG_PE , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU0_CTL_BDF2PE_12_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU0_CTL_BDF2PE_12_CONFIG_BDF , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU0_CTL_BDF2PE_12_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU2_CTL_BDF2PE_12_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU2_CTL_BDF2PE_12_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU2_CTL_BDF2PE_12_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_CTL_BDF2PE_12_CONFIG_PE , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU2_CTL_BDF2PE_12_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU2_CTL_BDF2PE_12_CONFIG_BDF , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU2_CTL_BDF2PE_12_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU_BDF2PE_20_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU_BDF2PE_20_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU_BDF2PE_20_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU_BDF2PE_20_CONFIG_PE , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU_BDF2PE_20_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU_BDF2PE_20_CONFIG_BDF , 8 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU_BDF2PE_20_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU_BDF2PE_21_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU_BDF2PE_21_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU_BDF2PE_21_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU_BDF2PE_21_CONFIG_PE , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU_BDF2PE_21_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU_BDF2PE_21_CONFIG_BDF , 8 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU_BDF2PE_21_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU_BDF2PE_22_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU_BDF2PE_22_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU_BDF2PE_22_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU_BDF2PE_22_CONFIG_PE , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU_BDF2PE_22_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU_BDF2PE_22_CONFIG_BDF , 8 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU_BDF2PE_22_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU_BDF2PE_30_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU_BDF2PE_30_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU_BDF2PE_30_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU_BDF2PE_30_CONFIG_PE , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU_BDF2PE_30_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU_BDF2PE_30_CONFIG_BDF , 8 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU_BDF2PE_30_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU_BDF2PE_31_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU_BDF2PE_31_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU_BDF2PE_31_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU_BDF2PE_31_CONFIG_PE , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU_BDF2PE_31_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU_BDF2PE_31_CONFIG_BDF , 8 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU_BDF2PE_31_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU_BDF2PE_32_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU_BDF2PE_32_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU_BDF2PE_32_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU_BDF2PE_32_CONFIG_PE , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU_BDF2PE_32_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU_BDF2PE_32_CONFIG_BDF , 8 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU_BDF2PE_32_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU_BDF2PE_40_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU_BDF2PE_40_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU_BDF2PE_40_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU_BDF2PE_40_CONFIG_PE , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU_BDF2PE_40_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU_BDF2PE_40_CONFIG_BDF , 8 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU_BDF2PE_40_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU_BDF2PE_41_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU_BDF2PE_41_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU_BDF2PE_41_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU_BDF2PE_41_CONFIG_PE , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU_BDF2PE_41_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU_BDF2PE_41_CONFIG_BDF , 8 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU_BDF2PE_41_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU_BDF2PE_42_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU_BDF2PE_42_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU_BDF2PE_42_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU_BDF2PE_42_CONFIG_PE , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU_BDF2PE_42_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU_BDF2PE_42_CONFIG_BDF , 8 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU_BDF2PE_42_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU_BDF2PE_50_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU_BDF2PE_50_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU_BDF2PE_50_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU_BDF2PE_50_CONFIG_PE , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU_BDF2PE_50_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU_BDF2PE_50_CONFIG_BDF , 8 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU_BDF2PE_50_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU , SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU_DAT_BDF2PE_51_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU_DAT_BDF2PE_51_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU_DAT_BDF2PE_51_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU_DAT_BDF2PE_51_CONFIG_PE , 4 , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU_DAT_BDF2PE_51_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU_DAT_BDF2PE_51_CONFIG_BDF , 8 , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU_DAT_BDF2PE_51_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PU_NPU_DAT_BDF2PE_52_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU_DAT_BDF2PE_52_CONFIG_RESERVED , 1 , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU_DAT_BDF2PE_52_CONFIG_RESERVED_LEN , 3 , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU_DAT_BDF2PE_52_CONFIG_PE , 4 , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU_DAT_BDF2PE_52_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU_DAT_BDF2PE_52_CONFIG_BDF , 8 , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM , SH_FLD_BDF ); REG64_FLD( PU_NPU_DAT_BDF2PE_52_CONFIG_BDF_LEN , 16 , SH_UNT_PU_NPU_DAT, SH_ACS_SCOM , SH_FLD_BDF_LEN ); REG64_FLD( PEC_BIST_TC_START_TEST_DC , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TC_START_TEST_DC ); REG64_FLD( PEC_BIST_TC_SRAM_ABIST_MODE_DC , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TC_SRAM_ABIST_MODE_DC ); REG64_FLD( PEC_BIST_TC_EDRAM_ABIST_MODE_DC , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TC_EDRAM_ABIST_MODE_DC ); REG64_FLD( PEC_BIST_TC_IOBIST_MODE_DC , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TC_IOBIST_MODE_DC ); REG64_FLD( PEC_BIST_PERV , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PERV ); REG64_FLD( PEC_BIST_UNIT1 , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT1 ); REG64_FLD( PEC_BIST_UNIT2 , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT2 ); REG64_FLD( PEC_BIST_UNIT3 , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT3 ); REG64_FLD( PEC_BIST_UNIT4 , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT4 ); REG64_FLD( PEC_BIST_UNIT5 , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT5 ); REG64_FLD( PEC_BIST_UNIT6 , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT6 ); REG64_FLD( PEC_BIST_UNIT7 , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT7 ); REG64_FLD( PEC_BIST_UNIT8 , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT8 ); REG64_FLD( PEC_BIST_UNIT9 , 13 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT9 ); REG64_FLD( PEC_BIST_UNIT10 , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT10 ); REG64_FLD( PEC_BIST_STROBE_WINDOW_EN , 48 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STROBE_WINDOW_EN ); REG64_FLD( CAPP_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL_TIMER_ENABLE , 1 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TIMER_ENABLE ); REG64_FLD( CAPP_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL_TIMER_PERIOD_MASK , 48 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TIMER_PERIOD_MASK ); REG64_FLD( CAPP_CAPP_EPOCH_AND_RECOVERY_TMR_CONTROL_TIMER_PERIOD_MASK_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TIMER_PERIOD_MASK_LEN ); REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_ERROR_RECOVERY_INITIATED , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_ERROR_RECOVERY_INITIATED ); REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_ERROR_RECOVERY_COMPLETE , 1 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_ERROR_RECOVERY_COMPLETE ); REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_TLBI_PSL_DEAD , 3 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TLBI_PSL_DEAD ); REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_TLBI_FENCE , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TLBI_FENCE ); REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_RECOVERY_FAILED , 5 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_RECOVERY_FAILED ); REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_RTAGFLUSH_FAILED , 6 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_RTAGFLUSH_FAILED ); REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_PRECISE_DIR_FLUSH_FAILED , 7 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PRECISE_DIR_FLUSH_FAILED ); REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_COURSE_DIR_FLUSH_FAILED , 8 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_COURSE_DIR_FLUSH_FAILED ); REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_RECOVERY_HANG_DETECTED , 9 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_RECOVERY_HANG_DETECTED ); REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_EPOCH_VALUE , 10 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_EPOCH_VALUE ); REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_EPOCH_VALUE_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_EPOCH_VALUE_LEN ); REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_FORCE_QUIESCE , 14 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_FORCE_QUIESCE ); REG64_FLD( CAPP_CAPP_ERR_STATUS_CONTROL_QUIESCE_DONE , 15 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_QUIESCE_DONE ); REG64_FLD( PEC_CC_ATOMIC_LOCK_REG_ENABLE , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PEC_CC_ATOMIC_LOCK_REG_ID , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ID ); REG64_FLD( PEC_CC_ATOMIC_LOCK_REG_ID_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ID_LEN ); REG64_FLD( PEC_CC_ATOMIC_LOCK_REG_ACTIVITY , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACTIVITY ); REG64_FLD( PEC_CC_ATOMIC_LOCK_REG_ACTIVITY_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACTIVITY_LEN ); REG64_FLD( PEC_CC_PROTECT_MODE_REG_READ_ENABLE , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_READ_ENABLE ); REG64_FLD( PEC_CC_PROTECT_MODE_REG_WRITE_ENABLE , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_WRITE_ENABLE ); REG64_FLD( PU_NPU0_CERR_ECC_FIRST_BITS , 10 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU0_CERR_ECC_FIRST_BITS_LEN , 54 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); REG64_FLD( PU_NPU1_CERR_ECC_FIRST_BITS , 10 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU1_CERR_ECC_FIRST_BITS_LEN , 54 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); REG64_FLD( PU_NPU2_CERR_ECC_FIRST_BITS , 10 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU2_CERR_ECC_FIRST_BITS_LEN , 54 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PT_UE , 10 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_PT_UE ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PT_UE_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_PT_UE_LEN ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PR_UE , 14 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_PR_UE ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PR_UE_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_PR_UE_LEN ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_BR_UE , 18 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_BR_UE ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_BR_UE_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_BR_UE_LEN ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_IR_UE , 20 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_IR_UE ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_IR_UE_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_IR_UE_LEN ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_OR_UE , 24 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_OR_UE ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_OR_UE_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_OR_UE_LEN ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PT_SUE , 28 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_PT_SUE ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PT_SUE_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_PT_SUE_LEN ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PR_SUE , 32 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_PR_SUE ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PR_SUE_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_PR_SUE_LEN ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_BR_SUE , 36 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_BR_SUE ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_BR_SUE_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_BR_SUE_LEN ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_IR_SUE , 38 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_IR_SUE ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_IR_SUE_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_IR_SUE_LEN ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_OR_SUE , 42 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_OR_SUE ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_OR_SUE_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_OR_SUE_LEN ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PT_CE , 46 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_PT_CE ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PT_CE_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_PT_CE_LEN ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PR_CE , 50 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_PR_CE ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_PR_CE_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_PR_CE_LEN ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_BR_CE , 54 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_BR_CE ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_BR_CE_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_BR_CE_LEN ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_IR_CE , 56 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_IR_CE ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_IR_CE_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_IR_CE_LEN ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_OR_CE , 60 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_OR_CE ); REG64_FLD( PU_NPU0_CERR_ECC_HOLD_IDIAL_OR_CE_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_OR_CE_LEN ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PT_UE , 10 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_PT_UE ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PT_UE_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_PT_UE_LEN ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PR_UE , 14 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_PR_UE ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PR_UE_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_PR_UE_LEN ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_BR_UE , 18 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_BR_UE ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_BR_UE_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_BR_UE_LEN ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_IR_UE , 20 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_IR_UE ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_IR_UE_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_IR_UE_LEN ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_OR_UE , 24 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_OR_UE ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_OR_UE_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_OR_UE_LEN ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PT_SUE , 28 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_PT_SUE ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PT_SUE_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_PT_SUE_LEN ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PR_SUE , 32 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_PR_SUE ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PR_SUE_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_PR_SUE_LEN ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_BR_SUE , 36 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_BR_SUE ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_BR_SUE_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_BR_SUE_LEN ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_IR_SUE , 38 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_IR_SUE ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_IR_SUE_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_IR_SUE_LEN ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_OR_SUE , 42 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_OR_SUE ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_OR_SUE_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_OR_SUE_LEN ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PT_CE , 46 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_PT_CE ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PT_CE_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_PT_CE_LEN ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PR_CE , 50 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_PR_CE ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_PR_CE_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_PR_CE_LEN ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_BR_CE , 54 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_BR_CE ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_BR_CE_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_BR_CE_LEN ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_IR_CE , 56 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_IR_CE ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_IR_CE_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_IR_CE_LEN ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_OR_CE , 60 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_OR_CE ); REG64_FLD( PU_NPU1_CERR_ECC_HOLD_IDIAL_OR_CE_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_OR_CE_LEN ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PT_UE , 10 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_PT_UE ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PT_UE_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_PT_UE_LEN ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PR_UE , 14 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_PR_UE ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PR_UE_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_PR_UE_LEN ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_BR_UE , 18 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_BR_UE ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_BR_UE_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_BR_UE_LEN ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_IR_UE , 20 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_IR_UE ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_IR_UE_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_IR_UE_LEN ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_OR_UE , 24 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_OR_UE ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_OR_UE_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_OR_UE_LEN ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PT_SUE , 28 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_PT_SUE ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PT_SUE_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_PT_SUE_LEN ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PR_SUE , 32 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_PR_SUE ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PR_SUE_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_PR_SUE_LEN ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_BR_SUE , 36 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_BR_SUE ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_BR_SUE_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_BR_SUE_LEN ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_IR_SUE , 38 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_IR_SUE ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_IR_SUE_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_IR_SUE_LEN ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_OR_SUE , 42 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_OR_SUE ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_OR_SUE_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_OR_SUE_LEN ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PT_CE , 46 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_PT_CE ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PT_CE_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_PT_CE_LEN ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PR_CE , 50 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_PR_CE ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_PR_CE_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_PR_CE_LEN ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_BR_CE , 54 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_BR_CE ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_BR_CE_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_BR_CE_LEN ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_IR_CE , 56 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_IR_CE ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_IR_CE_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_IR_CE_LEN ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_OR_CE , 60 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_OR_CE ); REG64_FLD( PU_NPU2_CERR_ECC_HOLD_IDIAL_OR_CE_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_OR_CE_LEN ); REG64_FLD( PU_NPU0_CERR_ECC_MASK_BITS , 10 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU0_CERR_ECC_MASK_BITS_LEN , 54 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); REG64_FLD( PU_NPU1_CERR_ECC_MASK_BITS , 10 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU1_CERR_ECC_MASK_BITS_LEN , 54 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); REG64_FLD( PU_NPU2_CERR_ECC_MASK_BITS , 10 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU2_CERR_ECC_MASK_BITS_LEN , 54 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_24 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_25 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_26 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_27 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_28 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_29 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_30 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_31 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_0 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_1 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_2 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_3 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_4 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_5 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_6 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_7 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_4 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_5 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_0 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_1 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_2 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_24 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_25 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_26 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_27 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_28 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_29 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_30 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_31 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_0 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_1 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_2 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_3 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_4 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_5 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_6 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_7 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_4 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_5 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_0 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_1 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_2 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_24 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_25 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_26 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_27 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_28 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_29 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_30 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_31 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_0 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_1 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_2 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_3 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_4 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_5 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_6 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_7 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_4 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_5 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_0 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_1 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_2 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_24 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_25 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_26 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_27 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_28 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_29 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_30 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_31 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_0 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_1 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_2 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_3 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_4 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_5 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_6 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_7 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_4 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_5 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_0 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_1 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_2 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_24 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_25 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_26 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_27 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_28 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_29 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_30 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_31 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_0 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_1 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_2 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_3 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_4 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_5 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_6 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_7 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_4 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_5 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_0 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_1 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_2 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_24 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_25 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_26 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_27 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_28 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_29 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_30 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_31 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_0 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_1 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_2 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_3 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_4 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_5 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_6 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_7 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_4 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_5 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_0 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_1 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_2 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_24 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_25 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_26 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_27 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_28 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_29 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_30 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_31 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_0 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_1 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_2 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_3 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_4 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_5 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_6 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_7 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_4 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_5 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_0 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_1 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_2 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_0 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_1 , 1 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_1 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_2 , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_2 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_3 , 3 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_3 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_4 , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_4 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_5 , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_5 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_6 , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_6 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_7 , 7 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_7 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_0 , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_0 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_1 , 9 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_1 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_2 , 10 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_2 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_3 , 11 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_3 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_4 , 12 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_4 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_5 , 13 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_5 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_6 , 14 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_6 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_7 , 15 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_7 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_8 , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_8 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_9 , 17 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_9 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_10 , 18 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_10 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_11 , 19 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_11 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_12 , 20 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_12 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_13 , 21 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_13 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_14 , 22 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_14 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_15 , 23 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_15 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_16 , 24 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_16 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_17 , 25 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_17 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_18 , 26 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_18 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_19 , 27 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_19 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_20 , 28 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_20 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_21 , 29 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_21 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_22 , 30 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_22 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_23 , 31 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_23 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_0 , 32 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV1_0 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_1 , 33 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV1_1 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_2 , 34 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV1_2 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_3 , 35 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV1_3 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_0 , 36 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_0 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_1 , 37 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_1 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_2 , 38 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_2 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_3 , 39 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_3 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_4 , 40 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_4 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_5 , 41 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_5 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_6 , 42 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_6 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_7 , 43 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_7 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_0 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_1 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_2 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_3 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_4 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_5 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_6 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_7 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_0 , 52 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_REG_0 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_1 , 53 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_REG_1 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_2 , 54 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_REG_2 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_3 , 55 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_REG_3 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_0 , 56 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_DUE_0 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_1 , 57 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_DUE_1 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_2 , 58 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_DUE_2 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_3 , 59 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_DUE_3 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_0 , 60 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PEF_0 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_1 , 61 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PEF_1 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_2 , 62 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PEF_2 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_3 , 63 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PEF_3 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_24 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_25 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_26 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_27 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_28 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_29 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_30 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_31 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_0 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_1 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_2 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_3 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_4 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_5 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_6 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_7 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_4 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_5 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_0 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_1 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_2 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_24 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_25 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_26 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_27 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_28 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_29 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_30 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_31 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_0 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_1 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_2 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_3 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_4 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_5 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_6 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_7 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_4 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_5 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_0 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_1 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_2 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_24 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_25 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_26 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_27 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_28 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_29 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_30 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_31 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_0 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_1 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_2 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_3 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_4 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_5 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_6 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_7 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_4 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_5 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_0 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_1 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_2 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_0 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_1 , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_1 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_2 , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_2 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_3 , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_3 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_4 , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_4 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_5 , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_5 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_6 , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_6 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_7 , 7 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_7 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_0 , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_0 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_1 , 9 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_1 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_2 , 10 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_2 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_3 , 11 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_3 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_4 , 12 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_4 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_5 , 13 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_5 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_6 , 14 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_6 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_7 , 15 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_7 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_8 , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_8 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_9 , 17 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_9 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_10 , 18 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_10 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_11 , 19 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_11 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_12 , 20 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_12 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_13 , 21 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_13 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_14 , 22 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_14 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_15 , 23 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_15 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_16 , 24 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_16 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_17 , 25 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_17 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_18 , 26 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_18 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_19 , 27 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_19 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_20 , 28 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_20 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_21 , 29 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_21 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_22 , 30 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_22 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_23 , 31 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_23 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_0 , 32 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV1_0 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_1 , 33 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV1_1 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_2 , 34 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV1_2 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_3 , 35 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV1_3 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_0 , 36 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_0 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_1 , 37 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_1 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_2 , 38 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_2 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_3 , 39 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_3 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_4 , 40 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_4 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_5 , 41 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_5 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_6 , 42 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_6 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_7 , 43 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_7 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_0 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_1 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_2 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_3 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_4 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_5 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_6 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_7 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_0 , 52 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_REG_0 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_1 , 53 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_REG_1 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_2 , 54 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_REG_2 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_3 , 55 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_REG_3 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_0 , 56 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_DUE_0 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_1 , 57 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_DUE_1 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_2 , 58 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_DUE_2 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_3 , 59 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_DUE_3 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_0 , 60 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PEF_0 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_1 , 61 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PEF_1 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_2 , 62 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PEF_2 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_3 , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PEF_3 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_0 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_1 , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_1 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_2 , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_2 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_3 , 3 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_3 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_4 , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_4 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_5 , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_5 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_6 , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_6 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NCF_7 , 7 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NCF_7 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_0 , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_0 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_1 , 9 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_1 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_2 , 10 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_2 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_3 , 11 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_3 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_4 , 12 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_4 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_5 , 13 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_5 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_6 , 14 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_6 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_7 , 15 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_7 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_8 , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_8 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_9 , 17 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_9 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_10 , 18 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_10 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_11 , 19 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_11 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_12 , 20 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_12 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_13 , 21 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_13 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_14 , 22 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_14 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_15 , 23 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_15 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_16 , 24 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_16 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_17 , 25 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_17 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_18 , 26 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_18 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_19 , 27 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_19 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_20 , 28 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_20 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_21 , 29 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_21 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_22 , 30 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_22 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_NVF_23 , 31 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NVF_23 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_0 , 32 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV1_0 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_1 , 33 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV1_1 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_2 , 34 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV1_2 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_RSV1_3 , 35 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV1_3 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_0 , 36 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_0 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_1 , 37 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_1 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_2 , 38 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_2 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_3 , 39 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_3 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_4 , 40 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_4 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_5 , 41 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_5 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_6 , 42 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_6 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_ASBE_7 , 43 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_ASBE_7 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_0 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_1 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_2 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_3 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_4 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_5 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_6 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBR_7 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_0 , 52 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_REG_0 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_1 , 53 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_REG_1 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_2 , 54 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_REG_2 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_REG_3 , 55 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_REG_3 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_0 , 56 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_DUE_0 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_1 , 57 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_DUE_1 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_2 , 58 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_DUE_2 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_DUE_3 , 59 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_DUE_3 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_0 , 60 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PEF_0 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_1 , 61 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PEF_1 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_2 , 62 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PEF_2 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST0_IDIAL_CTL_FIRST_PEF_3 , 63 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PEF_3 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_24 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_25 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_26 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_27 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_28 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_29 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_30 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_31 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_0 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_1 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_2 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_3 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_4 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_5 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_6 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_7 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_4 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_5 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_0 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_1 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_2 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_0 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_1 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_2 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_3 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_4 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_5 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_6 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_7 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_8 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_8 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_9 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_9 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_10 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_10 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_11 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_11 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_12 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_12 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_13 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_13 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_14 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_14 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_15 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_15 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_16 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_16 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_17 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_17 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_18 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_18 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_19 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_19 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_20 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_20 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_21 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_21 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_22 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_22 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_23 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_23 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_24 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_24 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_25 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_25 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_26 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_26 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_27 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_27 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_28 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_28 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_29 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_29 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_30 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_30 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NVF_31 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NVF_31 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_0 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_0 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_1 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_1 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_2 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_2 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_3 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_3 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_4 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_4 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_5 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_5 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_6 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_6 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_NCF_7 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NCF_7 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_0 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_1 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_2 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_ASBE_3 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_0 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_0 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_1 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_1 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_2 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_2 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_3 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_3 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_4 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_4 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_5 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_5 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_6 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_6 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_PBR_7 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBR_7 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_0 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_0 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_1 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_1 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_2 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_2 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST0_IDIAL_SM_FIRST_REG_3 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_REG_3 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_0 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_1 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_2 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_3 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_4 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_5 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_6 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_7 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_0 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_1 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_2 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_3 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_4 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_5 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_6 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_7 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_8 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_9 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_10 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_11 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_0 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_1 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_2 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_3 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_4 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_5 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_6 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_7 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_8 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_9 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_10 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_11 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_0 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_1 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_2 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_3 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_4 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_5 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_6 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_7 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_0 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_1 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_2 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_3 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_4 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_5 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_6 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_7 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_8 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_9 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_10 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_11 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_0 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_1 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_2 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_3 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_4 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_5 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_6 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_7 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_8 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_9 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_10 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_11 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_1 , 1 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_2 , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_3 , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_4 , 4 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_5 , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_6 , 6 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_7 , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_8 , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_9 , 9 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_10 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_11 , 11 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_12 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_13 , 13 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_14 , 14 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_15 , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_16 , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_17 , 17 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_18 , 18 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_19 , 19 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_20 , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_21 , 21 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_22 , 22 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_23 , 23 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_24 , 24 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_25 , 25 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_26 , 26 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_27 , 27 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_28 , 28 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_29 , 29 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_30 , 30 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_31 , 31 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_32 , 32 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_33 , 33 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_34 , 34 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_35 , 35 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_36 , 36 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_37 , 37 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_38 , 38 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_39 , 39 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_40 , 40 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_41 , 41 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_42 , 42 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_43 , 43 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_44 , 44 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_45 , 45 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_46 , 46 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_47 , 47 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_48 , 48 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_49 , 49 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_50 , 50 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_51 , 51 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_52 , 52 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_53 , 53 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_54 , 54 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_55 , 55 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_56 , 56 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_57 , 57 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_58 , 58 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_59 , 59 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_60 , 60 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_61 , 61 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_62 , 62 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST1_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_0 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_1 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_2 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_3 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_4 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_5 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_6 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_7 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_0 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_1 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_2 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_3 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_4 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_5 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_6 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_7 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_8 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_9 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_10 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_11 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_0 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_1 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_2 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_3 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_4 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_5 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_6 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_7 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_8 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_9 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_10 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_11 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_0 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_1 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_2 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_3 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_4 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_5 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_6 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_7 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_0 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_1 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_2 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_3 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_4 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_5 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_6 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_7 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_8 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_9 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_10 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_11 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_0 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_1 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_2 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_3 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_4 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_5 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_6 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_7 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_8 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_9 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_10 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_11 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_0 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_1 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_2 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_3 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_4 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_5 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_6 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_7 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_8 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_9 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_10 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_11 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_12 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_13 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_14 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_15 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_0 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_1 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_2 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_3 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_4 , 20 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_4 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_5 , 21 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_5 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_6 , 22 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_6 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_7 , 23 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_7 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_0 , 24 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_0 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_1 , 25 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_1 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_2 , 26 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_2 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_3 , 27 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_3 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_4 , 28 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_4 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_5 , 29 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_5 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_6 , 30 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_6 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_7 , 31 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_7 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_0 , 32 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_0 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_1 , 33 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_1 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_2 , 34 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_2 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_3 , 35 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_3 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_4 , 36 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_4 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_5 , 37 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_5 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_6 , 38 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_6 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_7 , 39 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_7 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_0 , 40 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_0 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_1 , 41 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_1 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_2 , 42 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_2 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_3 , 43 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_3 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_4 , 44 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_4 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_5 , 45 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_5 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_6 , 46 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_6 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_7 , 47 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_7 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_0 , 48 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_0 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_1 , 49 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_1 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_2 , 50 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_2 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_3 , 51 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_3 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_4 , 52 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_4 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_5 , 53 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_5 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_6 , 54 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_6 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_7 , 55 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_7 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_0 , 56 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV2_0 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_1 , 57 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV2_1 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_2 , 58 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV2_2 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_3 , 59 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV2_3 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_0 , 60 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV3_0 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_1 , 61 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV3_1 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_2 , 62 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV3_2 ); REG64_FLD( PU_NPU0_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_3 , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV3_3 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_0 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_1 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_2 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_3 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_4 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_5 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_6 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_7 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_0 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_1 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_2 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_3 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_4 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_5 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_6 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_7 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_8 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_9 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_10 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_11 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_0 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_1 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_2 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_3 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_4 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_5 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_6 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_7 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_8 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_9 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_10 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_11 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_0 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_1 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_2 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_3 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_4 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_5 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_6 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_7 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_0 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_1 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_2 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_3 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_4 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_5 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_6 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_7 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_8 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_9 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_10 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_11 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_0 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_1 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_2 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_3 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_4 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_5 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_6 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_7 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_8 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_9 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_10 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_11 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_1 , 1 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_2 , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_3 , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_4 , 4 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_5 , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_6 , 6 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_7 , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_8 , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_9 , 9 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_10 , 10 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_11 , 11 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_12 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_13 , 13 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_14 , 14 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_15 , 15 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_16 , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_17 , 17 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_18 , 18 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_19 , 19 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_20 , 20 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_21 , 21 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_22 , 22 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_23 , 23 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_24 , 24 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_25 , 25 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_26 , 26 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_27 , 27 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_28 , 28 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_29 , 29 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_30 , 30 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_31 , 31 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_32 , 32 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_33 , 33 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_34 , 34 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_35 , 35 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_36 , 36 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_37 , 37 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_38 , 38 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_39 , 39 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_40 , 40 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_41 , 41 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_42 , 42 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_43 , 43 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_44 , 44 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_45 , 45 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_46 , 46 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_47 , 47 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_48 , 48 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_49 , 49 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_50 , 50 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_51 , 51 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_52 , 52 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_53 , 53 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_54 , 54 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_55 , 55 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_56 , 56 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_57 , 57 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_58 , 58 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_59 , 59 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_60 , 60 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_61 , 61 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_62 , 62 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST1_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_0 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_1 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_2 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_3 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_4 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_5 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_6 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_7 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_0 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_1 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_2 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_3 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_4 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_5 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_6 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_7 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_8 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_9 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_10 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_11 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_0 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_1 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_2 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_3 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_4 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_5 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_6 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_7 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_8 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_9 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_10 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_11 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_0 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_1 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_2 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_3 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_4 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_5 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_6 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_7 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_0 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_1 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_2 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_3 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_4 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_5 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_6 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_7 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_8 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_9 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_10 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_11 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_0 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_1 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_2 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_3 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_4 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_5 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_6 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_7 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_8 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_9 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_10 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_11 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_0 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_1 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_2 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_3 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_4 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_5 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_6 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_7 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_0 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_1 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_2 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_3 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_4 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_5 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_6 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_7 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_8 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_9 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_10 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_11 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_0 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_1 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_2 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_3 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_4 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_5 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_6 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_7 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_8 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_9 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_10 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_11 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_0 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_1 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_2 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_3 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_4 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_5 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_6 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_7 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_8 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_9 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_10 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_11 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_12 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_13 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_14 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_15 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_0 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_1 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_2 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_3 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_4 , 20 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_4 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_5 , 21 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_5 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_6 , 22 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_6 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_7 , 23 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_7 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_0 , 24 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_0 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_1 , 25 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_1 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_2 , 26 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_2 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_3 , 27 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_3 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_4 , 28 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_4 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_5 , 29 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_5 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_6 , 30 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_6 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_7 , 31 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_7 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_0 , 32 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_0 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_1 , 33 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_1 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_2 , 34 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_2 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_3 , 35 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_3 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_4 , 36 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_4 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_5 , 37 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_5 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_6 , 38 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_6 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_7 , 39 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_7 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_0 , 40 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_0 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_1 , 41 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_1 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_2 , 42 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_2 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_3 , 43 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_3 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_4 , 44 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_4 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_5 , 45 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_5 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_6 , 46 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_6 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_7 , 47 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_7 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_0 , 48 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_0 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_1 , 49 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_1 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_2 , 50 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_2 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_3 , 51 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_3 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_4 , 52 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_4 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_5 , 53 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_5 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_6 , 54 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_6 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_7 , 55 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_7 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_0 , 56 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV2_0 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_1 , 57 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV2_1 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_2 , 58 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV2_2 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_3 , 59 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV2_3 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_0 , 60 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV3_0 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_1 , 61 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV3_1 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_2 , 62 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV3_2 ); REG64_FLD( PU_NPU1_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_3 , 63 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV3_3 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_0 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_1 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_2 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_3 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_4 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_5 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_6 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_7 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_0 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_1 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_2 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_3 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_4 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_5 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_6 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_7 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_8 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_9 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_10 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_11 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_0 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_1 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_2 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_3 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_4 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_5 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_6 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_7 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_8 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_9 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_10 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_11 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_0 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_1 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_2 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_3 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_4 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_5 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_6 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_7 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_0 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_1 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_2 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_3 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_4 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_5 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_6 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_7 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_8 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_9 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_10 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_11 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_0 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_1 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_2 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_3 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_4 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_5 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_6 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_7 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_8 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_9 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_10 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_11 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_0 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_1 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_2 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_3 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_4 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_5 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_6 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_7 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_8 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_9 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_10 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_11 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_12 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_13 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_14 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_NLG_15 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_0 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_1 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_2 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_3 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_4 , 20 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_4 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_5 , 21 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_5 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_6 , 22 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_6 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_FWD_7 , 23 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_FWD_7 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_0 , 24 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_0 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_1 , 25 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_1 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_2 , 26 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_2 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_3 , 27 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_3 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_4 , 28 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_4 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_5 , 29 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_5 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_6 , 30 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_6 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_AUE_7 , 31 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_AUE_7 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_0 , 32 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_0 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_1 , 33 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_1 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_2 , 34 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_2 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_3 , 35 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_3 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_4 , 36 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_4 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_5 , 37 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_5 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_6 , 38 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_6 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBP_7 , 39 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBP_7 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_0 , 40 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_0 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_1 , 41 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_1 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_2 , 42 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_2 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_3 , 43 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_3 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_4 , 44 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_4 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_5 , 45 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_5 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_6 , 46 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_6 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBF_7 , 47 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBF_7 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_0 , 48 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_0 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_1 , 49 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_1 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_2 , 50 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_2 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_3 , 51 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_3 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_4 , 52 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_4 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_5 , 53 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_5 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_6 , 54 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_6 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_PBC_7 , 55 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_PBC_7 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_0 , 56 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV2_0 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_1 , 57 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV2_1 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_2 , 58 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV2_2 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV2_3 , 59 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV2_3 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_0 , 60 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV3_0 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_1 , 61 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV3_1 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_2 , 62 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV3_2 ); REG64_FLD( PU_NPU2_CTL_CERR_FIRST1_IDIAL_CTL_FIRST_RSV3_3 , 63 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_FIRST_RSV3_3 ); REG64_FLD( NV_CERR_FIRST1_NTL_0 , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( NV_CERR_FIRST1_NTL_1 , 1 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( NV_CERR_FIRST1_NTL_2 , 2 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( NV_CERR_FIRST1_NTL_3 , 3 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( NV_CERR_FIRST1_NTL_4 , 4 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( NV_CERR_FIRST1_NTL_5 , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( NV_CERR_FIRST1_NTL_6 , 6 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( NV_CERR_FIRST1_NTL_7 , 7 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( NV_CERR_FIRST1_NTL_8 , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( NV_CERR_FIRST1_NTL_9 , 9 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( NV_CERR_FIRST1_NTL_10 , 10 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( NV_CERR_FIRST1_NTL_11 , 11 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( NV_CERR_FIRST1_NTL_12 , 12 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( NV_CERR_FIRST1_NTL_13 , 13 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( NV_CERR_FIRST1_NTL_14 , 14 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( NV_CERR_FIRST1_NTL_15 , 15 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( NV_CERR_FIRST1_NTL_16 , 16 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( NV_CERR_FIRST1_NTL_17 , 17 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( NV_CERR_FIRST1_NTL_18 , 18 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( NV_CERR_FIRST1_NTL_19 , 19 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( NV_CERR_FIRST1_NTL_20 , 20 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( NV_CERR_FIRST1_NTL_21 , 21 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( NV_CERR_FIRST1_NTL_22 , 22 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( NV_CERR_FIRST1_NTL_23 , 23 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( NV_CERR_FIRST1_NTL_24 , 24 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( NV_CERR_FIRST1_NTL_25 , 25 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( NV_CERR_FIRST1_NTL_26 , 26 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( NV_CERR_FIRST1_NTL_27 , 27 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( NV_CERR_FIRST1_NTL_28 , 28 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( NV_CERR_FIRST1_NTL_29 , 29 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( NV_CERR_FIRST1_NTL_30 , 30 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( NV_CERR_FIRST1_NTL_31 , 31 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( NV_CERR_FIRST1_NTL_32 , 32 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( NV_CERR_FIRST1_NTL_33 , 33 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( NV_CERR_FIRST1_NTL_34 , 34 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( NV_CERR_FIRST1_NTL_35 , 35 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( NV_CERR_FIRST1_NTL_36 , 36 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( NV_CERR_FIRST1_NTL_37 , 37 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( NV_CERR_FIRST1_NTL_38 , 38 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( NV_CERR_FIRST1_NTL_39 , 39 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( NV_CERR_FIRST1_NTL_40 , 40 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( NV_CERR_FIRST1_NTL_41 , 41 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( NV_CERR_FIRST1_NTL_42 , 42 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( NV_CERR_FIRST1_NTL_43 , 43 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( NV_CERR_FIRST1_NTL_44 , 44 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( NV_CERR_FIRST1_NTL_45 , 45 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( NV_CERR_FIRST1_NTL_46 , 46 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( NV_CERR_FIRST1_NTL_47 , 47 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( NV_CERR_FIRST1_NTL_48 , 48 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( NV_CERR_FIRST1_NTL_49 , 49 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( NV_CERR_FIRST1_NTL_50 , 50 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( NV_CERR_FIRST1_NTL_51 , 51 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( NV_CERR_FIRST1_NTL_52 , 52 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( NV_CERR_FIRST1_NTL_53 , 53 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( NV_CERR_FIRST1_NTL_54 , 54 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( NV_CERR_FIRST1_NTL_55 , 55 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( NV_CERR_FIRST1_NTL_56 , 56 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( NV_CERR_FIRST1_NTL_57 , 57 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( NV_CERR_FIRST1_NTL_58 , 58 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( NV_CERR_FIRST1_NTL_59 , 59 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( NV_CERR_FIRST1_NTL_60 , 60 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( NV_CERR_FIRST1_NTL_61 , 61 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( NV_CERR_FIRST1_NTL_62 , 62 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( NV_CERR_FIRST1_NTL_63 , 63 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_0 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_1 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_2 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_3 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_4 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_5 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_6 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_7 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_8 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_9 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_10 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_11 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_12 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_13 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_14 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLGX_15 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_0 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_0 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_1 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_1 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_2 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_2 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_FWD_3 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_FWD_3 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_0 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_0 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_1 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_1 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_2 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_2 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_AUE_3 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_AUE_3 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_0 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_0 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_1 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_1 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_2 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_2 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_3 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_3 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_4 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_4 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_5 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_5 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_6 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_6 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBP_7 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBP_7 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_0 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_0 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_1 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_1 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_2 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_2 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_3 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_3 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_4 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_4 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_5 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_5 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_6 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_6 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_7 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_7 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_8 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_8 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_9 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_9 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_10 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_10 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBF_11 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBF_11 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_0 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_0 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_1 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_1 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_2 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_2 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_3 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_3 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_4 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_4 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_5 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_5 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_6 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_6 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_7 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_7 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_8 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_8 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_9 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_9 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_10 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_10 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST1_IDIAL_SM_FIRST_PBC_11 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_PBC_11 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_0 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_1 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_2 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_3 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_4 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_5 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_6 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_7 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_8 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_9 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_10 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_11 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_12 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_13 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_14 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_15 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_16 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_17 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_18 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_19 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_20 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_21 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_22 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_23 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_24 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_25 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_26 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_27 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_28 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_29 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_30 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_31 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_32 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_33 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_34 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_35 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_36 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_37 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_38 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_39 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_40 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_41 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_42 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_43 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_44 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_45 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_46 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_47 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_48 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_49 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_50 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_51 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_52 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_53 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_54 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_55 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_56 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_57 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_58 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_59 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_60 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_61 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_62 ); REG64_FLD( PU_NPU0_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_63 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_1 , 1 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_2 , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_3 , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_4 , 4 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_5 , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_6 , 6 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_7 , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_8 , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_9 , 9 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_10 , 10 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_11 , 11 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_12 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_13 , 13 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_14 , 14 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_15 , 15 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_16 , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_17 , 17 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_18 , 18 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_19 , 19 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_20 , 20 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_21 , 21 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_22 , 22 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_23 , 23 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_24 , 24 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_25 , 25 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_26 , 26 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_27 , 27 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_28 , 28 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_29 , 29 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_30 , 30 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_31 , 31 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_32 , 32 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_33 , 33 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_34 , 34 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_35 , 35 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_36 , 36 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_37 , 37 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_38 , 38 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_39 , 39 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_40 , 40 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_41 , 41 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_42 , 42 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_43 , 43 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_44 , 44 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_45 , 45 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_46 , 46 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_47 , 47 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_48 , 48 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_49 , 49 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_50 , 50 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_51 , 51 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_52 , 52 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_53 , 53 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_54 , 54 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_55 , 55 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_56 , 56 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_57 , 57 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_58 , 58 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_59 , 59 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_60 , 60 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_61 , 61 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_62 , 62 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST2_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_0 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_1 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_2 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_3 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_4 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_5 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_6 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_7 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_8 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_9 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_10 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_11 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_12 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_13 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_14 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_15 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_16 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_17 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_18 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_19 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_20 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_21 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_22 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_23 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_24 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_25 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_26 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_27 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_28 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_29 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_30 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_31 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_32 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_33 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_34 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_35 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_36 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_37 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_38 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_39 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_40 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_41 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_42 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_43 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_44 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_45 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_46 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_47 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_48 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_49 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_50 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_51 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_52 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_53 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_54 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_55 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_56 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_57 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_58 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_59 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_60 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_61 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_62 ); REG64_FLD( PU_NPU1_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_63 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_0 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_1 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_2 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_3 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_4 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_5 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_6 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_7 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_8 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_9 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_10 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_11 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_12 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_13 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_14 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_15 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_16 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_17 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_18 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_19 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_20 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_21 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_22 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_23 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_24 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_25 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_26 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_27 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_28 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_29 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_30 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_31 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_32 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_33 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_34 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_35 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_36 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_37 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_38 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_39 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_40 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_41 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_42 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_43 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_44 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_45 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_46 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_47 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_48 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_49 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_50 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_51 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_52 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_53 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_54 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_55 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_56 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_57 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_58 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_59 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_60 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_61 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_62 ); REG64_FLD( PU_NPU2_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_63 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_0 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_1 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_2 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_3 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_4 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_5 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_6 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_7 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_8 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_9 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_10 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_11 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_12 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_13 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_14 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_15 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_16 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_17 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_18 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_19 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_20 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_21 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_22 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_23 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_24 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_25 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_26 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_27 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_28 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_29 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_30 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_31 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_32 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_33 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_34 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_35 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_36 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_37 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_38 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_39 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_40 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_41 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_42 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_43 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_44 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_45 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_46 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_47 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_48 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_49 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_50 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_51 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_52 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_53 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_54 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_55 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_56 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_57 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_58 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_59 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_60 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_61 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_62 ); REG64_FLD( PU_NPU1_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_63 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_0 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_1 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_2 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_3 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_4 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_5 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_6 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_7 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_8 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_9 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_10 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_11 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_12 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_13 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_14 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_15 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_16 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_17 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_18 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_19 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_20 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_21 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_22 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_23 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_24 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_25 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_26 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_27 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_28 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_29 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_30 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_31 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_32 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_33 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_34 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_35 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_36 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_37 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_38 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_39 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_40 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_41 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_42 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_43 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_44 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_45 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_46 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_47 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_48 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_49 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_50 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_51 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_52 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_53 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_54 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_55 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_56 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_57 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_58 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_59 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_60 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_61 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_62 ); REG64_FLD( PU_NPU0_SM3_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_63 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_1 , 1 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_2 , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_3 , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_4 , 4 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_5 , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_6 , 6 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_7 , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_8 , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_9 , 9 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_10 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_11 , 11 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_12 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_13 , 13 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_14 , 14 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_15 , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_16 , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_17 , 17 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_18 , 18 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_19 , 19 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_20 , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_21 , 21 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_22 , 22 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_23 , 23 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_24 , 24 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_25 , 25 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_26 , 26 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_27 , 27 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_28 , 28 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_29 , 29 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_30 , 30 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_31 , 31 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_32 , 32 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_33 , 33 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_34 , 34 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_35 , 35 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_36 , 36 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_37 , 37 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_38 , 38 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_39 , 39 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_40 , 40 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_41 , 41 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_42 , 42 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_43 , 43 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_44 , 44 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_45 , 45 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_46 , 46 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_47 , 47 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_48 , 48 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_49 , 49 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_50 , 50 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_51 , 51 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_52 , 52 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_53 , 53 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_54 , 54 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_55 , 55 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_56 , 56 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_57 , 57 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_58 , 58 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_59 , 59 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_60 , 60 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_61 , 61 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_62 , 62 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST2_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_0 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_1 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_2 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_3 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_4 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_5 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_6 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_7 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_8 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_9 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_10 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_11 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_12 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_13 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_14 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_15 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_16 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_17 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_18 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_19 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_20 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_21 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_22 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_23 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_24 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_25 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_26 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_27 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_28 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_29 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_30 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_31 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_32 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_33 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_34 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_35 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_36 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_37 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_38 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_39 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_40 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_41 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_42 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_43 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_44 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_45 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_46 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_47 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_48 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_49 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_50 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_51 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_52 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_53 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_54 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_55 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_56 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_57 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_58 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_59 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_60 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_61 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_62 ); REG64_FLD( PU_NPU1_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_63 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_0 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_1 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_2 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_3 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_4 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_5 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_6 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_7 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_8 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_9 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_10 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_11 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_12 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_13 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_14 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_15 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_16 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_17 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_18 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_19 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_20 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_21 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_22 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_23 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_24 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_25 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_26 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_27 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_28 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_29 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_30 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_31 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_32 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_33 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_34 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_35 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_36 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_37 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_38 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_39 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_40 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_41 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_42 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_43 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_44 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_45 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_46 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_47 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_48 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_49 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_50 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_51 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_52 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_53 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_54 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_55 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_56 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_57 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_58 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_59 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_60 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_61 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_62 ); REG64_FLD( PU_NPU2_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_63 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_0 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_1 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_2 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_3 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_4 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_5 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_6 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_7 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_8 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_9 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_10 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_11 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_12 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_13 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_14 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_15 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_16 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_17 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_18 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_19 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_20 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_21 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_22 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_23 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_24 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_25 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_26 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_27 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_28 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_29 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_30 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_31 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_32 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_33 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_34 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_35 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_36 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_37 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_38 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_39 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_40 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_41 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_42 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_43 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_44 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_45 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_46 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_47 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_48 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_49 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_50 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_51 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_52 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_53 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_54 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_55 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_56 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_57 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_58 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_59 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_60 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_61 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_62 ); REG64_FLD( PU_NPU2_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_63 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_0 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_1 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_2 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_3 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_4 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_5 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_6 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_7 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_8 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_9 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_10 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_11 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_12 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_13 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_14 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_15 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_16 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_17 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_18 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_19 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_20 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_21 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_22 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_23 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_24 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_25 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_26 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_27 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_28 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_29 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_30 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_31 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_32 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_33 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_34 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_35 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_36 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_37 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_38 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_39 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_40 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_41 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_42 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_43 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_44 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_45 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_46 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_47 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_48 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_49 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_50 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_51 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_52 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_53 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_54 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_55 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_56 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_57 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_58 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_59 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_60 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_61 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_62 ); REG64_FLD( PU_NPU0_SM2_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_63 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_0 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_1 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_2 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_3 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_4 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_5 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_6 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_7 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_8 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_9 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_10 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_11 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_12 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_13 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_14 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_15 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_16 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_17 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_18 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_19 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_20 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_21 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_22 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_23 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_24 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_25 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_26 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_27 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_28 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_29 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_30 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_31 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_32 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_33 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_34 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_35 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_36 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_37 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_38 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_39 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_40 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_41 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_42 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_43 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_44 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_45 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_46 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_47 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_48 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_49 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_50 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_51 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_52 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_53 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_54 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_55 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_56 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_57 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_58 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_59 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_60 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_61 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_62 ); REG64_FLD( PU_NPU2_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_63 ); REG64_FLD( NV_CERR_FIRST2_NTL_0 , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( NV_CERR_FIRST2_NTL_1 , 1 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( NV_CERR_FIRST2_NTL_2 , 2 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( NV_CERR_FIRST2_NTL_3 , 3 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( NV_CERR_FIRST2_NTL_4 , 4 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( NV_CERR_FIRST2_NTL_5 , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( NV_CERR_FIRST2_NTL_6 , 6 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( NV_CERR_FIRST2_NTL_7 , 7 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( NV_CERR_FIRST2_NTL_8 , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( NV_CERR_FIRST2_NTL_9 , 9 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( NV_CERR_FIRST2_NTL_10 , 10 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( NV_CERR_FIRST2_NTL_11 , 11 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( NV_CERR_FIRST2_NTL_12 , 12 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( NV_CERR_FIRST2_NTL_13 , 13 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( NV_CERR_FIRST2_NTL_14 , 14 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( NV_CERR_FIRST2_NTL_15 , 15 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( NV_CERR_FIRST2_NTL_16 , 16 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( NV_CERR_FIRST2_NTL_17 , 17 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( NV_CERR_FIRST2_NTL_18 , 18 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( NV_CERR_FIRST2_NTL_19 , 19 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( NV_CERR_FIRST2_NTL_20 , 20 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( NV_CERR_FIRST2_NTL_21 , 21 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( NV_CERR_FIRST2_NTL_22 , 22 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( NV_CERR_FIRST2_NTL_23 , 23 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( NV_CERR_FIRST2_NTL_24 , 24 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( NV_CERR_FIRST2_NTL_25 , 25 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( NV_CERR_FIRST2_NTL_26 , 26 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( NV_CERR_FIRST2_NTL_27 , 27 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( NV_CERR_FIRST2_NTL_28 , 28 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( NV_CERR_FIRST2_NTL_29 , 29 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( NV_CERR_FIRST2_NTL_30 , 30 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( NV_CERR_FIRST2_NTL_31 , 31 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( NV_CERR_FIRST2_NTL_32 , 32 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( NV_CERR_FIRST2_NTL_33 , 33 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( NV_CERR_FIRST2_NTL_34 , 34 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( NV_CERR_FIRST2_NTL_35 , 35 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( NV_CERR_FIRST2_NTL_36 , 36 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( NV_CERR_FIRST2_NTL_37 , 37 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( NV_CERR_FIRST2_NTL_38 , 38 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( NV_CERR_FIRST2_NTL_39 , 39 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( NV_CERR_FIRST2_NTL_40 , 40 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( NV_CERR_FIRST2_NTL_41 , 41 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( NV_CERR_FIRST2_NTL_42 , 42 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( NV_CERR_FIRST2_NTL_43 , 43 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( NV_CERR_FIRST2_NTL_44 , 44 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( NV_CERR_FIRST2_NTL_45 , 45 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( NV_CERR_FIRST2_NTL_46 , 46 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( NV_CERR_FIRST2_NTL_47 , 47 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( NV_CERR_FIRST2_NTL_48 , 48 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( NV_CERR_FIRST2_NTL_49 , 49 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( NV_CERR_FIRST2_NTL_50 , 50 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( NV_CERR_FIRST2_NTL_51 , 51 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( NV_CERR_FIRST2_NTL_52 , 52 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( NV_CERR_FIRST2_NTL_53 , 53 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( NV_CERR_FIRST2_NTL_54 , 54 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( NV_CERR_FIRST2_NTL_55 , 55 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( NV_CERR_FIRST2_NTL_56 , 56 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( NV_CERR_FIRST2_NTL_57 , 57 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( NV_CERR_FIRST2_NTL_58 , 58 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( NV_CERR_FIRST2_NTL_59 , 59 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( NV_CERR_FIRST2_NTL_60 , 60 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( NV_CERR_FIRST2_NTL_61 , 61 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( NV_CERR_FIRST2_NTL_62 , 62 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( NV_CERR_FIRST2_NTL_63 , 63 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_0 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_1 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_2 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_3 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_4 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_5 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_6 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_7 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_8 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_9 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_10 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_11 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_12 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_13 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_14 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_15 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_16 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_17 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_18 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_19 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_20 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_21 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_22 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_23 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_24 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_25 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_26 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_27 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_28 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_29 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_30 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_31 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_32 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_33 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_34 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_35 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_36 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_37 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_38 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_39 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_40 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_41 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_42 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_43 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_44 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_45 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_46 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_47 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_48 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_49 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_50 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_51 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_52 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_53 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_54 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_55 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_56 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_57 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_58 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_59 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_60 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_61 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_62 ); REG64_FLD( PU_NPU0_SM1_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_63 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_0 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_1 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_2 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_3 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_4 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_5 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_6 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_7 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_8 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_8 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_9 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_9 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_10 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_10 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_11 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_11 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_12 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_12 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_13 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_13 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_14 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_14 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_15 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_15 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_16 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_16 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_17 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_17 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_18 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_18 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_19 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_19 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_20 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_20 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_21 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_21 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_22 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_22 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_23 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_23 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_24 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_24 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_25 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_25 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_26 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_26 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_27 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_27 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_28 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_28 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_29 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_29 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_30 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_30 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_31 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_31 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_32 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_32 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_33 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_33 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_34 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_34 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_35 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_35 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_36 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_36 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_37 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_37 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_38 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_38 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_39 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_39 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_40 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_40 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_41 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_41 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_42 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_42 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_43 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_43 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_44 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_44 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_45 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_45 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_46 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_46 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_47 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_47 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_48 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_48 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_49 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_49 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_50 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_50 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_51 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_51 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_52 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_52 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_53 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_53 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_54 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_54 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_55 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_55 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_56 , 56 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_56 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_57 , 57 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_57 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_58 , 58 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_58 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_59 , 59 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_59 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_60 , 60 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_60 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_61 , 61 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_61 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_62 , 62 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_62 ); REG64_FLD( PU_NPU1_SM0_CERR_FIRST2_IDIAL_SM_FIRST_NLG_63 , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_FIRST_NLG_63 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_1 , 1 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_2 , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_3 , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_4 , 4 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_5 , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_6 , 6 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_7 , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_8 , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_9 , 9 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_10 , 10 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_11 , 11 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_12 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_13 , 13 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_14 , 14 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_15 , 15 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_16 , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_17 , 17 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_18 , 18 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_19 , 19 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_20 , 20 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_21 , 21 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_22 , 22 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_23 , 23 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_24 , 24 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_25 , 25 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_26 , 26 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_27 , 27 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_28 , 28 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_29 , 29 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_30 , 30 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_31 , 31 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_32 , 32 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_33 , 33 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_34 , 34 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_35 , 35 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_36 , 36 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_37 , 37 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_38 , 38 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_39 , 39 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_40 , 40 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_41 , 41 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_42 , 42 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_43 , 43 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_44 , 44 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_45 , 45 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_46 , 46 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_47 , 47 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_48 , 48 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_49 , 49 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_50 , 50 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_51 , 51 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_52 , 52 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_53 , 53 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_54 , 54 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_55 , 55 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_56 , 56 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_57 , 57 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_58 , 58 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_59 , 59 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_60 , 60 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_61 , 61 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_62 , 62 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK1_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_0 , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_1 , 1 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_2 , 2 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_3 , 3 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_4 , 4 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_5 , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_6 , 6 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_7 , 7 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_8 , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_9 , 9 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_10 , 10 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_11 , 11 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_12 , 12 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_13 , 13 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_14 , 14 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_15 , 15 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_16 , 16 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_17 , 17 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_18 , 18 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_19 , 19 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_20 , 20 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_21 , 21 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_22 , 22 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_23 , 23 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_24 , 24 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_25 , 25 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_26 , 26 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_27 , 27 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_28 , 28 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_29 , 29 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_30 , 30 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_31 , 31 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_32 , 32 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_33 , 33 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_34 , 34 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_35 , 35 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_36 , 36 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_37 , 37 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_38 , 38 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_39 , 39 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_40 , 40 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_41 , 41 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_42 , 42 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_43 , 43 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_44 , 44 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_45 , 45 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_46 , 46 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_47 , 47 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_48 , 48 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_49 , 49 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_50 , 50 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_51 , 51 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_52 , 52 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_53 , 53 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_54 , 54 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_55 , 55 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_56 , 56 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_57 , 57 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_58 , 58 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_59 , 59 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_60 , 60 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_61 , 61 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_62 , 62 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( NV_CERR_FIRST_MASK1_NTL_63 , 63 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_1 , 1 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_2 , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_3 , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_4 , 4 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_5 , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_6 , 6 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_7 , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_8 , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_9 , 9 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_10 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_11 , 11 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_12 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_13 , 13 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_14 , 14 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_15 , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_16 , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_17 , 17 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_18 , 18 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_19 , 19 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_20 , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_21 , 21 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_22 , 22 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_23 , 23 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_24 , 24 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_25 , 25 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_26 , 26 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_27 , 27 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_28 , 28 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_29 , 29 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_30 , 30 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_31 , 31 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_32 , 32 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_33 , 33 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_34 , 34 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_35 , 35 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_36 , 36 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_37 , 37 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_38 , 38 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_39 , 39 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_40 , 40 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_41 , 41 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_42 , 42 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_43 , 43 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_44 , 44 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_45 , 45 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_46 , 46 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_47 , 47 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_48 , 48 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_49 , 49 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_50 , 50 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_51 , 51 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_52 , 52 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_53 , 53 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_54 , 54 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_55 , 55 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_56 , 56 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_57 , 57 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_58 , 58 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_59 , 59 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_60 , 60 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_61 , 61 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_62 , 62 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK1_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_1 , 1 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_2 , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_3 , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_4 , 4 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_5 , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_6 , 6 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_7 , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_8 , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_9 , 9 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_10 , 10 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_11 , 11 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_12 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_13 , 13 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_14 , 14 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_15 , 15 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_16 , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_17 , 17 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_18 , 18 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_19 , 19 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_20 , 20 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_21 , 21 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_22 , 22 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_23 , 23 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_24 , 24 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_25 , 25 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_26 , 26 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_27 , 27 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_28 , 28 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_29 , 29 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_30 , 30 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_31 , 31 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_32 , 32 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_33 , 33 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_34 , 34 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_35 , 35 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_36 , 36 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_37 , 37 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_38 , 38 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_39 , 39 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_40 , 40 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_41 , 41 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_42 , 42 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_43 , 43 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_44 , 44 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_45 , 45 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_46 , 46 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_47 , 47 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_48 , 48 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_49 , 49 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_50 , 50 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_51 , 51 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_52 , 52 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_53 , 53 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_54 , 54 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_55 , 55 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_56 , 56 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_57 , 57 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_58 , 58 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_59 , 59 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_60 , 60 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_61 , 61 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_62 , 62 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( PU_NPU2_NTL0_CERR_FIRST_MASK2_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_0 , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_1 , 1 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_2 , 2 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_3 , 3 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_4 , 4 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_5 , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_6 , 6 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_7 , 7 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_8 , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_9 , 9 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_10 , 10 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_11 , 11 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_12 , 12 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_13 , 13 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_14 , 14 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_15 , 15 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_16 , 16 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_17 , 17 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_18 , 18 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_19 , 19 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_20 , 20 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_21 , 21 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_22 , 22 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_23 , 23 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_24 , 24 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_25 , 25 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_26 , 26 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_27 , 27 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_28 , 28 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_29 , 29 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_30 , 30 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_31 , 31 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_32 , 32 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_33 , 33 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_34 , 34 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_35 , 35 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_36 , 36 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_37 , 37 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_38 , 38 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_39 , 39 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_40 , 40 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_41 , 41 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_42 , 42 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_43 , 43 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_44 , 44 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_45 , 45 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_46 , 46 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_47 , 47 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_48 , 48 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_49 , 49 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_50 , 50 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_51 , 51 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_52 , 52 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_53 , 53 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_54 , 54 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_55 , 55 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_56 , 56 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_57 , 57 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_58 , 58 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_59 , 59 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_60 , 60 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_61 , 61 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_62 , 62 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( NV_CERR_FIRST_MASK2_NTL_63 , 63 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_1 , 1 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_2 , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_3 , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_4 , 4 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_5 , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_6 , 6 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_7 , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_8 , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_9 , 9 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_10 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_11 , 11 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_12 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_13 , 13 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_14 , 14 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_15 , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_16 , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_17 , 17 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_18 , 18 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_19 , 19 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_20 , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_21 , 21 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_22 , 22 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_23 , 23 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_24 , 24 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_25 , 25 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_26 , 26 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_27 , 27 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_28 , 28 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_29 , 29 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_30 , 30 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_31 , 31 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_32 , 32 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_33 , 33 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_34 , 34 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_35 , 35 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_36 , 36 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_37 , 37 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_38 , 38 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_39 , 39 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_40 , 40 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_41 , 41 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_42 , 42 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_43 , 43 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_44 , 44 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_45 , 45 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_46 , 46 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_47 , 47 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_48 , 48 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_49 , 49 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_50 , 50 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_51 , 51 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_52 , 52 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_53 , 53 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_54 , 54 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_55 , 55 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_56 , 56 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_57 , 57 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_58 , 58 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_59 , 59 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_60 , 60 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_61 , 61 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_62 , 62 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( PU_NPU2_NTL1_CERR_FIRST_MASK2_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_24 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_25 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_26 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_27 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_28 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_29 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_30 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_31 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_0 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_1 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_2 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_3 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_4 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_5 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_6 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_7 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_4 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_5 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_0 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_1 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_2 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_24 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_25 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_26 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_27 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_28 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_29 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_30 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_31 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_0 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_1 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_2 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_3 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_4 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_5 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_6 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_7 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_4 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_5 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_0 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_1 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_2 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_24 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_25 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_26 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_27 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_28 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_29 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_30 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_31 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_0 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_1 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_2 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_3 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_4 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_5 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_6 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_7 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_4 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_5 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_0 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_1 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_2 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_24 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_25 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_26 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_27 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_28 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_29 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_30 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_31 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_0 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_1 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_2 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_3 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_4 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_5 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_6 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_7 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_4 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_5 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_0 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_1 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_2 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_24 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_25 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_26 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_27 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_28 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_29 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_30 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_31 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_0 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_1 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_2 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_3 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_4 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_5 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_6 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_7 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_4 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_5 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_0 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_1 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_2 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_24 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_25 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_26 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_27 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_28 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_29 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_30 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_31 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_0 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_1 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_2 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_3 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_4 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_5 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_6 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_7 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_4 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_5 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_0 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_1 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_2 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_24 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_25 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_26 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_27 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_28 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_29 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_30 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_31 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_0 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_1 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_2 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_3 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_4 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_5 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_6 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_7 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_4 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_5 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_0 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_1 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_2 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_0 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_1 , 1 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_1 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_2 , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_2 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_3 , 3 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_3 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_4 , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_4 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_5 , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_5 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_6 , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_6 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_7 , 7 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_7 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_0 , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_0 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_1 , 9 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_1 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_2 , 10 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_2 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_3 , 11 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_3 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_4 , 12 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_4 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_5 , 13 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_5 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_6 , 14 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_6 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_7 , 15 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_7 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_8 , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_8 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_9 , 17 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_9 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_10 , 18 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_10 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_11 , 19 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_11 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_12 , 20 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_12 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_13 , 21 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_13 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_14 , 22 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_14 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_15 , 23 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_15 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_16 , 24 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_16 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_17 , 25 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_17 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_18 , 26 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_18 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_19 , 27 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_19 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_20 , 28 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_20 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_21 , 29 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_21 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_22 , 30 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_22 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_23 , 31 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_23 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_0 , 32 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV1_0 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_1 , 33 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV1_1 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_2 , 34 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV1_2 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_3 , 35 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV1_3 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_0 , 36 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_0 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_1 , 37 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_1 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_2 , 38 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_2 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_3 , 39 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_3 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_4 , 40 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_4 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_5 , 41 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_5 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_6 , 42 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_6 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_7 , 43 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_7 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_0 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_1 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_2 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_3 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_4 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_5 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_6 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_7 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_0 , 52 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_REG_0 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_1 , 53 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_REG_1 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_2 , 54 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_REG_2 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_3 , 55 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_REG_3 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_0 , 56 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_DUE_0 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_1 , 57 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_DUE_1 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_2 , 58 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_DUE_2 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_3 , 59 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_DUE_3 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_0 , 60 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PEF_0 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_1 , 61 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PEF_1 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_2 , 62 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PEF_2 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_3 , 63 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PEF_3 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_24 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_25 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_26 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_27 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_28 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_29 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_30 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_31 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_0 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_1 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_2 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_3 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_4 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_5 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_6 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_7 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_4 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_5 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_0 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_1 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_2 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_24 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_25 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_26 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_27 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_28 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_29 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_30 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_31 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_0 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_1 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_2 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_3 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_4 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_5 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_6 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_7 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_4 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_5 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_0 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_1 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_2 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_24 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_25 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_26 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_27 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_28 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_29 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_30 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_31 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_0 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_1 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_2 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_3 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_4 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_5 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_6 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_7 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_4 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_5 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_0 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_1 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_2 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_0 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_1 , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_1 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_2 , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_2 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_3 , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_3 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_4 , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_4 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_5 , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_5 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_6 , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_6 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_7 , 7 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_7 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_0 , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_0 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_1 , 9 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_1 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_2 , 10 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_2 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_3 , 11 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_3 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_4 , 12 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_4 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_5 , 13 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_5 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_6 , 14 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_6 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_7 , 15 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_7 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_8 , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_8 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_9 , 17 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_9 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_10 , 18 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_10 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_11 , 19 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_11 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_12 , 20 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_12 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_13 , 21 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_13 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_14 , 22 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_14 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_15 , 23 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_15 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_16 , 24 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_16 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_17 , 25 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_17 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_18 , 26 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_18 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_19 , 27 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_19 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_20 , 28 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_20 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_21 , 29 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_21 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_22 , 30 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_22 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_23 , 31 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_23 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_0 , 32 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV1_0 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_1 , 33 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV1_1 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_2 , 34 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV1_2 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_3 , 35 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV1_3 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_0 , 36 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_0 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_1 , 37 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_1 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_2 , 38 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_2 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_3 , 39 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_3 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_4 , 40 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_4 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_5 , 41 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_5 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_6 , 42 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_6 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_7 , 43 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_7 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_0 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_1 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_2 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_3 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_4 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_5 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_6 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_7 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_0 , 52 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_REG_0 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_1 , 53 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_REG_1 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_2 , 54 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_REG_2 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_3 , 55 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_REG_3 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_0 , 56 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_DUE_0 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_1 , 57 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_DUE_1 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_2 , 58 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_DUE_2 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_3 , 59 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_DUE_3 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_0 , 60 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PEF_0 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_1 , 61 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PEF_1 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_2 , 62 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PEF_2 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_3 , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PEF_3 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_0 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_1 , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_1 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_2 , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_2 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_3 , 3 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_3 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_4 , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_4 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_5 , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_5 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_6 , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_6 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NCF_7 , 7 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NCF_7 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_0 , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_0 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_1 , 9 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_1 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_2 , 10 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_2 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_3 , 11 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_3 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_4 , 12 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_4 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_5 , 13 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_5 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_6 , 14 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_6 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_7 , 15 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_7 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_8 , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_8 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_9 , 17 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_9 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_10 , 18 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_10 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_11 , 19 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_11 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_12 , 20 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_12 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_13 , 21 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_13 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_14 , 22 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_14 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_15 , 23 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_15 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_16 , 24 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_16 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_17 , 25 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_17 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_18 , 26 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_18 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_19 , 27 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_19 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_20 , 28 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_20 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_21 , 29 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_21 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_22 , 30 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_22 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_NVF_23 , 31 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NVF_23 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_0 , 32 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV1_0 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_1 , 33 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV1_1 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_2 , 34 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV1_2 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_RSV1_3 , 35 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV1_3 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_0 , 36 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_0 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_1 , 37 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_1 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_2 , 38 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_2 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_3 , 39 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_3 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_4 , 40 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_4 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_5 , 41 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_5 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_6 , 42 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_6 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_ASBE_7 , 43 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_ASBE_7 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_0 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_1 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_2 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_3 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_4 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_5 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_6 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBR_7 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_0 , 52 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_REG_0 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_1 , 53 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_REG_1 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_2 , 54 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_REG_2 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_REG_3 , 55 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_REG_3 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_0 , 56 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_DUE_0 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_1 , 57 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_DUE_1 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_2 , 58 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_DUE_2 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_DUE_3 , 59 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_DUE_3 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_0 , 60 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PEF_0 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_1 , 61 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PEF_1 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_2 , 62 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PEF_2 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD0_IDIAL_CTL_HOLD_PEF_3 , 63 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PEF_3 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_24 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_25 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_26 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_27 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_28 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_29 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_30 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_31 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_0 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_1 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_2 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_3 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_4 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_5 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_6 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_7 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_4 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_5 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_0 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_1 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_2 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_0 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_1 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_2 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_3 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_4 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_5 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_6 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_7 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_8 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_8 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_9 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_9 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_10 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_10 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_11 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_11 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_12 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_12 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_13 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_13 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_14 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_14 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_15 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_15 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_16 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_16 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_17 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_17 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_18 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_18 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_19 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_19 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_20 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_20 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_21 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_21 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_22 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_22 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_23 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_23 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_24 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_24 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_25 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_25 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_26 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_26 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_27 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_27 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_28 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_28 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_29 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_29 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_30 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_30 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NVF_31 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NVF_31 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_0 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_0 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_1 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_1 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_2 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_2 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_3 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_3 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_4 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_4 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_5 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_5 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_6 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_6 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_NCF_7 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NCF_7 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_0 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_1 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_2 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_ASBE_3 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_0 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_0 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_1 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_1 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_2 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_2 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_3 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_3 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_4 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_4 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_5 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_5 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_6 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_6 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_PBR_7 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBR_7 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_0 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_0 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_1 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_1 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_2 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_2 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD0_IDIAL_SM_HOLD_REG_3 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_REG_3 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_0 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_1 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_2 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_3 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_4 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_5 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_6 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_7 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_0 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_1 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_2 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_3 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_4 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_5 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_6 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_7 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_8 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_9 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_10 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_11 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_0 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_1 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_2 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_3 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_4 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_5 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_6 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_7 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_8 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_9 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_10 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_11 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_0 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_1 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_2 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_3 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_4 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_5 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_6 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_7 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_0 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_1 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_2 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_3 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_4 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_5 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_6 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_7 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_8 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_9 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_10 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_11 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_0 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_1 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_2 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_3 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_4 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_5 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_6 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_7 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_8 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_9 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_10 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_11 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_1 , 1 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_2 , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_3 , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_4 , 4 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_5 , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_6 , 6 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_7 , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_8 , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_9 , 9 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_10 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_11 , 11 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_12 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_13 , 13 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_14 , 14 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_15 , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_16 , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_17 , 17 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_18 , 18 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_19 , 19 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_20 , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_21 , 21 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_22 , 22 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_23 , 23 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_24 , 24 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_25 , 25 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_26 , 26 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_27 , 27 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_28 , 28 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_29 , 29 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_30 , 30 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_31 , 31 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_32 , 32 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_33 , 33 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_34 , 34 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_35 , 35 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_36 , 36 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_37 , 37 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_38 , 38 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_39 , 39 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_40 , 40 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_41 , 41 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_42 , 42 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_43 , 43 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_44 , 44 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_45 , 45 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_46 , 46 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_47 , 47 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_48 , 48 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_49 , 49 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_50 , 50 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_51 , 51 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_52 , 52 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_53 , 53 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_54 , 54 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_55 , 55 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_56 , 56 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_57 , 57 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_58 , 58 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_59 , 59 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_60 , 60 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_61 , 61 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_62 , 62 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD1_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_0 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_1 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_2 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_3 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_4 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_5 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_6 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_7 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_0 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_1 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_2 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_3 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_4 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_5 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_6 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_7 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_8 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_9 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_10 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_11 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_0 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_1 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_2 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_3 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_4 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_5 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_6 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_7 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_8 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_9 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_10 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_11 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_0 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_1 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_2 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_3 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_4 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_5 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_6 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_7 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_0 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_1 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_2 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_3 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_4 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_5 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_6 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_7 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_8 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_9 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_10 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_11 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_0 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_1 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_2 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_3 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_4 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_5 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_6 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_7 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_8 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_9 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_10 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_11 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_0 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_1 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_2 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_3 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_4 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_5 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_6 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_7 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_8 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_9 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_10 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_11 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_12 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_13 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_14 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_15 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_0 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_1 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_2 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_3 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_4 , 20 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_4 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_5 , 21 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_5 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_6 , 22 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_6 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_7 , 23 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_7 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_0 , 24 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_0 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_1 , 25 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_1 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_2 , 26 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_2 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_3 , 27 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_3 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_4 , 28 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_4 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_5 , 29 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_5 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_6 , 30 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_6 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_7 , 31 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_7 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_0 , 32 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_0 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_1 , 33 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_1 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_2 , 34 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_2 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_3 , 35 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_3 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_4 , 36 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_4 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_5 , 37 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_5 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_6 , 38 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_6 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_7 , 39 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_7 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_0 , 40 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_0 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_1 , 41 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_1 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_2 , 42 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_2 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_3 , 43 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_3 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_4 , 44 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_4 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_5 , 45 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_5 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_6 , 46 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_6 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_7 , 47 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_7 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_0 , 48 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_0 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_1 , 49 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_1 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_2 , 50 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_2 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_3 , 51 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_3 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_4 , 52 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_4 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_5 , 53 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_5 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_6 , 54 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_6 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_7 , 55 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_7 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_0 , 56 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV2_0 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_1 , 57 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV2_1 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_2 , 58 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV2_2 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_3 , 59 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV2_3 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_0 , 60 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV3_0 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_1 , 61 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV3_1 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_2 , 62 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV3_2 ); REG64_FLD( PU_NPU0_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_3 , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV3_3 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_0 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_1 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_2 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_3 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_4 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_5 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_6 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_7 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_0 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_1 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_2 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_3 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_4 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_5 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_6 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_7 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_8 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_9 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_10 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_11 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_0 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_1 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_2 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_3 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_4 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_5 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_6 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_7 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_8 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_9 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_10 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_11 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_0 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_1 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_2 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_3 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_4 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_5 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_6 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_7 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_0 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_1 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_2 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_3 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_4 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_5 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_6 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_7 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_8 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_9 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_10 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_11 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_0 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_1 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_2 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_3 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_4 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_5 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_6 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_7 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_8 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_9 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_10 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_11 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_1 , 1 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_2 , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_3 , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_4 , 4 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_5 , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_6 , 6 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_7 , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_8 , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_9 , 9 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_10 , 10 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_11 , 11 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_12 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_13 , 13 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_14 , 14 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_15 , 15 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_16 , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_17 , 17 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_18 , 18 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_19 , 19 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_20 , 20 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_21 , 21 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_22 , 22 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_23 , 23 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_24 , 24 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_25 , 25 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_26 , 26 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_27 , 27 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_28 , 28 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_29 , 29 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_30 , 30 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_31 , 31 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_32 , 32 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_33 , 33 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_34 , 34 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_35 , 35 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_36 , 36 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_37 , 37 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_38 , 38 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_39 , 39 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_40 , 40 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_41 , 41 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_42 , 42 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_43 , 43 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_44 , 44 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_45 , 45 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_46 , 46 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_47 , 47 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_48 , 48 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_49 , 49 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_50 , 50 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_51 , 51 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_52 , 52 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_53 , 53 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_54 , 54 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_55 , 55 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_56 , 56 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_57 , 57 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_58 , 58 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_59 , 59 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_60 , 60 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_61 , 61 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_62 , 62 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD1_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_0 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_1 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_2 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_3 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_4 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_5 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_6 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_7 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_0 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_1 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_2 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_3 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_4 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_5 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_6 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_7 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_8 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_9 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_10 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_11 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_0 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_1 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_2 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_3 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_4 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_5 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_6 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_7 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_8 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_9 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_10 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_11 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_0 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_1 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_2 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_3 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_4 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_5 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_6 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_7 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_0 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_1 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_2 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_3 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_4 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_5 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_6 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_7 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_8 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_9 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_10 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_11 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_0 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_1 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_2 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_3 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_4 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_5 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_6 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_7 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_8 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_9 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_10 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_11 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_0 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_1 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_2 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_3 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_4 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_5 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_6 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_7 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_0 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_1 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_2 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_3 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_4 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_5 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_6 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_7 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_8 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_9 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_10 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_11 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_0 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_1 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_2 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_3 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_4 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_5 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_6 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_7 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_8 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_9 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_10 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_11 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_0 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_1 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_2 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_3 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_4 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_5 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_6 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_7 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_8 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_9 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_10 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_11 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_12 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_13 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_14 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_15 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_0 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_1 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_2 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_3 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_4 , 20 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_4 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_5 , 21 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_5 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_6 , 22 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_6 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_7 , 23 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_7 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_0 , 24 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_0 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_1 , 25 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_1 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_2 , 26 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_2 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_3 , 27 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_3 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_4 , 28 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_4 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_5 , 29 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_5 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_6 , 30 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_6 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_7 , 31 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_7 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_0 , 32 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_0 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_1 , 33 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_1 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_2 , 34 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_2 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_3 , 35 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_3 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_4 , 36 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_4 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_5 , 37 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_5 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_6 , 38 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_6 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_7 , 39 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_7 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_0 , 40 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_0 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_1 , 41 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_1 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_2 , 42 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_2 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_3 , 43 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_3 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_4 , 44 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_4 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_5 , 45 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_5 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_6 , 46 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_6 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_7 , 47 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_7 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_0 , 48 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_0 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_1 , 49 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_1 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_2 , 50 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_2 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_3 , 51 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_3 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_4 , 52 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_4 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_5 , 53 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_5 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_6 , 54 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_6 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_7 , 55 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_7 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_0 , 56 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV2_0 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_1 , 57 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV2_1 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_2 , 58 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV2_2 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_3 , 59 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV2_3 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_0 , 60 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV3_0 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_1 , 61 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV3_1 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_2 , 62 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV3_2 ); REG64_FLD( PU_NPU1_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_3 , 63 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV3_3 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_0 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_1 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_2 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_3 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_4 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_5 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_6 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_7 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_0 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_1 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_2 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_3 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_4 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_5 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_6 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_7 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_8 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_9 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_10 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_11 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_0 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_1 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_2 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_3 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_4 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_5 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_6 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_7 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_8 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_9 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_10 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_11 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_0 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_1 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_2 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_3 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_4 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_5 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_6 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_7 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_0 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_1 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_2 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_3 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_4 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_5 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_6 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_7 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_8 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_9 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_10 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_11 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_0 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_1 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_2 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_3 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_4 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_5 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_6 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_7 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_8 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_9 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_10 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_11 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_0 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_1 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_2 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_3 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_4 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_5 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_6 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_7 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_8 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_9 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_10 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_11 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_12 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_13 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_14 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_NLG_15 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_0 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_1 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_2 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_3 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_4 , 20 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_4 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_5 , 21 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_5 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_6 , 22 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_6 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_FWD_7 , 23 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_FWD_7 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_0 , 24 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_0 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_1 , 25 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_1 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_2 , 26 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_2 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_3 , 27 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_3 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_4 , 28 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_4 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_5 , 29 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_5 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_6 , 30 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_6 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_AUE_7 , 31 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_AUE_7 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_0 , 32 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_0 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_1 , 33 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_1 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_2 , 34 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_2 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_3 , 35 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_3 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_4 , 36 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_4 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_5 , 37 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_5 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_6 , 38 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_6 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBP_7 , 39 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBP_7 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_0 , 40 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_0 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_1 , 41 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_1 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_2 , 42 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_2 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_3 , 43 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_3 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_4 , 44 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_4 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_5 , 45 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_5 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_6 , 46 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_6 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBF_7 , 47 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBF_7 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_0 , 48 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_0 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_1 , 49 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_1 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_2 , 50 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_2 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_3 , 51 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_3 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_4 , 52 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_4 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_5 , 53 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_5 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_6 , 54 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_6 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_PBC_7 , 55 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_PBC_7 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_0 , 56 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV2_0 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_1 , 57 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV2_1 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_2 , 58 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV2_2 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV2_3 , 59 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV2_3 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_0 , 60 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV3_0 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_1 , 61 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV3_1 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_2 , 62 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV3_2 ); REG64_FLD( PU_NPU2_CTL_CERR_HOLD1_IDIAL_CTL_HOLD_RSV3_3 , 63 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_HOLD_RSV3_3 ); REG64_FLD( NV_CERR_HOLD1_NTL_0 , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( NV_CERR_HOLD1_NTL_1 , 1 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( NV_CERR_HOLD1_NTL_2 , 2 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( NV_CERR_HOLD1_NTL_3 , 3 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( NV_CERR_HOLD1_NTL_4 , 4 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( NV_CERR_HOLD1_NTL_5 , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( NV_CERR_HOLD1_NTL_6 , 6 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( NV_CERR_HOLD1_NTL_7 , 7 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( NV_CERR_HOLD1_NTL_8 , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( NV_CERR_HOLD1_NTL_9 , 9 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( NV_CERR_HOLD1_NTL_10 , 10 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( NV_CERR_HOLD1_NTL_11 , 11 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( NV_CERR_HOLD1_NTL_12 , 12 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( NV_CERR_HOLD1_NTL_13 , 13 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( NV_CERR_HOLD1_NTL_14 , 14 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( NV_CERR_HOLD1_NTL_15 , 15 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( NV_CERR_HOLD1_NTL_16 , 16 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( NV_CERR_HOLD1_NTL_17 , 17 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( NV_CERR_HOLD1_NTL_18 , 18 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( NV_CERR_HOLD1_NTL_19 , 19 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( NV_CERR_HOLD1_NTL_20 , 20 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( NV_CERR_HOLD1_NTL_21 , 21 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( NV_CERR_HOLD1_NTL_22 , 22 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( NV_CERR_HOLD1_NTL_23 , 23 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( NV_CERR_HOLD1_NTL_24 , 24 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( NV_CERR_HOLD1_NTL_25 , 25 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( NV_CERR_HOLD1_NTL_26 , 26 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( NV_CERR_HOLD1_NTL_27 , 27 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( NV_CERR_HOLD1_NTL_28 , 28 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( NV_CERR_HOLD1_NTL_29 , 29 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( NV_CERR_HOLD1_NTL_30 , 30 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( NV_CERR_HOLD1_NTL_31 , 31 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( NV_CERR_HOLD1_NTL_32 , 32 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( NV_CERR_HOLD1_NTL_33 , 33 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( NV_CERR_HOLD1_NTL_34 , 34 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( NV_CERR_HOLD1_NTL_35 , 35 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( NV_CERR_HOLD1_NTL_36 , 36 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( NV_CERR_HOLD1_NTL_37 , 37 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( NV_CERR_HOLD1_NTL_38 , 38 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( NV_CERR_HOLD1_NTL_39 , 39 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( NV_CERR_HOLD1_NTL_40 , 40 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( NV_CERR_HOLD1_NTL_41 , 41 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( NV_CERR_HOLD1_NTL_42 , 42 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( NV_CERR_HOLD1_NTL_43 , 43 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( NV_CERR_HOLD1_NTL_44 , 44 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( NV_CERR_HOLD1_NTL_45 , 45 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( NV_CERR_HOLD1_NTL_46 , 46 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( NV_CERR_HOLD1_NTL_47 , 47 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( NV_CERR_HOLD1_NTL_48 , 48 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( NV_CERR_HOLD1_NTL_49 , 49 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( NV_CERR_HOLD1_NTL_50 , 50 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( NV_CERR_HOLD1_NTL_51 , 51 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( NV_CERR_HOLD1_NTL_52 , 52 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( NV_CERR_HOLD1_NTL_53 , 53 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( NV_CERR_HOLD1_NTL_54 , 54 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( NV_CERR_HOLD1_NTL_55 , 55 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( NV_CERR_HOLD1_NTL_56 , 56 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( NV_CERR_HOLD1_NTL_57 , 57 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( NV_CERR_HOLD1_NTL_58 , 58 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( NV_CERR_HOLD1_NTL_59 , 59 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( NV_CERR_HOLD1_NTL_60 , 60 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( NV_CERR_HOLD1_NTL_61 , 61 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( NV_CERR_HOLD1_NTL_62 , 62 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( NV_CERR_HOLD1_NTL_63 , 63 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_0 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_1 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_2 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_3 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_4 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_5 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_6 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_7 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_8 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_9 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_10 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_11 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_12 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_13 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_14 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLGX_15 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_0 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_0 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_1 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_1 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_2 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_2 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_FWD_3 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_FWD_3 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_0 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_0 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_1 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_1 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_2 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_2 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_AUE_3 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_AUE_3 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_0 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_0 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_1 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_1 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_2 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_2 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_3 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_3 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_4 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_4 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_5 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_5 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_6 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_6 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBP_7 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBP_7 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_0 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_0 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_1 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_1 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_2 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_2 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_3 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_3 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_4 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_4 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_5 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_5 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_6 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_6 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_7 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_7 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_8 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_8 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_9 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_9 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_10 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_10 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBF_11 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBF_11 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_0 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_0 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_1 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_1 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_2 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_2 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_3 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_3 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_4 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_4 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_5 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_5 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_6 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_6 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_7 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_7 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_8 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_8 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_9 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_9 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_10 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_10 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD1_IDIAL_SM_HOLD_PBC_11 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_PBC_11 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_0 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_1 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_2 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_3 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_4 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_5 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_6 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_7 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_8 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_9 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_10 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_11 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_12 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_13 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_14 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_15 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_16 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_17 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_18 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_19 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_20 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_21 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_22 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_23 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_24 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_25 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_26 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_27 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_28 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_29 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_30 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_31 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_32 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_33 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_34 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_35 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_36 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_37 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_38 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_39 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_40 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_41 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_42 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_43 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_44 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_45 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_46 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_47 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_48 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_49 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_50 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_51 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_52 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_53 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_54 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_55 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_56 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_57 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_58 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_59 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_60 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_61 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_62 ); REG64_FLD( PU_NPU0_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_63 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_1 , 1 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_2 , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_3 , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_4 , 4 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_5 , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_6 , 6 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_7 , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_8 , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_9 , 9 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_10 , 10 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_11 , 11 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_12 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_13 , 13 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_14 , 14 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_15 , 15 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_16 , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_17 , 17 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_18 , 18 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_19 , 19 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_20 , 20 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_21 , 21 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_22 , 22 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_23 , 23 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_24 , 24 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_25 , 25 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_26 , 26 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_27 , 27 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_28 , 28 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_29 , 29 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_30 , 30 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_31 , 31 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_32 , 32 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_33 , 33 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_34 , 34 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_35 , 35 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_36 , 36 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_37 , 37 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_38 , 38 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_39 , 39 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_40 , 40 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_41 , 41 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_42 , 42 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_43 , 43 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_44 , 44 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_45 , 45 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_46 , 46 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_47 , 47 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_48 , 48 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_49 , 49 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_50 , 50 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_51 , 51 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_52 , 52 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_53 , 53 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_54 , 54 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_55 , 55 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_56 , 56 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_57 , 57 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_58 , 58 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_59 , 59 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_60 , 60 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_61 , 61 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_62 , 62 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( PU_NPU2_NTL0_CERR_HOLD2_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_0 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_1 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_2 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_3 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_4 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_5 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_6 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_7 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_8 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_9 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_10 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_11 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_12 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_13 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_14 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_15 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_16 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_17 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_18 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_19 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_20 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_21 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_22 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_23 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_24 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_25 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_26 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_27 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_28 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_29 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_30 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_31 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_32 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_33 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_34 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_35 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_36 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_37 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_38 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_39 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_40 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_41 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_42 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_43 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_44 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_45 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_46 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_47 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_48 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_49 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_50 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_51 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_52 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_53 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_54 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_55 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_56 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_57 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_58 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_59 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_60 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_61 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_62 ); REG64_FLD( PU_NPU1_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_63 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_0 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_1 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_2 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_3 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_4 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_5 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_6 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_7 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_8 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_9 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_10 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_11 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_12 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_13 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_14 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_15 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_16 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_17 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_18 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_19 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_20 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_21 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_22 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_23 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_24 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_25 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_26 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_27 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_28 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_29 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_30 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_31 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_32 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_33 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_34 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_35 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_36 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_37 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_38 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_39 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_40 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_41 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_42 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_43 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_44 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_45 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_46 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_47 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_48 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_49 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_50 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_51 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_52 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_53 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_54 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_55 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_56 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_57 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_58 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_59 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_60 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_61 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_62 ); REG64_FLD( PU_NPU2_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_63 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_0 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_1 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_2 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_3 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_4 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_5 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_6 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_7 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_8 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_9 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_10 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_11 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_12 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_13 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_14 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_15 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_16 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_17 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_18 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_19 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_20 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_21 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_22 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_23 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_24 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_25 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_26 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_27 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_28 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_29 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_30 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_31 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_32 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_33 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_34 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_35 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_36 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_37 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_38 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_39 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_40 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_41 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_42 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_43 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_44 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_45 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_46 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_47 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_48 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_49 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_50 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_51 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_52 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_53 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_54 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_55 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_56 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_57 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_58 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_59 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_60 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_61 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_62 ); REG64_FLD( PU_NPU1_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_63 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_0 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_1 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_2 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_3 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_4 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_5 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_6 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_7 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_8 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_9 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_10 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_11 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_12 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_13 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_14 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_15 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_16 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_17 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_18 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_19 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_20 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_21 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_22 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_23 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_24 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_25 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_26 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_27 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_28 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_29 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_30 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_31 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_32 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_33 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_34 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_35 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_36 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_37 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_38 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_39 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_40 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_41 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_42 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_43 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_44 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_45 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_46 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_47 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_48 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_49 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_50 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_51 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_52 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_53 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_54 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_55 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_56 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_57 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_58 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_59 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_60 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_61 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_62 ); REG64_FLD( PU_NPU0_SM3_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_63 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_1 , 1 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_2 , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_3 , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_4 , 4 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_5 , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_6 , 6 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_7 , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_8 , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_9 , 9 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_10 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_11 , 11 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_12 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_13 , 13 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_14 , 14 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_15 , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_16 , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_17 , 17 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_18 , 18 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_19 , 19 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_20 , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_21 , 21 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_22 , 22 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_23 , 23 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_24 , 24 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_25 , 25 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_26 , 26 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_27 , 27 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_28 , 28 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_29 , 29 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_30 , 30 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_31 , 31 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_32 , 32 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_33 , 33 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_34 , 34 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_35 , 35 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_36 , 36 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_37 , 37 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_38 , 38 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_39 , 39 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_40 , 40 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_41 , 41 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_42 , 42 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_43 , 43 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_44 , 44 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_45 , 45 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_46 , 46 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_47 , 47 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_48 , 48 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_49 , 49 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_50 , 50 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_51 , 51 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_52 , 52 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_53 , 53 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_54 , 54 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_55 , 55 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_56 , 56 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_57 , 57 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_58 , 58 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_59 , 59 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_60 , 60 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_61 , 61 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_62 , 62 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( PU_NPU2_NTL1_CERR_HOLD2_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_0 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_1 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_2 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_3 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_4 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_5 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_6 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_7 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_8 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_9 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_10 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_11 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_12 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_13 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_14 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_15 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_16 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_17 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_18 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_19 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_20 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_21 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_22 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_23 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_24 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_25 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_26 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_27 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_28 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_29 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_30 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_31 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_32 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_33 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_34 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_35 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_36 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_37 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_38 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_39 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_40 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_41 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_42 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_43 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_44 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_45 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_46 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_47 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_48 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_49 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_50 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_51 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_52 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_53 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_54 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_55 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_56 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_57 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_58 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_59 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_60 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_61 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_62 ); REG64_FLD( PU_NPU1_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_63 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_0 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_1 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_2 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_3 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_4 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_5 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_6 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_7 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_8 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_9 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_10 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_11 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_12 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_13 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_14 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_15 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_16 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_17 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_18 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_19 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_20 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_21 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_22 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_23 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_24 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_25 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_26 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_27 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_28 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_29 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_30 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_31 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_32 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_33 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_34 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_35 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_36 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_37 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_38 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_39 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_40 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_41 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_42 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_43 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_44 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_45 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_46 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_47 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_48 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_49 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_50 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_51 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_52 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_53 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_54 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_55 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_56 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_57 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_58 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_59 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_60 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_61 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_62 ); REG64_FLD( PU_NPU2_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_63 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_0 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_1 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_2 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_3 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_4 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_5 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_6 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_7 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_8 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_9 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_10 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_11 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_12 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_13 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_14 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_15 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_16 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_17 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_18 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_19 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_20 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_21 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_22 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_23 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_24 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_25 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_26 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_27 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_28 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_29 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_30 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_31 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_32 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_33 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_34 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_35 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_36 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_37 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_38 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_39 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_40 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_41 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_42 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_43 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_44 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_45 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_46 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_47 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_48 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_49 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_50 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_51 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_52 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_53 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_54 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_55 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_56 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_57 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_58 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_59 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_60 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_61 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_62 ); REG64_FLD( PU_NPU2_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_63 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_0 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_1 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_2 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_3 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_4 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_5 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_6 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_7 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_8 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_9 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_10 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_11 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_12 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_13 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_14 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_15 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_16 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_17 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_18 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_19 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_20 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_21 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_22 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_23 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_24 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_25 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_26 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_27 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_28 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_29 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_30 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_31 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_32 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_33 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_34 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_35 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_36 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_37 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_38 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_39 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_40 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_41 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_42 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_43 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_44 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_45 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_46 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_47 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_48 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_49 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_50 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_51 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_52 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_53 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_54 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_55 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_56 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_57 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_58 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_59 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_60 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_61 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_62 ); REG64_FLD( PU_NPU0_SM2_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_63 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_0 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_1 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_2 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_3 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_4 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_5 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_6 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_7 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_8 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_9 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_10 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_11 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_12 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_13 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_14 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_15 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_16 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_17 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_18 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_19 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_20 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_21 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_22 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_23 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_24 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_25 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_26 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_27 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_28 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_29 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_30 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_31 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_32 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_33 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_34 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_35 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_36 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_37 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_38 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_39 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_40 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_41 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_42 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_43 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_44 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_45 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_46 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_47 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_48 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_49 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_50 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_51 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_52 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_53 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_54 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_55 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_56 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_57 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_58 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_59 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_60 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_61 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_62 ); REG64_FLD( PU_NPU2_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_63 ); REG64_FLD( NV_CERR_HOLD2_NTL_0 , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( NV_CERR_HOLD2_NTL_1 , 1 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( NV_CERR_HOLD2_NTL_2 , 2 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( NV_CERR_HOLD2_NTL_3 , 3 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( NV_CERR_HOLD2_NTL_4 , 4 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( NV_CERR_HOLD2_NTL_5 , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( NV_CERR_HOLD2_NTL_6 , 6 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( NV_CERR_HOLD2_NTL_7 , 7 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( NV_CERR_HOLD2_NTL_8 , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( NV_CERR_HOLD2_NTL_9 , 9 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( NV_CERR_HOLD2_NTL_10 , 10 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( NV_CERR_HOLD2_NTL_11 , 11 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( NV_CERR_HOLD2_NTL_12 , 12 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( NV_CERR_HOLD2_NTL_13 , 13 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( NV_CERR_HOLD2_NTL_14 , 14 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( NV_CERR_HOLD2_NTL_15 , 15 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( NV_CERR_HOLD2_NTL_16 , 16 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( NV_CERR_HOLD2_NTL_17 , 17 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( NV_CERR_HOLD2_NTL_18 , 18 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( NV_CERR_HOLD2_NTL_19 , 19 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( NV_CERR_HOLD2_NTL_20 , 20 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( NV_CERR_HOLD2_NTL_21 , 21 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( NV_CERR_HOLD2_NTL_22 , 22 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( NV_CERR_HOLD2_NTL_23 , 23 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( NV_CERR_HOLD2_NTL_24 , 24 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( NV_CERR_HOLD2_NTL_25 , 25 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( NV_CERR_HOLD2_NTL_26 , 26 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( NV_CERR_HOLD2_NTL_27 , 27 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( NV_CERR_HOLD2_NTL_28 , 28 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( NV_CERR_HOLD2_NTL_29 , 29 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( NV_CERR_HOLD2_NTL_30 , 30 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( NV_CERR_HOLD2_NTL_31 , 31 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( NV_CERR_HOLD2_NTL_32 , 32 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( NV_CERR_HOLD2_NTL_33 , 33 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( NV_CERR_HOLD2_NTL_34 , 34 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( NV_CERR_HOLD2_NTL_35 , 35 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( NV_CERR_HOLD2_NTL_36 , 36 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( NV_CERR_HOLD2_NTL_37 , 37 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( NV_CERR_HOLD2_NTL_38 , 38 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( NV_CERR_HOLD2_NTL_39 , 39 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( NV_CERR_HOLD2_NTL_40 , 40 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( NV_CERR_HOLD2_NTL_41 , 41 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( NV_CERR_HOLD2_NTL_42 , 42 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( NV_CERR_HOLD2_NTL_43 , 43 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( NV_CERR_HOLD2_NTL_44 , 44 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( NV_CERR_HOLD2_NTL_45 , 45 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( NV_CERR_HOLD2_NTL_46 , 46 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( NV_CERR_HOLD2_NTL_47 , 47 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( NV_CERR_HOLD2_NTL_48 , 48 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( NV_CERR_HOLD2_NTL_49 , 49 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( NV_CERR_HOLD2_NTL_50 , 50 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( NV_CERR_HOLD2_NTL_51 , 51 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( NV_CERR_HOLD2_NTL_52 , 52 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( NV_CERR_HOLD2_NTL_53 , 53 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( NV_CERR_HOLD2_NTL_54 , 54 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( NV_CERR_HOLD2_NTL_55 , 55 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( NV_CERR_HOLD2_NTL_56 , 56 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( NV_CERR_HOLD2_NTL_57 , 57 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( NV_CERR_HOLD2_NTL_58 , 58 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( NV_CERR_HOLD2_NTL_59 , 59 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( NV_CERR_HOLD2_NTL_60 , 60 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( NV_CERR_HOLD2_NTL_61 , 61 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( NV_CERR_HOLD2_NTL_62 , 62 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( NV_CERR_HOLD2_NTL_63 , 63 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_0 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_1 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_2 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_3 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_4 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_5 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_6 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_7 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_8 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_9 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_10 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_11 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_12 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_13 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_14 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_15 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_16 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_17 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_18 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_19 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_20 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_21 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_22 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_23 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_24 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_25 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_26 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_27 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_28 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_29 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_30 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_31 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_32 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_33 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_34 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_35 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_36 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_37 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_38 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_39 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_40 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_41 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_42 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_43 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_44 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_45 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_46 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_47 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_48 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_49 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_50 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_51 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_52 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_53 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_54 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_55 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_56 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_57 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_58 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_59 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_60 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_61 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_62 ); REG64_FLD( PU_NPU0_SM1_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_63 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_0 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_1 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_2 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_3 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_4 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_5 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_6 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_7 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_8 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_8 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_9 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_9 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_10 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_10 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_11 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_11 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_12 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_12 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_13 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_13 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_14 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_14 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_15 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_15 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_16 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_16 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_17 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_17 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_18 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_18 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_19 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_19 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_20 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_20 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_21 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_21 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_22 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_22 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_23 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_23 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_24 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_24 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_25 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_25 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_26 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_26 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_27 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_27 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_28 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_28 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_29 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_29 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_30 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_30 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_31 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_31 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_32 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_32 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_33 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_33 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_34 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_34 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_35 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_35 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_36 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_36 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_37 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_37 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_38 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_38 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_39 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_39 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_40 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_40 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_41 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_41 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_42 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_42 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_43 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_43 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_44 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_44 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_45 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_45 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_46 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_46 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_47 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_47 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_48 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_48 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_49 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_49 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_50 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_50 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_51 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_51 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_52 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_52 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_53 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_53 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_54 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_54 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_55 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_55 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_56 , 56 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_56 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_57 , 57 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_57 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_58 , 58 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_58 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_59 , 59 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_59 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_60 , 60 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_60 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_61 , 61 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_61 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_62 , 62 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_62 ); REG64_FLD( PU_NPU1_SM0_CERR_HOLD2_IDIAL_SM_HOLD_NLG_63 , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_HOLD_NLG_63 ); REG64_FLD( PU_NPU0_CERR_LOG_FIRST_BITS , 47 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU0_CERR_LOG_FIRST_BITS_LEN , 17 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); REG64_FLD( PU_NPU1_CERR_LOG_FIRST_BITS , 47 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU1_CERR_LOG_FIRST_BITS_LEN , 17 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); REG64_FLD( PU_NPU2_CERR_LOG_FIRST_BITS , 47 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU2_CERR_LOG_FIRST_BITS_LEN , 17 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_BBUF_RDWR , 47 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_BBUF_RDWR ); REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_IBUF_RDWR , 48 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_IBUF_RDWR ); REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_OBUF_RDWR , 49 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_OBUF_RDWR ); REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_RQIN_OVF , 50 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_RQIN_OVF ); REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_RQIN_OVF_LEN , 6 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_RQIN_OVF_LEN ); REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_IBUF_CTL_PIPE , 56 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_IBUF_CTL_PIPE ); REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_PBTX_PIPE , 57 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_PBTX_PIPE ); REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_MRG_IR_PIPE , 58 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_MRG_IR_PIPE ); REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_MRG_OR_PIPE , 59 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_MRG_OR_PIPE ); REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_AMO_ADDR , 60 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_AMO_ADDR ); REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_PBRX_RTAG , 61 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_PBRX_RTAG ); REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_IBUF_WRITE , 62 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_IBUF_WRITE ); REG64_FLD( PU_NPU0_CERR_LOG_HOLD_IDIAL_IBUF_WARB , 63 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_IBUF_WARB ); REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_BBUF_RDWR , 47 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_BBUF_RDWR ); REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_IBUF_RDWR , 48 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_IBUF_RDWR ); REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_OBUF_RDWR , 49 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_OBUF_RDWR ); REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_RQIN_OVF , 50 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_RQIN_OVF ); REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_RQIN_OVF_LEN , 6 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_RQIN_OVF_LEN ); REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_IBUF_CTL_PIPE , 56 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_IBUF_CTL_PIPE ); REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_PBTX_PIPE , 57 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_PBTX_PIPE ); REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_MRG_IR_PIPE , 58 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_MRG_IR_PIPE ); REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_MRG_OR_PIPE , 59 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_MRG_OR_PIPE ); REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_AMO_ADDR , 60 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_AMO_ADDR ); REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_PBRX_RTAG , 61 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_PBRX_RTAG ); REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_IBUF_WRITE , 62 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_IBUF_WRITE ); REG64_FLD( PU_NPU1_CERR_LOG_HOLD_IDIAL_IBUF_WARB , 63 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_IBUF_WARB ); REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_BBUF_RDWR , 47 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_BBUF_RDWR ); REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_IBUF_RDWR , 48 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_IBUF_RDWR ); REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_OBUF_RDWR , 49 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_OBUF_RDWR ); REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_RQIN_OVF , 50 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_RQIN_OVF ); REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_RQIN_OVF_LEN , 6 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_RQIN_OVF_LEN ); REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_IBUF_CTL_PIPE , 56 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_IBUF_CTL_PIPE ); REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_PBTX_PIPE , 57 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_PBTX_PIPE ); REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_MRG_IR_PIPE , 58 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_MRG_IR_PIPE ); REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_MRG_OR_PIPE , 59 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_MRG_OR_PIPE ); REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_AMO_ADDR , 60 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_AMO_ADDR ); REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_PBRX_RTAG , 61 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_PBRX_RTAG ); REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_IBUF_WRITE , 62 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_IBUF_WRITE ); REG64_FLD( PU_NPU2_CERR_LOG_HOLD_IDIAL_IBUF_WARB , 63 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_IBUF_WARB ); REG64_FLD( PU_NPU0_CERR_LOG_MASK_BITS , 47 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU0_CERR_LOG_MASK_BITS_LEN , 17 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); REG64_FLD( PU_NPU1_CERR_LOG_MASK_BITS , 47 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU1_CERR_LOG_MASK_BITS_LEN , 17 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); REG64_FLD( PU_NPU2_CERR_LOG_MASK_BITS , 47 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU2_CERR_LOG_MASK_BITS_LEN , 17 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_24 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_25 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_26 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_27 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_28 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_29 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_30 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_31 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_0 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_1 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_2 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_3 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_4 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_5 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_6 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_7 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_4 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_5 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_0 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_1 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_2 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_24 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_25 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_26 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_27 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_28 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_29 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_30 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_31 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_0 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_1 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_2 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_3 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_4 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_5 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_6 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_7 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_4 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_5 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_0 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_1 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_2 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_24 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_25 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_26 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_27 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_28 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_29 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_30 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_31 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_0 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_1 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_2 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_3 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_4 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_5 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_6 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_7 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_4 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_5 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_0 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_1 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_2 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_24 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_25 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_26 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_27 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_28 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_29 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_30 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_31 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_0 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_1 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_2 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_3 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_4 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_5 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_6 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_7 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_4 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_5 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_0 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_1 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_2 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_24 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_25 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_26 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_27 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_28 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_29 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_30 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_31 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_0 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_1 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_2 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_3 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_4 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_5 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_6 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_7 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_4 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_5 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_0 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_1 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_2 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_24 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_25 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_26 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_27 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_28 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_29 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_30 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_31 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_0 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_1 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_2 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_3 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_4 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_5 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_6 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_7 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_4 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_5 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_0 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_1 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_2 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_24 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_25 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_26 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_27 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_28 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_29 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_30 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_31 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_0 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_1 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_2 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_3 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_4 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_5 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_6 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_7 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_4 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_5 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_0 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_1 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_2 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_0 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_1 , 1 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_1 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_2 , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_2 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_3 , 3 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_3 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_4 , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_4 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_5 , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_5 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_6 , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_6 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_7 , 7 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_7 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_0 , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_0 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_1 , 9 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_1 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_2 , 10 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_2 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_3 , 11 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_3 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_4 , 12 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_4 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_5 , 13 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_5 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_6 , 14 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_6 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_7 , 15 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_7 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_8 , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_8 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_9 , 17 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_9 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_10 , 18 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_10 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_11 , 19 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_11 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_12 , 20 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_12 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_13 , 21 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_13 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_14 , 22 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_14 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_15 , 23 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_15 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_16 , 24 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_16 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_17 , 25 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_17 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_18 , 26 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_18 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_19 , 27 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_19 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_20 , 28 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_20 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_21 , 29 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_21 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_22 , 30 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_22 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_23 , 31 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_23 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_0 , 32 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV1_0 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_1 , 33 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV1_1 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_2 , 34 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV1_2 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_3 , 35 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV1_3 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_0 , 36 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_0 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_1 , 37 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_1 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_2 , 38 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_2 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_3 , 39 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_3 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_4 , 40 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_4 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_5 , 41 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_5 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_6 , 42 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_6 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_7 , 43 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_7 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_0 , 44 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_0 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_1 , 45 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_1 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_2 , 46 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_2 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_3 , 47 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_3 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_4 , 48 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_4 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_5 , 49 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_5 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_6 , 50 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_6 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_7 , 51 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_7 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_0 , 52 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_REG_0 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_1 , 53 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_REG_1 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_2 , 54 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_REG_2 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_3 , 55 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_REG_3 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_0 , 56 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_DUE_0 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_1 , 57 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_DUE_1 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_2 , 58 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_DUE_2 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_3 , 59 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_DUE_3 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_0 , 60 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PEF_0 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_1 , 61 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PEF_1 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_2 , 62 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PEF_2 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_3 , 63 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PEF_3 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_24 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_25 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_26 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_27 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_28 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_29 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_30 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_31 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_0 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_1 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_2 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_3 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_4 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_5 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_6 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_7 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_4 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_5 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_0 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_1 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_2 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_24 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_25 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_26 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_27 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_28 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_29 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_30 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_31 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_0 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_1 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_2 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_3 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_4 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_5 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_6 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_7 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_4 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_5 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_0 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_1 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_2 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_24 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_25 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_26 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_27 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_28 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_29 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_30 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_31 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_0 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_1 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_2 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_3 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_4 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_5 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_6 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_7 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_4 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_5 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_0 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_1 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_2 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_0 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_1 , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_1 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_2 , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_2 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_3 , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_3 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_4 , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_4 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_5 , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_5 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_6 , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_6 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_7 , 7 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_7 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_0 , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_0 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_1 , 9 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_1 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_2 , 10 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_2 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_3 , 11 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_3 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_4 , 12 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_4 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_5 , 13 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_5 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_6 , 14 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_6 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_7 , 15 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_7 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_8 , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_8 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_9 , 17 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_9 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_10 , 18 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_10 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_11 , 19 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_11 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_12 , 20 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_12 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_13 , 21 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_13 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_14 , 22 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_14 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_15 , 23 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_15 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_16 , 24 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_16 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_17 , 25 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_17 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_18 , 26 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_18 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_19 , 27 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_19 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_20 , 28 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_20 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_21 , 29 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_21 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_22 , 30 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_22 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_23 , 31 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_23 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_0 , 32 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV1_0 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_1 , 33 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV1_1 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_2 , 34 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV1_2 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_3 , 35 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV1_3 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_0 , 36 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_0 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_1 , 37 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_1 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_2 , 38 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_2 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_3 , 39 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_3 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_4 , 40 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_4 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_5 , 41 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_5 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_6 , 42 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_6 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_7 , 43 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_7 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_0 , 44 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_0 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_1 , 45 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_1 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_2 , 46 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_2 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_3 , 47 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_3 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_4 , 48 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_4 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_5 , 49 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_5 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_6 , 50 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_6 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_7 , 51 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_7 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_0 , 52 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_REG_0 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_1 , 53 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_REG_1 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_2 , 54 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_REG_2 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_3 , 55 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_REG_3 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_0 , 56 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_DUE_0 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_1 , 57 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_DUE_1 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_2 , 58 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_DUE_2 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_3 , 59 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_DUE_3 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_0 , 60 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PEF_0 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_1 , 61 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PEF_1 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_2 , 62 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PEF_2 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_3 , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PEF_3 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_0 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_1 , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_1 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_2 , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_2 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_3 , 3 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_3 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_4 , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_4 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_5 , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_5 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_6 , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_6 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NCF_7 , 7 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NCF_7 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_0 , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_0 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_1 , 9 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_1 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_2 , 10 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_2 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_3 , 11 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_3 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_4 , 12 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_4 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_5 , 13 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_5 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_6 , 14 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_6 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_7 , 15 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_7 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_8 , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_8 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_9 , 17 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_9 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_10 , 18 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_10 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_11 , 19 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_11 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_12 , 20 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_12 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_13 , 21 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_13 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_14 , 22 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_14 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_15 , 23 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_15 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_16 , 24 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_16 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_17 , 25 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_17 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_18 , 26 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_18 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_19 , 27 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_19 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_20 , 28 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_20 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_21 , 29 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_21 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_22 , 30 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_22 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_NVF_23 , 31 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NVF_23 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_0 , 32 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV1_0 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_1 , 33 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV1_1 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_2 , 34 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV1_2 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_RSV1_3 , 35 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV1_3 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_0 , 36 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_0 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_1 , 37 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_1 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_2 , 38 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_2 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_3 , 39 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_3 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_4 , 40 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_4 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_5 , 41 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_5 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_6 , 42 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_6 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_ASBE_7 , 43 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_ASBE_7 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_0 , 44 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_0 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_1 , 45 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_1 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_2 , 46 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_2 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_3 , 47 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_3 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_4 , 48 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_4 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_5 , 49 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_5 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_6 , 50 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_6 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PBR_7 , 51 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBR_7 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_0 , 52 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_REG_0 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_1 , 53 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_REG_1 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_2 , 54 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_REG_2 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_REG_3 , 55 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_REG_3 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_0 , 56 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_DUE_0 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_1 , 57 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_DUE_1 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_2 , 58 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_DUE_2 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_DUE_3 , 59 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_DUE_3 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_0 , 60 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PEF_0 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_1 , 61 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PEF_1 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_2 , 62 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PEF_2 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK0_IDIAL_CTL_MASK_PEF_3 , 63 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PEF_3 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_24 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_25 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_26 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_27 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_28 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_29 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_30 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_31 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_0 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_1 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_2 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_3 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_4 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_5 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_6 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_7 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_4 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_5 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_0 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_1 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_2 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_0 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_1 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_2 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_3 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_4 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_5 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_6 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_7 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_8 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_8 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_9 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_9 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_10 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_10 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_11 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_11 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_12 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_12 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_13 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_13 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_14 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_14 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_15 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_15 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_16 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_16 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_17 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_17 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_18 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_18 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_19 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_19 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_20 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_20 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_21 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_21 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_22 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_22 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_23 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_23 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_24 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_24 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_25 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_25 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_26 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_26 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_27 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_27 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_28 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_28 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_29 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_29 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_30 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_30 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NVF_31 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NVF_31 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_0 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_0 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_1 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_1 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_2 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_2 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_3 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_3 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_4 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_4 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_5 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_5 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_6 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_6 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_NCF_7 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NCF_7 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_0 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_0 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_1 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_1 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_2 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_2 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_ASBE_3 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_ASBE_3 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_0 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_0 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_1 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_1 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_2 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_2 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_3 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_3 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_4 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_4 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_5 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_5 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_6 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_6 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_PBR_7 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBR_7 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_0 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_0 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_1 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_1 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_2 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_2 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK0_IDIAL_SM_MASK_REG_3 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_REG_3 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_0 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_1 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_2 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_3 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_4 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_5 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_6 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_7 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_8 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_9 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_10 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_11 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_12 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_13 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_14 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_15 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_0 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_1 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_2 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_3 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_4 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_5 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_6 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_7 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_0 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_1 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_2 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_3 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_4 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_5 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_6 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_7 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_8 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_9 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_10 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_11 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_0 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_1 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_2 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_3 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_4 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_5 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_6 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_7 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_8 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_9 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_10 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_11 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_0 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_1 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_2 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_3 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_4 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_5 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_6 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_7 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_8 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_9 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_10 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_11 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_12 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_13 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_14 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_15 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_0 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_1 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_2 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_3 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_4 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_5 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_6 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_7 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_0 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_1 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_2 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_3 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_4 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_5 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_6 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_7 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_8 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_9 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_10 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_11 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_0 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_1 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_2 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_3 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_4 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_5 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_6 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_7 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_8 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_9 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_10 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_11 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_1 , 1 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_2 , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_3 , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_4 , 4 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_5 , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_6 , 6 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_7 , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_8 , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_9 , 9 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_10 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_11 , 11 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_12 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_13 , 13 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_14 , 14 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_15 , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_16 , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_17 , 17 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_18 , 18 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_19 , 19 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_20 , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_21 , 21 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_22 , 22 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_23 , 23 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_24 , 24 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_25 , 25 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_26 , 26 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_27 , 27 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_28 , 28 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_29 , 29 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_30 , 30 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_31 , 31 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_32 , 32 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_33 , 33 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_34 , 34 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_35 , 35 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_36 , 36 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_37 , 37 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_38 , 38 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_39 , 39 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_40 , 40 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_41 , 41 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_42 , 42 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_43 , 43 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_44 , 44 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_45 , 45 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_46 , 46 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_47 , 47 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_48 , 48 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_49 , 49 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_50 , 50 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_51 , 51 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_52 , 52 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_53 , 53 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_54 , 54 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_55 , 55 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_56 , 56 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_57 , 57 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_58 , 58 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_59 , 59 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_60 , 60 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_61 , 61 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_62 , 62 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK1_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_0 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_1 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_2 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_3 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_4 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_5 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_6 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_7 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_8 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_9 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_10 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_11 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_12 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_13 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_14 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_15 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_0 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_1 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_2 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_3 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_4 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_5 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_6 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_7 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_0 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_1 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_2 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_3 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_4 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_5 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_6 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_7 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_8 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_9 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_10 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_11 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_0 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_1 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_2 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_3 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_4 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_5 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_6 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_7 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_8 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_9 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_10 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_11 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_0 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_1 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_2 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_3 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_4 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_5 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_6 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_7 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_8 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_9 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_10 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_11 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_12 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_13 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_14 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_15 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_0 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_1 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_2 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_3 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_4 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_5 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_6 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_7 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_0 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_1 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_2 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_3 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_4 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_5 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_6 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_7 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_8 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_9 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_10 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_11 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_0 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_1 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_2 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_3 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_4 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_5 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_6 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_7 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_8 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_9 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_10 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_11 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_0 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_1 , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_1 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_2 , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_2 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_3 , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_3 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_4 , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_4 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_5 , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_5 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_6 , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_6 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_7 , 7 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_7 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_8 , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_8 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_9 , 9 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_9 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_10 , 10 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_10 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_11 , 11 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_11 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_12 , 12 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_12 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_13 , 13 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_13 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_14 , 14 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_14 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_15 , 15 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_15 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_0 , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_0 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_1 , 17 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_1 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_2 , 18 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_2 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_3 , 19 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_3 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_4 , 20 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_4 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_5 , 21 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_5 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_6 , 22 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_6 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_7 , 23 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_7 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_0 , 24 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_0 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_1 , 25 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_1 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_2 , 26 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_2 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_3 , 27 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_3 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_4 , 28 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_4 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_5 , 29 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_5 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_6 , 30 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_6 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_7 , 31 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_7 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_0 , 32 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_0 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_1 , 33 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_1 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_2 , 34 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_2 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_3 , 35 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_3 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_4 , 36 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_4 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_5 , 37 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_5 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_6 , 38 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_6 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_7 , 39 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_7 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_0 , 40 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_0 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_1 , 41 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_1 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_2 , 42 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_2 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_3 , 43 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_3 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_4 , 44 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_4 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_5 , 45 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_5 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_6 , 46 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_6 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_7 , 47 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_7 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_0 , 48 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_0 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_1 , 49 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_1 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_2 , 50 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_2 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_3 , 51 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_3 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_4 , 52 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_4 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_5 , 53 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_5 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_6 , 54 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_6 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_7 , 55 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_7 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_0 , 56 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV2_0 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_1 , 57 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV2_1 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_2 , 58 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV2_2 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_3 , 59 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV2_3 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_0 , 60 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV3_0 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_1 , 61 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV3_1 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_2 , 62 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV3_2 ); REG64_FLD( PU_NPU0_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_3 , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV3_3 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_0 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_1 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_2 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_3 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_4 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_5 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_6 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_7 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_8 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_9 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_10 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_11 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_12 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_13 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_14 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_15 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_0 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_1 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_2 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_3 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_4 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_5 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_6 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_7 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_0 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_1 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_2 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_3 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_4 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_5 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_6 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_7 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_8 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_9 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_10 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_11 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_0 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_1 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_2 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_3 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_4 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_5 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_6 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_7 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_8 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_9 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_10 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_11 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_0 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_1 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_2 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_3 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_4 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_5 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_6 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_7 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_8 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_9 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_10 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_11 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_12 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_13 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_14 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_15 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_0 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_1 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_2 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_3 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_4 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_5 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_6 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_7 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_0 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_1 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_2 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_3 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_4 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_5 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_6 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_7 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_8 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_9 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_10 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_11 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_0 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_1 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_2 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_3 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_4 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_5 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_6 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_7 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_8 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_9 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_10 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_11 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_1 , 1 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_2 , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_3 , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_4 , 4 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_5 , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_6 , 6 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_7 , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_8 , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_9 , 9 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_10 , 10 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_11 , 11 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_12 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_13 , 13 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_14 , 14 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_15 , 15 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_16 , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_17 , 17 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_18 , 18 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_19 , 19 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_20 , 20 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_21 , 21 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_22 , 22 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_23 , 23 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_24 , 24 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_25 , 25 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_26 , 26 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_27 , 27 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_28 , 28 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_29 , 29 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_30 , 30 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_31 , 31 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_32 , 32 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_33 , 33 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_34 , 34 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_35 , 35 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_36 , 36 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_37 , 37 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_38 , 38 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_39 , 39 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_40 , 40 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_41 , 41 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_42 , 42 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_43 , 43 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_44 , 44 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_45 , 45 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_46 , 46 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_47 , 47 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_48 , 48 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_49 , 49 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_50 , 50 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_51 , 51 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_52 , 52 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_53 , 53 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_54 , 54 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_55 , 55 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_56 , 56 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_57 , 57 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_58 , 58 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_59 , 59 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_60 , 60 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_61 , 61 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_62 , 62 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK1_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_0 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_1 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_2 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_3 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_4 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_5 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_6 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_7 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_8 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_9 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_10 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_11 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_12 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_13 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_14 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_15 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_0 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_1 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_2 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_3 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_4 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_5 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_6 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_7 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_0 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_1 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_2 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_3 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_4 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_5 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_6 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_7 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_8 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_9 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_10 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_11 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_0 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_1 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_2 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_3 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_4 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_5 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_6 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_7 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_8 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_9 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_10 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_11 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_0 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_1 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_2 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_3 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_4 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_5 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_6 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_7 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_8 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_9 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_10 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_11 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_12 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_13 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_14 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_15 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_0 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_1 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_2 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_3 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_4 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_5 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_6 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_7 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_0 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_1 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_2 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_3 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_4 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_5 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_6 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_7 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_8 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_9 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_10 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_11 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_0 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_1 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_2 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_3 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_4 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_5 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_6 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_7 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_8 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_9 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_10 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_11 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_0 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_1 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_2 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_3 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_4 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_5 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_6 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_7 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_8 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_9 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_10 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_11 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_12 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_13 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_14 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_15 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_0 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_1 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_2 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_3 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_4 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_5 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_6 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_7 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_0 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_1 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_2 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_3 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_4 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_5 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_6 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_7 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_8 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_9 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_10 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_11 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_0 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_1 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_2 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_3 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_4 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_5 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_6 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_7 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_8 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_9 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_10 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_11 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_0 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_1 , 1 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_1 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_2 , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_2 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_3 , 3 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_3 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_4 , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_4 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_5 , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_5 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_6 , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_6 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_7 , 7 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_7 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_8 , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_8 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_9 , 9 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_9 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_10 , 10 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_10 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_11 , 11 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_11 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_12 , 12 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_12 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_13 , 13 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_13 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_14 , 14 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_14 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_15 , 15 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_15 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_0 , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_0 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_1 , 17 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_1 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_2 , 18 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_2 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_3 , 19 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_3 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_4 , 20 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_4 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_5 , 21 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_5 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_6 , 22 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_6 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_7 , 23 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_7 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_0 , 24 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_0 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_1 , 25 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_1 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_2 , 26 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_2 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_3 , 27 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_3 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_4 , 28 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_4 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_5 , 29 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_5 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_6 , 30 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_6 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_7 , 31 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_7 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_0 , 32 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_0 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_1 , 33 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_1 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_2 , 34 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_2 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_3 , 35 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_3 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_4 , 36 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_4 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_5 , 37 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_5 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_6 , 38 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_6 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_7 , 39 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_7 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_0 , 40 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_0 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_1 , 41 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_1 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_2 , 42 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_2 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_3 , 43 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_3 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_4 , 44 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_4 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_5 , 45 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_5 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_6 , 46 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_6 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_7 , 47 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_7 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_0 , 48 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_0 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_1 , 49 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_1 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_2 , 50 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_2 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_3 , 51 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_3 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_4 , 52 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_4 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_5 , 53 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_5 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_6 , 54 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_6 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_7 , 55 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_7 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_0 , 56 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV2_0 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_1 , 57 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV2_1 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_2 , 58 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV2_2 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_3 , 59 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV2_3 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_0 , 60 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV3_0 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_1 , 61 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV3_1 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_2 , 62 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV3_2 ); REG64_FLD( PU_NPU1_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_3 , 63 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV3_3 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_0 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_1 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_2 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_3 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_4 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_5 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_6 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_7 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_8 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_9 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_10 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_11 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_12 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_13 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_14 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_15 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_0 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_1 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_2 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_3 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_4 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_5 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_6 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_7 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_0 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_1 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_2 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_3 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_4 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_5 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_6 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_7 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_8 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_9 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_10 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_11 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_0 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_1 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_2 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_3 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_4 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_5 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_6 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_7 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_8 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_9 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_10 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_11 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_0 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_1 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_2 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_3 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_4 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_5 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_6 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_7 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_8 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_9 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_10 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_11 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_12 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_13 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_14 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_15 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_0 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_1 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_2 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_3 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_4 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_5 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_6 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_7 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_0 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_1 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_2 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_3 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_4 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_5 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_6 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_7 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_8 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_9 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_10 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_11 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_0 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_1 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_2 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_3 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_4 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_5 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_6 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_7 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_8 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_9 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_10 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_11 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_0 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_1 , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_1 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_2 , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_2 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_3 , 3 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_3 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_4 , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_4 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_5 , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_5 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_6 , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_6 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_7 , 7 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_7 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_8 , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_8 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_9 , 9 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_9 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_10 , 10 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_10 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_11 , 11 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_11 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_12 , 12 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_12 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_13 , 13 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_13 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_14 , 14 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_14 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_NLG_15 , 15 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_NLG_15 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_0 , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_0 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_1 , 17 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_1 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_2 , 18 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_2 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_3 , 19 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_3 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_4 , 20 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_4 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_5 , 21 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_5 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_6 , 22 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_6 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_FWD_7 , 23 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_FWD_7 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_0 , 24 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_0 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_1 , 25 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_1 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_2 , 26 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_2 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_3 , 27 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_3 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_4 , 28 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_4 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_5 , 29 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_5 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_6 , 30 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_6 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_AUE_7 , 31 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_AUE_7 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_0 , 32 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_0 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_1 , 33 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_1 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_2 , 34 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_2 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_3 , 35 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_3 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_4 , 36 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_4 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_5 , 37 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_5 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_6 , 38 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_6 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBP_7 , 39 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBP_7 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_0 , 40 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_0 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_1 , 41 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_1 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_2 , 42 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_2 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_3 , 43 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_3 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_4 , 44 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_4 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_5 , 45 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_5 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_6 , 46 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_6 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBF_7 , 47 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBF_7 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_0 , 48 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_0 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_1 , 49 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_1 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_2 , 50 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_2 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_3 , 51 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_3 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_4 , 52 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_4 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_5 , 53 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_5 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_6 , 54 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_6 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_PBC_7 , 55 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_PBC_7 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_0 , 56 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV2_0 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_1 , 57 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV2_1 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_2 , 58 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV2_2 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV2_3 , 59 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV2_3 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_0 , 60 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV3_0 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_1 , 61 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV3_1 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_2 , 62 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV3_2 ); REG64_FLD( PU_NPU2_CTL_CERR_MASK1_IDIAL_CTL_MASK_RSV3_3 , 63 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CTL_MASK_RSV3_3 ); REG64_FLD( NV_CERR_MASK1_NTL_0 , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( NV_CERR_MASK1_NTL_1 , 1 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( NV_CERR_MASK1_NTL_2 , 2 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( NV_CERR_MASK1_NTL_3 , 3 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( NV_CERR_MASK1_NTL_4 , 4 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( NV_CERR_MASK1_NTL_5 , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( NV_CERR_MASK1_NTL_6 , 6 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( NV_CERR_MASK1_NTL_7 , 7 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( NV_CERR_MASK1_NTL_8 , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( NV_CERR_MASK1_NTL_9 , 9 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( NV_CERR_MASK1_NTL_10 , 10 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( NV_CERR_MASK1_NTL_11 , 11 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( NV_CERR_MASK1_NTL_12 , 12 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( NV_CERR_MASK1_NTL_13 , 13 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( NV_CERR_MASK1_NTL_14 , 14 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( NV_CERR_MASK1_NTL_15 , 15 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( NV_CERR_MASK1_NTL_16 , 16 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( NV_CERR_MASK1_NTL_17 , 17 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( NV_CERR_MASK1_NTL_18 , 18 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( NV_CERR_MASK1_NTL_19 , 19 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( NV_CERR_MASK1_NTL_20 , 20 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( NV_CERR_MASK1_NTL_21 , 21 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( NV_CERR_MASK1_NTL_22 , 22 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( NV_CERR_MASK1_NTL_23 , 23 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( NV_CERR_MASK1_NTL_24 , 24 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( NV_CERR_MASK1_NTL_25 , 25 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( NV_CERR_MASK1_NTL_26 , 26 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( NV_CERR_MASK1_NTL_27 , 27 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( NV_CERR_MASK1_NTL_28 , 28 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( NV_CERR_MASK1_NTL_29 , 29 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( NV_CERR_MASK1_NTL_30 , 30 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( NV_CERR_MASK1_NTL_31 , 31 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( NV_CERR_MASK1_NTL_32 , 32 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( NV_CERR_MASK1_NTL_33 , 33 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( NV_CERR_MASK1_NTL_34 , 34 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( NV_CERR_MASK1_NTL_35 , 35 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( NV_CERR_MASK1_NTL_36 , 36 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( NV_CERR_MASK1_NTL_37 , 37 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( NV_CERR_MASK1_NTL_38 , 38 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( NV_CERR_MASK1_NTL_39 , 39 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( NV_CERR_MASK1_NTL_40 , 40 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( NV_CERR_MASK1_NTL_41 , 41 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( NV_CERR_MASK1_NTL_42 , 42 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( NV_CERR_MASK1_NTL_43 , 43 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( NV_CERR_MASK1_NTL_44 , 44 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( NV_CERR_MASK1_NTL_45 , 45 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( NV_CERR_MASK1_NTL_46 , 46 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( NV_CERR_MASK1_NTL_47 , 47 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( NV_CERR_MASK1_NTL_48 , 48 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( NV_CERR_MASK1_NTL_49 , 49 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( NV_CERR_MASK1_NTL_50 , 50 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( NV_CERR_MASK1_NTL_51 , 51 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( NV_CERR_MASK1_NTL_52 , 52 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( NV_CERR_MASK1_NTL_53 , 53 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( NV_CERR_MASK1_NTL_54 , 54 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( NV_CERR_MASK1_NTL_55 , 55 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( NV_CERR_MASK1_NTL_56 , 56 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( NV_CERR_MASK1_NTL_57 , 57 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( NV_CERR_MASK1_NTL_58 , 58 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( NV_CERR_MASK1_NTL_59 , 59 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( NV_CERR_MASK1_NTL_60 , 60 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( NV_CERR_MASK1_NTL_61 , 61 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( NV_CERR_MASK1_NTL_62 , 62 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( NV_CERR_MASK1_NTL_63 , 63 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_0 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_1 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_2 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_3 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_4 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_5 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_6 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_7 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_8 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_8 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_9 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_9 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_10 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_10 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_11 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_11 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_12 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_12 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_13 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_13 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_14 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_14 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_NLGX_15 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLGX_15 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_0 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_0 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_1 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_1 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_2 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_2 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_FWD_3 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_FWD_3 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_0 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_0 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_1 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_1 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_2 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_2 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_AUE_3 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_AUE_3 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_0 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_0 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_1 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_1 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_2 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_2 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_3 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_3 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_4 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_4 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_5 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_5 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_6 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_6 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBP_7 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBP_7 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_0 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_0 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_1 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_1 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_2 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_2 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_3 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_3 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_4 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_4 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_5 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_5 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_6 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_6 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_7 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_7 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_8 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_8 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_9 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_9 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_10 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_10 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBF_11 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBF_11 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_0 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_0 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_1 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_1 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_2 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_2 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_3 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_3 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_4 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_4 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_5 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_5 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_6 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_6 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_7 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_7 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_8 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_8 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_9 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_9 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_10 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_10 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK1_IDIAL_SM_MASK_PBC_11 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_PBC_11 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_0 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_1 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_2 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_3 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_4 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_5 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_6 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_7 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_8 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_9 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_10 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_11 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_12 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_13 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_14 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_15 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_16 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_17 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_18 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_19 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_20 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_21 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_22 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_23 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_24 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_25 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_26 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_27 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_28 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_29 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_30 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_31 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_32 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_33 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_34 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_35 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_36 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_37 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_38 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_39 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_40 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_41 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_42 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_43 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_44 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_45 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_46 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_47 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_48 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_49 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_50 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_51 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_52 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_53 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_54 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_55 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_56 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_57 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_58 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_59 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_60 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_61 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_62 ); REG64_FLD( PU_NPU0_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_63 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_1 , 1 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_2 , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_3 , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_4 , 4 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_5 , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_6 , 6 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_7 , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_8 , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_9 , 9 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_10 , 10 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_11 , 11 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_12 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_13 , 13 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_14 , 14 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_15 , 15 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_16 , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_17 , 17 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_18 , 18 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_19 , 19 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_20 , 20 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_21 , 21 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_22 , 22 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_23 , 23 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_24 , 24 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_25 , 25 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_26 , 26 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_27 , 27 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_28 , 28 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_29 , 29 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_30 , 30 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_31 , 31 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_32 , 32 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_33 , 33 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_34 , 34 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_35 , 35 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_36 , 36 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_37 , 37 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_38 , 38 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_39 , 39 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_40 , 40 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_41 , 41 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_42 , 42 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_43 , 43 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_44 , 44 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_45 , 45 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_46 , 46 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_47 , 47 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_48 , 48 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_49 , 49 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_50 , 50 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_51 , 51 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_52 , 52 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_53 , 53 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_54 , 54 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_55 , 55 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_56 , 56 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_57 , 57 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_58 , 58 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_59 , 59 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_60 , 60 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_61 , 61 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_62 , 62 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( PU_NPU2_NTL0_CERR_MASK2_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_0 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_1 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_2 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_3 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_4 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_5 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_6 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_7 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_8 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_9 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_10 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_11 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_12 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_13 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_14 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_15 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_16 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_17 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_18 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_19 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_20 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_21 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_22 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_23 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_24 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_25 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_26 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_27 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_28 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_29 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_30 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_31 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_32 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_33 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_34 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_35 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_36 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_37 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_38 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_39 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_40 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_41 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_42 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_43 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_44 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_45 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_46 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_47 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_48 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_49 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_50 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_51 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_52 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_53 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_54 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_55 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_56 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_57 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_58 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_59 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_60 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_61 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_62 ); REG64_FLD( PU_NPU1_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_63 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_0 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_1 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_2 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_3 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_4 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_5 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_6 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_7 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_8 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_9 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_10 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_11 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_12 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_13 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_14 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_15 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_16 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_17 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_18 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_19 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_20 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_21 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_22 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_23 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_24 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_25 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_26 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_27 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_28 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_29 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_30 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_31 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_32 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_33 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_34 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_35 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_36 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_37 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_38 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_39 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_40 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_41 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_42 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_43 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_44 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_45 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_46 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_47 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_48 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_49 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_50 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_51 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_52 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_53 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_54 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_55 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_56 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_57 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_58 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_59 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_60 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_61 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_62 ); REG64_FLD( PU_NPU2_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_63 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_0 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_1 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_2 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_3 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_4 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_5 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_6 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_7 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_8 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_9 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_10 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_11 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_12 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_13 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_14 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_15 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_16 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_17 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_18 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_19 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_20 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_21 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_22 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_23 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_24 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_25 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_26 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_27 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_28 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_29 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_30 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_31 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_32 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_33 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_34 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_35 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_36 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_37 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_38 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_39 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_40 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_41 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_42 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_43 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_44 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_45 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_46 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_47 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_48 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_49 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_50 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_51 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_52 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_53 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_54 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_55 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_56 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_57 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_58 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_59 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_60 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_61 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_62 ); REG64_FLD( PU_NPU1_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_63 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_0 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_1 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_2 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_3 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_4 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_5 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_6 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_7 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_8 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_9 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_10 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_11 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_12 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_13 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_14 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_15 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_16 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_17 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_18 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_19 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_20 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_21 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_22 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_23 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_24 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_25 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_26 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_27 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_28 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_29 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_30 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_31 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_32 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_33 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_34 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_35 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_36 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_37 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_38 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_39 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_40 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_41 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_42 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_43 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_44 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_45 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_46 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_47 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_48 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_49 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_50 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_51 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_52 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_53 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_54 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_55 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_56 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_57 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_58 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_59 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_60 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_61 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_62 ); REG64_FLD( PU_NPU0_SM3_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_63 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_1 , 1 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_2 , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_3 , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_4 , 4 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_5 , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_6 , 6 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_7 , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_8 , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_9 , 9 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_10 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_11 , 11 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_12 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_13 , 13 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_14 , 14 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_15 , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_16 , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_17 , 17 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_18 , 18 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_19 , 19 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_20 , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_21 , 21 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_22 , 22 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_23 , 23 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_24 , 24 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_25 , 25 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_26 , 26 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_27 , 27 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_28 , 28 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_29 , 29 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_30 , 30 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_31 , 31 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_32 , 32 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_33 , 33 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_34 , 34 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_35 , 35 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_36 , 36 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_37 , 37 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_38 , 38 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_39 , 39 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_40 , 40 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_41 , 41 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_42 , 42 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_43 , 43 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_44 , 44 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_45 , 45 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_46 , 46 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_47 , 47 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_48 , 48 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_49 , 49 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_50 , 50 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_51 , 51 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_52 , 52 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_53 , 53 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_54 , 54 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_55 , 55 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_56 , 56 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_57 , 57 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_58 , 58 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_59 , 59 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_60 , 60 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_61 , 61 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_62 , 62 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( PU_NPU2_NTL1_CERR_MASK2_NTL_63 , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_0 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_1 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_2 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_3 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_4 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_5 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_6 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_7 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_8 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_9 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_10 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_11 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_12 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_13 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_14 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_15 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_16 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_17 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_18 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_19 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_20 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_21 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_22 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_23 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_24 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_25 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_26 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_27 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_28 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_29 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_30 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_31 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_32 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_33 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_34 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_35 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_36 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_37 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_38 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_39 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_40 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_41 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_42 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_43 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_44 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_45 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_46 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_47 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_48 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_49 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_50 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_51 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_52 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_53 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_54 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_55 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_56 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_57 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_58 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_59 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_60 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_61 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_62 ); REG64_FLD( PU_NPU1_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_63 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_0 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_1 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_2 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_3 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_4 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_5 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_6 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_7 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_8 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_9 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_10 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_11 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_12 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_13 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_14 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_15 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_16 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_17 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_18 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_19 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_20 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_21 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_22 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_23 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_24 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_25 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_26 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_27 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_28 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_29 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_30 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_31 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_32 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_33 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_34 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_35 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_36 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_37 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_38 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_39 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_40 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_41 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_42 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_43 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_44 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_45 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_46 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_47 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_48 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_49 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_50 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_51 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_52 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_53 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_54 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_55 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_56 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_57 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_58 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_59 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_60 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_61 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_62 ); REG64_FLD( PU_NPU2_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_63 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_0 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_1 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_2 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_3 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_4 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_5 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_6 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_7 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_8 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_9 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_10 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_11 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_12 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_13 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_14 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_15 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_16 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_17 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_18 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_19 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_20 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_21 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_22 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_23 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_24 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_25 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_26 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_27 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_28 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_29 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_30 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_31 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_32 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_33 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_34 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_35 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_36 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_37 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_38 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_39 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_40 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_41 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_42 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_43 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_44 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_45 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_46 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_47 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_48 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_49 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_50 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_51 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_52 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_53 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_54 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_55 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_56 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_57 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_58 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_59 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_60 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_61 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_62 ); REG64_FLD( PU_NPU2_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_63 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_0 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_1 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_2 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_3 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_4 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_5 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_6 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_7 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_8 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_9 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_10 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_11 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_12 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_13 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_14 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_15 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_16 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_17 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_18 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_19 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_20 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_21 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_22 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_23 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_24 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_25 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_26 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_27 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_28 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_29 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_30 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_31 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_32 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_33 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_34 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_35 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_36 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_37 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_38 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_39 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_40 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_41 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_42 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_43 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_44 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_45 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_46 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_47 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_48 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_49 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_50 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_51 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_52 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_53 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_54 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_55 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_56 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_57 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_58 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_59 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_60 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_61 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_62 ); REG64_FLD( PU_NPU0_SM2_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_63 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_0 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_1 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_2 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_3 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_4 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_5 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_6 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_7 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_8 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_9 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_10 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_11 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_12 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_13 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_14 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_15 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_16 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_17 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_18 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_19 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_20 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_21 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_22 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_23 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_24 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_25 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_26 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_27 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_28 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_29 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_30 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_31 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_32 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_33 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_34 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_35 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_36 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_37 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_38 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_39 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_40 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_41 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_42 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_43 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_44 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_45 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_46 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_47 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_48 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_49 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_50 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_51 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_52 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_53 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_54 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_55 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_56 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_57 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_58 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_59 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_60 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_61 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_62 ); REG64_FLD( PU_NPU2_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_63 ); REG64_FLD( NV_CERR_MASK2_NTL_0 , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_0 ); REG64_FLD( NV_CERR_MASK2_NTL_1 , 1 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_1 ); REG64_FLD( NV_CERR_MASK2_NTL_2 , 2 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_2 ); REG64_FLD( NV_CERR_MASK2_NTL_3 , 3 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_3 ); REG64_FLD( NV_CERR_MASK2_NTL_4 , 4 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_4 ); REG64_FLD( NV_CERR_MASK2_NTL_5 , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_5 ); REG64_FLD( NV_CERR_MASK2_NTL_6 , 6 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_6 ); REG64_FLD( NV_CERR_MASK2_NTL_7 , 7 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_7 ); REG64_FLD( NV_CERR_MASK2_NTL_8 , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_8 ); REG64_FLD( NV_CERR_MASK2_NTL_9 , 9 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_9 ); REG64_FLD( NV_CERR_MASK2_NTL_10 , 10 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_10 ); REG64_FLD( NV_CERR_MASK2_NTL_11 , 11 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_11 ); REG64_FLD( NV_CERR_MASK2_NTL_12 , 12 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_12 ); REG64_FLD( NV_CERR_MASK2_NTL_13 , 13 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_13 ); REG64_FLD( NV_CERR_MASK2_NTL_14 , 14 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_14 ); REG64_FLD( NV_CERR_MASK2_NTL_15 , 15 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_15 ); REG64_FLD( NV_CERR_MASK2_NTL_16 , 16 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_16 ); REG64_FLD( NV_CERR_MASK2_NTL_17 , 17 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_17 ); REG64_FLD( NV_CERR_MASK2_NTL_18 , 18 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_18 ); REG64_FLD( NV_CERR_MASK2_NTL_19 , 19 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_19 ); REG64_FLD( NV_CERR_MASK2_NTL_20 , 20 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_20 ); REG64_FLD( NV_CERR_MASK2_NTL_21 , 21 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_21 ); REG64_FLD( NV_CERR_MASK2_NTL_22 , 22 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_22 ); REG64_FLD( NV_CERR_MASK2_NTL_23 , 23 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_23 ); REG64_FLD( NV_CERR_MASK2_NTL_24 , 24 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_24 ); REG64_FLD( NV_CERR_MASK2_NTL_25 , 25 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_25 ); REG64_FLD( NV_CERR_MASK2_NTL_26 , 26 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_26 ); REG64_FLD( NV_CERR_MASK2_NTL_27 , 27 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_27 ); REG64_FLD( NV_CERR_MASK2_NTL_28 , 28 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_28 ); REG64_FLD( NV_CERR_MASK2_NTL_29 , 29 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_29 ); REG64_FLD( NV_CERR_MASK2_NTL_30 , 30 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_30 ); REG64_FLD( NV_CERR_MASK2_NTL_31 , 31 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_31 ); REG64_FLD( NV_CERR_MASK2_NTL_32 , 32 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_32 ); REG64_FLD( NV_CERR_MASK2_NTL_33 , 33 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_33 ); REG64_FLD( NV_CERR_MASK2_NTL_34 , 34 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_34 ); REG64_FLD( NV_CERR_MASK2_NTL_35 , 35 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_35 ); REG64_FLD( NV_CERR_MASK2_NTL_36 , 36 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_36 ); REG64_FLD( NV_CERR_MASK2_NTL_37 , 37 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_37 ); REG64_FLD( NV_CERR_MASK2_NTL_38 , 38 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_38 ); REG64_FLD( NV_CERR_MASK2_NTL_39 , 39 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_39 ); REG64_FLD( NV_CERR_MASK2_NTL_40 , 40 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_40 ); REG64_FLD( NV_CERR_MASK2_NTL_41 , 41 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_41 ); REG64_FLD( NV_CERR_MASK2_NTL_42 , 42 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_42 ); REG64_FLD( NV_CERR_MASK2_NTL_43 , 43 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_43 ); REG64_FLD( NV_CERR_MASK2_NTL_44 , 44 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_44 ); REG64_FLD( NV_CERR_MASK2_NTL_45 , 45 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_45 ); REG64_FLD( NV_CERR_MASK2_NTL_46 , 46 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_46 ); REG64_FLD( NV_CERR_MASK2_NTL_47 , 47 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_47 ); REG64_FLD( NV_CERR_MASK2_NTL_48 , 48 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_48 ); REG64_FLD( NV_CERR_MASK2_NTL_49 , 49 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_49 ); REG64_FLD( NV_CERR_MASK2_NTL_50 , 50 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_50 ); REG64_FLD( NV_CERR_MASK2_NTL_51 , 51 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_51 ); REG64_FLD( NV_CERR_MASK2_NTL_52 , 52 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_52 ); REG64_FLD( NV_CERR_MASK2_NTL_53 , 53 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_53 ); REG64_FLD( NV_CERR_MASK2_NTL_54 , 54 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_54 ); REG64_FLD( NV_CERR_MASK2_NTL_55 , 55 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_55 ); REG64_FLD( NV_CERR_MASK2_NTL_56 , 56 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_56 ); REG64_FLD( NV_CERR_MASK2_NTL_57 , 57 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_57 ); REG64_FLD( NV_CERR_MASK2_NTL_58 , 58 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_58 ); REG64_FLD( NV_CERR_MASK2_NTL_59 , 59 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_59 ); REG64_FLD( NV_CERR_MASK2_NTL_60 , 60 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_60 ); REG64_FLD( NV_CERR_MASK2_NTL_61 , 61 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_61 ); REG64_FLD( NV_CERR_MASK2_NTL_62 , 62 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_62 ); REG64_FLD( NV_CERR_MASK2_NTL_63 , 63 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_63 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_0 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_1 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_2 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_3 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_4 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_5 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_6 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_7 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_8 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_9 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_10 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_11 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_12 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_13 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_14 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_15 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_16 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_17 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_18 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_19 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_20 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_21 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_22 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_23 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_24 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_25 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_26 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_27 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_28 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_29 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_30 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_31 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_32 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_33 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_34 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_35 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_36 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_37 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_38 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_39 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_40 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_41 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_42 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_43 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_44 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_45 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_46 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_47 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_48 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_49 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_50 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_51 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_52 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_53 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_54 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_55 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_56 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_57 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_58 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_59 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_60 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_61 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_62 ); REG64_FLD( PU_NPU0_SM1_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_63 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_0 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_1 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_2 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_3 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_3 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_4 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_4 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_5 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_5 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_6 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_6 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_7 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_7 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_8 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_8 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_9 , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_9 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_10 , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_10 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_11 , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_11 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_12 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_12 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_13 , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_13 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_14 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_14 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_15 , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_15 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_16 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_16 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_17 , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_17 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_18 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_18 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_19 , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_19 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_20 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_20 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_21 , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_21 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_22 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_22 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_23 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_23 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_24 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_24 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_25 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_25 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_26 , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_26 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_27 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_27 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_28 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_28 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_29 , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_29 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_30 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_30 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_31 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_31 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_32 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_32 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_33 , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_33 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_34 , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_34 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_35 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_35 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_36 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_36 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_37 , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_37 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_38 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_38 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_39 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_39 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_40 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_40 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_41 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_41 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_42 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_42 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_43 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_43 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_44 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_44 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_45 , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_45 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_46 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_46 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_47 , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_47 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_48 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_48 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_49 , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_49 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_50 , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_50 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_51 , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_51 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_52 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_52 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_53 , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_53 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_54 , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_54 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_55 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_55 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_56 , 56 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_56 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_57 , 57 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_57 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_58 , 58 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_58 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_59 , 59 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_59 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_60 , 60 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_60 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_61 , 61 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_61 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_62 , 62 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_62 ); REG64_FLD( PU_NPU1_SM0_CERR_MASK2_IDIAL_SM_MASK_NLG_63 , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_IDIAL_SM_MASK_NLG_63 ); REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0 ); REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0_LEN ); REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0 ); REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0_LEN ); REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0 ); REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0_LEN ); REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0 ); REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0_LEN ); REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0 ); REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0_LEN ); REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0 ); REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0_LEN ); REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0 ); REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0_LEN ); REG64_FLD( PU_NPU1_CTL_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0 ); REG64_FLD( PU_NPU1_CTL_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0_LEN ); REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0 ); REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0_LEN ); REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0 ); REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0_LEN ); REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0 ); REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0_LEN ); REG64_FLD( PU_NPU0_CTL_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0 ); REG64_FLD( PU_NPU0_CTL_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0_LEN ); REG64_FLD( PU_NPU2_CTL_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0 ); REG64_FLD( PU_NPU2_CTL_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0_LEN ); REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0 ); REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0_LEN ); REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE0_MESSAGE_BITS0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0 ); REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE0_MESSAGE_BITS0_LEN , 64 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS0_LEN ); REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1 ); REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1_LEN ); REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1 ); REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1_LEN ); REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1 ); REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1_LEN ); REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1 ); REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1_LEN ); REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1 ); REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1_LEN ); REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1 ); REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1_LEN ); REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1 ); REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1_LEN ); REG64_FLD( PU_NPU1_CTL_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1 ); REG64_FLD( PU_NPU1_CTL_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1_LEN ); REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1 ); REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1_LEN ); REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1 ); REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1_LEN ); REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1 ); REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1_LEN ); REG64_FLD( PU_NPU0_CTL_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1 ); REG64_FLD( PU_NPU0_CTL_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1_LEN ); REG64_FLD( PU_NPU2_CTL_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1 ); REG64_FLD( PU_NPU2_CTL_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1_LEN ); REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1 ); REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1_LEN ); REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE1_MESSAGE_BITS1 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1 ); REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE1_MESSAGE_BITS1_LEN , 64 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS1_LEN ); REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2 ); REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2_LEN ); REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2 ); REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2_LEN ); REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2 ); REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2_LEN ); REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2 ); REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2_LEN ); REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2 ); REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2_LEN ); REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2 ); REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2_LEN ); REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2 ); REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2_LEN ); REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2 ); REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2_LEN ); REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2 ); REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2_LEN ); REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2 ); REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2_LEN ); REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2 ); REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2_LEN ); REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE2_MESSAGE_BITS2 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2 ); REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE2_MESSAGE_BITS2_LEN , 64 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS2_LEN ); REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3 ); REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3_LEN ); REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3 ); REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3_LEN ); REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3 ); REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3_LEN ); REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3 ); REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3_LEN ); REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3 ); REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3_LEN ); REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3 ); REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3_LEN ); REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3 ); REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3_LEN ); REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3 ); REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3_LEN ); REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3 ); REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3_LEN ); REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3 ); REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3_LEN ); REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3 ); REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3_LEN ); REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE3_MESSAGE_BITS3 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3 ); REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE3_MESSAGE_BITS3_LEN , 64 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS3_LEN ); REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4 ); REG64_FLD( PU_NPU0_SM0_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4_LEN ); REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4 ); REG64_FLD( PU_NPU1_SM2_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4_LEN ); REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4 ); REG64_FLD( PU_NPU2_SM3_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4_LEN ); REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4 ); REG64_FLD( PU_NPU1_SM3_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4_LEN ); REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4 ); REG64_FLD( PU_NPU0_SM3_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4_LEN ); REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4 ); REG64_FLD( PU_NPU1_SM1_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4_LEN ); REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4 ); REG64_FLD( PU_NPU2_SM2_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4_LEN ); REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4 ); REG64_FLD( PU_NPU2_SM1_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4_LEN ); REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4 ); REG64_FLD( PU_NPU0_SM2_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4_LEN ); REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4 ); REG64_FLD( PU_NPU2_SM0_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4_LEN ); REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4 ); REG64_FLD( PU_NPU0_SM1_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4_LEN ); REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE4_MESSAGE_BITS4 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4 ); REG64_FLD( PU_NPU1_SM0_CERR_MESSAGE4_MESSAGE_BITS4_LEN , 64 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_MESSAGE_BITS4_LEN ); REG64_FLD( PU_NPU0_CERR_PTY_FIRST_BITS , 37 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU0_CERR_PTY_FIRST_BITS_LEN , 27 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); REG64_FLD( PU_NPU1_CERR_PTY_FIRST_BITS , 37 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU1_CERR_PTY_FIRST_BITS_LEN , 27 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); REG64_FLD( PU_NPU2_CERR_PTY_FIRST_BITS , 37 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU2_CERR_PTY_FIRST_BITS_LEN , 27 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_INHIBIT_CONFIG , 37 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_INHIBIT_CONFIG ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_MISC_STATE , 38 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_MISC_STATE ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_MRG_STATE , 39 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_MRG_STATE ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_OBUF_STATE , 40 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_OBUF_STATE ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_PBTX_STATE , 41 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_PBTX_STATE ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_RQIN_STATE , 42 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_RQIN_STATE ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_IBUF_STATE , 43 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_IBUF_STATE ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_ERRINJ , 44 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_ERRINJ ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_PBTX_AMO , 45 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_PBTX_AMO ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_PBTX_AMO_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_PBTX_AMO_LEN ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_IBRD , 49 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_IBRD ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_IBRD_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_IBRD_LEN ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_OBRD , 53 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_OBRD ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_OBRD_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_OBRD_LEN ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_BBRD , 57 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_BBRD ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_BBRD_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_BBRD_LEN ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_PBRX_RTAG , 59 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_PBRX_RTAG ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_ECC_CONFIG , 60 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_ECC_CONFIG ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_CONFIG1 , 61 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_CONFIG1 ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_DEBUG0_CONFIG , 62 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_DEBUG0_CONFIG ); REG64_FLD( PU_NPU0_CERR_PTY_HOLD_IDIAL_DEBUG1_CONFIG , 63 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_DEBUG1_CONFIG ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_INHIBIT_CONFIG , 37 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_INHIBIT_CONFIG ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_MISC_STATE , 38 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_MISC_STATE ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_MRG_STATE , 39 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_MRG_STATE ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_OBUF_STATE , 40 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_OBUF_STATE ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_PBTX_STATE , 41 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_PBTX_STATE ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_RQIN_STATE , 42 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_RQIN_STATE ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_IBUF_STATE , 43 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_IBUF_STATE ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_ERRINJ , 44 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_ERRINJ ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_PBTX_AMO , 45 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_PBTX_AMO ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_PBTX_AMO_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_PBTX_AMO_LEN ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_IBRD , 49 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_IBRD ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_IBRD_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_IBRD_LEN ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_OBRD , 53 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_OBRD ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_OBRD_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_OBRD_LEN ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_BBRD , 57 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_BBRD ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_BBRD_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_BBRD_LEN ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_PBRX_RTAG , 59 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_PBRX_RTAG ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_ECC_CONFIG , 60 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_ECC_CONFIG ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_CONFIG1 , 61 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_CONFIG1 ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_DEBUG0_CONFIG , 62 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_DEBUG0_CONFIG ); REG64_FLD( PU_NPU1_CERR_PTY_HOLD_IDIAL_DEBUG1_CONFIG , 63 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_DEBUG1_CONFIG ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_INHIBIT_CONFIG , 37 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_INHIBIT_CONFIG ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_MISC_STATE , 38 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_MISC_STATE ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_MRG_STATE , 39 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_MRG_STATE ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_OBUF_STATE , 40 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_OBUF_STATE ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_PBTX_STATE , 41 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_PBTX_STATE ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_RQIN_STATE , 42 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_RQIN_STATE ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_IBUF_STATE , 43 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_IBUF_STATE ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_ERRINJ , 44 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_ERRINJ ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_PBTX_AMO , 45 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_PBTX_AMO ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_PBTX_AMO_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_PBTX_AMO_LEN ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_IBRD , 49 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_IBRD ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_IBRD_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_IBRD_LEN ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_OBRD , 53 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_OBRD ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_OBRD_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_OBRD_LEN ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_BBRD , 57 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_BBRD ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_BBRD_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_BBRD_LEN ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_PBRX_RTAG , 59 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_PBRX_RTAG ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_ECC_CONFIG , 60 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_ECC_CONFIG ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_CONFIG1 , 61 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_CONFIG1 ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_DEBUG0_CONFIG , 62 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_DEBUG0_CONFIG ); REG64_FLD( PU_NPU2_CERR_PTY_HOLD_IDIAL_DEBUG1_CONFIG , 63 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_DEBUG1_CONFIG ); REG64_FLD( PU_NPU0_CERR_PTY_MASK_BITS , 37 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU0_CERR_PTY_MASK_BITS_LEN , 27 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); REG64_FLD( PU_NPU1_CERR_PTY_MASK_BITS , 37 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU1_CERR_PTY_MASK_BITS_LEN , 27 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); REG64_FLD( PU_NPU2_CERR_PTY_MASK_BITS , 37 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU2_CERR_PTY_MASK_BITS_LEN , 27 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BITS_LEN ); REG64_FLD( PEC_CLK_REGION_CLOCK_CMD , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CLOCK_CMD ); REG64_FLD( PEC_CLK_REGION_CLOCK_CMD_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CLOCK_CMD_LEN ); REG64_FLD( PEC_CLK_REGION_SLAVE_MODE , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SLAVE_MODE ); REG64_FLD( PEC_CLK_REGION_MASTER_MODE , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MASTER_MODE ); REG64_FLD( PEC_CLK_REGION_CLOCK_PERV , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CLOCK_PERV ); REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT1 , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT1 ); REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT2 , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT2 ); REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT3 , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT3 ); REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT4 , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT4 ); REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT5 , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT5 ); REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT6 , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT6 ); REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT7 , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT7 ); REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT8 , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT8 ); REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT9 , 13 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT9 ); REG64_FLD( PEC_CLK_REGION_CLOCK_UNIT10 , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CLOCK_UNIT10 ); REG64_FLD( PEC_CLK_REGION_SEL_THOLD_SL , 48 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEL_THOLD_SL ); REG64_FLD( PEC_CLK_REGION_SEL_THOLD_NSL , 49 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEL_THOLD_NSL ); REG64_FLD( PEC_CLK_REGION_SEL_THOLD_ARY , 50 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEL_THOLD_ARY ); REG64_FLD( PEC_CLK_REGION_CLOCK_PULSE_USE_EVEN , 52 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CLOCK_PULSE_USE_EVEN ); REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_PERV , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_PERV ); REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT1 , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT1 ); REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT2 , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT2 ); REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT3 , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT3 ); REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT4 , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT4 ); REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT5 , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT5 ); REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT6 , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT6 ); REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT7 , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT7 ); REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT8 , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT8 ); REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT9 , 13 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT9 ); REG64_FLD( PEC_CLOCK_STAT_ARY_STATUS_UNIT10 , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT10 ); REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_PERV , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_PERV ); REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT1 , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT1 ); REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT2 , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT2 ); REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT3 , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT3 ); REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT4 , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT4 ); REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT5 , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT5 ); REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT6 , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT6 ); REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT7 , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT7 ); REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT8 , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT8 ); REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT9 , 13 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT9 ); REG64_FLD( PEC_CLOCK_STAT_NSL_STATUS_UNIT10 , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT10 ); REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_PERV , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_PERV ); REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT1 , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT1 ); REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT2 , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT2 ); REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT3 , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT3 ); REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT4 , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT4 ); REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT5 , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT5 ); REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT6 , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT6 ); REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT7 , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT7 ); REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT8 , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT8 ); REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT9 , 13 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT9 ); REG64_FLD( PEC_CLOCK_STAT_SL_STATUS_UNIT10 , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATUS_UNIT10 ); REG64_FLD( PU_CME4_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_EN ); REG64_FLD( PU_CME4_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME4_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); REG64_FLD( PU_CME4_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_RESERVED3 ); REG64_FLD( PU_CME4_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_EN_INTR_ADDR ); REG64_FLD( PU_CME4_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_EXTRA ); REG64_FLD( PU_CME4_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_STALL ); REG64_FLD( PU_CME4_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_EN_WAIT_CYCLES ); REG64_FLD( PU_CME4_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_EN_FULL_SPEED ); REG64_FLD( PU_CME4_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_RESERVED9 ); REG64_FLD( PU_CME4_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME4_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); REG64_FLD( PU_CME4_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME4_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME4_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); REG64_FLD( PU_CME4_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME4_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME3_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_EN ); REG64_FLD( PU_CME3_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME3_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); REG64_FLD( PU_CME3_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_RESERVED3 ); REG64_FLD( PU_CME3_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_EN_INTR_ADDR ); REG64_FLD( PU_CME3_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_EXTRA ); REG64_FLD( PU_CME3_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_STALL ); REG64_FLD( PU_CME3_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_EN_WAIT_CYCLES ); REG64_FLD( PU_CME3_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_EN_FULL_SPEED ); REG64_FLD( PU_CME3_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_RESERVED9 ); REG64_FLD( PU_CME3_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME3_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); REG64_FLD( PU_CME3_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME3_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME3_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); REG64_FLD( PU_CME3_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME3_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME11_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_EN ); REG64_FLD( PU_CME11_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME11_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); REG64_FLD( PU_CME11_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_RESERVED3 ); REG64_FLD( PU_CME11_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_EN_INTR_ADDR ); REG64_FLD( PU_CME11_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_EXTRA ); REG64_FLD( PU_CME11_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_STALL ); REG64_FLD( PU_CME11_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_EN_WAIT_CYCLES ); REG64_FLD( PU_CME11_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_EN_FULL_SPEED ); REG64_FLD( PU_CME11_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_RESERVED9 ); REG64_FLD( PU_CME11_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME11_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); REG64_FLD( PU_CME11_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME11_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME11_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); REG64_FLD( PU_CME11_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME11_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME2_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_EN ); REG64_FLD( PU_CME2_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME2_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); REG64_FLD( PU_CME2_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_RESERVED3 ); REG64_FLD( PU_CME2_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_EN_INTR_ADDR ); REG64_FLD( PU_CME2_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_EXTRA ); REG64_FLD( PU_CME2_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_STALL ); REG64_FLD( PU_CME2_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_EN_WAIT_CYCLES ); REG64_FLD( PU_CME2_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_EN_FULL_SPEED ); REG64_FLD( PU_CME2_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_RESERVED9 ); REG64_FLD( PU_CME2_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME2_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); REG64_FLD( PU_CME2_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME2_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME2_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); REG64_FLD( PU_CME2_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME2_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME5_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_EN ); REG64_FLD( PU_CME5_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME5_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); REG64_FLD( PU_CME5_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_RESERVED3 ); REG64_FLD( PU_CME5_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_EN_INTR_ADDR ); REG64_FLD( PU_CME5_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_EXTRA ); REG64_FLD( PU_CME5_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_STALL ); REG64_FLD( PU_CME5_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_EN_WAIT_CYCLES ); REG64_FLD( PU_CME5_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_EN_FULL_SPEED ); REG64_FLD( PU_CME5_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_RESERVED9 ); REG64_FLD( PU_CME5_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME5_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); REG64_FLD( PU_CME5_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME5_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME5_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); REG64_FLD( PU_CME5_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME5_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME9_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_EN ); REG64_FLD( PU_CME9_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME9_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); REG64_FLD( PU_CME9_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_RESERVED3 ); REG64_FLD( PU_CME9_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_EN_INTR_ADDR ); REG64_FLD( PU_CME9_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_EXTRA ); REG64_FLD( PU_CME9_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_STALL ); REG64_FLD( PU_CME9_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_EN_WAIT_CYCLES ); REG64_FLD( PU_CME9_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_EN_FULL_SPEED ); REG64_FLD( PU_CME9_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_RESERVED9 ); REG64_FLD( PU_CME9_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME9_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); REG64_FLD( PU_CME9_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME9_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME9_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); REG64_FLD( PU_CME9_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME9_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME6_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_EN ); REG64_FLD( PU_CME6_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME6_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); REG64_FLD( PU_CME6_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_RESERVED3 ); REG64_FLD( PU_CME6_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_EN_INTR_ADDR ); REG64_FLD( PU_CME6_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_EXTRA ); REG64_FLD( PU_CME6_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_STALL ); REG64_FLD( PU_CME6_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_EN_WAIT_CYCLES ); REG64_FLD( PU_CME6_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_EN_FULL_SPEED ); REG64_FLD( PU_CME6_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_RESERVED9 ); REG64_FLD( PU_CME6_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME6_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); REG64_FLD( PU_CME6_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME6_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME6_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); REG64_FLD( PU_CME6_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME6_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME10_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_EN ); REG64_FLD( PU_CME10_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME10_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); REG64_FLD( PU_CME10_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_RESERVED3 ); REG64_FLD( PU_CME10_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_EN_INTR_ADDR ); REG64_FLD( PU_CME10_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_EXTRA ); REG64_FLD( PU_CME10_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_STALL ); REG64_FLD( PU_CME10_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_EN_WAIT_CYCLES ); REG64_FLD( PU_CME10_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_EN_FULL_SPEED ); REG64_FLD( PU_CME10_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_RESERVED9 ); REG64_FLD( PU_CME10_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME10_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); REG64_FLD( PU_CME10_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME10_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME10_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); REG64_FLD( PU_CME10_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME10_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME8_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_EN ); REG64_FLD( PU_CME8_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME8_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); REG64_FLD( PU_CME8_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_RESERVED3 ); REG64_FLD( PU_CME8_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_EN_INTR_ADDR ); REG64_FLD( PU_CME8_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_EXTRA ); REG64_FLD( PU_CME8_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_STALL ); REG64_FLD( PU_CME8_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_EN_WAIT_CYCLES ); REG64_FLD( PU_CME8_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_EN_FULL_SPEED ); REG64_FLD( PU_CME8_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_RESERVED9 ); REG64_FLD( PU_CME8_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME8_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); REG64_FLD( PU_CME8_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME8_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME8_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); REG64_FLD( PU_CME8_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME8_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME1_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_EN ); REG64_FLD( PU_CME1_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME1_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); REG64_FLD( PU_CME1_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_RESERVED3 ); REG64_FLD( PU_CME1_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_EN_INTR_ADDR ); REG64_FLD( PU_CME1_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_EXTRA ); REG64_FLD( PU_CME1_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_STALL ); REG64_FLD( PU_CME1_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_EN_WAIT_CYCLES ); REG64_FLD( PU_CME1_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_EN_FULL_SPEED ); REG64_FLD( PU_CME1_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_RESERVED9 ); REG64_FLD( PU_CME1_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME1_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); REG64_FLD( PU_CME1_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME1_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME1_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); REG64_FLD( PU_CME1_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME1_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME0_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_EN ); REG64_FLD( PU_CME0_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME0_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); REG64_FLD( PU_CME0_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_RESERVED3 ); REG64_FLD( PU_CME0_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_EN_INTR_ADDR ); REG64_FLD( PU_CME0_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_EXTRA ); REG64_FLD( PU_CME0_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_STALL ); REG64_FLD( PU_CME0_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_EN_WAIT_CYCLES ); REG64_FLD( PU_CME0_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_EN_FULL_SPEED ); REG64_FLD( PU_CME0_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_RESERVED9 ); REG64_FLD( PU_CME0_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME0_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); REG64_FLD( PU_CME0_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME0_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME0_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); REG64_FLD( PU_CME0_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME0_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME7_CME_LCL_DBG_EN , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_EN ); REG64_FLD( PU_CME7_CME_LCL_DBG_HALT_ON_XSTOP , 1 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_CME7_CME_LCL_DBG_HALT_ON_TRIG , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_HALT_ON_TRIG ); REG64_FLD( PU_CME7_CME_LCL_DBG_RESERVED3 , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_RESERVED3 ); REG64_FLD( PU_CME7_CME_LCL_DBG_EN_INTR_ADDR , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_EN_INTR_ADDR ); REG64_FLD( PU_CME7_CME_LCL_DBG_EN_TRACE_EXTRA , 5 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_EXTRA ); REG64_FLD( PU_CME7_CME_LCL_DBG_EN_TRACE_STALL , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_EN_TRACE_STALL ); REG64_FLD( PU_CME7_CME_LCL_DBG_EN_WAIT_CYCLES , 7 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_EN_WAIT_CYCLES ); REG64_FLD( PU_CME7_CME_LCL_DBG_EN_FULL_SPEED , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_EN_FULL_SPEED ); REG64_FLD( PU_CME7_CME_LCL_DBG_RESERVED9 , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_RESERVED9 ); REG64_FLD( PU_CME7_CME_LCL_DBG_TRACE_MODE_SEL , 10 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_CME7_CME_LCL_DBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_TRACE_MODE_SEL_LEN ); REG64_FLD( PU_CME7_CME_LCL_DBG_FIR_TRIGGER , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_CME7_CME_LCL_DBG_MIB_GPIO , 17 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO ); REG64_FLD( PU_CME7_CME_LCL_DBG_MIB_GPIO_LEN , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_MIB_GPIO_LEN ); REG64_FLD( PU_CME7_CME_LCL_DBG_TRACE_DATA_SEL , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_CME7_CME_LCL_DBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_CME4_CME_LCL_EIMR_INTERRUPT_MASK , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK ); REG64_FLD( PU_CME4_CME_LCL_EIMR_INTERRUPT_MASK_LEN , 44 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK_LEN ); REG64_FLD( PU_CME3_CME_LCL_EIMR_INTERRUPT_MASK , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK ); REG64_FLD( PU_CME3_CME_LCL_EIMR_INTERRUPT_MASK_LEN , 44 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK_LEN ); REG64_FLD( PU_CME11_CME_LCL_EIMR_INTERRUPT_MASK , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK ); REG64_FLD( PU_CME11_CME_LCL_EIMR_INTERRUPT_MASK_LEN , 44 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK_LEN ); REG64_FLD( PU_CME2_CME_LCL_EIMR_INTERRUPT_MASK , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK ); REG64_FLD( PU_CME2_CME_LCL_EIMR_INTERRUPT_MASK_LEN , 44 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK_LEN ); REG64_FLD( PU_CME5_CME_LCL_EIMR_INTERRUPT_MASK , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK ); REG64_FLD( PU_CME5_CME_LCL_EIMR_INTERRUPT_MASK_LEN , 44 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK_LEN ); REG64_FLD( PU_CME9_CME_LCL_EIMR_INTERRUPT_MASK , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK ); REG64_FLD( PU_CME9_CME_LCL_EIMR_INTERRUPT_MASK_LEN , 44 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK_LEN ); REG64_FLD( PU_CME6_CME_LCL_EIMR_INTERRUPT_MASK , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK ); REG64_FLD( PU_CME6_CME_LCL_EIMR_INTERRUPT_MASK_LEN , 44 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK_LEN ); REG64_FLD( PU_CME10_CME_LCL_EIMR_INTERRUPT_MASK , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK ); REG64_FLD( PU_CME10_CME_LCL_EIMR_INTERRUPT_MASK_LEN , 44 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK_LEN ); REG64_FLD( PU_CME8_CME_LCL_EIMR_INTERRUPT_MASK , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK ); REG64_FLD( PU_CME8_CME_LCL_EIMR_INTERRUPT_MASK_LEN , 44 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK_LEN ); REG64_FLD( PU_CME1_CME_LCL_EIMR_INTERRUPT_MASK , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK ); REG64_FLD( PU_CME1_CME_LCL_EIMR_INTERRUPT_MASK_LEN , 44 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK_LEN ); REG64_FLD( PU_CME0_CME_LCL_EIMR_INTERRUPT_MASK , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK ); REG64_FLD( PU_CME0_CME_LCL_EIMR_INTERRUPT_MASK_LEN , 44 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK_LEN ); REG64_FLD( PU_CME7_CME_LCL_EIMR_INTERRUPT_MASK , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK ); REG64_FLD( PU_CME7_CME_LCL_EIMR_INTERRUPT_MASK_LEN , 44 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_MASK_LEN ); REG64_FLD( PU_CME4_CME_LCL_EINR_INTERRUPT_INPUT , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT ); REG64_FLD( PU_CME4_CME_LCL_EINR_INTERRUPT_INPUT_LEN , 44 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT_LEN ); REG64_FLD( PU_CME3_CME_LCL_EINR_INTERRUPT_INPUT , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT ); REG64_FLD( PU_CME3_CME_LCL_EINR_INTERRUPT_INPUT_LEN , 44 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT_LEN ); REG64_FLD( PU_CME11_CME_LCL_EINR_INTERRUPT_INPUT , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT ); REG64_FLD( PU_CME11_CME_LCL_EINR_INTERRUPT_INPUT_LEN , 44 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT_LEN ); REG64_FLD( PU_CME2_CME_LCL_EINR_INTERRUPT_INPUT , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT ); REG64_FLD( PU_CME2_CME_LCL_EINR_INTERRUPT_INPUT_LEN , 44 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT_LEN ); REG64_FLD( PU_CME5_CME_LCL_EINR_INTERRUPT_INPUT , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT ); REG64_FLD( PU_CME5_CME_LCL_EINR_INTERRUPT_INPUT_LEN , 44 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT_LEN ); REG64_FLD( PU_CME9_CME_LCL_EINR_INTERRUPT_INPUT , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT ); REG64_FLD( PU_CME9_CME_LCL_EINR_INTERRUPT_INPUT_LEN , 44 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT_LEN ); REG64_FLD( PU_CME6_CME_LCL_EINR_INTERRUPT_INPUT , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT ); REG64_FLD( PU_CME6_CME_LCL_EINR_INTERRUPT_INPUT_LEN , 44 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT_LEN ); REG64_FLD( PU_CME10_CME_LCL_EINR_INTERRUPT_INPUT , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT ); REG64_FLD( PU_CME10_CME_LCL_EINR_INTERRUPT_INPUT_LEN , 44 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT_LEN ); REG64_FLD( PU_CME8_CME_LCL_EINR_INTERRUPT_INPUT , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT ); REG64_FLD( PU_CME8_CME_LCL_EINR_INTERRUPT_INPUT_LEN , 44 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT_LEN ); REG64_FLD( PU_CME1_CME_LCL_EINR_INTERRUPT_INPUT , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT ); REG64_FLD( PU_CME1_CME_LCL_EINR_INTERRUPT_INPUT_LEN , 44 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT_LEN ); REG64_FLD( PU_CME0_CME_LCL_EINR_INTERRUPT_INPUT , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT ); REG64_FLD( PU_CME0_CME_LCL_EINR_INTERRUPT_INPUT_LEN , 44 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT_LEN ); REG64_FLD( PU_CME7_CME_LCL_EINR_INTERRUPT_INPUT , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT ); REG64_FLD( PU_CME7_CME_LCL_EINR_INTERRUPT_INPUT_LEN , 44 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_INTERRUPT_INPUT_LEN ); REG64_FLD( PU_CME4_CME_LCL_EIPR_INTERRUPT_POLARITY , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY ); REG64_FLD( PU_CME4_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN , 44 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY_LEN ); REG64_FLD( PU_CME3_CME_LCL_EIPR_INTERRUPT_POLARITY , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY ); REG64_FLD( PU_CME3_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN , 44 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY_LEN ); REG64_FLD( PU_CME11_CME_LCL_EIPR_INTERRUPT_POLARITY , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY ); REG64_FLD( PU_CME11_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN , 44 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY_LEN ); REG64_FLD( PU_CME2_CME_LCL_EIPR_INTERRUPT_POLARITY , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY ); REG64_FLD( PU_CME2_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN , 44 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY_LEN ); REG64_FLD( PU_CME5_CME_LCL_EIPR_INTERRUPT_POLARITY , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY ); REG64_FLD( PU_CME5_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN , 44 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY_LEN ); REG64_FLD( PU_CME9_CME_LCL_EIPR_INTERRUPT_POLARITY , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY ); REG64_FLD( PU_CME9_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN , 44 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY_LEN ); REG64_FLD( PU_CME6_CME_LCL_EIPR_INTERRUPT_POLARITY , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY ); REG64_FLD( PU_CME6_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN , 44 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY_LEN ); REG64_FLD( PU_CME10_CME_LCL_EIPR_INTERRUPT_POLARITY , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY ); REG64_FLD( PU_CME10_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN , 44 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY_LEN ); REG64_FLD( PU_CME8_CME_LCL_EIPR_INTERRUPT_POLARITY , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY ); REG64_FLD( PU_CME8_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN , 44 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY_LEN ); REG64_FLD( PU_CME1_CME_LCL_EIPR_INTERRUPT_POLARITY , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY ); REG64_FLD( PU_CME1_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN , 44 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY_LEN ); REG64_FLD( PU_CME0_CME_LCL_EIPR_INTERRUPT_POLARITY , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY ); REG64_FLD( PU_CME0_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN , 44 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY_LEN ); REG64_FLD( PU_CME7_CME_LCL_EIPR_INTERRUPT_POLARITY , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY ); REG64_FLD( PU_CME7_CME_LCL_EIPR_INTERRUPT_POLARITY_LEN , 44 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_POLARITY_LEN ); REG64_FLD( PU_CME4_CME_LCL_EISR_DEBUGGER , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_DEBUGGER ); REG64_FLD( PU_CME4_CME_LCL_EISR_DEBUG_TRIGGER , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_DEBUG_TRIGGER ); REG64_FLD( PU_CME4_CME_LCL_EISR_QUAD_CHECKSTOP , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_QUAD_CHECKSTOP ); REG64_FLD( PU_CME4_CME_LCL_EISR_PVREF_FAIL , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PVREF_FAIL ); REG64_FLD( PU_CME4_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME4_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME4_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); REG64_FLD( PU_CME4_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME4_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME4_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_BCE_TIMEOUT ); REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL3_C0 , 10 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C0 ); REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL3_C1 , 11 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C1 ); REG64_FLD( PU_CME4_CME_LCL_EISR_PC_INTR_PENDING_C0 , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C0 ); REG64_FLD( PU_CME4_CME_LCL_EISR_PC_INTR_PENDING_C1 , 13 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C1 ); REG64_FLD( PU_CME4_CME_LCL_EISR_SPECIAL_WAKEUP_C0 , 14 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C0 ); REG64_FLD( PU_CME4_CME_LCL_EISR_SPECIAL_WAKEUP_C1 , 15 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C1 ); REG64_FLD( PU_CME4_CME_LCL_EISR_REG_WAKEUP_C0 , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C0 ); REG64_FLD( PU_CME4_CME_LCL_EISR_REG_WAKEUP_C1 , 17 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C1 ); REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL2_C0 , 18 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C0 ); REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL2_C1 , 19 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C1 ); REG64_FLD( PU_CME4_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME4_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 , 21 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME4_CME_LCL_EISR_L2_PURGE_DONE , 22 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_DONE ); REG64_FLD( PU_CME4_CME_LCL_EISR_NCU_PURGE_DONE , 23 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_DONE ); REG64_FLD( PU_CME4_CME_LCL_EISR_CHTM_PURGE_DONE_C0 , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C0 ); REG64_FLD( PU_CME4_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME4_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); REG64_FLD( PU_CME4_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01 ); REG64_FLD( PU_CME4_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME4_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME4_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_ACK ); REG64_FLD( PU_CME4_CME_LCL_EISR_COMM_SEND_NACK , 31 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_NACK ); REG64_FLD( PU_CME4_CME_LCL_EISR_SPARE_32_33 , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33 ); REG64_FLD( PU_CME4_CME_LCL_EISR_SPARE_32_33_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33_LEN ); REG64_FLD( PU_CME4_CME_LCL_EISR_PMCR_UPDATE_C0 , 34 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C0 ); REG64_FLD( PU_CME4_CME_LCL_EISR_PMCR_UPDATE_C1 , 35 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C1 ); REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); REG64_FLD( PU_CME4_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2 ); REG64_FLD( PU_CME4_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME4_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C1 ); REG64_FLD( PU_CME4_CME_LCL_EISR_RESERVED_42_43 , 42 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43 ); REG64_FLD( PU_CME4_CME_LCL_EISR_RESERVED_42_43_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43_LEN ); REG64_FLD( PU_CME3_CME_LCL_EISR_DEBUGGER , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_DEBUGGER ); REG64_FLD( PU_CME3_CME_LCL_EISR_DEBUG_TRIGGER , 1 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_DEBUG_TRIGGER ); REG64_FLD( PU_CME3_CME_LCL_EISR_QUAD_CHECKSTOP , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_QUAD_CHECKSTOP ); REG64_FLD( PU_CME3_CME_LCL_EISR_PVREF_FAIL , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PVREF_FAIL ); REG64_FLD( PU_CME3_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME3_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME3_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); REG64_FLD( PU_CME3_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME3_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME3_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_BCE_TIMEOUT ); REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL3_C0 , 10 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C0 ); REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL3_C1 , 11 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C1 ); REG64_FLD( PU_CME3_CME_LCL_EISR_PC_INTR_PENDING_C0 , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C0 ); REG64_FLD( PU_CME3_CME_LCL_EISR_PC_INTR_PENDING_C1 , 13 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C1 ); REG64_FLD( PU_CME3_CME_LCL_EISR_SPECIAL_WAKEUP_C0 , 14 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C0 ); REG64_FLD( PU_CME3_CME_LCL_EISR_SPECIAL_WAKEUP_C1 , 15 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C1 ); REG64_FLD( PU_CME3_CME_LCL_EISR_REG_WAKEUP_C0 , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C0 ); REG64_FLD( PU_CME3_CME_LCL_EISR_REG_WAKEUP_C1 , 17 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C1 ); REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL2_C0 , 18 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C0 ); REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL2_C1 , 19 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C1 ); REG64_FLD( PU_CME3_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME3_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 , 21 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME3_CME_LCL_EISR_L2_PURGE_DONE , 22 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_DONE ); REG64_FLD( PU_CME3_CME_LCL_EISR_NCU_PURGE_DONE , 23 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_DONE ); REG64_FLD( PU_CME3_CME_LCL_EISR_CHTM_PURGE_DONE_C0 , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C0 ); REG64_FLD( PU_CME3_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME3_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); REG64_FLD( PU_CME3_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01 ); REG64_FLD( PU_CME3_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME3_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME3_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_ACK ); REG64_FLD( PU_CME3_CME_LCL_EISR_COMM_SEND_NACK , 31 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_NACK ); REG64_FLD( PU_CME3_CME_LCL_EISR_SPARE_32_33 , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33 ); REG64_FLD( PU_CME3_CME_LCL_EISR_SPARE_32_33_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33_LEN ); REG64_FLD( PU_CME3_CME_LCL_EISR_PMCR_UPDATE_C0 , 34 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C0 ); REG64_FLD( PU_CME3_CME_LCL_EISR_PMCR_UPDATE_C1 , 35 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C1 ); REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); REG64_FLD( PU_CME3_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2 ); REG64_FLD( PU_CME3_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME3_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C1 ); REG64_FLD( PU_CME3_CME_LCL_EISR_RESERVED_42_43 , 42 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43 ); REG64_FLD( PU_CME3_CME_LCL_EISR_RESERVED_42_43_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43_LEN ); REG64_FLD( PU_CME11_CME_LCL_EISR_DEBUGGER , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_DEBUGGER ); REG64_FLD( PU_CME11_CME_LCL_EISR_DEBUG_TRIGGER , 1 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_DEBUG_TRIGGER ); REG64_FLD( PU_CME11_CME_LCL_EISR_QUAD_CHECKSTOP , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_QUAD_CHECKSTOP ); REG64_FLD( PU_CME11_CME_LCL_EISR_PVREF_FAIL , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PVREF_FAIL ); REG64_FLD( PU_CME11_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME11_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME11_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); REG64_FLD( PU_CME11_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME11_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME11_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_BCE_TIMEOUT ); REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL3_C0 , 10 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C0 ); REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL3_C1 , 11 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C1 ); REG64_FLD( PU_CME11_CME_LCL_EISR_PC_INTR_PENDING_C0 , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C0 ); REG64_FLD( PU_CME11_CME_LCL_EISR_PC_INTR_PENDING_C1 , 13 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C1 ); REG64_FLD( PU_CME11_CME_LCL_EISR_SPECIAL_WAKEUP_C0 , 14 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C0 ); REG64_FLD( PU_CME11_CME_LCL_EISR_SPECIAL_WAKEUP_C1 , 15 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C1 ); REG64_FLD( PU_CME11_CME_LCL_EISR_REG_WAKEUP_C0 , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C0 ); REG64_FLD( PU_CME11_CME_LCL_EISR_REG_WAKEUP_C1 , 17 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C1 ); REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL2_C0 , 18 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C0 ); REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL2_C1 , 19 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C1 ); REG64_FLD( PU_CME11_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME11_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 , 21 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME11_CME_LCL_EISR_L2_PURGE_DONE , 22 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_DONE ); REG64_FLD( PU_CME11_CME_LCL_EISR_NCU_PURGE_DONE , 23 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_DONE ); REG64_FLD( PU_CME11_CME_LCL_EISR_CHTM_PURGE_DONE_C0 , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C0 ); REG64_FLD( PU_CME11_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME11_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); REG64_FLD( PU_CME11_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01 ); REG64_FLD( PU_CME11_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME11_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME11_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_ACK ); REG64_FLD( PU_CME11_CME_LCL_EISR_COMM_SEND_NACK , 31 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_NACK ); REG64_FLD( PU_CME11_CME_LCL_EISR_SPARE_32_33 , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33 ); REG64_FLD( PU_CME11_CME_LCL_EISR_SPARE_32_33_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33_LEN ); REG64_FLD( PU_CME11_CME_LCL_EISR_PMCR_UPDATE_C0 , 34 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C0 ); REG64_FLD( PU_CME11_CME_LCL_EISR_PMCR_UPDATE_C1 , 35 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C1 ); REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); REG64_FLD( PU_CME11_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2 ); REG64_FLD( PU_CME11_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME11_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C1 ); REG64_FLD( PU_CME11_CME_LCL_EISR_RESERVED_42_43 , 42 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43 ); REG64_FLD( PU_CME11_CME_LCL_EISR_RESERVED_42_43_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43_LEN ); REG64_FLD( PU_CME2_CME_LCL_EISR_DEBUGGER , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_DEBUGGER ); REG64_FLD( PU_CME2_CME_LCL_EISR_DEBUG_TRIGGER , 1 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_DEBUG_TRIGGER ); REG64_FLD( PU_CME2_CME_LCL_EISR_QUAD_CHECKSTOP , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_QUAD_CHECKSTOP ); REG64_FLD( PU_CME2_CME_LCL_EISR_PVREF_FAIL , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PVREF_FAIL ); REG64_FLD( PU_CME2_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME2_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME2_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); REG64_FLD( PU_CME2_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME2_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME2_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_BCE_TIMEOUT ); REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL3_C0 , 10 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C0 ); REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL3_C1 , 11 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C1 ); REG64_FLD( PU_CME2_CME_LCL_EISR_PC_INTR_PENDING_C0 , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C0 ); REG64_FLD( PU_CME2_CME_LCL_EISR_PC_INTR_PENDING_C1 , 13 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C1 ); REG64_FLD( PU_CME2_CME_LCL_EISR_SPECIAL_WAKEUP_C0 , 14 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C0 ); REG64_FLD( PU_CME2_CME_LCL_EISR_SPECIAL_WAKEUP_C1 , 15 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C1 ); REG64_FLD( PU_CME2_CME_LCL_EISR_REG_WAKEUP_C0 , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C0 ); REG64_FLD( PU_CME2_CME_LCL_EISR_REG_WAKEUP_C1 , 17 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C1 ); REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL2_C0 , 18 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C0 ); REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL2_C1 , 19 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C1 ); REG64_FLD( PU_CME2_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME2_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 , 21 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME2_CME_LCL_EISR_L2_PURGE_DONE , 22 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_DONE ); REG64_FLD( PU_CME2_CME_LCL_EISR_NCU_PURGE_DONE , 23 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_DONE ); REG64_FLD( PU_CME2_CME_LCL_EISR_CHTM_PURGE_DONE_C0 , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C0 ); REG64_FLD( PU_CME2_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME2_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); REG64_FLD( PU_CME2_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01 ); REG64_FLD( PU_CME2_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME2_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME2_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_ACK ); REG64_FLD( PU_CME2_CME_LCL_EISR_COMM_SEND_NACK , 31 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_NACK ); REG64_FLD( PU_CME2_CME_LCL_EISR_SPARE_32_33 , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33 ); REG64_FLD( PU_CME2_CME_LCL_EISR_SPARE_32_33_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33_LEN ); REG64_FLD( PU_CME2_CME_LCL_EISR_PMCR_UPDATE_C0 , 34 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C0 ); REG64_FLD( PU_CME2_CME_LCL_EISR_PMCR_UPDATE_C1 , 35 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C1 ); REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); REG64_FLD( PU_CME2_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2 ); REG64_FLD( PU_CME2_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME2_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C1 ); REG64_FLD( PU_CME2_CME_LCL_EISR_RESERVED_42_43 , 42 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43 ); REG64_FLD( PU_CME2_CME_LCL_EISR_RESERVED_42_43_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43_LEN ); REG64_FLD( PU_CME5_CME_LCL_EISR_DEBUGGER , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_DEBUGGER ); REG64_FLD( PU_CME5_CME_LCL_EISR_DEBUG_TRIGGER , 1 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_DEBUG_TRIGGER ); REG64_FLD( PU_CME5_CME_LCL_EISR_QUAD_CHECKSTOP , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_QUAD_CHECKSTOP ); REG64_FLD( PU_CME5_CME_LCL_EISR_PVREF_FAIL , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PVREF_FAIL ); REG64_FLD( PU_CME5_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME5_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME5_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); REG64_FLD( PU_CME5_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME5_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME5_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_BCE_TIMEOUT ); REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL3_C0 , 10 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C0 ); REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL3_C1 , 11 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C1 ); REG64_FLD( PU_CME5_CME_LCL_EISR_PC_INTR_PENDING_C0 , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C0 ); REG64_FLD( PU_CME5_CME_LCL_EISR_PC_INTR_PENDING_C1 , 13 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C1 ); REG64_FLD( PU_CME5_CME_LCL_EISR_SPECIAL_WAKEUP_C0 , 14 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C0 ); REG64_FLD( PU_CME5_CME_LCL_EISR_SPECIAL_WAKEUP_C1 , 15 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C1 ); REG64_FLD( PU_CME5_CME_LCL_EISR_REG_WAKEUP_C0 , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C0 ); REG64_FLD( PU_CME5_CME_LCL_EISR_REG_WAKEUP_C1 , 17 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C1 ); REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL2_C0 , 18 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C0 ); REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL2_C1 , 19 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C1 ); REG64_FLD( PU_CME5_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME5_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 , 21 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME5_CME_LCL_EISR_L2_PURGE_DONE , 22 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_DONE ); REG64_FLD( PU_CME5_CME_LCL_EISR_NCU_PURGE_DONE , 23 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_DONE ); REG64_FLD( PU_CME5_CME_LCL_EISR_CHTM_PURGE_DONE_C0 , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C0 ); REG64_FLD( PU_CME5_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME5_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); REG64_FLD( PU_CME5_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01 ); REG64_FLD( PU_CME5_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME5_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME5_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_ACK ); REG64_FLD( PU_CME5_CME_LCL_EISR_COMM_SEND_NACK , 31 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_NACK ); REG64_FLD( PU_CME5_CME_LCL_EISR_SPARE_32_33 , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33 ); REG64_FLD( PU_CME5_CME_LCL_EISR_SPARE_32_33_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33_LEN ); REG64_FLD( PU_CME5_CME_LCL_EISR_PMCR_UPDATE_C0 , 34 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C0 ); REG64_FLD( PU_CME5_CME_LCL_EISR_PMCR_UPDATE_C1 , 35 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C1 ); REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); REG64_FLD( PU_CME5_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2 ); REG64_FLD( PU_CME5_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME5_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C1 ); REG64_FLD( PU_CME5_CME_LCL_EISR_RESERVED_42_43 , 42 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43 ); REG64_FLD( PU_CME5_CME_LCL_EISR_RESERVED_42_43_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43_LEN ); REG64_FLD( PU_CME9_CME_LCL_EISR_DEBUGGER , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_DEBUGGER ); REG64_FLD( PU_CME9_CME_LCL_EISR_DEBUG_TRIGGER , 1 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_DEBUG_TRIGGER ); REG64_FLD( PU_CME9_CME_LCL_EISR_QUAD_CHECKSTOP , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_QUAD_CHECKSTOP ); REG64_FLD( PU_CME9_CME_LCL_EISR_PVREF_FAIL , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PVREF_FAIL ); REG64_FLD( PU_CME9_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME9_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME9_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); REG64_FLD( PU_CME9_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME9_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME9_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_BCE_TIMEOUT ); REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL3_C0 , 10 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C0 ); REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL3_C1 , 11 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C1 ); REG64_FLD( PU_CME9_CME_LCL_EISR_PC_INTR_PENDING_C0 , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C0 ); REG64_FLD( PU_CME9_CME_LCL_EISR_PC_INTR_PENDING_C1 , 13 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C1 ); REG64_FLD( PU_CME9_CME_LCL_EISR_SPECIAL_WAKEUP_C0 , 14 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C0 ); REG64_FLD( PU_CME9_CME_LCL_EISR_SPECIAL_WAKEUP_C1 , 15 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C1 ); REG64_FLD( PU_CME9_CME_LCL_EISR_REG_WAKEUP_C0 , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C0 ); REG64_FLD( PU_CME9_CME_LCL_EISR_REG_WAKEUP_C1 , 17 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C1 ); REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL2_C0 , 18 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C0 ); REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL2_C1 , 19 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C1 ); REG64_FLD( PU_CME9_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME9_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 , 21 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME9_CME_LCL_EISR_L2_PURGE_DONE , 22 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_DONE ); REG64_FLD( PU_CME9_CME_LCL_EISR_NCU_PURGE_DONE , 23 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_DONE ); REG64_FLD( PU_CME9_CME_LCL_EISR_CHTM_PURGE_DONE_C0 , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C0 ); REG64_FLD( PU_CME9_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME9_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); REG64_FLD( PU_CME9_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01 ); REG64_FLD( PU_CME9_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME9_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME9_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_ACK ); REG64_FLD( PU_CME9_CME_LCL_EISR_COMM_SEND_NACK , 31 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_NACK ); REG64_FLD( PU_CME9_CME_LCL_EISR_SPARE_32_33 , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33 ); REG64_FLD( PU_CME9_CME_LCL_EISR_SPARE_32_33_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33_LEN ); REG64_FLD( PU_CME9_CME_LCL_EISR_PMCR_UPDATE_C0 , 34 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C0 ); REG64_FLD( PU_CME9_CME_LCL_EISR_PMCR_UPDATE_C1 , 35 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C1 ); REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); REG64_FLD( PU_CME9_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2 ); REG64_FLD( PU_CME9_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME9_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C1 ); REG64_FLD( PU_CME9_CME_LCL_EISR_RESERVED_42_43 , 42 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43 ); REG64_FLD( PU_CME9_CME_LCL_EISR_RESERVED_42_43_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43_LEN ); REG64_FLD( PU_CME6_CME_LCL_EISR_DEBUGGER , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_DEBUGGER ); REG64_FLD( PU_CME6_CME_LCL_EISR_DEBUG_TRIGGER , 1 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_DEBUG_TRIGGER ); REG64_FLD( PU_CME6_CME_LCL_EISR_QUAD_CHECKSTOP , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_QUAD_CHECKSTOP ); REG64_FLD( PU_CME6_CME_LCL_EISR_PVREF_FAIL , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PVREF_FAIL ); REG64_FLD( PU_CME6_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME6_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME6_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); REG64_FLD( PU_CME6_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME6_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME6_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_BCE_TIMEOUT ); REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL3_C0 , 10 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C0 ); REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL3_C1 , 11 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C1 ); REG64_FLD( PU_CME6_CME_LCL_EISR_PC_INTR_PENDING_C0 , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C0 ); REG64_FLD( PU_CME6_CME_LCL_EISR_PC_INTR_PENDING_C1 , 13 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C1 ); REG64_FLD( PU_CME6_CME_LCL_EISR_SPECIAL_WAKEUP_C0 , 14 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C0 ); REG64_FLD( PU_CME6_CME_LCL_EISR_SPECIAL_WAKEUP_C1 , 15 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C1 ); REG64_FLD( PU_CME6_CME_LCL_EISR_REG_WAKEUP_C0 , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C0 ); REG64_FLD( PU_CME6_CME_LCL_EISR_REG_WAKEUP_C1 , 17 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C1 ); REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL2_C0 , 18 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C0 ); REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL2_C1 , 19 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C1 ); REG64_FLD( PU_CME6_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME6_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 , 21 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME6_CME_LCL_EISR_L2_PURGE_DONE , 22 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_DONE ); REG64_FLD( PU_CME6_CME_LCL_EISR_NCU_PURGE_DONE , 23 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_DONE ); REG64_FLD( PU_CME6_CME_LCL_EISR_CHTM_PURGE_DONE_C0 , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C0 ); REG64_FLD( PU_CME6_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME6_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); REG64_FLD( PU_CME6_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01 ); REG64_FLD( PU_CME6_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME6_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME6_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_ACK ); REG64_FLD( PU_CME6_CME_LCL_EISR_COMM_SEND_NACK , 31 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_NACK ); REG64_FLD( PU_CME6_CME_LCL_EISR_SPARE_32_33 , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33 ); REG64_FLD( PU_CME6_CME_LCL_EISR_SPARE_32_33_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33_LEN ); REG64_FLD( PU_CME6_CME_LCL_EISR_PMCR_UPDATE_C0 , 34 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C0 ); REG64_FLD( PU_CME6_CME_LCL_EISR_PMCR_UPDATE_C1 , 35 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C1 ); REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); REG64_FLD( PU_CME6_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2 ); REG64_FLD( PU_CME6_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME6_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C1 ); REG64_FLD( PU_CME6_CME_LCL_EISR_RESERVED_42_43 , 42 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43 ); REG64_FLD( PU_CME6_CME_LCL_EISR_RESERVED_42_43_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43_LEN ); REG64_FLD( PU_CME10_CME_LCL_EISR_DEBUGGER , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_DEBUGGER ); REG64_FLD( PU_CME10_CME_LCL_EISR_DEBUG_TRIGGER , 1 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_DEBUG_TRIGGER ); REG64_FLD( PU_CME10_CME_LCL_EISR_QUAD_CHECKSTOP , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_QUAD_CHECKSTOP ); REG64_FLD( PU_CME10_CME_LCL_EISR_PVREF_FAIL , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PVREF_FAIL ); REG64_FLD( PU_CME10_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME10_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME10_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); REG64_FLD( PU_CME10_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME10_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME10_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_BCE_TIMEOUT ); REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL3_C0 , 10 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C0 ); REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL3_C1 , 11 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C1 ); REG64_FLD( PU_CME10_CME_LCL_EISR_PC_INTR_PENDING_C0 , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C0 ); REG64_FLD( PU_CME10_CME_LCL_EISR_PC_INTR_PENDING_C1 , 13 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C1 ); REG64_FLD( PU_CME10_CME_LCL_EISR_SPECIAL_WAKEUP_C0 , 14 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C0 ); REG64_FLD( PU_CME10_CME_LCL_EISR_SPECIAL_WAKEUP_C1 , 15 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C1 ); REG64_FLD( PU_CME10_CME_LCL_EISR_REG_WAKEUP_C0 , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C0 ); REG64_FLD( PU_CME10_CME_LCL_EISR_REG_WAKEUP_C1 , 17 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C1 ); REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL2_C0 , 18 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C0 ); REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL2_C1 , 19 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C1 ); REG64_FLD( PU_CME10_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME10_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 , 21 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME10_CME_LCL_EISR_L2_PURGE_DONE , 22 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_DONE ); REG64_FLD( PU_CME10_CME_LCL_EISR_NCU_PURGE_DONE , 23 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_DONE ); REG64_FLD( PU_CME10_CME_LCL_EISR_CHTM_PURGE_DONE_C0 , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C0 ); REG64_FLD( PU_CME10_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME10_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); REG64_FLD( PU_CME10_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01 ); REG64_FLD( PU_CME10_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME10_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME10_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_ACK ); REG64_FLD( PU_CME10_CME_LCL_EISR_COMM_SEND_NACK , 31 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_NACK ); REG64_FLD( PU_CME10_CME_LCL_EISR_SPARE_32_33 , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33 ); REG64_FLD( PU_CME10_CME_LCL_EISR_SPARE_32_33_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33_LEN ); REG64_FLD( PU_CME10_CME_LCL_EISR_PMCR_UPDATE_C0 , 34 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C0 ); REG64_FLD( PU_CME10_CME_LCL_EISR_PMCR_UPDATE_C1 , 35 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C1 ); REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); REG64_FLD( PU_CME10_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2 ); REG64_FLD( PU_CME10_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME10_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C1 ); REG64_FLD( PU_CME10_CME_LCL_EISR_RESERVED_42_43 , 42 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43 ); REG64_FLD( PU_CME10_CME_LCL_EISR_RESERVED_42_43_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43_LEN ); REG64_FLD( PU_CME8_CME_LCL_EISR_DEBUGGER , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_DEBUGGER ); REG64_FLD( PU_CME8_CME_LCL_EISR_DEBUG_TRIGGER , 1 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_DEBUG_TRIGGER ); REG64_FLD( PU_CME8_CME_LCL_EISR_QUAD_CHECKSTOP , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_QUAD_CHECKSTOP ); REG64_FLD( PU_CME8_CME_LCL_EISR_PVREF_FAIL , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PVREF_FAIL ); REG64_FLD( PU_CME8_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME8_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME8_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); REG64_FLD( PU_CME8_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME8_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME8_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_BCE_TIMEOUT ); REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL3_C0 , 10 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C0 ); REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL3_C1 , 11 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C1 ); REG64_FLD( PU_CME8_CME_LCL_EISR_PC_INTR_PENDING_C0 , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C0 ); REG64_FLD( PU_CME8_CME_LCL_EISR_PC_INTR_PENDING_C1 , 13 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C1 ); REG64_FLD( PU_CME8_CME_LCL_EISR_SPECIAL_WAKEUP_C0 , 14 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C0 ); REG64_FLD( PU_CME8_CME_LCL_EISR_SPECIAL_WAKEUP_C1 , 15 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C1 ); REG64_FLD( PU_CME8_CME_LCL_EISR_REG_WAKEUP_C0 , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C0 ); REG64_FLD( PU_CME8_CME_LCL_EISR_REG_WAKEUP_C1 , 17 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C1 ); REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL2_C0 , 18 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C0 ); REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL2_C1 , 19 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C1 ); REG64_FLD( PU_CME8_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME8_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 , 21 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME8_CME_LCL_EISR_L2_PURGE_DONE , 22 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_DONE ); REG64_FLD( PU_CME8_CME_LCL_EISR_NCU_PURGE_DONE , 23 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_DONE ); REG64_FLD( PU_CME8_CME_LCL_EISR_CHTM_PURGE_DONE_C0 , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C0 ); REG64_FLD( PU_CME8_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME8_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); REG64_FLD( PU_CME8_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01 ); REG64_FLD( PU_CME8_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME8_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME8_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_ACK ); REG64_FLD( PU_CME8_CME_LCL_EISR_COMM_SEND_NACK , 31 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_NACK ); REG64_FLD( PU_CME8_CME_LCL_EISR_SPARE_32_33 , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33 ); REG64_FLD( PU_CME8_CME_LCL_EISR_SPARE_32_33_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33_LEN ); REG64_FLD( PU_CME8_CME_LCL_EISR_PMCR_UPDATE_C0 , 34 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C0 ); REG64_FLD( PU_CME8_CME_LCL_EISR_PMCR_UPDATE_C1 , 35 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C1 ); REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); REG64_FLD( PU_CME8_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2 ); REG64_FLD( PU_CME8_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME8_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C1 ); REG64_FLD( PU_CME8_CME_LCL_EISR_RESERVED_42_43 , 42 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43 ); REG64_FLD( PU_CME8_CME_LCL_EISR_RESERVED_42_43_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43_LEN ); REG64_FLD( PU_CME1_CME_LCL_EISR_DEBUGGER , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_DEBUGGER ); REG64_FLD( PU_CME1_CME_LCL_EISR_DEBUG_TRIGGER , 1 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_DEBUG_TRIGGER ); REG64_FLD( PU_CME1_CME_LCL_EISR_QUAD_CHECKSTOP , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_QUAD_CHECKSTOP ); REG64_FLD( PU_CME1_CME_LCL_EISR_PVREF_FAIL , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PVREF_FAIL ); REG64_FLD( PU_CME1_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME1_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME1_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); REG64_FLD( PU_CME1_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME1_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME1_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_BCE_TIMEOUT ); REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL3_C0 , 10 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C0 ); REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL3_C1 , 11 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C1 ); REG64_FLD( PU_CME1_CME_LCL_EISR_PC_INTR_PENDING_C0 , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C0 ); REG64_FLD( PU_CME1_CME_LCL_EISR_PC_INTR_PENDING_C1 , 13 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C1 ); REG64_FLD( PU_CME1_CME_LCL_EISR_SPECIAL_WAKEUP_C0 , 14 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C0 ); REG64_FLD( PU_CME1_CME_LCL_EISR_SPECIAL_WAKEUP_C1 , 15 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C1 ); REG64_FLD( PU_CME1_CME_LCL_EISR_REG_WAKEUP_C0 , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C0 ); REG64_FLD( PU_CME1_CME_LCL_EISR_REG_WAKEUP_C1 , 17 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C1 ); REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL2_C0 , 18 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C0 ); REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL2_C1 , 19 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C1 ); REG64_FLD( PU_CME1_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME1_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 , 21 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME1_CME_LCL_EISR_L2_PURGE_DONE , 22 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_DONE ); REG64_FLD( PU_CME1_CME_LCL_EISR_NCU_PURGE_DONE , 23 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_DONE ); REG64_FLD( PU_CME1_CME_LCL_EISR_CHTM_PURGE_DONE_C0 , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C0 ); REG64_FLD( PU_CME1_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME1_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); REG64_FLD( PU_CME1_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01 ); REG64_FLD( PU_CME1_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME1_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME1_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_ACK ); REG64_FLD( PU_CME1_CME_LCL_EISR_COMM_SEND_NACK , 31 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_NACK ); REG64_FLD( PU_CME1_CME_LCL_EISR_SPARE_32_33 , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33 ); REG64_FLD( PU_CME1_CME_LCL_EISR_SPARE_32_33_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33_LEN ); REG64_FLD( PU_CME1_CME_LCL_EISR_PMCR_UPDATE_C0 , 34 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C0 ); REG64_FLD( PU_CME1_CME_LCL_EISR_PMCR_UPDATE_C1 , 35 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C1 ); REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); REG64_FLD( PU_CME1_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2 ); REG64_FLD( PU_CME1_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME1_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C1 ); REG64_FLD( PU_CME1_CME_LCL_EISR_RESERVED_42_43 , 42 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43 ); REG64_FLD( PU_CME1_CME_LCL_EISR_RESERVED_42_43_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43_LEN ); REG64_FLD( PU_CME0_CME_LCL_EISR_DEBUGGER , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_DEBUGGER ); REG64_FLD( PU_CME0_CME_LCL_EISR_DEBUG_TRIGGER , 1 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_DEBUG_TRIGGER ); REG64_FLD( PU_CME0_CME_LCL_EISR_QUAD_CHECKSTOP , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_QUAD_CHECKSTOP ); REG64_FLD( PU_CME0_CME_LCL_EISR_PVREF_FAIL , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PVREF_FAIL ); REG64_FLD( PU_CME0_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME0_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME0_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); REG64_FLD( PU_CME0_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME0_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME0_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_BCE_TIMEOUT ); REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL3_C0 , 10 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C0 ); REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL3_C1 , 11 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C1 ); REG64_FLD( PU_CME0_CME_LCL_EISR_PC_INTR_PENDING_C0 , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C0 ); REG64_FLD( PU_CME0_CME_LCL_EISR_PC_INTR_PENDING_C1 , 13 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C1 ); REG64_FLD( PU_CME0_CME_LCL_EISR_SPECIAL_WAKEUP_C0 , 14 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C0 ); REG64_FLD( PU_CME0_CME_LCL_EISR_SPECIAL_WAKEUP_C1 , 15 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C1 ); REG64_FLD( PU_CME0_CME_LCL_EISR_REG_WAKEUP_C0 , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C0 ); REG64_FLD( PU_CME0_CME_LCL_EISR_REG_WAKEUP_C1 , 17 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C1 ); REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL2_C0 , 18 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C0 ); REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL2_C1 , 19 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C1 ); REG64_FLD( PU_CME0_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME0_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 , 21 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME0_CME_LCL_EISR_L2_PURGE_DONE , 22 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_DONE ); REG64_FLD( PU_CME0_CME_LCL_EISR_NCU_PURGE_DONE , 23 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_DONE ); REG64_FLD( PU_CME0_CME_LCL_EISR_CHTM_PURGE_DONE_C0 , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C0 ); REG64_FLD( PU_CME0_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME0_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); REG64_FLD( PU_CME0_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01 ); REG64_FLD( PU_CME0_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME0_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME0_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_ACK ); REG64_FLD( PU_CME0_CME_LCL_EISR_COMM_SEND_NACK , 31 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_NACK ); REG64_FLD( PU_CME0_CME_LCL_EISR_SPARE_32_33 , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33 ); REG64_FLD( PU_CME0_CME_LCL_EISR_SPARE_32_33_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33_LEN ); REG64_FLD( PU_CME0_CME_LCL_EISR_PMCR_UPDATE_C0 , 34 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C0 ); REG64_FLD( PU_CME0_CME_LCL_EISR_PMCR_UPDATE_C1 , 35 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C1 ); REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); REG64_FLD( PU_CME0_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2 ); REG64_FLD( PU_CME0_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME0_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C1 ); REG64_FLD( PU_CME0_CME_LCL_EISR_RESERVED_42_43 , 42 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43 ); REG64_FLD( PU_CME0_CME_LCL_EISR_RESERVED_42_43_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43_LEN ); REG64_FLD( PU_CME7_CME_LCL_EISR_DEBUGGER , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_DEBUGGER ); REG64_FLD( PU_CME7_CME_LCL_EISR_DEBUG_TRIGGER , 1 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_DEBUG_TRIGGER ); REG64_FLD( PU_CME7_CME_LCL_EISR_QUAD_CHECKSTOP , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_QUAD_CHECKSTOP ); REG64_FLD( PU_CME7_CME_LCL_EISR_PVREF_FAIL , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PVREF_FAIL ); REG64_FLD( PU_CME7_CME_LCL_EISR_OCC_HEARTBEAT_LOST , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_OCC_HEARTBEAT_LOST ); REG64_FLD( PU_CME7_CME_LCL_EISR_CORE_CHECKSTOP , 5 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_CORE_CHECKSTOP ); REG64_FLD( PU_CME7_CME_LCL_EISR_DROPOUT_DETECT , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_DROPOUT_DETECT ); REG64_FLD( PU_CME7_CME_LCL_EISR_INTERCME_DIRECT_IN_0 , 7 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_0 ); REG64_FLD( PU_CME7_CME_LCL_EISR_BCE_BUSY_HIGH , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_HIGH ); REG64_FLD( PU_CME7_CME_LCL_EISR_BCE_TIMEOUT , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_BCE_TIMEOUT ); REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL3_C0 , 10 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C0 ); REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL3_C1 , 11 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_DOORBELL3_C1 ); REG64_FLD( PU_CME7_CME_LCL_EISR_PC_INTR_PENDING_C0 , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C0 ); REG64_FLD( PU_CME7_CME_LCL_EISR_PC_INTR_PENDING_C1 , 13 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PC_INTR_PENDING_C1 ); REG64_FLD( PU_CME7_CME_LCL_EISR_SPECIAL_WAKEUP_C0 , 14 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C0 ); REG64_FLD( PU_CME7_CME_LCL_EISR_SPECIAL_WAKEUP_C1 , 15 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WAKEUP_C1 ); REG64_FLD( PU_CME7_CME_LCL_EISR_REG_WAKEUP_C0 , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C0 ); REG64_FLD( PU_CME7_CME_LCL_EISR_REG_WAKEUP_C1 , 17 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_REG_WAKEUP_C1 ); REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL2_C0 , 18 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C0 ); REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL2_C1 , 19 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_DOORBELL2_C1 ); REG64_FLD( PU_CME7_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C0 , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME7_CME_LCL_EISR_PC_PM_STATE_ACTIVE_C1 , 21 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PC_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME7_CME_LCL_EISR_L2_PURGE_DONE , 22 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_DONE ); REG64_FLD( PU_CME7_CME_LCL_EISR_NCU_PURGE_DONE , 23 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_DONE ); REG64_FLD( PU_CME7_CME_LCL_EISR_CHTM_PURGE_DONE_C0 , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C0 ); REG64_FLD( PU_CME7_CME_LCL_EISR_CHTM_PURGE_DONE_C1 , 25 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_DONE_C1 ); REG64_FLD( PU_CME7_CME_LCL_EISR_BCE_BUSY_LOW , 26 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_BCE_BUSY_LOW ); REG64_FLD( PU_CME7_CME_LCL_EISR_FINAL_VDM_DATA01 , 27 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01 ); REG64_FLD( PU_CME7_CME_LCL_EISR_FINAL_VDM_DATA01_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_FINAL_VDM_DATA01_LEN ); REG64_FLD( PU_CME7_CME_LCL_EISR_COMM_RECVD , 29 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_COMM_RECVD ); REG64_FLD( PU_CME7_CME_LCL_EISR_COMM_SEND_ACK , 30 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_ACK ); REG64_FLD( PU_CME7_CME_LCL_EISR_COMM_SEND_NACK , 31 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_COMM_SEND_NACK ); REG64_FLD( PU_CME7_CME_LCL_EISR_SPARE_32_33 , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33 ); REG64_FLD( PU_CME7_CME_LCL_EISR_SPARE_32_33_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_SPARE_32_33_LEN ); REG64_FLD( PU_CME7_CME_LCL_EISR_PMCR_UPDATE_C0 , 34 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C0 ); REG64_FLD( PU_CME7_CME_LCL_EISR_PMCR_UPDATE_C1 , 35 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PMCR_UPDATE_C1 ); REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL0_C0 , 36 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C0 ); REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL0_C1 , 37 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_DOORBELL0_C1 ); REG64_FLD( PU_CME7_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2 , 38 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2 ); REG64_FLD( PU_CME7_CME_LCL_EISR_INTERCME_DIRECT_IN_1_2_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_INTERCME_DIRECT_IN_1_2_LEN ); REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL1_C0 , 40 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C0 ); REG64_FLD( PU_CME7_CME_LCL_EISR_DOORBELL1_C1 , 41 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_DOORBELL1_C1 ); REG64_FLD( PU_CME7_CME_LCL_EISR_RESERVED_42_43 , 42 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43 ); REG64_FLD( PU_CME7_CME_LCL_EISR_RESERVED_42_43_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_RESERVED_42_43_LEN ); REG64_FLD( PU_CME4_CME_LCL_EITR_INTERRUPT_TYPE , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE ); REG64_FLD( PU_CME4_CME_LCL_EITR_INTERRUPT_TYPE_LEN , 44 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE_LEN ); REG64_FLD( PU_CME3_CME_LCL_EITR_INTERRUPT_TYPE , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE ); REG64_FLD( PU_CME3_CME_LCL_EITR_INTERRUPT_TYPE_LEN , 44 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE_LEN ); REG64_FLD( PU_CME11_CME_LCL_EITR_INTERRUPT_TYPE , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE ); REG64_FLD( PU_CME11_CME_LCL_EITR_INTERRUPT_TYPE_LEN , 44 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE_LEN ); REG64_FLD( PU_CME2_CME_LCL_EITR_INTERRUPT_TYPE , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE ); REG64_FLD( PU_CME2_CME_LCL_EITR_INTERRUPT_TYPE_LEN , 44 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE_LEN ); REG64_FLD( PU_CME5_CME_LCL_EITR_INTERRUPT_TYPE , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE ); REG64_FLD( PU_CME5_CME_LCL_EITR_INTERRUPT_TYPE_LEN , 44 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE_LEN ); REG64_FLD( PU_CME9_CME_LCL_EITR_INTERRUPT_TYPE , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE ); REG64_FLD( PU_CME9_CME_LCL_EITR_INTERRUPT_TYPE_LEN , 44 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE_LEN ); REG64_FLD( PU_CME6_CME_LCL_EITR_INTERRUPT_TYPE , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE ); REG64_FLD( PU_CME6_CME_LCL_EITR_INTERRUPT_TYPE_LEN , 44 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE_LEN ); REG64_FLD( PU_CME10_CME_LCL_EITR_INTERRUPT_TYPE , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE ); REG64_FLD( PU_CME10_CME_LCL_EITR_INTERRUPT_TYPE_LEN , 44 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE_LEN ); REG64_FLD( PU_CME8_CME_LCL_EITR_INTERRUPT_TYPE , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE ); REG64_FLD( PU_CME8_CME_LCL_EITR_INTERRUPT_TYPE_LEN , 44 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE_LEN ); REG64_FLD( PU_CME1_CME_LCL_EITR_INTERRUPT_TYPE , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE ); REG64_FLD( PU_CME1_CME_LCL_EITR_INTERRUPT_TYPE_LEN , 44 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE_LEN ); REG64_FLD( PU_CME0_CME_LCL_EITR_INTERRUPT_TYPE , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE ); REG64_FLD( PU_CME0_CME_LCL_EITR_INTERRUPT_TYPE_LEN , 44 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE_LEN ); REG64_FLD( PU_CME7_CME_LCL_EITR_INTERRUPT_TYPE , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE ); REG64_FLD( PU_CME7_CME_LCL_EITR_INTERRUPT_TYPE_LEN , 44 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_INTERRUPT_TYPE_LEN ); REG64_FLD( PU_CME4_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME4_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); REG64_FLD( PU_CME4_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT ); REG64_FLD( PU_CME4_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); REG64_FLD( PU_CME4_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN ); REG64_FLD( PU_CME4_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME3_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME3_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); REG64_FLD( PU_CME3_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT ); REG64_FLD( PU_CME3_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); REG64_FLD( PU_CME3_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN ); REG64_FLD( PU_CME3_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME11_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME11_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); REG64_FLD( PU_CME11_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT ); REG64_FLD( PU_CME11_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); REG64_FLD( PU_CME11_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN ); REG64_FLD( PU_CME11_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME2_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME2_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); REG64_FLD( PU_CME2_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT ); REG64_FLD( PU_CME2_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); REG64_FLD( PU_CME2_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN ); REG64_FLD( PU_CME2_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME5_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME5_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); REG64_FLD( PU_CME5_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT ); REG64_FLD( PU_CME5_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); REG64_FLD( PU_CME5_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN ); REG64_FLD( PU_CME5_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME9_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME9_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); REG64_FLD( PU_CME9_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT ); REG64_FLD( PU_CME9_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); REG64_FLD( PU_CME9_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN ); REG64_FLD( PU_CME9_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME6_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME6_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); REG64_FLD( PU_CME6_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT ); REG64_FLD( PU_CME6_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); REG64_FLD( PU_CME6_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN ); REG64_FLD( PU_CME6_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME10_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME10_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); REG64_FLD( PU_CME10_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT ); REG64_FLD( PU_CME10_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); REG64_FLD( PU_CME10_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN ); REG64_FLD( PU_CME10_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME8_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME8_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); REG64_FLD( PU_CME8_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT ); REG64_FLD( PU_CME8_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); REG64_FLD( PU_CME8_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN ); REG64_FLD( PU_CME8_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME1_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME1_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); REG64_FLD( PU_CME1_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT ); REG64_FLD( PU_CME1_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); REG64_FLD( PU_CME1_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN ); REG64_FLD( PU_CME1_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME0_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME0_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); REG64_FLD( PU_CME0_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT ); REG64_FLD( PU_CME0_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); REG64_FLD( PU_CME0_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN ); REG64_FLD( PU_CME0_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME7_CME_LCL_ICCR_COMM_ACK , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_COMM_ACK ); REG64_FLD( PU_CME7_CME_LCL_ICCR_COMM_NACK , 1 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_COMM_NACK ); REG64_FLD( PU_CME7_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT , 5 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT ); REG64_FLD( PU_CME7_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_OUT_LEN , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_OUT_LEN ); REG64_FLD( PU_CME7_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN ); REG64_FLD( PU_CME7_CME_LCL_ICCR_ICRR_INTERCME_DIRECT_IN_LEN , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_ICRR_INTERCME_DIRECT_IN_LEN ); REG64_FLD( PU_CME4_CME_LCL_ICRR_COMM_RECV , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_COMM_RECV ); REG64_FLD( PU_CME4_CME_LCL_ICRR_COMM_RECV_LEN , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_COMM_RECV_LEN ); REG64_FLD( PU_CME3_CME_LCL_ICRR_COMM_RECV , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_COMM_RECV ); REG64_FLD( PU_CME3_CME_LCL_ICRR_COMM_RECV_LEN , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_COMM_RECV_LEN ); REG64_FLD( PU_CME11_CME_LCL_ICRR_COMM_RECV , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_COMM_RECV ); REG64_FLD( PU_CME11_CME_LCL_ICRR_COMM_RECV_LEN , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_COMM_RECV_LEN ); REG64_FLD( PU_CME2_CME_LCL_ICRR_COMM_RECV , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_COMM_RECV ); REG64_FLD( PU_CME2_CME_LCL_ICRR_COMM_RECV_LEN , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_COMM_RECV_LEN ); REG64_FLD( PU_CME5_CME_LCL_ICRR_COMM_RECV , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_COMM_RECV ); REG64_FLD( PU_CME5_CME_LCL_ICRR_COMM_RECV_LEN , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_COMM_RECV_LEN ); REG64_FLD( PU_CME9_CME_LCL_ICRR_COMM_RECV , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_COMM_RECV ); REG64_FLD( PU_CME9_CME_LCL_ICRR_COMM_RECV_LEN , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_COMM_RECV_LEN ); REG64_FLD( PU_CME6_CME_LCL_ICRR_COMM_RECV , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_COMM_RECV ); REG64_FLD( PU_CME6_CME_LCL_ICRR_COMM_RECV_LEN , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_COMM_RECV_LEN ); REG64_FLD( PU_CME10_CME_LCL_ICRR_COMM_RECV , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_COMM_RECV ); REG64_FLD( PU_CME10_CME_LCL_ICRR_COMM_RECV_LEN , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_COMM_RECV_LEN ); REG64_FLD( PU_CME8_CME_LCL_ICRR_COMM_RECV , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_COMM_RECV ); REG64_FLD( PU_CME8_CME_LCL_ICRR_COMM_RECV_LEN , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_COMM_RECV_LEN ); REG64_FLD( PU_CME1_CME_LCL_ICRR_COMM_RECV , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_COMM_RECV ); REG64_FLD( PU_CME1_CME_LCL_ICRR_COMM_RECV_LEN , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_COMM_RECV_LEN ); REG64_FLD( PU_CME0_CME_LCL_ICRR_COMM_RECV , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_COMM_RECV ); REG64_FLD( PU_CME0_CME_LCL_ICRR_COMM_RECV_LEN , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_COMM_RECV_LEN ); REG64_FLD( PU_CME7_CME_LCL_ICRR_COMM_RECV , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_COMM_RECV ); REG64_FLD( PU_CME7_CME_LCL_ICRR_COMM_RECV_LEN , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_COMM_RECV_LEN ); REG64_FLD( PU_CME4_CME_LCL_ICSR_COMM_SEND , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_COMM_SEND ); REG64_FLD( PU_CME4_CME_LCL_ICSR_COMM_SEND_LEN , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_COMM_SEND_LEN ); REG64_FLD( PU_CME3_CME_LCL_ICSR_COMM_SEND , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_COMM_SEND ); REG64_FLD( PU_CME3_CME_LCL_ICSR_COMM_SEND_LEN , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_COMM_SEND_LEN ); REG64_FLD( PU_CME11_CME_LCL_ICSR_COMM_SEND , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_COMM_SEND ); REG64_FLD( PU_CME11_CME_LCL_ICSR_COMM_SEND_LEN , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_COMM_SEND_LEN ); REG64_FLD( PU_CME2_CME_LCL_ICSR_COMM_SEND , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_COMM_SEND ); REG64_FLD( PU_CME2_CME_LCL_ICSR_COMM_SEND_LEN , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_COMM_SEND_LEN ); REG64_FLD( PU_CME5_CME_LCL_ICSR_COMM_SEND , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_COMM_SEND ); REG64_FLD( PU_CME5_CME_LCL_ICSR_COMM_SEND_LEN , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_COMM_SEND_LEN ); REG64_FLD( PU_CME9_CME_LCL_ICSR_COMM_SEND , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_COMM_SEND ); REG64_FLD( PU_CME9_CME_LCL_ICSR_COMM_SEND_LEN , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_COMM_SEND_LEN ); REG64_FLD( PU_CME6_CME_LCL_ICSR_COMM_SEND , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_COMM_SEND ); REG64_FLD( PU_CME6_CME_LCL_ICSR_COMM_SEND_LEN , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_COMM_SEND_LEN ); REG64_FLD( PU_CME10_CME_LCL_ICSR_COMM_SEND , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_COMM_SEND ); REG64_FLD( PU_CME10_CME_LCL_ICSR_COMM_SEND_LEN , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_COMM_SEND_LEN ); REG64_FLD( PU_CME8_CME_LCL_ICSR_COMM_SEND , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_COMM_SEND ); REG64_FLD( PU_CME8_CME_LCL_ICSR_COMM_SEND_LEN , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_COMM_SEND_LEN ); REG64_FLD( PU_CME1_CME_LCL_ICSR_COMM_SEND , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_COMM_SEND ); REG64_FLD( PU_CME1_CME_LCL_ICSR_COMM_SEND_LEN , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_COMM_SEND_LEN ); REG64_FLD( PU_CME0_CME_LCL_ICSR_COMM_SEND , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_COMM_SEND ); REG64_FLD( PU_CME0_CME_LCL_ICSR_COMM_SEND_LEN , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_COMM_SEND_LEN ); REG64_FLD( PU_CME7_CME_LCL_ICSR_COMM_SEND , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_COMM_SEND ); REG64_FLD( PU_CME7_CME_LCL_ICSR_COMM_SEND_LEN , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_COMM_SEND_LEN ); REG64_FLD( PU_CME4_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); REG64_FLD( PU_CME4_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SET_ECC_INJECT_ERR ); REG64_FLD( PU_CME4_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME4_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME4_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); REG64_FLD( PU_CME4_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); REG64_FLD( PU_CME4_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME3_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); REG64_FLD( PU_CME3_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SET_ECC_INJECT_ERR ); REG64_FLD( PU_CME3_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME3_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME3_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); REG64_FLD( PU_CME3_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); REG64_FLD( PU_CME3_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME11_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); REG64_FLD( PU_CME11_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SET_ECC_INJECT_ERR ); REG64_FLD( PU_CME11_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME11_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME11_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); REG64_FLD( PU_CME11_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); REG64_FLD( PU_CME11_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME2_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); REG64_FLD( PU_CME2_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SET_ECC_INJECT_ERR ); REG64_FLD( PU_CME2_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME2_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME2_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); REG64_FLD( PU_CME2_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); REG64_FLD( PU_CME2_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME5_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); REG64_FLD( PU_CME5_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SET_ECC_INJECT_ERR ); REG64_FLD( PU_CME5_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME5_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME5_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); REG64_FLD( PU_CME5_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); REG64_FLD( PU_CME5_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME9_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); REG64_FLD( PU_CME9_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SET_ECC_INJECT_ERR ); REG64_FLD( PU_CME9_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME9_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME9_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); REG64_FLD( PU_CME9_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); REG64_FLD( PU_CME9_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME6_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); REG64_FLD( PU_CME6_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SET_ECC_INJECT_ERR ); REG64_FLD( PU_CME6_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME6_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME6_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); REG64_FLD( PU_CME6_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); REG64_FLD( PU_CME6_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME10_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); REG64_FLD( PU_CME10_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SET_ECC_INJECT_ERR ); REG64_FLD( PU_CME10_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME10_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME10_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); REG64_FLD( PU_CME10_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); REG64_FLD( PU_CME10_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME8_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); REG64_FLD( PU_CME8_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SET_ECC_INJECT_ERR ); REG64_FLD( PU_CME8_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME8_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME8_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); REG64_FLD( PU_CME8_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); REG64_FLD( PU_CME8_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME1_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); REG64_FLD( PU_CME1_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SET_ECC_INJECT_ERR ); REG64_FLD( PU_CME1_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME1_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME1_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); REG64_FLD( PU_CME1_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); REG64_FLD( PU_CME1_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME0_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); REG64_FLD( PU_CME0_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SET_ECC_INJECT_ERR ); REG64_FLD( PU_CME0_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME0_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME0_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); REG64_FLD( PU_CME0_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); REG64_FLD( PU_CME0_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME7_CME_LCL_LMCR_RESET_IMPRECISE_QERR , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_RESET_IMPRECISE_QERR ); REG64_FLD( PU_CME7_CME_LCL_LMCR_SET_ECC_INJECT_ERR , 33 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SET_ECC_INJECT_ERR ); REG64_FLD( PU_CME7_CME_LCL_LMCR_C0_HALTED_STOP_OVERRIDE_DISABLE , 34 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_C0_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME7_CME_LCL_LMCR_C1_HALTED_STOP_OVERRIDE_DISABLE , 35 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_C1_HALTED_STOP_OVERRIDE_DISABLE ); REG64_FLD( PU_CME7_CME_LCL_LMCR_FENCE_EISR , 36 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_FENCE_EISR ); REG64_FLD( PU_CME7_CME_LCL_LMCR_SPECIAL_WAKEUP_DONE_OVERRIDE , 37 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_OVERRIDE ); REG64_FLD( PU_CME7_CME_LCL_LMCR_PC_DISABLE_DROOP , 38 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PC_DISABLE_DROOP ); REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T1 , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T2 , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T3 , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME4_CME_LCL_PECESR0_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME4_CME_LCL_PECESR0_USE_PECE , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME4_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T1 , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T2 , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T3 , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME3_CME_LCL_PECESR0_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME3_CME_LCL_PECESR0_USE_PECE , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME3_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T1 , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T2 , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T3 , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME11_CME_LCL_PECESR0_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME11_CME_LCL_PECESR0_USE_PECE , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME11_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T1 , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T2 , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T3 , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME2_CME_LCL_PECESR0_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME2_CME_LCL_PECESR0_USE_PECE , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME2_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T1 , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T2 , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T3 , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME5_CME_LCL_PECESR0_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME5_CME_LCL_PECESR0_USE_PECE , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME5_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T1 , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T2 , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T3 , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME9_CME_LCL_PECESR0_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME9_CME_LCL_PECESR0_USE_PECE , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME9_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T1 , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T2 , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T3 , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME6_CME_LCL_PECESR0_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME6_CME_LCL_PECESR0_USE_PECE , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME6_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T1 , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T2 , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T3 , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME10_CME_LCL_PECESR0_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME10_CME_LCL_PECESR0_USE_PECE , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME10_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T1 , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T2 , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T3 , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME8_CME_LCL_PECESR0_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME8_CME_LCL_PECESR0_USE_PECE , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME8_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T1 , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T2 , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T3 , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME1_CME_LCL_PECESR0_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME1_CME_LCL_PECESR0_USE_PECE , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME1_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T1 , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T2 , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T3 , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME0_CME_LCL_PECESR0_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME0_CME_LCL_PECESR0_USE_PECE , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME0_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T0 , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T1 , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T2 , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T3 , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME7_CME_LCL_PECESR0_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME7_CME_LCL_PECESR0_USE_PECE , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME7_CME_LCL_PECESR0_USE_PECE_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T1 , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T2 , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T3 , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME4_CME_LCL_PECESR1_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME4_CME_LCL_PECESR1_USE_PECE , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME4_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T1 , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T2 , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T3 , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME3_CME_LCL_PECESR1_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME3_CME_LCL_PECESR1_USE_PECE , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME3_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T1 , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T2 , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T3 , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME11_CME_LCL_PECESR1_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME11_CME_LCL_PECESR1_USE_PECE , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME11_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T1 , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T2 , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T3 , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME2_CME_LCL_PECESR1_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME2_CME_LCL_PECESR1_USE_PECE , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME2_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T1 , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T2 , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T3 , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME5_CME_LCL_PECESR1_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME5_CME_LCL_PECESR1_USE_PECE , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME5_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T1 , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T2 , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T3 , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME9_CME_LCL_PECESR1_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME9_CME_LCL_PECESR1_USE_PECE , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME9_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T1 , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T2 , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T3 , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME6_CME_LCL_PECESR1_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME6_CME_LCL_PECESR1_USE_PECE , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME6_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T1 , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T2 , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T3 , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME10_CME_LCL_PECESR1_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME10_CME_LCL_PECESR1_USE_PECE , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME10_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T1 , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T2 , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T3 , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME8_CME_LCL_PECESR1_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME8_CME_LCL_PECESR1_USE_PECE , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME8_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T1 , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T2 , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T3 , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME1_CME_LCL_PECESR1_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME1_CME_LCL_PECESR1_USE_PECE , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME1_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T1 , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T2 , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T3 , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME0_CME_LCL_PECESR1_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME0_CME_LCL_PECESR1_USE_PECE , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME0_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T0 , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0 ); REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T0_LEN , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PECE_C_N_T0_LEN ); REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T1 , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1 ); REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T1_LEN , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PECE_C_N_T1_LEN ); REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T2 , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2 ); REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T2_LEN , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PECE_C_N_T2_LEN ); REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T3 , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3 ); REG64_FLD( PU_CME7_CME_LCL_PECESR1_PECE_C_N_T3_LEN , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PECE_C_N_T3_LEN ); REG64_FLD( PU_CME7_CME_LCL_PECESR1_USE_PECE , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_USE_PECE ); REG64_FLD( PU_CME7_CME_LCL_PECESR1_USE_PECE_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_USE_PECE_LEN ); REG64_FLD( PU_CME4_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); REG64_FLD( PU_CME4_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); REG64_FLD( PU_CME4_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); REG64_FLD( PU_CME4_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); REG64_FLD( PU_CME4_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME4_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_RESERVED_6_8 ); REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_RESERVED_6_8_LEN ); REG64_FLD( PU_CME4_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME4_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME4_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME4_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME4_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_RESERVED_18_29 ); REG64_FLD( PU_CME4_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_RESERVED_18_29_LEN ); REG64_FLD( PU_CME4_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); REG64_FLD( PU_CME4_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME4_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME4_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PM_STATE_C0 ); REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PM_STATE_C0_LEN ); REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C0 ); REG64_FLD( PU_CME4_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C1 ); REG64_FLD( PU_CME4_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C0 ); REG64_FLD( PU_CME4_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C1 ); REG64_FLD( PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0 ); REG64_FLD( PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); REG64_FLD( PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME4_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); REG64_FLD( PU_CME4_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); REG64_FLD( PU_CME4_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C1 ); REG64_FLD( PU_CME3_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); REG64_FLD( PU_CME3_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); REG64_FLD( PU_CME3_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); REG64_FLD( PU_CME3_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); REG64_FLD( PU_CME3_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME3_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_RESERVED_6_8 ); REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_RESERVED_6_8_LEN ); REG64_FLD( PU_CME3_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME3_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME3_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME3_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME3_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_RESERVED_18_29 ); REG64_FLD( PU_CME3_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_RESERVED_18_29_LEN ); REG64_FLD( PU_CME3_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); REG64_FLD( PU_CME3_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME3_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME3_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PM_STATE_C0 ); REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PM_STATE_C0_LEN ); REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C0 ); REG64_FLD( PU_CME3_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C1 ); REG64_FLD( PU_CME3_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C0 ); REG64_FLD( PU_CME3_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C1 ); REG64_FLD( PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0 ); REG64_FLD( PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); REG64_FLD( PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME3_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); REG64_FLD( PU_CME3_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); REG64_FLD( PU_CME3_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C1 ); REG64_FLD( PU_CME11_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); REG64_FLD( PU_CME11_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); REG64_FLD( PU_CME11_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); REG64_FLD( PU_CME11_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); REG64_FLD( PU_CME11_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME11_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_RESERVED_6_8 ); REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_RESERVED_6_8_LEN ); REG64_FLD( PU_CME11_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME11_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME11_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME11_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME11_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_RESERVED_18_29 ); REG64_FLD( PU_CME11_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_RESERVED_18_29_LEN ); REG64_FLD( PU_CME11_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); REG64_FLD( PU_CME11_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME11_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME11_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PM_STATE_C0 ); REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PM_STATE_C0_LEN ); REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C0 ); REG64_FLD( PU_CME11_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C1 ); REG64_FLD( PU_CME11_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C0 ); REG64_FLD( PU_CME11_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C1 ); REG64_FLD( PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0 ); REG64_FLD( PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); REG64_FLD( PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME11_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); REG64_FLD( PU_CME11_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); REG64_FLD( PU_CME11_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C1 ); REG64_FLD( PU_CME2_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); REG64_FLD( PU_CME2_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); REG64_FLD( PU_CME2_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); REG64_FLD( PU_CME2_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); REG64_FLD( PU_CME2_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME2_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_RESERVED_6_8 ); REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_RESERVED_6_8_LEN ); REG64_FLD( PU_CME2_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME2_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME2_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME2_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME2_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_RESERVED_18_29 ); REG64_FLD( PU_CME2_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_RESERVED_18_29_LEN ); REG64_FLD( PU_CME2_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); REG64_FLD( PU_CME2_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME2_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME2_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PM_STATE_C0 ); REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PM_STATE_C0_LEN ); REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C0 ); REG64_FLD( PU_CME2_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C1 ); REG64_FLD( PU_CME2_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C0 ); REG64_FLD( PU_CME2_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C1 ); REG64_FLD( PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0 ); REG64_FLD( PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); REG64_FLD( PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME2_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); REG64_FLD( PU_CME2_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); REG64_FLD( PU_CME2_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C1 ); REG64_FLD( PU_CME5_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); REG64_FLD( PU_CME5_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); REG64_FLD( PU_CME5_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); REG64_FLD( PU_CME5_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); REG64_FLD( PU_CME5_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME5_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_RESERVED_6_8 ); REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_RESERVED_6_8_LEN ); REG64_FLD( PU_CME5_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME5_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME5_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME5_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME5_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_RESERVED_18_29 ); REG64_FLD( PU_CME5_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_RESERVED_18_29_LEN ); REG64_FLD( PU_CME5_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); REG64_FLD( PU_CME5_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME5_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME5_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PM_STATE_C0 ); REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PM_STATE_C0_LEN ); REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C0 ); REG64_FLD( PU_CME5_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C1 ); REG64_FLD( PU_CME5_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C0 ); REG64_FLD( PU_CME5_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C1 ); REG64_FLD( PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0 ); REG64_FLD( PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); REG64_FLD( PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME5_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); REG64_FLD( PU_CME5_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); REG64_FLD( PU_CME5_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C1 ); REG64_FLD( PU_CME9_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); REG64_FLD( PU_CME9_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); REG64_FLD( PU_CME9_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); REG64_FLD( PU_CME9_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); REG64_FLD( PU_CME9_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME9_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_RESERVED_6_8 ); REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_RESERVED_6_8_LEN ); REG64_FLD( PU_CME9_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME9_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME9_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME9_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME9_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_RESERVED_18_29 ); REG64_FLD( PU_CME9_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_RESERVED_18_29_LEN ); REG64_FLD( PU_CME9_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); REG64_FLD( PU_CME9_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME9_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME9_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PM_STATE_C0 ); REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PM_STATE_C0_LEN ); REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C0 ); REG64_FLD( PU_CME9_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C1 ); REG64_FLD( PU_CME9_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C0 ); REG64_FLD( PU_CME9_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C1 ); REG64_FLD( PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0 ); REG64_FLD( PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); REG64_FLD( PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME9_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); REG64_FLD( PU_CME9_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); REG64_FLD( PU_CME9_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C1 ); REG64_FLD( PU_CME6_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); REG64_FLD( PU_CME6_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); REG64_FLD( PU_CME6_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); REG64_FLD( PU_CME6_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); REG64_FLD( PU_CME6_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME6_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_RESERVED_6_8 ); REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_RESERVED_6_8_LEN ); REG64_FLD( PU_CME6_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME6_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME6_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME6_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME6_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_RESERVED_18_29 ); REG64_FLD( PU_CME6_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_RESERVED_18_29_LEN ); REG64_FLD( PU_CME6_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); REG64_FLD( PU_CME6_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME6_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME6_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PM_STATE_C0 ); REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PM_STATE_C0_LEN ); REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C0 ); REG64_FLD( PU_CME6_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C1 ); REG64_FLD( PU_CME6_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C0 ); REG64_FLD( PU_CME6_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C1 ); REG64_FLD( PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0 ); REG64_FLD( PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); REG64_FLD( PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME6_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); REG64_FLD( PU_CME6_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); REG64_FLD( PU_CME6_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C1 ); REG64_FLD( PU_CME10_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); REG64_FLD( PU_CME10_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); REG64_FLD( PU_CME10_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); REG64_FLD( PU_CME10_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); REG64_FLD( PU_CME10_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME10_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_RESERVED_6_8 ); REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_RESERVED_6_8_LEN ); REG64_FLD( PU_CME10_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME10_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME10_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME10_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME10_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_RESERVED_18_29 ); REG64_FLD( PU_CME10_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_RESERVED_18_29_LEN ); REG64_FLD( PU_CME10_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); REG64_FLD( PU_CME10_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME10_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME10_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PM_STATE_C0 ); REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PM_STATE_C0_LEN ); REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C0 ); REG64_FLD( PU_CME10_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C1 ); REG64_FLD( PU_CME10_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C0 ); REG64_FLD( PU_CME10_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C1 ); REG64_FLD( PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0 ); REG64_FLD( PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); REG64_FLD( PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME10_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); REG64_FLD( PU_CME10_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); REG64_FLD( PU_CME10_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C1 ); REG64_FLD( PU_CME8_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); REG64_FLD( PU_CME8_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); REG64_FLD( PU_CME8_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); REG64_FLD( PU_CME8_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); REG64_FLD( PU_CME8_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME8_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_RESERVED_6_8 ); REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_RESERVED_6_8_LEN ); REG64_FLD( PU_CME8_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME8_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME8_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME8_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME8_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_RESERVED_18_29 ); REG64_FLD( PU_CME8_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_RESERVED_18_29_LEN ); REG64_FLD( PU_CME8_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); REG64_FLD( PU_CME8_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME8_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME8_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PM_STATE_C0 ); REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PM_STATE_C0_LEN ); REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C0 ); REG64_FLD( PU_CME8_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C1 ); REG64_FLD( PU_CME8_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C0 ); REG64_FLD( PU_CME8_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C1 ); REG64_FLD( PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0 ); REG64_FLD( PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); REG64_FLD( PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME8_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); REG64_FLD( PU_CME8_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); REG64_FLD( PU_CME8_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C1 ); REG64_FLD( PU_CME1_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); REG64_FLD( PU_CME1_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); REG64_FLD( PU_CME1_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); REG64_FLD( PU_CME1_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); REG64_FLD( PU_CME1_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME1_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_RESERVED_6_8 ); REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_RESERVED_6_8_LEN ); REG64_FLD( PU_CME1_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME1_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME1_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME1_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME1_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_RESERVED_18_29 ); REG64_FLD( PU_CME1_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_RESERVED_18_29_LEN ); REG64_FLD( PU_CME1_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); REG64_FLD( PU_CME1_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME1_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME1_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PM_STATE_C0 ); REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PM_STATE_C0_LEN ); REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C0 ); REG64_FLD( PU_CME1_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C1 ); REG64_FLD( PU_CME1_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C0 ); REG64_FLD( PU_CME1_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C1 ); REG64_FLD( PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0 ); REG64_FLD( PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); REG64_FLD( PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME1_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); REG64_FLD( PU_CME1_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); REG64_FLD( PU_CME1_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C1 ); REG64_FLD( PU_CME0_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); REG64_FLD( PU_CME0_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); REG64_FLD( PU_CME0_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); REG64_FLD( PU_CME0_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); REG64_FLD( PU_CME0_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME0_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_RESERVED_6_8 ); REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_RESERVED_6_8_LEN ); REG64_FLD( PU_CME0_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME0_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME0_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME0_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME0_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_RESERVED_18_29 ); REG64_FLD( PU_CME0_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_RESERVED_18_29_LEN ); REG64_FLD( PU_CME0_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); REG64_FLD( PU_CME0_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME0_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME0_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PM_STATE_C0 ); REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PM_STATE_C0_LEN ); REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C0 ); REG64_FLD( PU_CME0_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C1 ); REG64_FLD( PU_CME0_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C0 ); REG64_FLD( PU_CME0_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C1 ); REG64_FLD( PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0 ); REG64_FLD( PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); REG64_FLD( PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME0_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); REG64_FLD( PU_CME0_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); REG64_FLD( PU_CME0_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C1 ); REG64_FLD( PU_CME7_CME_LCL_SISR_PM_ENTRY_ACK_C0_ACTUAL , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C0_ACTUAL ); REG64_FLD( PU_CME7_CME_LCL_SISR_PM_ENTRY_ACK_C1_ACTUAL , 1 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PM_ENTRY_ACK_C1_ACTUAL ); REG64_FLD( PU_CME7_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C0_ACTUAL , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C0_ACTUAL ); REG64_FLD( PU_CME7_CME_LCL_SISR_PM_BLOCK_INTERRUPTS_C1_ACTUAL , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PM_BLOCK_INTERRUPTS_C1_ACTUAL ); REG64_FLD( PU_CME7_CME_LCL_SISR_PM_EXIT_C0_ACTUAL , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PM_EXIT_C0_ACTUAL ); REG64_FLD( PU_CME7_CME_LCL_SISR_PM_EXIT_C1_ACTUAL , 5 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PM_EXIT_C1_ACTUAL ); REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_6_8 , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_RESERVED_6_8 ); REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_6_8_LEN , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_RESERVED_6_8_LEN ); REG64_FLD( PU_CME7_CME_LCL_SISR_PC_FUSED_CORE_MODE , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PC_FUSED_CORE_MODE ); REG64_FLD( PU_CME7_CME_LCL_SISR_PCBMUX_GRANT_C0 , 10 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C0 ); REG64_FLD( PU_CME7_CME_LCL_SISR_PCBMUX_GRANT_C1 , 11 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PCBMUX_GRANT_C1 ); REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_12_15 , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME7_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C0_ACTUAL , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C0_ACTUAL ); REG64_FLD( PU_CME7_CME_LCL_SISR_SPECIAL_WAKEUP_DONE_C1_ACTUAL , 17 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SPECIAL_WAKEUP_DONE_C1_ACTUAL ); REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_18_29 , 18 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_RESERVED_18_29 ); REG64_FLD( PU_CME7_CME_LCL_SISR_RESERVED_18_29_LEN , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_RESERVED_18_29_LEN ); REG64_FLD( PU_CME7_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1 , 30 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1 ); REG64_FLD( PU_CME7_CME_LCL_SISR_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_L2_INTF_QUIESCE_DONE_LVL_0_1_LEN ); REG64_FLD( PU_CME7_CME_LCL_SISR_PC_UNMASKED_ATTN_C0 , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C0 ); REG64_FLD( PU_CME7_CME_LCL_SISR_PC_UNMASKED_ATTN_C1 , 33 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PC_UNMASKED_ATTN_C1 ); REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_ACTIVE_C0 , 34 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C0 ); REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_ACTIVE_C1 , 35 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PM_STATE_ACTIVE_C1 ); REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_C0 , 36 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PM_STATE_C0 ); REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_C0_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PM_STATE_C0_LEN ); REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_C1 , 40 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PM_STATE_C1 ); REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_C1_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PM_STATE_C1_LEN ); REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_ALL_HV_C0 , 44 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C0 ); REG64_FLD( PU_CME7_CME_LCL_SISR_PM_STATE_ALL_HV_C1 , 45 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PM_STATE_ALL_HV_C1 ); REG64_FLD( PU_CME7_CME_LCL_SISR_PC_INSTR_RUNNING_C0 , 46 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C0 ); REG64_FLD( PU_CME7_CME_LCL_SISR_PC_INSTR_RUNNING_C1 , 47 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PC_INSTR_RUNNING_C1 ); REG64_FLD( PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C0 , 48 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0 ); REG64_FLD( PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C0_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C0_LEN ); REG64_FLD( PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C1 , 52 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1 ); REG64_FLD( PU_CME7_CME_LCL_SISR_PC_NON_HV_RUNNING_C1_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PC_NON_HV_RUNNING_C1_LEN ); REG64_FLD( PU_CME7_CME_LCL_SISR_ALLOW_REG_WAKEUP_C0 , 56 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C0 ); REG64_FLD( PU_CME7_CME_LCL_SISR_ALLOW_REG_WAKEUP_C1 , 57 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_ALLOW_REG_WAKEUP_C1 ); REG64_FLD( PU_CME4_CME_LCL_TSEL_FIT_SEL , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_FIT_SEL ); REG64_FLD( PU_CME4_CME_LCL_TSEL_FIT_SEL_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_FIT_SEL_LEN ); REG64_FLD( PU_CME4_CME_LCL_TSEL_WATCHDOG_SEL , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL ); REG64_FLD( PU_CME4_CME_LCL_TSEL_WATCHDOG_SEL_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL_LEN ); REG64_FLD( PU_CME3_CME_LCL_TSEL_FIT_SEL , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_FIT_SEL ); REG64_FLD( PU_CME3_CME_LCL_TSEL_FIT_SEL_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_FIT_SEL_LEN ); REG64_FLD( PU_CME3_CME_LCL_TSEL_WATCHDOG_SEL , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL ); REG64_FLD( PU_CME3_CME_LCL_TSEL_WATCHDOG_SEL_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL_LEN ); REG64_FLD( PU_CME11_CME_LCL_TSEL_FIT_SEL , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_FIT_SEL ); REG64_FLD( PU_CME11_CME_LCL_TSEL_FIT_SEL_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_FIT_SEL_LEN ); REG64_FLD( PU_CME11_CME_LCL_TSEL_WATCHDOG_SEL , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL ); REG64_FLD( PU_CME11_CME_LCL_TSEL_WATCHDOG_SEL_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL_LEN ); REG64_FLD( PU_CME2_CME_LCL_TSEL_FIT_SEL , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_FIT_SEL ); REG64_FLD( PU_CME2_CME_LCL_TSEL_FIT_SEL_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_FIT_SEL_LEN ); REG64_FLD( PU_CME2_CME_LCL_TSEL_WATCHDOG_SEL , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL ); REG64_FLD( PU_CME2_CME_LCL_TSEL_WATCHDOG_SEL_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL_LEN ); REG64_FLD( PU_CME5_CME_LCL_TSEL_FIT_SEL , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_FIT_SEL ); REG64_FLD( PU_CME5_CME_LCL_TSEL_FIT_SEL_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_FIT_SEL_LEN ); REG64_FLD( PU_CME5_CME_LCL_TSEL_WATCHDOG_SEL , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL ); REG64_FLD( PU_CME5_CME_LCL_TSEL_WATCHDOG_SEL_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL_LEN ); REG64_FLD( PU_CME9_CME_LCL_TSEL_FIT_SEL , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_FIT_SEL ); REG64_FLD( PU_CME9_CME_LCL_TSEL_FIT_SEL_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_FIT_SEL_LEN ); REG64_FLD( PU_CME9_CME_LCL_TSEL_WATCHDOG_SEL , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL ); REG64_FLD( PU_CME9_CME_LCL_TSEL_WATCHDOG_SEL_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL_LEN ); REG64_FLD( PU_CME6_CME_LCL_TSEL_FIT_SEL , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_FIT_SEL ); REG64_FLD( PU_CME6_CME_LCL_TSEL_FIT_SEL_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_FIT_SEL_LEN ); REG64_FLD( PU_CME6_CME_LCL_TSEL_WATCHDOG_SEL , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL ); REG64_FLD( PU_CME6_CME_LCL_TSEL_WATCHDOG_SEL_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL_LEN ); REG64_FLD( PU_CME10_CME_LCL_TSEL_FIT_SEL , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_FIT_SEL ); REG64_FLD( PU_CME10_CME_LCL_TSEL_FIT_SEL_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_FIT_SEL_LEN ); REG64_FLD( PU_CME10_CME_LCL_TSEL_WATCHDOG_SEL , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL ); REG64_FLD( PU_CME10_CME_LCL_TSEL_WATCHDOG_SEL_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL_LEN ); REG64_FLD( PU_CME8_CME_LCL_TSEL_FIT_SEL , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_FIT_SEL ); REG64_FLD( PU_CME8_CME_LCL_TSEL_FIT_SEL_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_FIT_SEL_LEN ); REG64_FLD( PU_CME8_CME_LCL_TSEL_WATCHDOG_SEL , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL ); REG64_FLD( PU_CME8_CME_LCL_TSEL_WATCHDOG_SEL_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL_LEN ); REG64_FLD( PU_CME1_CME_LCL_TSEL_FIT_SEL , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_FIT_SEL ); REG64_FLD( PU_CME1_CME_LCL_TSEL_FIT_SEL_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_FIT_SEL_LEN ); REG64_FLD( PU_CME1_CME_LCL_TSEL_WATCHDOG_SEL , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL ); REG64_FLD( PU_CME1_CME_LCL_TSEL_WATCHDOG_SEL_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL_LEN ); REG64_FLD( PU_CME0_CME_LCL_TSEL_FIT_SEL , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_FIT_SEL ); REG64_FLD( PU_CME0_CME_LCL_TSEL_FIT_SEL_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_FIT_SEL_LEN ); REG64_FLD( PU_CME0_CME_LCL_TSEL_WATCHDOG_SEL , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL ); REG64_FLD( PU_CME0_CME_LCL_TSEL_WATCHDOG_SEL_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL_LEN ); REG64_FLD( PU_CME7_CME_LCL_TSEL_FIT_SEL , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_FIT_SEL ); REG64_FLD( PU_CME7_CME_LCL_TSEL_FIT_SEL_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_FIT_SEL_LEN ); REG64_FLD( PU_CME7_CME_LCL_TSEL_WATCHDOG_SEL , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL ); REG64_FLD( PU_CME7_CME_LCL_TSEL_WATCHDOG_SEL_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_WATCHDOG_SEL_LEN ); REG64_FLD( PU_CME4_CME_SCOM_AFSR_INST_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE ); REG64_FLD( PU_CME4_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME4_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE ); REG64_FLD( PU_CME4_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME4_CME_SCOM_AFSR_SAMPLE_VALID , 63 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SAMPLE_VALID ); REG64_FLD( PU_CME3_CME_SCOM_AFSR_INST_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE ); REG64_FLD( PU_CME3_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME3_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE ); REG64_FLD( PU_CME3_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME3_CME_SCOM_AFSR_SAMPLE_VALID , 63 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SAMPLE_VALID ); REG64_FLD( PU_CME11_CME_SCOM_AFSR_INST_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE ); REG64_FLD( PU_CME11_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME11_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE ); REG64_FLD( PU_CME11_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME11_CME_SCOM_AFSR_SAMPLE_VALID , 63 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SAMPLE_VALID ); REG64_FLD( PU_CME2_CME_SCOM_AFSR_INST_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE ); REG64_FLD( PU_CME2_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME2_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE ); REG64_FLD( PU_CME2_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME2_CME_SCOM_AFSR_SAMPLE_VALID , 63 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SAMPLE_VALID ); REG64_FLD( PU_CME5_CME_SCOM_AFSR_INST_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE ); REG64_FLD( PU_CME5_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME5_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE ); REG64_FLD( PU_CME5_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME5_CME_SCOM_AFSR_SAMPLE_VALID , 63 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SAMPLE_VALID ); REG64_FLD( PU_CME9_CME_SCOM_AFSR_INST_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE ); REG64_FLD( PU_CME9_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME9_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE ); REG64_FLD( PU_CME9_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME9_CME_SCOM_AFSR_SAMPLE_VALID , 63 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SAMPLE_VALID ); REG64_FLD( PU_CME6_CME_SCOM_AFSR_INST_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE ); REG64_FLD( PU_CME6_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME6_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE ); REG64_FLD( PU_CME6_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME6_CME_SCOM_AFSR_SAMPLE_VALID , 63 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SAMPLE_VALID ); REG64_FLD( PU_CME10_CME_SCOM_AFSR_INST_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE ); REG64_FLD( PU_CME10_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME10_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE ); REG64_FLD( PU_CME10_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME10_CME_SCOM_AFSR_SAMPLE_VALID , 63 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SAMPLE_VALID ); REG64_FLD( PU_CME8_CME_SCOM_AFSR_INST_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE ); REG64_FLD( PU_CME8_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME8_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE ); REG64_FLD( PU_CME8_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME8_CME_SCOM_AFSR_SAMPLE_VALID , 63 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SAMPLE_VALID ); REG64_FLD( PU_CME1_CME_SCOM_AFSR_INST_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE ); REG64_FLD( PU_CME1_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME1_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE ); REG64_FLD( PU_CME1_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME1_CME_SCOM_AFSR_SAMPLE_VALID , 63 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SAMPLE_VALID ); REG64_FLD( PU_CME0_CME_SCOM_AFSR_INST_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE ); REG64_FLD( PU_CME0_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME0_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE ); REG64_FLD( PU_CME0_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME0_CME_SCOM_AFSR_SAMPLE_VALID , 63 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SAMPLE_VALID ); REG64_FLD( PU_CME7_CME_SCOM_AFSR_INST_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE ); REG64_FLD( PU_CME7_CME_SCOM_AFSR_INST_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_INST_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME7_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE ); REG64_FLD( PU_CME7_CME_SCOM_AFSR_AVG_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_AVG_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME7_CME_SCOM_AFSR_SAMPLE_VALID , 63 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SAMPLE_VALID ); REG64_FLD( PU_CME4_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE ); REG64_FLD( PU_CME4_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME4_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE ); REG64_FLD( PU_CME4_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME3_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE ); REG64_FLD( PU_CME3_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME3_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE ); REG64_FLD( PU_CME3_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME11_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE ); REG64_FLD( PU_CME11_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME11_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE ); REG64_FLD( PU_CME11_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME2_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE ); REG64_FLD( PU_CME2_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME2_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE ); REG64_FLD( PU_CME2_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME5_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE ); REG64_FLD( PU_CME5_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME5_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE ); REG64_FLD( PU_CME5_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME9_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE ); REG64_FLD( PU_CME9_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME9_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE ); REG64_FLD( PU_CME9_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME6_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE ); REG64_FLD( PU_CME6_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME6_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE ); REG64_FLD( PU_CME6_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME10_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE ); REG64_FLD( PU_CME10_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME10_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE ); REG64_FLD( PU_CME10_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME8_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE ); REG64_FLD( PU_CME8_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME8_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE ); REG64_FLD( PU_CME8_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME1_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE ); REG64_FLD( PU_CME1_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME1_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE ); REG64_FLD( PU_CME1_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME0_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE ); REG64_FLD( PU_CME0_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME0_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE ); REG64_FLD( PU_CME0_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME7_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE ); REG64_FLD( PU_CME7_CME_SCOM_AFTR_MAX_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MAX_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME7_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE ); REG64_FLD( PU_CME7_CME_SCOM_AFTR_MIN_CYCLE_SAMPLE_LEN , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MIN_CYCLE_SAMPLE_LEN ); REG64_FLD( PU_CME4_CME_SCOM_BCECSR_BUSY , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_BUSY ); REG64_FLD( PU_CME4_CME_SCOM_BCECSR_ERROR , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_ERROR ); REG64_FLD( PU_CME4_CME_SCOM_BCECSR_RNW , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_RNW ); REG64_FLD( PU_CME4_CME_SCOM_BCECSR_BARSEL , 5 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_BARSEL ); REG64_FLD( PU_CME4_CME_SCOM_BCECSR_PRIORITY , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_PRIORITY ); REG64_FLD( PU_CME4_CME_SCOM_BCECSR_INJECT_ERR , 7 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_INJECT_ERR ); REG64_FLD( PU_CME4_CME_SCOM_BCECSR_TYPE , 13 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_TYPE ); REG64_FLD( PU_CME4_CME_SCOM_BCECSR_TYPE_LEN , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_TYPE_LEN ); REG64_FLD( PU_CME4_CME_SCOM_BCECSR_NUM_BLOCKS , 17 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS ); REG64_FLD( PU_CME4_CME_SCOM_BCECSR_NUM_BLOCKS_LEN , 11 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS_LEN ); REG64_FLD( PU_CME4_CME_SCOM_BCECSR_SBASE , 28 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SBASE ); REG64_FLD( PU_CME4_CME_SCOM_BCECSR_SBASE_LEN , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SBASE_LEN ); REG64_FLD( PU_CME4_CME_SCOM_BCECSR_MBASE , 42 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MBASE ); REG64_FLD( PU_CME4_CME_SCOM_BCECSR_MBASE_LEN , 22 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MBASE_LEN ); REG64_FLD( PU_CME3_CME_SCOM_BCECSR_BUSY , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_BUSY ); REG64_FLD( PU_CME3_CME_SCOM_BCECSR_ERROR , 1 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_ERROR ); REG64_FLD( PU_CME3_CME_SCOM_BCECSR_RNW , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_RNW ); REG64_FLD( PU_CME3_CME_SCOM_BCECSR_BARSEL , 5 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_BARSEL ); REG64_FLD( PU_CME3_CME_SCOM_BCECSR_PRIORITY , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_PRIORITY ); REG64_FLD( PU_CME3_CME_SCOM_BCECSR_INJECT_ERR , 7 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_INJECT_ERR ); REG64_FLD( PU_CME3_CME_SCOM_BCECSR_TYPE , 13 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_TYPE ); REG64_FLD( PU_CME3_CME_SCOM_BCECSR_TYPE_LEN , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_TYPE_LEN ); REG64_FLD( PU_CME3_CME_SCOM_BCECSR_NUM_BLOCKS , 17 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS ); REG64_FLD( PU_CME3_CME_SCOM_BCECSR_NUM_BLOCKS_LEN , 11 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS_LEN ); REG64_FLD( PU_CME3_CME_SCOM_BCECSR_SBASE , 28 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SBASE ); REG64_FLD( PU_CME3_CME_SCOM_BCECSR_SBASE_LEN , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SBASE_LEN ); REG64_FLD( PU_CME3_CME_SCOM_BCECSR_MBASE , 42 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MBASE ); REG64_FLD( PU_CME3_CME_SCOM_BCECSR_MBASE_LEN , 22 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MBASE_LEN ); REG64_FLD( PU_CME11_CME_SCOM_BCECSR_BUSY , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_BUSY ); REG64_FLD( PU_CME11_CME_SCOM_BCECSR_ERROR , 1 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_ERROR ); REG64_FLD( PU_CME11_CME_SCOM_BCECSR_RNW , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_RNW ); REG64_FLD( PU_CME11_CME_SCOM_BCECSR_BARSEL , 5 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_BARSEL ); REG64_FLD( PU_CME11_CME_SCOM_BCECSR_PRIORITY , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_PRIORITY ); REG64_FLD( PU_CME11_CME_SCOM_BCECSR_INJECT_ERR , 7 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_INJECT_ERR ); REG64_FLD( PU_CME11_CME_SCOM_BCECSR_TYPE , 13 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_TYPE ); REG64_FLD( PU_CME11_CME_SCOM_BCECSR_TYPE_LEN , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_TYPE_LEN ); REG64_FLD( PU_CME11_CME_SCOM_BCECSR_NUM_BLOCKS , 17 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS ); REG64_FLD( PU_CME11_CME_SCOM_BCECSR_NUM_BLOCKS_LEN , 11 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS_LEN ); REG64_FLD( PU_CME11_CME_SCOM_BCECSR_SBASE , 28 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SBASE ); REG64_FLD( PU_CME11_CME_SCOM_BCECSR_SBASE_LEN , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SBASE_LEN ); REG64_FLD( PU_CME11_CME_SCOM_BCECSR_MBASE , 42 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MBASE ); REG64_FLD( PU_CME11_CME_SCOM_BCECSR_MBASE_LEN , 22 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MBASE_LEN ); REG64_FLD( PU_CME2_CME_SCOM_BCECSR_BUSY , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_BUSY ); REG64_FLD( PU_CME2_CME_SCOM_BCECSR_ERROR , 1 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_ERROR ); REG64_FLD( PU_CME2_CME_SCOM_BCECSR_RNW , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_RNW ); REG64_FLD( PU_CME2_CME_SCOM_BCECSR_BARSEL , 5 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_BARSEL ); REG64_FLD( PU_CME2_CME_SCOM_BCECSR_PRIORITY , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_PRIORITY ); REG64_FLD( PU_CME2_CME_SCOM_BCECSR_INJECT_ERR , 7 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_INJECT_ERR ); REG64_FLD( PU_CME2_CME_SCOM_BCECSR_TYPE , 13 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_TYPE ); REG64_FLD( PU_CME2_CME_SCOM_BCECSR_TYPE_LEN , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_TYPE_LEN ); REG64_FLD( PU_CME2_CME_SCOM_BCECSR_NUM_BLOCKS , 17 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS ); REG64_FLD( PU_CME2_CME_SCOM_BCECSR_NUM_BLOCKS_LEN , 11 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS_LEN ); REG64_FLD( PU_CME2_CME_SCOM_BCECSR_SBASE , 28 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SBASE ); REG64_FLD( PU_CME2_CME_SCOM_BCECSR_SBASE_LEN , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SBASE_LEN ); REG64_FLD( PU_CME2_CME_SCOM_BCECSR_MBASE , 42 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MBASE ); REG64_FLD( PU_CME2_CME_SCOM_BCECSR_MBASE_LEN , 22 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MBASE_LEN ); REG64_FLD( PU_CME5_CME_SCOM_BCECSR_BUSY , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_BUSY ); REG64_FLD( PU_CME5_CME_SCOM_BCECSR_ERROR , 1 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_ERROR ); REG64_FLD( PU_CME5_CME_SCOM_BCECSR_RNW , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_RNW ); REG64_FLD( PU_CME5_CME_SCOM_BCECSR_BARSEL , 5 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_BARSEL ); REG64_FLD( PU_CME5_CME_SCOM_BCECSR_PRIORITY , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_PRIORITY ); REG64_FLD( PU_CME5_CME_SCOM_BCECSR_INJECT_ERR , 7 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_INJECT_ERR ); REG64_FLD( PU_CME5_CME_SCOM_BCECSR_TYPE , 13 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_TYPE ); REG64_FLD( PU_CME5_CME_SCOM_BCECSR_TYPE_LEN , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_TYPE_LEN ); REG64_FLD( PU_CME5_CME_SCOM_BCECSR_NUM_BLOCKS , 17 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS ); REG64_FLD( PU_CME5_CME_SCOM_BCECSR_NUM_BLOCKS_LEN , 11 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS_LEN ); REG64_FLD( PU_CME5_CME_SCOM_BCECSR_SBASE , 28 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SBASE ); REG64_FLD( PU_CME5_CME_SCOM_BCECSR_SBASE_LEN , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SBASE_LEN ); REG64_FLD( PU_CME5_CME_SCOM_BCECSR_MBASE , 42 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MBASE ); REG64_FLD( PU_CME5_CME_SCOM_BCECSR_MBASE_LEN , 22 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MBASE_LEN ); REG64_FLD( PU_CME9_CME_SCOM_BCECSR_BUSY , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_BUSY ); REG64_FLD( PU_CME9_CME_SCOM_BCECSR_ERROR , 1 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_ERROR ); REG64_FLD( PU_CME9_CME_SCOM_BCECSR_RNW , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_RNW ); REG64_FLD( PU_CME9_CME_SCOM_BCECSR_BARSEL , 5 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_BARSEL ); REG64_FLD( PU_CME9_CME_SCOM_BCECSR_PRIORITY , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_PRIORITY ); REG64_FLD( PU_CME9_CME_SCOM_BCECSR_INJECT_ERR , 7 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_INJECT_ERR ); REG64_FLD( PU_CME9_CME_SCOM_BCECSR_TYPE , 13 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_TYPE ); REG64_FLD( PU_CME9_CME_SCOM_BCECSR_TYPE_LEN , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_TYPE_LEN ); REG64_FLD( PU_CME9_CME_SCOM_BCECSR_NUM_BLOCKS , 17 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS ); REG64_FLD( PU_CME9_CME_SCOM_BCECSR_NUM_BLOCKS_LEN , 11 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS_LEN ); REG64_FLD( PU_CME9_CME_SCOM_BCECSR_SBASE , 28 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SBASE ); REG64_FLD( PU_CME9_CME_SCOM_BCECSR_SBASE_LEN , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SBASE_LEN ); REG64_FLD( PU_CME9_CME_SCOM_BCECSR_MBASE , 42 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MBASE ); REG64_FLD( PU_CME9_CME_SCOM_BCECSR_MBASE_LEN , 22 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MBASE_LEN ); REG64_FLD( PU_CME6_CME_SCOM_BCECSR_BUSY , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_BUSY ); REG64_FLD( PU_CME6_CME_SCOM_BCECSR_ERROR , 1 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_ERROR ); REG64_FLD( PU_CME6_CME_SCOM_BCECSR_RNW , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_RNW ); REG64_FLD( PU_CME6_CME_SCOM_BCECSR_BARSEL , 5 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_BARSEL ); REG64_FLD( PU_CME6_CME_SCOM_BCECSR_PRIORITY , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_PRIORITY ); REG64_FLD( PU_CME6_CME_SCOM_BCECSR_INJECT_ERR , 7 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_INJECT_ERR ); REG64_FLD( PU_CME6_CME_SCOM_BCECSR_TYPE , 13 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_TYPE ); REG64_FLD( PU_CME6_CME_SCOM_BCECSR_TYPE_LEN , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_TYPE_LEN ); REG64_FLD( PU_CME6_CME_SCOM_BCECSR_NUM_BLOCKS , 17 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS ); REG64_FLD( PU_CME6_CME_SCOM_BCECSR_NUM_BLOCKS_LEN , 11 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS_LEN ); REG64_FLD( PU_CME6_CME_SCOM_BCECSR_SBASE , 28 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SBASE ); REG64_FLD( PU_CME6_CME_SCOM_BCECSR_SBASE_LEN , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SBASE_LEN ); REG64_FLD( PU_CME6_CME_SCOM_BCECSR_MBASE , 42 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MBASE ); REG64_FLD( PU_CME6_CME_SCOM_BCECSR_MBASE_LEN , 22 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MBASE_LEN ); REG64_FLD( PU_CME10_CME_SCOM_BCECSR_BUSY , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_BUSY ); REG64_FLD( PU_CME10_CME_SCOM_BCECSR_ERROR , 1 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_ERROR ); REG64_FLD( PU_CME10_CME_SCOM_BCECSR_RNW , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_RNW ); REG64_FLD( PU_CME10_CME_SCOM_BCECSR_BARSEL , 5 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_BARSEL ); REG64_FLD( PU_CME10_CME_SCOM_BCECSR_PRIORITY , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_PRIORITY ); REG64_FLD( PU_CME10_CME_SCOM_BCECSR_INJECT_ERR , 7 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_INJECT_ERR ); REG64_FLD( PU_CME10_CME_SCOM_BCECSR_TYPE , 13 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_TYPE ); REG64_FLD( PU_CME10_CME_SCOM_BCECSR_TYPE_LEN , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_TYPE_LEN ); REG64_FLD( PU_CME10_CME_SCOM_BCECSR_NUM_BLOCKS , 17 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS ); REG64_FLD( PU_CME10_CME_SCOM_BCECSR_NUM_BLOCKS_LEN , 11 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS_LEN ); REG64_FLD( PU_CME10_CME_SCOM_BCECSR_SBASE , 28 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SBASE ); REG64_FLD( PU_CME10_CME_SCOM_BCECSR_SBASE_LEN , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SBASE_LEN ); REG64_FLD( PU_CME10_CME_SCOM_BCECSR_MBASE , 42 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MBASE ); REG64_FLD( PU_CME10_CME_SCOM_BCECSR_MBASE_LEN , 22 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MBASE_LEN ); REG64_FLD( PU_CME8_CME_SCOM_BCECSR_BUSY , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_BUSY ); REG64_FLD( PU_CME8_CME_SCOM_BCECSR_ERROR , 1 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_ERROR ); REG64_FLD( PU_CME8_CME_SCOM_BCECSR_RNW , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_RNW ); REG64_FLD( PU_CME8_CME_SCOM_BCECSR_BARSEL , 5 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_BARSEL ); REG64_FLD( PU_CME8_CME_SCOM_BCECSR_PRIORITY , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_PRIORITY ); REG64_FLD( PU_CME8_CME_SCOM_BCECSR_INJECT_ERR , 7 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_INJECT_ERR ); REG64_FLD( PU_CME8_CME_SCOM_BCECSR_TYPE , 13 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_TYPE ); REG64_FLD( PU_CME8_CME_SCOM_BCECSR_TYPE_LEN , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_TYPE_LEN ); REG64_FLD( PU_CME8_CME_SCOM_BCECSR_NUM_BLOCKS , 17 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS ); REG64_FLD( PU_CME8_CME_SCOM_BCECSR_NUM_BLOCKS_LEN , 11 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS_LEN ); REG64_FLD( PU_CME8_CME_SCOM_BCECSR_SBASE , 28 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SBASE ); REG64_FLD( PU_CME8_CME_SCOM_BCECSR_SBASE_LEN , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SBASE_LEN ); REG64_FLD( PU_CME8_CME_SCOM_BCECSR_MBASE , 42 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MBASE ); REG64_FLD( PU_CME8_CME_SCOM_BCECSR_MBASE_LEN , 22 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MBASE_LEN ); REG64_FLD( PU_CME1_CME_SCOM_BCECSR_BUSY , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_BUSY ); REG64_FLD( PU_CME1_CME_SCOM_BCECSR_ERROR , 1 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_ERROR ); REG64_FLD( PU_CME1_CME_SCOM_BCECSR_RNW , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_RNW ); REG64_FLD( PU_CME1_CME_SCOM_BCECSR_BARSEL , 5 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_BARSEL ); REG64_FLD( PU_CME1_CME_SCOM_BCECSR_PRIORITY , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_PRIORITY ); REG64_FLD( PU_CME1_CME_SCOM_BCECSR_INJECT_ERR , 7 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_INJECT_ERR ); REG64_FLD( PU_CME1_CME_SCOM_BCECSR_TYPE , 13 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_TYPE ); REG64_FLD( PU_CME1_CME_SCOM_BCECSR_TYPE_LEN , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_TYPE_LEN ); REG64_FLD( PU_CME1_CME_SCOM_BCECSR_NUM_BLOCKS , 17 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS ); REG64_FLD( PU_CME1_CME_SCOM_BCECSR_NUM_BLOCKS_LEN , 11 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS_LEN ); REG64_FLD( PU_CME1_CME_SCOM_BCECSR_SBASE , 28 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SBASE ); REG64_FLD( PU_CME1_CME_SCOM_BCECSR_SBASE_LEN , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SBASE_LEN ); REG64_FLD( PU_CME1_CME_SCOM_BCECSR_MBASE , 42 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MBASE ); REG64_FLD( PU_CME1_CME_SCOM_BCECSR_MBASE_LEN , 22 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MBASE_LEN ); REG64_FLD( PU_CME0_CME_SCOM_BCECSR_BUSY , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_BUSY ); REG64_FLD( PU_CME0_CME_SCOM_BCECSR_ERROR , 1 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_ERROR ); REG64_FLD( PU_CME0_CME_SCOM_BCECSR_RNW , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_RNW ); REG64_FLD( PU_CME0_CME_SCOM_BCECSR_BARSEL , 5 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_BARSEL ); REG64_FLD( PU_CME0_CME_SCOM_BCECSR_PRIORITY , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_PRIORITY ); REG64_FLD( PU_CME0_CME_SCOM_BCECSR_INJECT_ERR , 7 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_INJECT_ERR ); REG64_FLD( PU_CME0_CME_SCOM_BCECSR_TYPE , 13 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_TYPE ); REG64_FLD( PU_CME0_CME_SCOM_BCECSR_TYPE_LEN , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_TYPE_LEN ); REG64_FLD( PU_CME0_CME_SCOM_BCECSR_NUM_BLOCKS , 17 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS ); REG64_FLD( PU_CME0_CME_SCOM_BCECSR_NUM_BLOCKS_LEN , 11 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS_LEN ); REG64_FLD( PU_CME0_CME_SCOM_BCECSR_SBASE , 28 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SBASE ); REG64_FLD( PU_CME0_CME_SCOM_BCECSR_SBASE_LEN , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SBASE_LEN ); REG64_FLD( PU_CME0_CME_SCOM_BCECSR_MBASE , 42 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MBASE ); REG64_FLD( PU_CME0_CME_SCOM_BCECSR_MBASE_LEN , 22 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MBASE_LEN ); REG64_FLD( PU_CME7_CME_SCOM_BCECSR_BUSY , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_BUSY ); REG64_FLD( PU_CME7_CME_SCOM_BCECSR_ERROR , 1 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_ERROR ); REG64_FLD( PU_CME7_CME_SCOM_BCECSR_RNW , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_RNW ); REG64_FLD( PU_CME7_CME_SCOM_BCECSR_BARSEL , 5 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_BARSEL ); REG64_FLD( PU_CME7_CME_SCOM_BCECSR_PRIORITY , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_PRIORITY ); REG64_FLD( PU_CME7_CME_SCOM_BCECSR_INJECT_ERR , 7 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_INJECT_ERR ); REG64_FLD( PU_CME7_CME_SCOM_BCECSR_TYPE , 13 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_TYPE ); REG64_FLD( PU_CME7_CME_SCOM_BCECSR_TYPE_LEN , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_TYPE_LEN ); REG64_FLD( PU_CME7_CME_SCOM_BCECSR_NUM_BLOCKS , 17 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS ); REG64_FLD( PU_CME7_CME_SCOM_BCECSR_NUM_BLOCKS_LEN , 11 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_NUM_BLOCKS_LEN ); REG64_FLD( PU_CME7_CME_SCOM_BCECSR_SBASE , 28 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SBASE ); REG64_FLD( PU_CME7_CME_SCOM_BCECSR_SBASE_LEN , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SBASE_LEN ); REG64_FLD( PU_CME7_CME_SCOM_BCECSR_MBASE , 42 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MBASE ); REG64_FLD( PU_CME7_CME_SCOM_BCECSR_MBASE_LEN , 22 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MBASE_LEN ); REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME4_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME3_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME11_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME2_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME5_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME9_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME6_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME10_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME8_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME1_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME0_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C0_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C0_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_C0_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C1_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT , 56 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME7_CME_SCOM_CIDSR_C1_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_C1_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME4_CME_SCOM_FLAGS_DATA , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_DATA ); REG64_FLD( PU_CME4_CME_SCOM_FLAGS_DATA_LEN , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME3_CME_SCOM_FLAGS_DATA , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_DATA ); REG64_FLD( PU_CME3_CME_SCOM_FLAGS_DATA_LEN , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME11_CME_SCOM_FLAGS_DATA , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_DATA ); REG64_FLD( PU_CME11_CME_SCOM_FLAGS_DATA_LEN , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME2_CME_SCOM_FLAGS_DATA , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_DATA ); REG64_FLD( PU_CME2_CME_SCOM_FLAGS_DATA_LEN , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME5_CME_SCOM_FLAGS_DATA , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_DATA ); REG64_FLD( PU_CME5_CME_SCOM_FLAGS_DATA_LEN , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME9_CME_SCOM_FLAGS_DATA , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_DATA ); REG64_FLD( PU_CME9_CME_SCOM_FLAGS_DATA_LEN , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME6_CME_SCOM_FLAGS_DATA , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_DATA ); REG64_FLD( PU_CME6_CME_SCOM_FLAGS_DATA_LEN , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME10_CME_SCOM_FLAGS_DATA , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_DATA ); REG64_FLD( PU_CME10_CME_SCOM_FLAGS_DATA_LEN , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME8_CME_SCOM_FLAGS_DATA , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_DATA ); REG64_FLD( PU_CME8_CME_SCOM_FLAGS_DATA_LEN , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME1_CME_SCOM_FLAGS_DATA , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_DATA ); REG64_FLD( PU_CME1_CME_SCOM_FLAGS_DATA_LEN , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME0_CME_SCOM_FLAGS_DATA , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_DATA ); REG64_FLD( PU_CME0_CME_SCOM_FLAGS_DATA_LEN , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME7_CME_SCOM_FLAGS_DATA , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_DATA ); REG64_FLD( PU_CME7_CME_SCOM_FLAGS_DATA_LEN , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD ); REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD ); REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DROPOUT_TIMER_MODE ); REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DROPOUT_CHAR_MODE ); REG64_FLD( PU_CME4_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME4_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME4_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SPARE ); REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DROPOUT_NOTIFY_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME4_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE ); REG64_FLD( PU_CME4_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD ); REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD ); REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DROPOUT_TIMER_MODE ); REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DROPOUT_CHAR_MODE ); REG64_FLD( PU_CME3_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME3_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME3_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SPARE ); REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DROPOUT_NOTIFY_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME3_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE ); REG64_FLD( PU_CME3_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD ); REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD ); REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DROPOUT_TIMER_MODE ); REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DROPOUT_CHAR_MODE ); REG64_FLD( PU_CME11_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME11_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME11_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SPARE ); REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DROPOUT_NOTIFY_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME11_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE ); REG64_FLD( PU_CME11_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD ); REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD ); REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DROPOUT_TIMER_MODE ); REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DROPOUT_CHAR_MODE ); REG64_FLD( PU_CME2_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME2_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME2_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SPARE ); REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DROPOUT_NOTIFY_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME2_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE ); REG64_FLD( PU_CME2_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD ); REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD ); REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DROPOUT_TIMER_MODE ); REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DROPOUT_CHAR_MODE ); REG64_FLD( PU_CME5_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME5_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME5_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SPARE ); REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DROPOUT_NOTIFY_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME5_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE ); REG64_FLD( PU_CME5_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD ); REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD ); REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DROPOUT_TIMER_MODE ); REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DROPOUT_CHAR_MODE ); REG64_FLD( PU_CME9_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME9_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME9_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SPARE ); REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DROPOUT_NOTIFY_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME9_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE ); REG64_FLD( PU_CME9_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD ); REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD ); REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DROPOUT_TIMER_MODE ); REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DROPOUT_CHAR_MODE ); REG64_FLD( PU_CME6_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME6_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME6_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SPARE ); REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DROPOUT_NOTIFY_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME6_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE ); REG64_FLD( PU_CME6_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD ); REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD ); REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DROPOUT_TIMER_MODE ); REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DROPOUT_CHAR_MODE ); REG64_FLD( PU_CME10_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME10_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME10_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SPARE ); REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DROPOUT_NOTIFY_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME10_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE ); REG64_FLD( PU_CME10_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD ); REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD ); REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DROPOUT_TIMER_MODE ); REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DROPOUT_CHAR_MODE ); REG64_FLD( PU_CME8_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME8_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME8_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SPARE ); REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DROPOUT_NOTIFY_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME8_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE ); REG64_FLD( PU_CME8_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD ); REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD ); REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DROPOUT_TIMER_MODE ); REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DROPOUT_CHAR_MODE ); REG64_FLD( PU_CME1_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME1_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME1_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SPARE ); REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DROPOUT_NOTIFY_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME1_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE ); REG64_FLD( PU_CME1_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD ); REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD ); REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DROPOUT_TIMER_MODE ); REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DROPOUT_CHAR_MODE ); REG64_FLD( PU_CME0_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME0_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME0_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SPARE ); REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DROPOUT_NOTIFY_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME0_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE ); REG64_FLD( PU_CME0_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD ); REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_EVENT_THRESHOLD_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DROPOUT_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD ); REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_INAROW_THRESHOLD_LEN , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DROPOUT_INAROW_THRESHOLD_LEN ); REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_TIMER_MODE , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DROPOUT_TIMER_MODE ); REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_CHAR_MODE , 33 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DROPOUT_CHAR_MODE ); REG64_FLD( PU_CME7_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE , 34 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_IDCR_SIBLING_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SIBLING_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME7_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE , 36 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_IDCR_CORE_DROPOUT_ENABLE_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_CORE_DROPOUT_ENABLE_LEN ); REG64_FLD( PU_CME7_CME_SCOM_IDCR_CACHE_DROPOUT_ENABLE , 38 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_IDCR_SPARE , 39 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SPARE ); REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DROPOUT_NOTIFY_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_IDCR_SPARE41_43 , 41 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME7_CME_SCOM_IDCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE , 59 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE ); REG64_FLD( PU_CME7_CME_SCOM_IDCR_DROPOUT_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PMCRS0_DATA , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME4_CME_SCOM_PMCRS0_DATA_LEN , 64 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PMCRS0_DATA , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME3_CME_SCOM_PMCRS0_DATA_LEN , 64 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PMCRS0_DATA , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME11_CME_SCOM_PMCRS0_DATA_LEN , 64 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PMCRS0_DATA , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME2_CME_SCOM_PMCRS0_DATA_LEN , 64 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PMCRS0_DATA , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME5_CME_SCOM_PMCRS0_DATA_LEN , 64 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PMCRS0_DATA , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME9_CME_SCOM_PMCRS0_DATA_LEN , 64 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PMCRS0_DATA , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME6_CME_SCOM_PMCRS0_DATA_LEN , 64 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PMCRS0_DATA , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME10_CME_SCOM_PMCRS0_DATA_LEN , 64 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PMCRS0_DATA , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME8_CME_SCOM_PMCRS0_DATA_LEN , 64 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PMCRS0_DATA , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME1_CME_SCOM_PMCRS0_DATA_LEN , 64 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PMCRS0_DATA , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME0_CME_SCOM_PMCRS0_DATA_LEN , 64 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PMCRS0_DATA , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME7_CME_SCOM_PMCRS0_DATA_LEN , 64 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PMCRS1_DATA , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME4_CME_SCOM_PMCRS1_DATA_LEN , 64 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PMCRS1_DATA , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME3_CME_SCOM_PMCRS1_DATA_LEN , 64 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PMCRS1_DATA , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME11_CME_SCOM_PMCRS1_DATA_LEN , 64 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PMCRS1_DATA , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME2_CME_SCOM_PMCRS1_DATA_LEN , 64 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PMCRS1_DATA , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME5_CME_SCOM_PMCRS1_DATA_LEN , 64 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PMCRS1_DATA , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME9_CME_SCOM_PMCRS1_DATA_LEN , 64 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PMCRS1_DATA , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME6_CME_SCOM_PMCRS1_DATA_LEN , 64 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PMCRS1_DATA , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME10_CME_SCOM_PMCRS1_DATA_LEN , 64 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PMCRS1_DATA , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME8_CME_SCOM_PMCRS1_DATA_LEN , 64 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PMCRS1_DATA , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME1_CME_SCOM_PMCRS1_DATA_LEN , 64 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PMCRS1_DATA , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME0_CME_SCOM_PMCRS1_DATA_LEN , 64 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PMCRS1_DATA , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME7_CME_SCOM_PMCRS1_DATA_LEN , 64 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PMSRS0_DATA , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME4_CME_SCOM_PMSRS0_DATA_LEN , 64 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PMSRS0_DATA , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME3_CME_SCOM_PMSRS0_DATA_LEN , 64 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PMSRS0_DATA , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME11_CME_SCOM_PMSRS0_DATA_LEN , 64 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PMSRS0_DATA , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME2_CME_SCOM_PMSRS0_DATA_LEN , 64 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PMSRS0_DATA , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME5_CME_SCOM_PMSRS0_DATA_LEN , 64 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PMSRS0_DATA , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME9_CME_SCOM_PMSRS0_DATA_LEN , 64 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PMSRS0_DATA , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME6_CME_SCOM_PMSRS0_DATA_LEN , 64 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PMSRS0_DATA , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME10_CME_SCOM_PMSRS0_DATA_LEN , 64 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PMSRS0_DATA , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME8_CME_SCOM_PMSRS0_DATA_LEN , 64 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PMSRS0_DATA , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME1_CME_SCOM_PMSRS0_DATA_LEN , 64 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PMSRS0_DATA , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME0_CME_SCOM_PMSRS0_DATA_LEN , 64 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PMSRS0_DATA , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME7_CME_SCOM_PMSRS0_DATA_LEN , 64 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PMSRS1_DATA , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME4_CME_SCOM_PMSRS1_DATA_LEN , 64 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PMSRS1_DATA , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME3_CME_SCOM_PMSRS1_DATA_LEN , 64 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PMSRS1_DATA , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME11_CME_SCOM_PMSRS1_DATA_LEN , 64 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PMSRS1_DATA , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME2_CME_SCOM_PMSRS1_DATA_LEN , 64 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PMSRS1_DATA , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME5_CME_SCOM_PMSRS1_DATA_LEN , 64 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PMSRS1_DATA , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME9_CME_SCOM_PMSRS1_DATA_LEN , 64 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PMSRS1_DATA , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME6_CME_SCOM_PMSRS1_DATA_LEN , 64 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PMSRS1_DATA , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME10_CME_SCOM_PMSRS1_DATA_LEN , 64 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PMSRS1_DATA , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME8_CME_SCOM_PMSRS1_DATA_LEN , 64 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PMSRS1_DATA , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME1_CME_SCOM_PMSRS1_DATA_LEN , 64 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PMSRS1_DATA , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME0_CME_SCOM_PMSRS1_DATA_LEN , 64 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PMSRS1_DATA , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME7_CME_SCOM_PMSRS1_DATA_LEN , 64 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_SPARE0 , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_SPARE0 , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_SPARE0 , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_SPARE0 , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_SPARE0 , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_SPARE0 , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_SPARE0 , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_SPARE0 , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_SPARE0 , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_SPARE0 , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_SPARE0 , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_SPARE0 , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS00_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_SPARE0 , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_SPARE0 , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_SPARE0 , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_SPARE0 , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_SPARE0 , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_SPARE0 , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_SPARE0 , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_SPARE0 , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_SPARE0 , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_SPARE0 , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_SPARE0 , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_SPARE0 , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS01_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_SPARE0 , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_SPARE0 , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_SPARE0 , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_SPARE0 , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_SPARE0 , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_SPARE0 , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_SPARE0 , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_SPARE0 , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_SPARE0 , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_SPARE0 , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_SPARE0 , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_SPARE0 , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS02_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_SPARE0 , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_SPARE0 , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_SPARE0 , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_SPARE0 , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_SPARE0 , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_SPARE0 , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_SPARE0 , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_SPARE0 , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_SPARE0 , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_SPARE0 , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_SPARE0 , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_SPARE0 , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS03_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_SPARE0 , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_SPARE0 , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_SPARE0 , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_SPARE0 , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_SPARE0 , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_SPARE0 , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_SPARE0 , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_SPARE0 , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_SPARE0 , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_SPARE0 , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_SPARE0 , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_SPARE0 , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS10_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_SPARE0 , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_SPARE0 , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_SPARE0 , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_SPARE0 , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_SPARE0 , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_SPARE0 , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_SPARE0 , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_SPARE0 , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_SPARE0 , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_SPARE0 , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_SPARE0 , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_SPARE0 , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS11_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_SPARE0 , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_SPARE0 , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_SPARE0 , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_SPARE0 , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_SPARE0 , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_SPARE0 , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_SPARE0 , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_SPARE0 , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_SPARE0 , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_SPARE0 , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_SPARE0 , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_SPARE0 , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS12_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_SPARE0 , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME4_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_SPARE0 , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME3_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_SPARE0 , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME11_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_SPARE0 , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME2_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_SPARE0 , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME5_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_SPARE0 , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME9_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_SPARE0 , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME6_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_SPARE0 , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME10_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_SPARE0 , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME8_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_SPARE0 , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME1_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_SPARE0 , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME0_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_SPARE0 , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SPARE0 ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_OS_STATUS_DISABLE_A_N , 1 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_OS_STATUS_DISABLE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_STATE_LOSS_ENABLE_A_N , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STATE_LOSS_ENABLE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_EXIT_CRITERION_A_N , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXIT_CRITERION_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_POWER_SAVING_LIMIT_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_POWER_SAVING_LIMIT_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_HYP_VIRT_EXIT_ENABLE , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_HYP_VIRT_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_EXT_EBB_EXIT_ENABLE , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_EBB_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_EXT_RESUME_EXIT_ENABLE , 10 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_RESUME_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_EXT_EXIT_ENABLE , 11 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXT_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_DEC_EXIT_ENABLE , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DEC_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_HMI_EXIT_ENABLE , 13 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_HMI_EXIT_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N , 14 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_LEVEL_TRANSITION_RATE_A_N_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LEVEL_TRANSITION_RATE_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_MAX_PROMOTE_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_MAX_PROMOTE_LEVEL_A_N_LEN ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N ); REG64_FLD( PU_CME7_CME_SCOM_PSCRS13_STOP_REQUEST_LEVEL_A_N_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STOP_REQUEST_LEVEL_A_N_LEN ); REG64_FLD( PU_CME4_CME_SCOM_QFMR_TIMEBASE , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_TIMEBASE ); REG64_FLD( PU_CME4_CME_SCOM_QFMR_TIMEBASE_LEN , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_TIMEBASE_LEN ); REG64_FLD( PU_CME4_CME_SCOM_QFMR_CYCLES , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_CYCLES ); REG64_FLD( PU_CME4_CME_SCOM_QFMR_CYCLES_LEN , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_CYCLES_LEN ); REG64_FLD( PU_CME3_CME_SCOM_QFMR_TIMEBASE , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_TIMEBASE ); REG64_FLD( PU_CME3_CME_SCOM_QFMR_TIMEBASE_LEN , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_TIMEBASE_LEN ); REG64_FLD( PU_CME3_CME_SCOM_QFMR_CYCLES , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_CYCLES ); REG64_FLD( PU_CME3_CME_SCOM_QFMR_CYCLES_LEN , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_CYCLES_LEN ); REG64_FLD( PU_CME11_CME_SCOM_QFMR_TIMEBASE , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_TIMEBASE ); REG64_FLD( PU_CME11_CME_SCOM_QFMR_TIMEBASE_LEN , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_TIMEBASE_LEN ); REG64_FLD( PU_CME11_CME_SCOM_QFMR_CYCLES , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_CYCLES ); REG64_FLD( PU_CME11_CME_SCOM_QFMR_CYCLES_LEN , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_CYCLES_LEN ); REG64_FLD( PU_CME2_CME_SCOM_QFMR_TIMEBASE , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_TIMEBASE ); REG64_FLD( PU_CME2_CME_SCOM_QFMR_TIMEBASE_LEN , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_TIMEBASE_LEN ); REG64_FLD( PU_CME2_CME_SCOM_QFMR_CYCLES , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_CYCLES ); REG64_FLD( PU_CME2_CME_SCOM_QFMR_CYCLES_LEN , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_CYCLES_LEN ); REG64_FLD( PU_CME5_CME_SCOM_QFMR_TIMEBASE , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_TIMEBASE ); REG64_FLD( PU_CME5_CME_SCOM_QFMR_TIMEBASE_LEN , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_TIMEBASE_LEN ); REG64_FLD( PU_CME5_CME_SCOM_QFMR_CYCLES , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_CYCLES ); REG64_FLD( PU_CME5_CME_SCOM_QFMR_CYCLES_LEN , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_CYCLES_LEN ); REG64_FLD( PU_CME9_CME_SCOM_QFMR_TIMEBASE , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_TIMEBASE ); REG64_FLD( PU_CME9_CME_SCOM_QFMR_TIMEBASE_LEN , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_TIMEBASE_LEN ); REG64_FLD( PU_CME9_CME_SCOM_QFMR_CYCLES , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_CYCLES ); REG64_FLD( PU_CME9_CME_SCOM_QFMR_CYCLES_LEN , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_CYCLES_LEN ); REG64_FLD( PU_CME6_CME_SCOM_QFMR_TIMEBASE , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_TIMEBASE ); REG64_FLD( PU_CME6_CME_SCOM_QFMR_TIMEBASE_LEN , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_TIMEBASE_LEN ); REG64_FLD( PU_CME6_CME_SCOM_QFMR_CYCLES , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_CYCLES ); REG64_FLD( PU_CME6_CME_SCOM_QFMR_CYCLES_LEN , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_CYCLES_LEN ); REG64_FLD( PU_CME10_CME_SCOM_QFMR_TIMEBASE , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_TIMEBASE ); REG64_FLD( PU_CME10_CME_SCOM_QFMR_TIMEBASE_LEN , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_TIMEBASE_LEN ); REG64_FLD( PU_CME10_CME_SCOM_QFMR_CYCLES , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_CYCLES ); REG64_FLD( PU_CME10_CME_SCOM_QFMR_CYCLES_LEN , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_CYCLES_LEN ); REG64_FLD( PU_CME8_CME_SCOM_QFMR_TIMEBASE , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_TIMEBASE ); REG64_FLD( PU_CME8_CME_SCOM_QFMR_TIMEBASE_LEN , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_TIMEBASE_LEN ); REG64_FLD( PU_CME8_CME_SCOM_QFMR_CYCLES , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_CYCLES ); REG64_FLD( PU_CME8_CME_SCOM_QFMR_CYCLES_LEN , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_CYCLES_LEN ); REG64_FLD( PU_CME1_CME_SCOM_QFMR_TIMEBASE , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_TIMEBASE ); REG64_FLD( PU_CME1_CME_SCOM_QFMR_TIMEBASE_LEN , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_TIMEBASE_LEN ); REG64_FLD( PU_CME1_CME_SCOM_QFMR_CYCLES , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_CYCLES ); REG64_FLD( PU_CME1_CME_SCOM_QFMR_CYCLES_LEN , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_CYCLES_LEN ); REG64_FLD( PU_CME0_CME_SCOM_QFMR_TIMEBASE , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_TIMEBASE ); REG64_FLD( PU_CME0_CME_SCOM_QFMR_TIMEBASE_LEN , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_TIMEBASE_LEN ); REG64_FLD( PU_CME0_CME_SCOM_QFMR_CYCLES , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_CYCLES ); REG64_FLD( PU_CME0_CME_SCOM_QFMR_CYCLES_LEN , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_CYCLES_LEN ); REG64_FLD( PU_CME7_CME_SCOM_QFMR_TIMEBASE , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_TIMEBASE ); REG64_FLD( PU_CME7_CME_SCOM_QFMR_TIMEBASE_LEN , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_TIMEBASE_LEN ); REG64_FLD( PU_CME7_CME_SCOM_QFMR_CYCLES , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_CYCLES ); REG64_FLD( PU_CME7_CME_SCOM_QFMR_CYCLES_LEN , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_CYCLES_LEN ); REG64_FLD( PU_CME4_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME4_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME4_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME4_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME4_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE ); REG64_FLD( PU_CME4_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_LEN ); REG64_FLD( PU_CME3_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME3_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME3_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME3_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME3_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE ); REG64_FLD( PU_CME3_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_LEN ); REG64_FLD( PU_CME11_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME11_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME11_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME11_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME11_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE ); REG64_FLD( PU_CME11_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_LEN ); REG64_FLD( PU_CME2_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME2_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME2_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME2_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME2_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE ); REG64_FLD( PU_CME2_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_LEN ); REG64_FLD( PU_CME5_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME5_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME5_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME5_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME5_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE ); REG64_FLD( PU_CME5_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_LEN ); REG64_FLD( PU_CME9_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME9_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME9_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME9_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME9_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE ); REG64_FLD( PU_CME9_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_LEN ); REG64_FLD( PU_CME6_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME6_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME6_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME6_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME6_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE ); REG64_FLD( PU_CME6_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_LEN ); REG64_FLD( PU_CME10_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME10_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME10_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME10_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME10_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE ); REG64_FLD( PU_CME10_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_LEN ); REG64_FLD( PU_CME8_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME8_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME8_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME8_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME8_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE ); REG64_FLD( PU_CME8_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_LEN ); REG64_FLD( PU_CME1_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME1_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME1_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME1_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME1_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE ); REG64_FLD( PU_CME1_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_LEN ); REG64_FLD( PU_CME0_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME0_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME0_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME0_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME0_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE ); REG64_FLD( PU_CME0_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_LEN ); REG64_FLD( PU_CME7_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT ); REG64_FLD( PU_CME7_CME_SCOM_QIDSR_CACHE_DROPOUT_EVENT_COUNT_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_EVENT_COUNT_LEN ); REG64_FLD( PU_CME7_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT ); REG64_FLD( PU_CME7_CME_SCOM_QIDSR_CACHE_DROPOUT_INAROW_COUNT_LEN , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_CACHE_DROPOUT_INAROW_COUNT_LEN ); REG64_FLD( PU_CME7_CME_SCOM_QIDSR_DROPOUT_SAMPLE , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE ); REG64_FLD( PU_CME7_CME_SCOM_QIDSR_DROPOUT_SAMPLE_LEN , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DROPOUT_SAMPLE_LEN ); REG64_FLD( PU_CME4_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C0 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C1 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C0 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C0 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C1 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME4_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C0 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C1 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); REG64_FLD( PU_CME4_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_RESERVED20 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME4_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); REG64_FLD( PU_CME4_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); REG64_FLD( PU_CME4_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31 ); REG64_FLD( PU_CME4_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31_LEN ); REG64_FLD( PU_CME3_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C0 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C1 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C0 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C0 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C1 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME3_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C0 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C1 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); REG64_FLD( PU_CME3_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_RESERVED20 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME3_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); REG64_FLD( PU_CME3_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); REG64_FLD( PU_CME3_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31 ); REG64_FLD( PU_CME3_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31_LEN ); REG64_FLD( PU_CME11_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C0 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C1 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C0 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C0 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C1 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME11_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C0 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C1 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); REG64_FLD( PU_CME11_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_RESERVED20 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME11_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); REG64_FLD( PU_CME11_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); REG64_FLD( PU_CME11_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31 ); REG64_FLD( PU_CME11_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31_LEN ); REG64_FLD( PU_CME2_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C0 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C1 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C0 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C0 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C1 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME2_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C0 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C1 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); REG64_FLD( PU_CME2_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_RESERVED20 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME2_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); REG64_FLD( PU_CME2_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); REG64_FLD( PU_CME2_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31 ); REG64_FLD( PU_CME2_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31_LEN ); REG64_FLD( PU_CME5_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C0 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C1 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C0 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C0 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C1 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME5_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C0 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C1 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); REG64_FLD( PU_CME5_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_RESERVED20 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME5_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); REG64_FLD( PU_CME5_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); REG64_FLD( PU_CME5_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31 ); REG64_FLD( PU_CME5_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31_LEN ); REG64_FLD( PU_CME9_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C0 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C1 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C0 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C0 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C1 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME9_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C0 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C1 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); REG64_FLD( PU_CME9_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_RESERVED20 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME9_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); REG64_FLD( PU_CME9_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); REG64_FLD( PU_CME9_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31 ); REG64_FLD( PU_CME9_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31_LEN ); REG64_FLD( PU_CME6_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C0 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C1 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C0 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C0 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C1 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME6_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C0 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C1 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); REG64_FLD( PU_CME6_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_RESERVED20 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME6_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); REG64_FLD( PU_CME6_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); REG64_FLD( PU_CME6_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31 ); REG64_FLD( PU_CME6_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31_LEN ); REG64_FLD( PU_CME10_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C0 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C1 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C0 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C0 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C1 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME10_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C0 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C1 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); REG64_FLD( PU_CME10_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_RESERVED20 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME10_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); REG64_FLD( PU_CME10_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); REG64_FLD( PU_CME10_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31 ); REG64_FLD( PU_CME10_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31_LEN ); REG64_FLD( PU_CME8_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C0 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C1 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C0 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C0 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C1 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME8_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C0 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C1 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); REG64_FLD( PU_CME8_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_RESERVED20 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME8_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); REG64_FLD( PU_CME8_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); REG64_FLD( PU_CME8_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31 ); REG64_FLD( PU_CME8_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31_LEN ); REG64_FLD( PU_CME1_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C0 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C1 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C0 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C0 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C1 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME1_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C0 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C1 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); REG64_FLD( PU_CME1_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_RESERVED20 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME1_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); REG64_FLD( PU_CME1_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); REG64_FLD( PU_CME1_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31 ); REG64_FLD( PU_CME1_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31_LEN ); REG64_FLD( PU_CME0_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C0 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C1 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C0 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C0 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C1 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME0_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C0 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C1 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); REG64_FLD( PU_CME0_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_RESERVED20 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME0_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); REG64_FLD( PU_CME0_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); REG64_FLD( PU_CME0_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31 ); REG64_FLD( PU_CME0_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31_LEN ); REG64_FLD( PU_CME7_CME_SCOM_SICR_PM_ENTRY_ACK_C0 , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C0 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_PM_ENTRY_ACK_C1 , 1 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PM_ENTRY_ACK_C1 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C0 , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C0 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_PM_BLOCK_INTERRUPTS_C1 , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PM_BLOCK_INTERRUPTS_C1 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_PM_EXIT_C0 , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C0 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_PM_EXIT_C1 , 5 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PM_EXIT_C1 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C0 , 6 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_PCC_CORE_INTF_QUIESCE_C1 , 7 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PCC_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C0 , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C0 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_CORE_INTF_QUIESCE_C1 , 9 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_L2_CORE_INTF_QUIESCE_C1 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_PCBMUX_REQ_C0 , 10 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C0 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_PCBMUX_REQ_C1 , 11 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PCBMUX_REQ_C1 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_12_15 , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_12_15_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_CME7_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C0 , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C0 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_SPECIAL_WKUP_DONE_C1 , 17 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_SPECIAL_WKUP_DONE_C1 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_PURGE , 18 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_L2_PURGE ); REG64_FLD( PU_CME7_CME_SCOM_SICR_L2_PURGE_ABORT , 19 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_L2_PURGE_ABORT ); REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED20 , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_RESERVED20 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_NCU_TLBIE_QUIESCE , 21 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_NCU_TLBIE_QUIESCE ); REG64_FLD( PU_CME7_CME_SCOM_SICR_NCU_PURGE , 22 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE ); REG64_FLD( PU_CME7_CME_SCOM_SICR_NCU_PURGE_ABORT , 23 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_NCU_PURGE_ABORT ); REG64_FLD( PU_CME7_CME_SCOM_SICR_CHTM_PURGE_C0 , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C0 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_CHTM_PURGE_C1 , 25 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_CHTM_PURGE_C1 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_HMI_REQUEST_C0 , 26 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C0 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_HMI_REQUEST_C1 , 27 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_HMI_REQUEST_C1 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_PPM_SPARE_OUT_C0 , 28 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C0 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_PPM_SPARE_OUT_C1 , 29 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_PPM_SPARE_OUT_C1 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_30_31 , 30 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31 ); REG64_FLD( PU_CME7_CME_SCOM_SICR_RESERVED_30_31_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE2 , SH_FLD_RESERVED_30_31_LEN ); REG64_FLD( PU_CME4_CME_SCOM_SRTCH0_DATA , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME4_CME_SCOM_SRTCH0_DATA_LEN , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME3_CME_SCOM_SRTCH0_DATA , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME3_CME_SCOM_SRTCH0_DATA_LEN , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME11_CME_SCOM_SRTCH0_DATA , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME11_CME_SCOM_SRTCH0_DATA_LEN , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME2_CME_SCOM_SRTCH0_DATA , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME2_CME_SCOM_SRTCH0_DATA_LEN , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME5_CME_SCOM_SRTCH0_DATA , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME5_CME_SCOM_SRTCH0_DATA_LEN , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME9_CME_SCOM_SRTCH0_DATA , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME9_CME_SCOM_SRTCH0_DATA_LEN , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME6_CME_SCOM_SRTCH0_DATA , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME6_CME_SCOM_SRTCH0_DATA_LEN , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME10_CME_SCOM_SRTCH0_DATA , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME10_CME_SCOM_SRTCH0_DATA_LEN , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME8_CME_SCOM_SRTCH0_DATA , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME8_CME_SCOM_SRTCH0_DATA_LEN , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME1_CME_SCOM_SRTCH0_DATA , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME1_CME_SCOM_SRTCH0_DATA_LEN , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME0_CME_SCOM_SRTCH0_DATA , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME0_CME_SCOM_SRTCH0_DATA_LEN , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME7_CME_SCOM_SRTCH0_DATA , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME7_CME_SCOM_SRTCH0_DATA_LEN , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME4_CME_SCOM_SRTCH1_DATA , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME4_CME_SCOM_SRTCH1_DATA_LEN , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME3_CME_SCOM_SRTCH1_DATA , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME3_CME_SCOM_SRTCH1_DATA_LEN , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME11_CME_SCOM_SRTCH1_DATA , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME11_CME_SCOM_SRTCH1_DATA_LEN , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME2_CME_SCOM_SRTCH1_DATA , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME2_CME_SCOM_SRTCH1_DATA_LEN , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME5_CME_SCOM_SRTCH1_DATA , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME5_CME_SCOM_SRTCH1_DATA_LEN , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME9_CME_SCOM_SRTCH1_DATA , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME9_CME_SCOM_SRTCH1_DATA_LEN , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME6_CME_SCOM_SRTCH1_DATA , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME6_CME_SCOM_SRTCH1_DATA_LEN , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME10_CME_SCOM_SRTCH1_DATA , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME10_CME_SCOM_SRTCH1_DATA_LEN , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME8_CME_SCOM_SRTCH1_DATA , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME8_CME_SCOM_SRTCH1_DATA_LEN , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME1_CME_SCOM_SRTCH1_DATA , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME1_CME_SCOM_SRTCH1_DATA_LEN , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME0_CME_SCOM_SRTCH1_DATA , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME0_CME_SCOM_SRTCH1_DATA_LEN , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME7_CME_SCOM_SRTCH1_DATA , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DATA ); REG64_FLD( PU_CME7_CME_SCOM_SRTCH1_DATA_LEN , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DATA_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD ); REG64_FLD( PU_CME4_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD ); REG64_FLD( PU_CME4_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD ); REG64_FLD( PU_CME4_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE ); REG64_FLD( PU_CME4_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DROOP_TIMER_MODE ); REG64_FLD( PU_CME4_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DROOP_CHAR_MODE ); REG64_FLD( PU_CME4_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DROOP_NOTIFY_ENABLE ); REG64_FLD( PU_CME4_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME4_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE ); REG64_FLD( PU_CME4_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD ); REG64_FLD( PU_CME3_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD ); REG64_FLD( PU_CME3_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD ); REG64_FLD( PU_CME3_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE ); REG64_FLD( PU_CME3_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DROOP_TIMER_MODE ); REG64_FLD( PU_CME3_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DROOP_CHAR_MODE ); REG64_FLD( PU_CME3_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DROOP_NOTIFY_ENABLE ); REG64_FLD( PU_CME3_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME3_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE ); REG64_FLD( PU_CME3_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD ); REG64_FLD( PU_CME11_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD ); REG64_FLD( PU_CME11_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD ); REG64_FLD( PU_CME11_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE ); REG64_FLD( PU_CME11_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DROOP_TIMER_MODE ); REG64_FLD( PU_CME11_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DROOP_CHAR_MODE ); REG64_FLD( PU_CME11_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DROOP_NOTIFY_ENABLE ); REG64_FLD( PU_CME11_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME11_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE ); REG64_FLD( PU_CME11_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD ); REG64_FLD( PU_CME2_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD ); REG64_FLD( PU_CME2_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD ); REG64_FLD( PU_CME2_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE ); REG64_FLD( PU_CME2_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DROOP_TIMER_MODE ); REG64_FLD( PU_CME2_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DROOP_CHAR_MODE ); REG64_FLD( PU_CME2_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DROOP_NOTIFY_ENABLE ); REG64_FLD( PU_CME2_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME2_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE ); REG64_FLD( PU_CME2_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD ); REG64_FLD( PU_CME5_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD ); REG64_FLD( PU_CME5_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD ); REG64_FLD( PU_CME5_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE ); REG64_FLD( PU_CME5_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DROOP_TIMER_MODE ); REG64_FLD( PU_CME5_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DROOP_CHAR_MODE ); REG64_FLD( PU_CME5_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DROOP_NOTIFY_ENABLE ); REG64_FLD( PU_CME5_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME5_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE ); REG64_FLD( PU_CME5_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD ); REG64_FLD( PU_CME9_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD ); REG64_FLD( PU_CME9_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD ); REG64_FLD( PU_CME9_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE ); REG64_FLD( PU_CME9_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DROOP_TIMER_MODE ); REG64_FLD( PU_CME9_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DROOP_CHAR_MODE ); REG64_FLD( PU_CME9_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DROOP_NOTIFY_ENABLE ); REG64_FLD( PU_CME9_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME9_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE ); REG64_FLD( PU_CME9_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD ); REG64_FLD( PU_CME6_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD ); REG64_FLD( PU_CME6_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD ); REG64_FLD( PU_CME6_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE ); REG64_FLD( PU_CME6_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DROOP_TIMER_MODE ); REG64_FLD( PU_CME6_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DROOP_CHAR_MODE ); REG64_FLD( PU_CME6_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DROOP_NOTIFY_ENABLE ); REG64_FLD( PU_CME6_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME6_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE ); REG64_FLD( PU_CME6_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD ); REG64_FLD( PU_CME10_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD ); REG64_FLD( PU_CME10_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD ); REG64_FLD( PU_CME10_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE ); REG64_FLD( PU_CME10_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DROOP_TIMER_MODE ); REG64_FLD( PU_CME10_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DROOP_CHAR_MODE ); REG64_FLD( PU_CME10_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DROOP_NOTIFY_ENABLE ); REG64_FLD( PU_CME10_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME10_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE ); REG64_FLD( PU_CME10_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD ); REG64_FLD( PU_CME8_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD ); REG64_FLD( PU_CME8_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD ); REG64_FLD( PU_CME8_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE ); REG64_FLD( PU_CME8_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DROOP_TIMER_MODE ); REG64_FLD( PU_CME8_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DROOP_CHAR_MODE ); REG64_FLD( PU_CME8_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DROOP_NOTIFY_ENABLE ); REG64_FLD( PU_CME8_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME8_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE ); REG64_FLD( PU_CME8_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD ); REG64_FLD( PU_CME1_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD ); REG64_FLD( PU_CME1_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD ); REG64_FLD( PU_CME1_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE ); REG64_FLD( PU_CME1_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DROOP_TIMER_MODE ); REG64_FLD( PU_CME1_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DROOP_CHAR_MODE ); REG64_FLD( PU_CME1_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DROOP_NOTIFY_ENABLE ); REG64_FLD( PU_CME1_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME1_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE ); REG64_FLD( PU_CME1_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD ); REG64_FLD( PU_CME0_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD ); REG64_FLD( PU_CME0_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD ); REG64_FLD( PU_CME0_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE ); REG64_FLD( PU_CME0_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DROOP_TIMER_MODE ); REG64_FLD( PU_CME0_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DROOP_CHAR_MODE ); REG64_FLD( PU_CME0_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DROOP_NOTIFY_ENABLE ); REG64_FLD( PU_CME0_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME0_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE ); REG64_FLD( PU_CME0_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD ); REG64_FLD( PU_CME7_CME_SCOM_VCCR_SMALL_EVENT_THRESHOLD_LEN , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD ); REG64_FLD( PU_CME7_CME_SCOM_VCCR_LARGE_EVENT_THRESHOLD_LEN , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD , 28 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD ); REG64_FLD( PU_CME7_CME_SCOM_VCCR_EXTREME_EVENT_THRESHOLD_LEN , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXTREME_EVENT_THRESHOLD_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VCCR_DROOP_PROFILE_TYPE , 36 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE ); REG64_FLD( PU_CME7_CME_SCOM_VCCR_DROOP_PROFILE_TYPE_LEN , 2 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DROOP_PROFILE_TYPE_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VCCR_DROOP_TIMER_MODE , 38 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DROOP_TIMER_MODE ); REG64_FLD( PU_CME7_CME_SCOM_VCCR_DROOP_CHAR_MODE , 39 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DROOP_CHAR_MODE ); REG64_FLD( PU_CME7_CME_SCOM_VCCR_DROOP_NOTIFY_ENABLE , 40 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DROOP_NOTIFY_ENABLE ); REG64_FLD( PU_CME7_CME_SCOM_VCCR_SPARE41_43 , 41 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SPARE41_43 ); REG64_FLD( PU_CME7_CME_SCOM_VCCR_SPARE41_43_LEN , 3 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SPARE41_43_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VCCR_DROOP_SAMPLE_RATE , 59 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE ); REG64_FLD( PU_CME7_CME_SCOM_VCCR_DROOP_SAMPLE_RATE_LEN , 5 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_DROOP_SAMPLE_RATE_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR ); REG64_FLD( PU_CME4_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR ); REG64_FLD( PU_CME4_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR ); REG64_FLD( PU_CME4_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR ); REG64_FLD( PU_CME3_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR ); REG64_FLD( PU_CME3_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR ); REG64_FLD( PU_CME3_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR ); REG64_FLD( PU_CME11_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR ); REG64_FLD( PU_CME11_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR ); REG64_FLD( PU_CME11_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR ); REG64_FLD( PU_CME2_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR ); REG64_FLD( PU_CME2_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR ); REG64_FLD( PU_CME2_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR ); REG64_FLD( PU_CME5_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR ); REG64_FLD( PU_CME5_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR ); REG64_FLD( PU_CME5_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR ); REG64_FLD( PU_CME9_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR ); REG64_FLD( PU_CME9_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR ); REG64_FLD( PU_CME9_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR ); REG64_FLD( PU_CME6_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR ); REG64_FLD( PU_CME6_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR ); REG64_FLD( PU_CME6_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR ); REG64_FLD( PU_CME10_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR ); REG64_FLD( PU_CME10_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR ); REG64_FLD( PU_CME10_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR ); REG64_FLD( PU_CME8_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR ); REG64_FLD( PU_CME8_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR ); REG64_FLD( PU_CME8_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR ); REG64_FLD( PU_CME1_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR ); REG64_FLD( PU_CME1_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR ); REG64_FLD( PU_CME1_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR ); REG64_FLD( PU_CME0_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR ); REG64_FLD( PU_CME0_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR ); REG64_FLD( PU_CME0_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR ); REG64_FLD( PU_CME7_CME_SCOM_VDCR_VDM_EXTREME_DROOP_CTR_LEN , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_VDM_EXTREME_DROOP_CTR_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR ); REG64_FLD( PU_CME7_CME_SCOM_VDCR_VDM_LARGE_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_VDM_LARGE_DROOP_CTR_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR , 40 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR ); REG64_FLD( PU_CME7_CME_SCOM_VDCR_VDM_SMALL_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_VDM_SMALL_DROOP_CTR_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA , 20 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA , 36 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA , 40 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA , 44 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA , 48 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA , 52 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA ); REG64_FLD( PU_CME4_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA , 20 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA , 36 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA , 40 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA , 44 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA , 48 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA , 52 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA ); REG64_FLD( PU_CME3_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA , 20 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA , 36 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA , 40 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA , 44 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA , 48 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA , 52 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA ); REG64_FLD( PU_CME11_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA , 20 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA , 36 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA , 40 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA , 44 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA , 48 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA , 52 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA ); REG64_FLD( PU_CME2_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA , 20 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA , 36 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA , 40 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA , 44 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA , 48 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA , 52 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA ); REG64_FLD( PU_CME5_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA , 20 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA , 36 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA , 40 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA , 44 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA , 48 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA , 52 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA ); REG64_FLD( PU_CME9_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA , 20 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA , 36 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA , 40 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA , 44 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA , 48 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA , 52 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA ); REG64_FLD( PU_CME6_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA , 20 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA , 36 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA , 40 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA , 44 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA , 48 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA , 52 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA ); REG64_FLD( PU_CME10_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA , 20 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA , 36 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA , 40 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA , 44 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA , 48 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA , 52 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA ); REG64_FLD( PU_CME8_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA , 20 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA , 36 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA , 40 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA , 44 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA , 48 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA , 52 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA ); REG64_FLD( PU_CME1_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA , 20 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA , 36 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA , 40 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA , 44 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA , 48 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA , 52 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA ); REG64_FLD( PU_CME0_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_INSTANT_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_INSTANT_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_INSTANT_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_INSTANT_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_INSTANT_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA , 20 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_INSTANT_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_INSTANT_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_VDM_CONTROL_SUMMARY_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STICKY_VDM_CONTROL_SUMMARY_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA , 36 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CACHE_VDM_DATA_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STICKY_CACHE_VDM_DATA_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA , 40 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE0_VDM_DATA_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STICKY_CORE0_VDM_DATA_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA , 44 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE1_VDM_DATA_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STICKY_CORE1_VDM_DATA_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA , 48 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE2_VDM_DATA_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STICKY_CORE2_VDM_DATA_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA , 52 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA ); REG64_FLD( PU_CME7_CME_SCOM_VDSR_STICKY_CORE3_VDM_DATA_LEN , 4 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_STICKY_CORE3_VDM_DATA_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR ); REG64_FLD( PU_CME4_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME4_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR ); REG64_FLD( PU_CME4_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME4_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR ); REG64_FLD( PU_CME4_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR ); REG64_FLD( PU_CME3_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME3_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR ); REG64_FLD( PU_CME3_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME3_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR ); REG64_FLD( PU_CME3_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR ); REG64_FLD( PU_CME11_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME11_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR ); REG64_FLD( PU_CME11_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME11_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR ); REG64_FLD( PU_CME11_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR ); REG64_FLD( PU_CME2_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME2_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR ); REG64_FLD( PU_CME2_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME2_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR ); REG64_FLD( PU_CME2_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR ); REG64_FLD( PU_CME5_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME5_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR ); REG64_FLD( PU_CME5_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME5_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR ); REG64_FLD( PU_CME5_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR ); REG64_FLD( PU_CME9_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME9_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR ); REG64_FLD( PU_CME9_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME9_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR ); REG64_FLD( PU_CME9_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR ); REG64_FLD( PU_CME6_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME6_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR ); REG64_FLD( PU_CME6_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME6_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR ); REG64_FLD( PU_CME6_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR ); REG64_FLD( PU_CME10_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME10_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR ); REG64_FLD( PU_CME10_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME10_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR ); REG64_FLD( PU_CME10_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR ); REG64_FLD( PU_CME8_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME8_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR ); REG64_FLD( PU_CME8_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME8_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR ); REG64_FLD( PU_CME8_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR ); REG64_FLD( PU_CME1_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME1_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR ); REG64_FLD( PU_CME1_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME1_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR ); REG64_FLD( PU_CME1_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR ); REG64_FLD( PU_CME0_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME0_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR ); REG64_FLD( PU_CME0_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME0_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR ); REG64_FLD( PU_CME0_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR , 0 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR ); REG64_FLD( PU_CME7_CME_SCOM_VECR_TOTAL_DROOP_EVENT_CTR_LEN , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_TOTAL_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME7_CME_SCOM_VECR_SMALL_EVENT_PROFILE_CTR_LEN , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_SMALL_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR , 32 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR ); REG64_FLD( PU_CME7_CME_SCOM_VECR_LARGER_DROOP_EVENT_CTR_LEN , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LARGER_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR , 44 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR ); REG64_FLD( PU_CME7_CME_SCOM_VECR_LARGE_EVENT_PROFILE_CTR_LEN , 12 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_LARGE_EVENT_PROFILE_CTR_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR , 56 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR ); REG64_FLD( PU_CME7_CME_SCOM_VECR_EXTREME_DROOP_EVENT_CTR_LEN , 8 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_EXTREME_DROOP_EVENT_CTR_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); REG64_FLD( PU_CME4_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); REG64_FLD( PU_CME4_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); REG64_FLD( PU_CME4_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME4 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); REG64_FLD( PU_CME3_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); REG64_FLD( PU_CME3_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); REG64_FLD( PU_CME3_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME3 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); REG64_FLD( PU_CME11_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); REG64_FLD( PU_CME11_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); REG64_FLD( PU_CME11_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME11 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); REG64_FLD( PU_CME2_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); REG64_FLD( PU_CME2_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); REG64_FLD( PU_CME2_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME2 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); REG64_FLD( PU_CME5_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); REG64_FLD( PU_CME5_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); REG64_FLD( PU_CME5_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME5 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); REG64_FLD( PU_CME9_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); REG64_FLD( PU_CME9_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); REG64_FLD( PU_CME9_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME9 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); REG64_FLD( PU_CME6_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); REG64_FLD( PU_CME6_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); REG64_FLD( PU_CME6_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME6 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); REG64_FLD( PU_CME10_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); REG64_FLD( PU_CME10_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); REG64_FLD( PU_CME10_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME10 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); REG64_FLD( PU_CME8_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); REG64_FLD( PU_CME8_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); REG64_FLD( PU_CME8_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME8 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); REG64_FLD( PU_CME1_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); REG64_FLD( PU_CME1_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); REG64_FLD( PU_CME1_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME1 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); REG64_FLD( PU_CME0_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); REG64_FLD( PU_CME0_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); REG64_FLD( PU_CME0_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME0 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VNCR_VDM_NO_DROOP_CTR , 16 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR ); REG64_FLD( PU_CME7_CME_SCOM_VNCR_VDM_NO_DROOP_CTR_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_VDM_NO_DROOP_CTR_LEN ); REG64_FLD( PU_CME7_CME_SCOM_VNCR_VDM_OVERVOLT_CTR , 40 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR ); REG64_FLD( PU_CME7_CME_SCOM_VNCR_VDM_OVERVOLT_CTR_LEN , 24 , SH_UNT_PU_CME7 , SH_ACS_PPE , SH_FLD_VDM_OVERVOLT_CTR_LEN ); REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_BIT_WITHSTART , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMD_REG_BIT_WITHSTART ); REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_BIT_WITHADDR , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMD_REG_BIT_WITHADDR ); REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_BIT_READCONT , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMD_REG_BIT_READCONT ); REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_BIT_WITHSTOP , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMD_REG_BIT_WITHSTOP ); REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_LENGTH , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMD_REG_LENGTH ); REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_LENGTH_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMD_REG_LENGTH_LEN ); REG32_FLD( PU_COMMAND_REGISTER_UNUSED_8_14 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_8_14 ); REG32_FLD( PU_COMMAND_REGISTER_UNUSED_8_14_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_8_14_LEN ); REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_BIT_RNW , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMD_REG_BIT_RNW ); REG32_FLD( PU_COMMAND_REGISTER_UNUSED_16_22 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_16_22 ); REG32_FLD( PU_COMMAND_REGISTER_UNUSED_16_22_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_16_22_LEN ); REG32_FLD( PU_COMMAND_REGISTER_REG_ADDR_LENGTH , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_REG_ADDR_LENGTH ); REG32_FLD( PU_COMMAND_REGISTER_REG_ADDR_LENGTH_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_REG_ADDR_LENGTH_LEN ); REG32_FLD( PU_COMMAND_REGISTER_UNUSED_26_31 , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_26_31 ); REG32_FLD( PU_COMMAND_REGISTER_UNUSED_26_31_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_26_31_LEN ); REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_1 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMD_REG_ADDR_1 ); REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMD_REG_ADDR_1_LEN ); REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_2 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMD_REG_ADDR_2 ); REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMD_REG_ADDR_2_LEN ); REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_3 , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMD_REG_ADDR_3 ); REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMD_REG_ADDR_3_LEN ); REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_4 , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMD_REG_ADDR_4 ); REG32_FLD( PU_COMMAND_REGISTER_CMD_REG_ADDR_4_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMD_REG_ADDR_4_LEN ); REG64_FLD( PU_COMMAND_REGISTER_B_WITH_START_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_WITH_START_0 ); REG64_FLD( PU_COMMAND_REGISTER_B_WITH_ADDRESS_0 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_WITH_ADDRESS_0 ); REG64_FLD( PU_COMMAND_REGISTER_B_READ_CONTINUE_0 , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_READ_CONTINUE_0 ); REG64_FLD( PU_COMMAND_REGISTER_B_WITH_STOP_0 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_WITH_STOP_0 ); REG64_FLD( PU_COMMAND_REGISTER_B_NOT_USED_0 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_NOT_USED_0 ); REG64_FLD( PU_COMMAND_REGISTER_B_NOT_USED_0_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_NOT_USED_0_LEN ); REG64_FLD( PU_COMMAND_REGISTER_B_DEVICE_ADDRESS_0 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_DEVICE_ADDRESS_0 ); REG64_FLD( PU_COMMAND_REGISTER_B_DEVICE_ADDRESS_0_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_DEVICE_ADDRESS_0_LEN ); REG64_FLD( PU_COMMAND_REGISTER_B_READ_NOT_WRITE_0 , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_READ_NOT_WRITE_0 ); REG64_FLD( PU_COMMAND_REGISTER_B_LENGTH_IN_BYTES_0 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_LENGTH_IN_BYTES_0 ); REG64_FLD( PU_COMMAND_REGISTER_B_LENGTH_IN_BYTES_0_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_LENGTH_IN_BYTES_0_LEN ); REG64_FLD( PU_COMMAND_REGISTER_B_PEEK_DATA1_0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0 ); REG64_FLD( PU_COMMAND_REGISTER_B_PEEK_DATA1_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0_LEN ); REG64_FLD( PU_COMMAND_REGISTER_B_LBUS_PARITY_ERR1_0 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_0 ); REG64_FLD( PU_COMMAND_REGISTER_C_WITH_START_1 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_WITH_START_1 ); REG64_FLD( PU_COMMAND_REGISTER_C_WITH_ADDRESS_1 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_WITH_ADDRESS_1 ); REG64_FLD( PU_COMMAND_REGISTER_C_READ_CONTINUE_1 , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_READ_CONTINUE_1 ); REG64_FLD( PU_COMMAND_REGISTER_C_WITH_STOP_1 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_WITH_STOP_1 ); REG64_FLD( PU_COMMAND_REGISTER_C_NOT_USED_1 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_NOT_USED_1 ); REG64_FLD( PU_COMMAND_REGISTER_C_NOT_USED_1_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_NOT_USED_1_LEN ); REG64_FLD( PU_COMMAND_REGISTER_C_DEVICE_ADDRESS_1 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_DEVICE_ADDRESS_1 ); REG64_FLD( PU_COMMAND_REGISTER_C_DEVICE_ADDRESS_1_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_DEVICE_ADDRESS_1_LEN ); REG64_FLD( PU_COMMAND_REGISTER_C_READ_NOT_WRITE_1 , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_READ_NOT_WRITE_1 ); REG64_FLD( PU_COMMAND_REGISTER_C_LENGTH_IN_BYTES_1 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_LENGTH_IN_BYTES_1 ); REG64_FLD( PU_COMMAND_REGISTER_C_LENGTH_IN_BYTES_1_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_LENGTH_IN_BYTES_1_LEN ); REG64_FLD( PU_COMMAND_REGISTER_C_PEEK_DATA1_1 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1 ); REG64_FLD( PU_COMMAND_REGISTER_C_PEEK_DATA1_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1_LEN ); REG64_FLD( PU_COMMAND_REGISTER_C_LBUS_PARITY_ERR1_1 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_1 ); REG64_FLD( PU_COMMAND_REGISTER_D_WITH_START_2 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_WITH_START_2 ); REG64_FLD( PU_COMMAND_REGISTER_D_WITH_ADDRESS_2 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_WITH_ADDRESS_2 ); REG64_FLD( PU_COMMAND_REGISTER_D_READ_CONTINUE_2 , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_READ_CONTINUE_2 ); REG64_FLD( PU_COMMAND_REGISTER_D_WITH_STOP_2 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_WITH_STOP_2 ); REG64_FLD( PU_COMMAND_REGISTER_D_NOT_USED_2 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_NOT_USED_2 ); REG64_FLD( PU_COMMAND_REGISTER_D_NOT_USED_2_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_NOT_USED_2_LEN ); REG64_FLD( PU_COMMAND_REGISTER_D_DEVICE_ADDRESS_2 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_DEVICE_ADDRESS_2 ); REG64_FLD( PU_COMMAND_REGISTER_D_DEVICE_ADDRESS_2_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_DEVICE_ADDRESS_2_LEN ); REG64_FLD( PU_COMMAND_REGISTER_D_READ_NOT_WRITE_2 , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_READ_NOT_WRITE_2 ); REG64_FLD( PU_COMMAND_REGISTER_D_LENGTH_IN_BYTES_2 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_LENGTH_IN_BYTES_2 ); REG64_FLD( PU_COMMAND_REGISTER_D_LENGTH_IN_BYTES_2_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_LENGTH_IN_BYTES_2_LEN ); REG64_FLD( PU_COMMAND_REGISTER_D_PEEK_DATA1_2 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2 ); REG64_FLD( PU_COMMAND_REGISTER_D_PEEK_DATA1_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2_LEN ); REG64_FLD( PU_COMMAND_REGISTER_D_LBUS_PARITY_ERR1_2 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_2 ); REG64_FLD( PU_COMMAND_REGISTER_E_WITH_START_3 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_WITH_START_3 ); REG64_FLD( PU_COMMAND_REGISTER_E_WITH_ADDRESS_3 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_WITH_ADDRESS_3 ); REG64_FLD( PU_COMMAND_REGISTER_E_READ_CONTINUE_3 , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_READ_CONTINUE_3 ); REG64_FLD( PU_COMMAND_REGISTER_E_WITH_STOP_3 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_WITH_STOP_3 ); REG64_FLD( PU_COMMAND_REGISTER_E_NOT_USED_3 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_NOT_USED_3 ); REG64_FLD( PU_COMMAND_REGISTER_E_NOT_USED_3_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_NOT_USED_3_LEN ); REG64_FLD( PU_COMMAND_REGISTER_E_DEVICE_ADDRESS_3 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_DEVICE_ADDRESS_3 ); REG64_FLD( PU_COMMAND_REGISTER_E_DEVICE_ADDRESS_3_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_DEVICE_ADDRESS_3_LEN ); REG64_FLD( PU_COMMAND_REGISTER_E_READ_NOT_WRITE_3 , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_READ_NOT_WRITE_3 ); REG64_FLD( PU_COMMAND_REGISTER_E_LENGTH_IN_BYTES_3 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_LENGTH_IN_BYTES_3 ); REG64_FLD( PU_COMMAND_REGISTER_E_LENGTH_IN_BYTES_3_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_LENGTH_IN_BYTES_3_LEN ); REG64_FLD( PU_COMMAND_REGISTER_E_PEEK_DATA1_3 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3 ); REG64_FLD( PU_COMMAND_REGISTER_E_PEEK_DATA1_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3_LEN ); REG64_FLD( PU_COMMAND_REGISTER_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED1 ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_ADR_BAR_MODE , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADR_BAR_MODE ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_NN_RN , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_NN_RN ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_G , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_G ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_LN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_LN ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_SKIP_G , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_SKIP_G ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_INC_PRI_MASK , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_INC_PRI_MASK_LEN , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG1_RESERVED2 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2 ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_B , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_B ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_C , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_C ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_A , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_A ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_B , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_B ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_C , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_C ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RESERVED4 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RESERVED4 ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MACH_CORRENAB , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_CORRENAB ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RXO_CORRENAB , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_CORRENAB ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RSI_CORRENAB , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_CORRENAB ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_EVAPORATE_BY_LCO , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_EVAPORATE_BY_LCO ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MRBGP_TRACK_ALL , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_TRACK_ALL ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_MRBSP_TRACK_ALL , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_TRACK_ALL ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_ENABLE_PBUS , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_PBUS ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_BRAZOS_MODE , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_BRAZOS_MODE ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_ENABLE_SNARF_CPM , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_SNARF_CPM ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_REQ0 , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ0 ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_PRB0 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB0 ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_REQ1 , 43 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ1 ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_PRB1 , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB1 ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_PREALLOC2_XATS , 45 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_XATS ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_DISABLE_INJECT , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_INJECT ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); REG64_FLD( PU_NPU0_SM0_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_OPT_SNOOP_CP ); REG64_FLD( PU_NPU0_SM0_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( PU_NPU0_SM0_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED1 ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_ADR_BAR_MODE , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADR_BAR_MODE ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_DISABLE_NN_RN , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_NN_RN ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_DISABLE_G , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_G ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_DISABLE_LN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_LN ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_SKIP_G , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_SKIP_G ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_INC_PRI_MASK , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_INC_PRI_MASK_LEN , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG1_RESERVED2 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2 ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_B , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_B ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_C , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_C ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_A , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_A ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_B , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_B ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_C , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_C ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RESERVED4 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RESERVED4 ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MACH_CORRENAB , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_CORRENAB ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RXO_CORRENAB , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_CORRENAB ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RSI_CORRENAB , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_CORRENAB ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_EVAPORATE_BY_LCO , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_EVAPORATE_BY_LCO ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MRBGP_TRACK_ALL , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_TRACK_ALL ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_MRBSP_TRACK_ALL , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_TRACK_ALL ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_ENABLE_PBUS , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_PBUS ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_BRAZOS_MODE , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_BRAZOS_MODE ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_ENABLE_SNARF_CPM , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_SNARF_CPM ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_PREALLOC2_REQ0 , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ0 ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_PREALLOC2_PRB0 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB0 ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_PREALLOC2_REQ1 , 43 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ1 ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_PREALLOC2_PRB1 , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB1 ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_PREALLOC2_XATS , 45 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_XATS ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_DISABLE_INJECT , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_INJECT ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); REG64_FLD( PU_NPU1_SM2_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_OPT_SNOOP_CP ); REG64_FLD( PU_NPU1_SM2_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( PU_NPU1_SM2_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED1 ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_ADR_BAR_MODE , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADR_BAR_MODE ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_NN_RN , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_NN_RN ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_G , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_G ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_LN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_LN ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_SKIP_G , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_SKIP_G ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_INC_PRI_MASK , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_INC_PRI_MASK_LEN , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG1_RESERVED2 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2 ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_B , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_B ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_C , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_C ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_A , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_A ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_B , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_B ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_C , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_C ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RESERVED4 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RESERVED4 ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MACH_CORRENAB , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_CORRENAB ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RXO_CORRENAB , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_CORRENAB ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RSI_CORRENAB , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_CORRENAB ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_EVAPORATE_BY_LCO , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_EVAPORATE_BY_LCO ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MRBGP_TRACK_ALL , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_TRACK_ALL ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_MRBSP_TRACK_ALL , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_TRACK_ALL ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_ENABLE_PBUS , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_PBUS ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_BRAZOS_MODE , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_BRAZOS_MODE ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_ENABLE_SNARF_CPM , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_SNARF_CPM ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_REQ0 , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ0 ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_PRB0 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB0 ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_REQ1 , 43 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ1 ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_PRB1 , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB1 ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_PREALLOC2_XATS , 45 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_XATS ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_DISABLE_INJECT , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_INJECT ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); REG64_FLD( PU_NPU2_SM3_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_OPT_SNOOP_CP ); REG64_FLD( PU_NPU2_SM3_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( PU_NPU2_SM3_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED1 ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_ADR_BAR_MODE , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADR_BAR_MODE ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_DISABLE_NN_RN , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_NN_RN ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_DISABLE_G , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_G ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_DISABLE_LN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_LN ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_SKIP_G , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_SKIP_G ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_INC_PRI_MASK , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_INC_PRI_MASK_LEN , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG1_RESERVED2 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2 ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_B , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_B ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_C , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_C ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_A , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_A ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_B , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_B ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_C , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_C ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RESERVED4 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RESERVED4 ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MACH_CORRENAB , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_CORRENAB ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RXO_CORRENAB , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_CORRENAB ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RSI_CORRENAB , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_CORRENAB ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_EVAPORATE_BY_LCO , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_EVAPORATE_BY_LCO ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MRBGP_TRACK_ALL , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_TRACK_ALL ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_MRBSP_TRACK_ALL , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_TRACK_ALL ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_ENABLE_PBUS , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_PBUS ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_BRAZOS_MODE , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_BRAZOS_MODE ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_ENABLE_SNARF_CPM , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_SNARF_CPM ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_PREALLOC2_REQ0 , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ0 ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_PREALLOC2_PRB0 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB0 ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_PREALLOC2_REQ1 , 43 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ1 ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_PREALLOC2_PRB1 , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB1 ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_PREALLOC2_XATS , 45 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_XATS ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_DISABLE_INJECT , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_INJECT ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); REG64_FLD( PU_NPU1_SM3_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_OPT_SNOOP_CP ); REG64_FLD( PU_NPU1_SM3_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( PU_NPU1_SM3_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED1 ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_ADR_BAR_MODE , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADR_BAR_MODE ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_NN_RN , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_NN_RN ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_G , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_G ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_LN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_LN ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_SKIP_G , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_SKIP_G ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_INC_PRI_MASK , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_INC_PRI_MASK_LEN , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG1_RESERVED2 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2 ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_B , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_B ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_C , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_C ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_A , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_A ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_B , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_B ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_SCRESP_OPT_C , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_C ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RESERVED4 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RESERVED4 ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MACH_CORRENAB , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_CORRENAB ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RXO_CORRENAB , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_CORRENAB ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RSI_CORRENAB , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_CORRENAB ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_EVAPORATE_BY_LCO , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_EVAPORATE_BY_LCO ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MRBGP_TRACK_ALL , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_TRACK_ALL ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_MRBSP_TRACK_ALL , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_TRACK_ALL ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_ENABLE_PBUS , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_PBUS ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_BRAZOS_MODE , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_BRAZOS_MODE ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_ENABLE_SNARF_CPM , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_SNARF_CPM ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_REQ0 , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ0 ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_PRB0 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB0 ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_REQ1 , 43 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ1 ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_PRB1 , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB1 ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_PREALLOC2_XATS , 45 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_XATS ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_DISABLE_INJECT , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_INJECT ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); REG64_FLD( PU_NPU0_SM3_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_OPT_SNOOP_CP ); REG64_FLD( PU_NPU0_SM3_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( PU_NPU0_SM3_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED1 ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_ADR_BAR_MODE , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADR_BAR_MODE ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_DISABLE_NN_RN , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_NN_RN ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_DISABLE_G , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_G ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_DISABLE_LN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_LN ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_SKIP_G , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_SKIP_G ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_INC_PRI_MASK , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_INC_PRI_MASK_LEN , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG1_RESERVED2 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2 ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_B , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_B ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_C , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_C ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_A , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_A ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_B , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_B ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_C , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_C ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RESERVED4 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RESERVED4 ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MACH_CORRENAB , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_CORRENAB ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RXO_CORRENAB , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_CORRENAB ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RSI_CORRENAB , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_CORRENAB ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_EVAPORATE_BY_LCO , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_EVAPORATE_BY_LCO ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MRBGP_TRACK_ALL , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_TRACK_ALL ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_MRBSP_TRACK_ALL , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_TRACK_ALL ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_ENABLE_PBUS , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_PBUS ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_BRAZOS_MODE , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_BRAZOS_MODE ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_ENABLE_SNARF_CPM , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_SNARF_CPM ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_PREALLOC2_REQ0 , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ0 ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_PREALLOC2_PRB0 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB0 ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_PREALLOC2_REQ1 , 43 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ1 ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_PREALLOC2_PRB1 , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB1 ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_PREALLOC2_XATS , 45 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_XATS ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_DISABLE_INJECT , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_INJECT ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); REG64_FLD( PU_NPU1_SM1_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_OPT_SNOOP_CP ); REG64_FLD( PU_NPU1_SM1_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( PU_NPU1_SM1_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED1 ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_ADR_BAR_MODE , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADR_BAR_MODE ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_DISABLE_NN_RN , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_NN_RN ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_DISABLE_G , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_G ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_DISABLE_LN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_LN ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_SKIP_G , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_SKIP_G ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_INC_PRI_MASK , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_INC_PRI_MASK_LEN , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG1_RESERVED2 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2 ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_B , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_B ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_C , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_C ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_A , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_A ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_B , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_B ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_C , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_C ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RESERVED4 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RESERVED4 ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MACH_CORRENAB , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_CORRENAB ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RXO_CORRENAB , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_CORRENAB ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RSI_CORRENAB , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_CORRENAB ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_EVAPORATE_BY_LCO , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_EVAPORATE_BY_LCO ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MRBGP_TRACK_ALL , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_TRACK_ALL ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_MRBSP_TRACK_ALL , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_TRACK_ALL ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_ENABLE_PBUS , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_PBUS ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_BRAZOS_MODE , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_BRAZOS_MODE ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_ENABLE_SNARF_CPM , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_SNARF_CPM ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_PREALLOC2_REQ0 , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ0 ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_PREALLOC2_PRB0 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB0 ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_PREALLOC2_REQ1 , 43 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ1 ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_PREALLOC2_PRB1 , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB1 ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_PREALLOC2_XATS , 45 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_XATS ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_DISABLE_INJECT , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_INJECT ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); REG64_FLD( PU_NPU2_SM2_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_OPT_SNOOP_CP ); REG64_FLD( PU_NPU2_SM2_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( PU_NPU2_SM2_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED0 ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED1 , 1 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED1 ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED1_LEN , 3 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED1_LEN ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_ADR_BAR_MODE , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_ADR_BAR_MODE ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_GEN_HEAD_DELAY , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_GEN_HEAD_DELAY ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_GEN_HEAD_DELAY_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_GEN_HEAD_DELAY_LEN ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_DIV2_COUNT_AT_EXP , 10 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_DIV2_COUNT_AT_EXP ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_DIV2_COUNT_AT_EXP , 11 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_DIV2_COUNT_AT_EXP ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_DIS_DYN_ADJ , 12 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_DIS_DYN_ADJ ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_DIS_DYN_ADJ , 13 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_DIS_DYN_ADJ ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_DIS_DYN_LVL_ADJ , 14 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_DIS_DYN_LVL_ADJ ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_DIS_DYN_LVL_ADJ , 15 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_DIS_DYN_LVL_ADJ ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_THRESH1 , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_THRESH1 ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_THRESH1_LEN , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_THRESH1_LEN ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_THRESH2 , 22 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_THRESH2 ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_THRESH2_LEN , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_THRESH2_LEN ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_THRESH1 , 28 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_THRESH1 ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_THRESH1_LEN , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_THRESH1_LEN ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_THRESH2 , 34 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_THRESH2 ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_THRESH2_LEN , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_THRESH2_LEN ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_MAX_LEVEL , 40 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_MAX_LEVEL ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBGP_MAX_LEVEL_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_MAX_LEVEL_LEN ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_MAX_LEVEL , 44 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_MAX_LEVEL ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_MRBSP_MAX_LEVEL_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_MAX_LEVEL_LEN ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_BRAZOS_MODE , 48 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_BRAZOS_MODE ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_DISABLE_PBM_ECC_COR , 49 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_PBM_ECC_COR ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_01 , 50 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_LAB_RANDOMIZE_PE_01 ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_23 , 51 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_LAB_RANDOMIZE_PE_23 ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED2 , 52 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2 ); REG64_FLD( PU_NPU1_CTL_CONFIG0_CONFIG1_RESERVED2_LEN , 12 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED1 ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_ADR_BAR_MODE , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADR_BAR_MODE ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_NN_RN , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_NN_RN ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_G , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_G ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_LN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_LN ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_SKIP_G , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_SKIP_G ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_INC_PRI_MASK , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_INC_PRI_MASK_LEN , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG1_RESERVED2 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2 ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_B , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_B ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_C , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_C ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_A , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_A ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_B , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_B ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_C , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_C ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RESERVED4 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RESERVED4 ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MACH_CORRENAB , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_CORRENAB ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RXO_CORRENAB , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_CORRENAB ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RSI_CORRENAB , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_CORRENAB ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_EVAPORATE_BY_LCO , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_EVAPORATE_BY_LCO ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MRBGP_TRACK_ALL , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_TRACK_ALL ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_MRBSP_TRACK_ALL , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_TRACK_ALL ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_ENABLE_PBUS , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_PBUS ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_BRAZOS_MODE , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_BRAZOS_MODE ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_ENABLE_SNARF_CPM , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_SNARF_CPM ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_REQ0 , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ0 ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_PRB0 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB0 ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_REQ1 , 43 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ1 ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_PRB1 , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB1 ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_PREALLOC2_XATS , 45 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_XATS ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_DISABLE_INJECT , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_INJECT ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); REG64_FLD( PU_NPU2_SM1_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_OPT_SNOOP_CP ); REG64_FLD( PU_NPU2_SM1_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( PU_NPU2_SM1_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED1 ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_ADR_BAR_MODE , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADR_BAR_MODE ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_DISABLE_NN_RN , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_NN_RN ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_DISABLE_G , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_G ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_DISABLE_LN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_LN ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_SKIP_G , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_SKIP_G ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_INC_PRI_MASK , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_INC_PRI_MASK_LEN , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG1_RESERVED2 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2 ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_B , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_B ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_C , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_C ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_A , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_A ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_B , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_B ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_SCRESP_OPT_C , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_C ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RESERVED4 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RESERVED4 ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MACH_CORRENAB , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_CORRENAB ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RXO_CORRENAB , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_CORRENAB ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RSI_CORRENAB , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_CORRENAB ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_EVAPORATE_BY_LCO , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_EVAPORATE_BY_LCO ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MRBGP_TRACK_ALL , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_TRACK_ALL ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_MRBSP_TRACK_ALL , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_TRACK_ALL ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_ENABLE_PBUS , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_PBUS ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_BRAZOS_MODE , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_BRAZOS_MODE ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_ENABLE_SNARF_CPM , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_SNARF_CPM ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_PREALLOC2_REQ0 , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ0 ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_PREALLOC2_PRB0 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB0 ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_PREALLOC2_REQ1 , 43 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ1 ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_PREALLOC2_PRB1 , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB1 ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_PREALLOC2_XATS , 45 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_XATS ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_DISABLE_INJECT , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_INJECT ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); REG64_FLD( PU_NPU0_SM2_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_OPT_SNOOP_CP ); REG64_FLD( PU_NPU0_SM2_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( PU_NPU0_SM2_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED1 ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_ADR_BAR_MODE , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADR_BAR_MODE ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_NN_RN , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_NN_RN ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_G , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_G ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_LN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_LN ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_SKIP_G , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_SKIP_G ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_INC_PRI_MASK , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_INC_PRI_MASK_LEN , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG1_RESERVED2 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2 ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_B , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_B ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_C , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_C ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_A , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_A ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_B , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_B ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_C , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_C ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RESERVED4 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RESERVED4 ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MACH_CORRENAB , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_CORRENAB ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RXO_CORRENAB , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_CORRENAB ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RSI_CORRENAB , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_CORRENAB ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_EVAPORATE_BY_LCO , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_EVAPORATE_BY_LCO ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MRBGP_TRACK_ALL , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_TRACK_ALL ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_MRBSP_TRACK_ALL , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_TRACK_ALL ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_ENABLE_PBUS , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_PBUS ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_BRAZOS_MODE , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_BRAZOS_MODE ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_ENABLE_SNARF_CPM , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_SNARF_CPM ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_REQ0 , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ0 ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_PRB0 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB0 ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_REQ1 , 43 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ1 ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_PRB1 , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB1 ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_PREALLOC2_XATS , 45 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_XATS ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_DISABLE_INJECT , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_INJECT ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); REG64_FLD( PU_NPU2_SM0_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_OPT_SNOOP_CP ); REG64_FLD( PU_NPU2_SM0_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( PU_NPU2_SM0_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED0 ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED1 , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED1 ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED1_LEN , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED1_LEN ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_ADR_BAR_MODE , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_ADR_BAR_MODE ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_GEN_HEAD_DELAY , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_GEN_HEAD_DELAY ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_GEN_HEAD_DELAY_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_GEN_HEAD_DELAY_LEN ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_DIV2_COUNT_AT_EXP , 10 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_DIV2_COUNT_AT_EXP ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_DIV2_COUNT_AT_EXP , 11 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_DIV2_COUNT_AT_EXP ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_DIS_DYN_ADJ , 12 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_DIS_DYN_ADJ ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_DIS_DYN_ADJ , 13 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_DIS_DYN_ADJ ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_DIS_DYN_LVL_ADJ , 14 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_DIS_DYN_LVL_ADJ ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_DIS_DYN_LVL_ADJ , 15 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_DIS_DYN_LVL_ADJ ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_THRESH1 , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_THRESH1 ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_THRESH1_LEN , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_THRESH1_LEN ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_THRESH2 , 22 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_THRESH2 ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_THRESH2_LEN , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_THRESH2_LEN ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_THRESH1 , 28 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_THRESH1 ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_THRESH1_LEN , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_THRESH1_LEN ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_THRESH2 , 34 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_THRESH2 ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_THRESH2_LEN , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_THRESH2_LEN ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_MAX_LEVEL , 40 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_MAX_LEVEL ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBGP_MAX_LEVEL_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_MAX_LEVEL_LEN ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_MAX_LEVEL , 44 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_MAX_LEVEL ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_MRBSP_MAX_LEVEL_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_MAX_LEVEL_LEN ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_BRAZOS_MODE , 48 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_BRAZOS_MODE ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_DISABLE_PBM_ECC_COR , 49 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_PBM_ECC_COR ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_01 , 50 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_LAB_RANDOMIZE_PE_01 ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_23 , 51 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_LAB_RANDOMIZE_PE_23 ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED2 , 52 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2 ); REG64_FLD( PU_NPU0_CTL_CONFIG0_CONFIG1_RESERVED2_LEN , 12 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2_LEN ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED0 ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED1 , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED1 ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED1_LEN ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_ADR_BAR_MODE , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_ADR_BAR_MODE ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_GEN_HEAD_DELAY , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_GEN_HEAD_DELAY ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_GEN_HEAD_DELAY_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_GEN_HEAD_DELAY_LEN ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_DIV2_COUNT_AT_EXP , 10 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_DIV2_COUNT_AT_EXP ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_DIV2_COUNT_AT_EXP , 11 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_DIV2_COUNT_AT_EXP ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_DIS_DYN_ADJ , 12 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_DIS_DYN_ADJ ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_DIS_DYN_ADJ , 13 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_DIS_DYN_ADJ ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_DIS_DYN_LVL_ADJ , 14 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_DIS_DYN_LVL_ADJ ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_DIS_DYN_LVL_ADJ , 15 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_DIS_DYN_LVL_ADJ ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_THRESH1 , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_THRESH1 ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_THRESH1_LEN , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_THRESH1_LEN ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_THRESH2 , 22 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_THRESH2 ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_THRESH2_LEN , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_THRESH2_LEN ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_THRESH1 , 28 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_THRESH1 ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_THRESH1_LEN , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_THRESH1_LEN ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_THRESH2 , 34 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_THRESH2 ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_THRESH2_LEN , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_THRESH2_LEN ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_MAX_LEVEL , 40 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_MAX_LEVEL ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBGP_MAX_LEVEL_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_MAX_LEVEL_LEN ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_MAX_LEVEL , 44 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_MAX_LEVEL ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_MRBSP_MAX_LEVEL_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_MAX_LEVEL_LEN ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_BRAZOS_MODE , 48 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_BRAZOS_MODE ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_DISABLE_PBM_ECC_COR , 49 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_PBM_ECC_COR ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_01 , 50 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_LAB_RANDOMIZE_PE_01 ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG_LAB_RANDOMIZE_PE_23 , 51 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_LAB_RANDOMIZE_PE_23 ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED2 , 52 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2 ); REG64_FLD( PU_NPU2_CTL_CONFIG0_CONFIG1_RESERVED2_LEN , 12 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED1 ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_ADR_BAR_MODE , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADR_BAR_MODE ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_NN_RN , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_NN_RN ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_G , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_G ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_LN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_LN ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_SKIP_G , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_SKIP_G ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_INC_PRI_MASK , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_INC_PRI_MASK_LEN , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG1_RESERVED2 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2 ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_B , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_B ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_C , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_C ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_A , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_A ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_B , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_B ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_SCRESP_OPT_C , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_C ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RESERVED4 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RESERVED4 ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MACH_CORRENAB , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_CORRENAB ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RXO_CORRENAB , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_CORRENAB ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RSI_CORRENAB , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_CORRENAB ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_EVAPORATE_BY_LCO , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_EVAPORATE_BY_LCO ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MRBGP_TRACK_ALL , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_TRACK_ALL ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_MRBSP_TRACK_ALL , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_TRACK_ALL ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_ENABLE_PBUS , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_PBUS ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_BRAZOS_MODE , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_BRAZOS_MODE ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_ENABLE_SNARF_CPM , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_SNARF_CPM ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_REQ0 , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ0 ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_PRB0 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB0 ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_REQ1 , 43 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ1 ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_PRB1 , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB1 ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_PREALLOC2_XATS , 45 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_XATS ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_DISABLE_INJECT , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_INJECT ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); REG64_FLD( PU_NPU0_SM1_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_OPT_SNOOP_CP ); REG64_FLD( PU_NPU0_SM1_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( PU_NPU0_SM1_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG1_RESERVED1 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED1 ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_DSA_OPT_CLAIM_UR , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_CLAIM_UR ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_DSA_OPT_FLUSH_UR , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_FLUSH_UR ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_DSA_OPT_RP_MODE , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_RP_MODE ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_ADR_BAR_MODE , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADR_BAR_MODE ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_DISABLE_NN_RN , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_NN_RN ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_DISABLE_VG_NOT_SYS , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_VG_NOT_SYS ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_DISABLE_G , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_G ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_DISABLE_LN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_LN ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_SKIP_G , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_SKIP_G ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_WRP , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_WRP ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_INJ , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_INJ ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_MCRESP_OPT_RTY_DMA , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_MCRESP_OPT_RTY_DMA ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_INC_PRI_MASK , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_INC_PRI_MASK_LEN , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_INC_PRI_MASK_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG1_RESERVED2 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG1_RESERVED2 ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_B , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_B ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_C , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_C ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_A , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_A ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_B , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_B ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_SCRESP_OPT_C , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_SCRESP_OPT_C ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RESERVED4 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RESERVED4 ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MACH_CORRENAB , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_CORRENAB ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE1 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE1 ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MACH_INJECT_ENABLE2 , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MACH_INJECT_ENABLE2 ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RXO_CORRENAB , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_CORRENAB ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE1 , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE1 ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RXO_INJECT_ENABLE2 , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RXO_INJECT_ENABLE2 ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RSI_CORRENAB , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_CORRENAB ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE1 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE1 ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RSI_INJECT_ENABLE2 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_INJECT_ENABLE2 ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_RSNOOP_OPT_DCLAIM_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MA_DSA_OPT_DMA_UPG , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MA_DSA_OPT_DMA_UPG ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_EVAPORATE_BY_LCO , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_EVAPORATE_BY_LCO ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MRBGP_TRACK_ALL , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MRBGP_TRACK_ALL ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_MRBSP_TRACK_ALL , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MRBSP_TRACK_ALL ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_ENABLE_PBUS , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_PBUS ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_BRAZOS_MODE , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_BRAZOS_MODE ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_ENABLE_SNARF_CPM , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_SNARF_CPM ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_PREALLOC2_REQ0 , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ0 ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_PREALLOC2_PRB0 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB0 ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_PREALLOC2_REQ1 , 43 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_REQ1 ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_PREALLOC2_PRB1 , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_PRB1 ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_PREALLOC2_XATS , 45 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PREALLOC2_XATS ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_DISABLE_INJECT , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DISABLE_INJECT ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_DCACHE_MODE , 47 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_MODE ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_DCACHE_REPORTS_PHYSICAL , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_DCACHE_REPORTS_PHYSICAL ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_RSI_DISABLE_DATIN_FASTPATH , 49 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RSI_DISABLE_DATIN_FASTPATH ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_PCKT_BLK_PRB , 50 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PCKT_BLK_PRB ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_P9P9_MODE , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_P9P9_MODE ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_FORBID_MMIO_READ_GT_32 , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_READ_GT_32 ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_FORBID_MMIO_ATOMIC , 53 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_FORBID_MMIO_ATOMIC ); REG64_FLD( PU_NPU1_SM0_CONFIG0_CONFIG_OPT_SNOOP_CP , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_OPT_SNOOP_CP ); REG64_FLD( PU_NPU1_SM0_CONFIG0_RESERVED3 , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( PU_NPU1_SM0_CONFIG0_RESERVED3_LEN , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); REG64_FLD( PU_NPU1_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU1_SM2_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); REG64_FLD( PU_NPU1_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU1_SM3_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_NTL1_CONFIG1_COMPRESSED_RSP_ENA , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_COMPRESSED_RSP_ENA ); REG64_FLD( PU_NPU2_NTL1_CONFIG1_RESERVED1 , 1 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL1_CONFIG1_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL1_CONFIG1_CREQ_AE_ALWAYS , 4 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_CREQ_AE_ALWAYS ); REG64_FLD( PU_NPU2_NTL1_CONFIG1_DGD_AE_ALWAYS , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_DGD_AE_ALWAYS ); REG64_FLD( PU_NPU2_NTL1_CONFIG1_RSP_AE_ALWAYS , 6 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RSP_AE_ALWAYS ); REG64_FLD( PU_NPU2_NTL1_CONFIG1_RESERVED2 , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_NTL1_CONFIG1_NTL_RESET , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_RESET ); REG64_FLD( PU_NPU2_NTL1_CONFIG1_NTL_RESET_LEN , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NTL_RESET_LEN ); REG64_FLD( PU_NPU2_NTL1_CONFIG1_RESERVED3 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( PU_NPU2_NTL1_CONFIG1_RESERVED3_LEN , 54 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); REG64_FLD( PU_NPU1_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU1_SM1_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); REG64_FLD( PU_NPU0_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU0_SM2_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_CTL_CONFIG1_IDIAL , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU0_CTL_CONFIG1_IDIAL_LEN , 64 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_NPU1_CONFIG1_MGR_CREDIT , 0 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MGR_CREDIT ); REG64_FLD( PU_NPU1_CONFIG1_MGR_CREDIT_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MGR_CREDIT_LEN ); REG64_FLD( PU_NPU1_CONFIG1_MRG_PBTX_NBUF , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_PBTX_NBUF ); REG64_FLD( PU_NPU1_CONFIG1_MRG_PBTX_NBUF_LEN , 3 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_PBTX_NBUF_LEN ); REG64_FLD( PU_NPU1_CONFIG1_MRG_RDBF_NBUF , 5 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_RDBF_NBUF ); REG64_FLD( PU_NPU1_CONFIG1_MRG_RDBF_NBUF_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_RDBF_NBUF_LEN ); REG64_FLD( PU_NPU1_CONFIG1_MRG_IBWR_NBUF , 9 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_IBWR_NBUF ); REG64_FLD( PU_NPU1_CONFIG1_MRG_IBWR_NBUF_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_IBWR_NBUF_LEN ); REG64_FLD( PU_NPU1_CONFIG1_MRG_IBRD_NBUF , 13 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_IBRD_NBUF ); REG64_FLD( PU_NPU1_CONFIG1_MRG_IBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_IBRD_NBUF_LEN ); REG64_FLD( PU_NPU1_CONFIG1_MRG_BBRD_NBUF , 16 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_BBRD_NBUF ); REG64_FLD( PU_NPU1_CONFIG1_MRG_BBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_BBRD_NBUF_LEN ); REG64_FLD( PU_NPU1_CONFIG1_MRG_OBRD_NBUF , 19 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_OBRD_NBUF ); REG64_FLD( PU_NPU1_CONFIG1_MRG_OBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_OBRD_NBUF_LEN ); REG64_FLD( PU_NPU1_CONFIG1_MRG_CR_DIS , 22 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_CR_DIS ); REG64_FLD( PU_NPU1_CONFIG1_MRG_CTLW_CR_DIS , 23 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_MRG_CTLW_CR_DIS ); REG64_FLD( PU_NPU1_CONFIG1_NTLR_PAUSE_THRESH , 24 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_NTLR_PAUSE_THRESH ); REG64_FLD( PU_NPU1_CONFIG1_NTLR_PAUSE_THRESH_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_NTLR_PAUSE_THRESH_LEN ); REG64_FLD( PU_NPU1_CONFIG1_CTLR_HP_THRESH , 26 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_CTLR_HP_THRESH ); REG64_FLD( PU_NPU1_CONFIG1_CTLR_HP_THRESH_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_CTLR_HP_THRESH_LEN ); REG64_FLD( PU_NPU1_CONFIG1_NTLW_PAUSE_THRESH , 28 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_NTLW_PAUSE_THRESH ); REG64_FLD( PU_NPU1_CONFIG1_NTLW_PAUSE_THRESH_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_NTLW_PAUSE_THRESH_LEN ); REG64_FLD( PU_NPU1_CONFIG1_CTLW_HP_THRESH , 30 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_CTLW_HP_THRESH ); REG64_FLD( PU_NPU1_CONFIG1_CTLW_HP_THRESH_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_CTLW_HP_THRESH_LEN ); REG64_FLD( PU_NPU1_CONFIG1_PBTX_REDUCE_RTAG , 32 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_PBTX_REDUCE_RTAG ); REG64_FLD( PU_NPU1_CONFIG1_PBTX_DELAY_BDONE , 33 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_PBTX_DELAY_BDONE ); REG64_FLD( PU_NPU1_CONFIG1_PBTX_FLIP_IMIN_BIG , 34 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_PBTX_FLIP_IMIN_BIG ); REG64_FLD( PU_NPU1_CONFIG1_PBTX_FLIP_IMIN_LITTLE , 35 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_PBTX_FLIP_IMIN_LITTLE ); REG64_FLD( PU_NPU1_CONFIG1_ALU_SAFE_LATENCY , 36 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_ALU_SAFE_LATENCY ); REG64_FLD( PU_NPU1_CONFIG1_ALU_FLIP_ENDIAN_BIG , 37 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_ALU_FLIP_ENDIAN_BIG ); REG64_FLD( PU_NPU1_CONFIG1_ALU_FLIP_ENDIAN_LITTLE , 38 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_ALU_FLIP_ENDIAN_LITTLE ); REG64_FLD( PU_NPU1_CONFIG1_PBTX_EARLY_AFTAG , 39 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_PBTX_EARLY_AFTAG ); REG64_FLD( PU_NPU1_CONFIG1_RESERVED1 , 40 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_CONFIG1_RESERVED1_LEN , 24 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); REG64_FLD( PU_NPU0_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU0_SM1_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); REG64_FLD( PU_NPU0_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU0_SM0_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_NTL0_CONFIG1_COMPRESSED_RSP_ENA , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_COMPRESSED_RSP_ENA ); REG64_FLD( PU_NPU2_NTL0_CONFIG1_RESERVED1 , 1 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL0_CONFIG1_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL0_CONFIG1_CREQ_AE_ALWAYS , 4 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_CREQ_AE_ALWAYS ); REG64_FLD( PU_NPU2_NTL0_CONFIG1_DGD_AE_ALWAYS , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_DGD_AE_ALWAYS ); REG64_FLD( PU_NPU2_NTL0_CONFIG1_RSP_AE_ALWAYS , 6 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RSP_AE_ALWAYS ); REG64_FLD( PU_NPU2_NTL0_CONFIG1_RESERVED2 , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_NTL0_CONFIG1_NTL_RESET , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_RESET ); REG64_FLD( PU_NPU2_NTL0_CONFIG1_NTL_RESET_LEN , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NTL_RESET_LEN ); REG64_FLD( PU_NPU2_NTL0_CONFIG1_RESERVED3 , 10 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( PU_NPU2_NTL0_CONFIG1_RESERVED3_LEN , 54 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); REG64_FLD( PU_NPU2_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU2_SM3_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); REG64_FLD( PU_NPU0_SM3_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU0_SM3_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); REG64_FLD( PU_NPU2_SM2_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU2_SM2_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU0_CONFIG1_MGR_CREDIT , 0 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_MGR_CREDIT ); REG64_FLD( PU_NPU0_CONFIG1_MGR_CREDIT_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_MGR_CREDIT_LEN ); REG64_FLD( PU_NPU0_CONFIG1_MRG_PBTX_NBUF , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_MRG_PBTX_NBUF ); REG64_FLD( PU_NPU0_CONFIG1_MRG_PBTX_NBUF_LEN , 3 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_MRG_PBTX_NBUF_LEN ); REG64_FLD( PU_NPU0_CONFIG1_MRG_RDBF_NBUF , 5 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_MRG_RDBF_NBUF ); REG64_FLD( PU_NPU0_CONFIG1_MRG_RDBF_NBUF_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_MRG_RDBF_NBUF_LEN ); REG64_FLD( PU_NPU0_CONFIG1_MRG_IBWR_NBUF , 9 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_MRG_IBWR_NBUF ); REG64_FLD( PU_NPU0_CONFIG1_MRG_IBWR_NBUF_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_MRG_IBWR_NBUF_LEN ); REG64_FLD( PU_NPU0_CONFIG1_MRG_IBRD_NBUF , 13 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_MRG_IBRD_NBUF ); REG64_FLD( PU_NPU0_CONFIG1_MRG_IBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_MRG_IBRD_NBUF_LEN ); REG64_FLD( PU_NPU0_CONFIG1_MRG_BBRD_NBUF , 16 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_MRG_BBRD_NBUF ); REG64_FLD( PU_NPU0_CONFIG1_MRG_BBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_MRG_BBRD_NBUF_LEN ); REG64_FLD( PU_NPU0_CONFIG1_MRG_OBRD_NBUF , 19 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_MRG_OBRD_NBUF ); REG64_FLD( PU_NPU0_CONFIG1_MRG_OBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_MRG_OBRD_NBUF_LEN ); REG64_FLD( PU_NPU0_CONFIG1_MRG_CR_DIS , 22 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_MRG_CR_DIS ); REG64_FLD( PU_NPU0_CONFIG1_MRG_CTLW_CR_DIS , 23 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_MRG_CTLW_CR_DIS ); REG64_FLD( PU_NPU0_CONFIG1_NTLR_PAUSE_THRESH , 24 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_NTLR_PAUSE_THRESH ); REG64_FLD( PU_NPU0_CONFIG1_NTLR_PAUSE_THRESH_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_NTLR_PAUSE_THRESH_LEN ); REG64_FLD( PU_NPU0_CONFIG1_CTLR_HP_THRESH , 26 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_CTLR_HP_THRESH ); REG64_FLD( PU_NPU0_CONFIG1_CTLR_HP_THRESH_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_CTLR_HP_THRESH_LEN ); REG64_FLD( PU_NPU0_CONFIG1_NTLW_PAUSE_THRESH , 28 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_NTLW_PAUSE_THRESH ); REG64_FLD( PU_NPU0_CONFIG1_NTLW_PAUSE_THRESH_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_NTLW_PAUSE_THRESH_LEN ); REG64_FLD( PU_NPU0_CONFIG1_CTLW_HP_THRESH , 30 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_CTLW_HP_THRESH ); REG64_FLD( PU_NPU0_CONFIG1_CTLW_HP_THRESH_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_CTLW_HP_THRESH_LEN ); REG64_FLD( PU_NPU0_CONFIG1_PBTX_REDUCE_RTAG , 32 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_PBTX_REDUCE_RTAG ); REG64_FLD( PU_NPU0_CONFIG1_PBTX_DELAY_BDONE , 33 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_PBTX_DELAY_BDONE ); REG64_FLD( PU_NPU0_CONFIG1_PBTX_FLIP_IMIN_BIG , 34 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_PBTX_FLIP_IMIN_BIG ); REG64_FLD( PU_NPU0_CONFIG1_PBTX_FLIP_IMIN_LITTLE , 35 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_PBTX_FLIP_IMIN_LITTLE ); REG64_FLD( PU_NPU0_CONFIG1_ALU_SAFE_LATENCY , 36 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_ALU_SAFE_LATENCY ); REG64_FLD( PU_NPU0_CONFIG1_ALU_FLIP_ENDIAN_BIG , 37 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_ALU_FLIP_ENDIAN_BIG ); REG64_FLD( PU_NPU0_CONFIG1_ALU_FLIP_ENDIAN_LITTLE , 38 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_ALU_FLIP_ENDIAN_LITTLE ); REG64_FLD( PU_NPU0_CONFIG1_PBTX_EARLY_AFTAG , 39 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_PBTX_EARLY_AFTAG ); REG64_FLD( PU_NPU0_CONFIG1_RESERVED1 , 40 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_CONFIG1_RESERVED1_LEN , 24 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_CTL_CONFIG1_IDIAL , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU1_CTL_CONFIG1_IDIAL_LEN , 64 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); REG64_FLD( PU_NPU2_SM1_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU2_SM1_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); REG64_FLD( PU_NPU2_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU2_SM0_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_CTL_CONFIG1_IDIAL , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU2_CTL_CONFIG1_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( NV_CONFIG1_COMPRESSED_RSP_ENA , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_COMPRESSED_RSP_ENA ); REG64_FLD( NV_CONFIG1_RESERVED1 , 1 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( NV_CONFIG1_RESERVED1_LEN , 3 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( NV_CONFIG1_CREQ_AE_ALWAYS , 4 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_CREQ_AE_ALWAYS ); REG64_FLD( NV_CONFIG1_DGD_AE_ALWAYS , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_DGD_AE_ALWAYS ); REG64_FLD( NV_CONFIG1_RSP_AE_ALWAYS , 6 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RSP_AE_ALWAYS ); REG64_FLD( NV_CONFIG1_RESERVED2 , 7 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( NV_CONFIG1_NTL_RESET , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_RESET ); REG64_FLD( NV_CONFIG1_NTL_RESET_LEN , 2 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NTL_RESET_LEN ); REG64_FLD( NV_CONFIG1_RESERVED3 , 10 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( NV_CONFIG1_RESERVED3_LEN , 54 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU2_CONFIG1_MGR_CREDIT , 0 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MGR_CREDIT ); REG64_FLD( PU_NPU2_CONFIG1_MGR_CREDIT_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MGR_CREDIT_LEN ); REG64_FLD( PU_NPU2_CONFIG1_MRG_PBTX_NBUF , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_PBTX_NBUF ); REG64_FLD( PU_NPU2_CONFIG1_MRG_PBTX_NBUF_LEN , 3 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_PBTX_NBUF_LEN ); REG64_FLD( PU_NPU2_CONFIG1_MRG_RDBF_NBUF , 5 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_RDBF_NBUF ); REG64_FLD( PU_NPU2_CONFIG1_MRG_RDBF_NBUF_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_RDBF_NBUF_LEN ); REG64_FLD( PU_NPU2_CONFIG1_MRG_IBWR_NBUF , 9 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_IBWR_NBUF ); REG64_FLD( PU_NPU2_CONFIG1_MRG_IBWR_NBUF_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_IBWR_NBUF_LEN ); REG64_FLD( PU_NPU2_CONFIG1_MRG_IBRD_NBUF , 13 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_IBRD_NBUF ); REG64_FLD( PU_NPU2_CONFIG1_MRG_IBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_IBRD_NBUF_LEN ); REG64_FLD( PU_NPU2_CONFIG1_MRG_BBRD_NBUF , 16 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_BBRD_NBUF ); REG64_FLD( PU_NPU2_CONFIG1_MRG_BBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_BBRD_NBUF_LEN ); REG64_FLD( PU_NPU2_CONFIG1_MRG_OBRD_NBUF , 19 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_OBRD_NBUF ); REG64_FLD( PU_NPU2_CONFIG1_MRG_OBRD_NBUF_LEN , 3 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_OBRD_NBUF_LEN ); REG64_FLD( PU_NPU2_CONFIG1_MRG_CR_DIS , 22 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_CR_DIS ); REG64_FLD( PU_NPU2_CONFIG1_MRG_CTLW_CR_DIS , 23 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_MRG_CTLW_CR_DIS ); REG64_FLD( PU_NPU2_CONFIG1_NTLR_PAUSE_THRESH , 24 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_NTLR_PAUSE_THRESH ); REG64_FLD( PU_NPU2_CONFIG1_NTLR_PAUSE_THRESH_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_NTLR_PAUSE_THRESH_LEN ); REG64_FLD( PU_NPU2_CONFIG1_CTLR_HP_THRESH , 26 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_CTLR_HP_THRESH ); REG64_FLD( PU_NPU2_CONFIG1_CTLR_HP_THRESH_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_CTLR_HP_THRESH_LEN ); REG64_FLD( PU_NPU2_CONFIG1_NTLW_PAUSE_THRESH , 28 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_NTLW_PAUSE_THRESH ); REG64_FLD( PU_NPU2_CONFIG1_NTLW_PAUSE_THRESH_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_NTLW_PAUSE_THRESH_LEN ); REG64_FLD( PU_NPU2_CONFIG1_CTLW_HP_THRESH , 30 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_CTLW_HP_THRESH ); REG64_FLD( PU_NPU2_CONFIG1_CTLW_HP_THRESH_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_CTLW_HP_THRESH_LEN ); REG64_FLD( PU_NPU2_CONFIG1_PBTX_REDUCE_RTAG , 32 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_PBTX_REDUCE_RTAG ); REG64_FLD( PU_NPU2_CONFIG1_PBTX_DELAY_BDONE , 33 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_PBTX_DELAY_BDONE ); REG64_FLD( PU_NPU2_CONFIG1_PBTX_FLIP_IMIN_BIG , 34 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_PBTX_FLIP_IMIN_BIG ); REG64_FLD( PU_NPU2_CONFIG1_PBTX_FLIP_IMIN_LITTLE , 35 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_PBTX_FLIP_IMIN_LITTLE ); REG64_FLD( PU_NPU2_CONFIG1_ALU_SAFE_LATENCY , 36 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_ALU_SAFE_LATENCY ); REG64_FLD( PU_NPU2_CONFIG1_ALU_FLIP_ENDIAN_BIG , 37 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_ALU_FLIP_ENDIAN_BIG ); REG64_FLD( PU_NPU2_CONFIG1_ALU_FLIP_ENDIAN_LITTLE , 38 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_ALU_FLIP_ENDIAN_LITTLE ); REG64_FLD( PU_NPU2_CONFIG1_PBTX_EARLY_AFTAG , 39 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_PBTX_EARLY_AFTAG ); REG64_FLD( PU_NPU2_CONFIG1_RESERVED1 , 40 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_CONFIG1_RESERVED1_LEN , 24 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK ); REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_RANDOM_BACKOFF_DUR_MASK_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ ); REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_REQ_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB ); REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHGRATE_HANG_SLOWDOWN_PRB_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY ); REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_ARB_NONCRR_SAFETY_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ARB_NONCRR_SAFETY_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT ); REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_EPSILON_WLN_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_EPSILON_WLN_COUNT_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL ); REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_POLL_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_POLL_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA ); REG64_FLD( PU_NPU1_SM0_CONFIG1_CONFIG_SCALE_RPT_HANG_DATA_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_SCALE_RPT_HANG_DATA_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG1_RESERVED , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU1_SM0_CONFIG1_RESERVED_LEN , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_BRICK_ENABLE , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_BRICK_ENABLE ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_RSP_CTL_CRED_SINGLE_ENA , 1 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RSP_CTL_CRED_SINGLE_ENA ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_CREQ_BE_128 , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_CREQ_BE_128 ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_DGD_BE_128 , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_DGD_BE_128 ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_WR_SPLIT_UT0_ENA , 4 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_WR_SPLIT_UT0_ENA ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_WR_SPLIT_UT1_ENA , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_WR_SPLIT_UT1_ENA ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_BRICK_DEBUG_MODE , 6 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_BRICK_DEBUG_MODE ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_P9_TO_P9_MODE , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_P9_TO_P9_MODE ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED1 , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_CAM256_MAX_CNT , 10 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_CAM256_MAX_CNT ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_CAM256_MAX_CNT_LEN , 6 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_CAM256_MAX_CNT_LEN ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_NDL_RX_PARITY_ENA , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NDL_RX_PARITY_ENA ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_NDL_TX_PARITY_ENA , 17 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NDL_TX_PARITY_ENA ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_NDL_PRI_PARITY_ENA , 18 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NDL_PRI_PARITY_ENA ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_RCV_CREDIT_OVERFLOW_ENA , 19 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RCV_CREDIT_OVERFLOW_ENA ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_HDR_ARR_ECC_CORR_ENA , 20 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_HDR_ARR_ECC_CORR_ENA ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_DAT_ARR_ECC_CORR_ENA , 21 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_DAT_ARR_ECC_CORR_ENA ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_TX_DATA_ECC_CORR_ENA , 22 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_TX_DATA_ECC_CORR_ENA ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED2 , 23 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_PARITY_ERROR_SUE_ENA , 24 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_PARITY_ERROR_SUE_ENA ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_DATA_POISON_SUE_ENA , 25 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_DATA_POISON_SUE_ENA ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_HDR_ARR_ECC_SUE_ENA , 26 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_HDR_ARR_ECC_SUE_ENA ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_DAT_ARR_ECC_SUE_ENA , 27 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_DAT_ARR_ECC_SUE_ENA ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_TX_ECC_DATA_POISON_ENA , 28 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_TX_ECC_DATA_POISON_ENA ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED3 , 29 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED3_LEN , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_PRI_STATE_MACHINE_RESET , 32 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_PRI_STATE_MACHINE_RESET ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED4 , 33 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED4 ); REG64_FLD( PU_NPU2_NTL0_CONFIG2_RESERVED4_LEN , 31 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED4_LEN ); REG64_FLD( PU_NPU1_CTL_CONFIG2_IDIAL , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU1_CTL_CONFIG2_IDIAL_LEN , 64 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_NPU0_CTL_CONFIG2_IDIAL , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU0_CTL_CONFIG2_IDIAL_LEN , 64 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_NPU2_CTL_CONFIG2_IDIAL , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU2_CTL_CONFIG2_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( NV_CONFIG2_BRICK_ENABLE , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_BRICK_ENABLE ); REG64_FLD( NV_CONFIG2_RSP_CTL_CRED_SINGLE_ENA , 1 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RSP_CTL_CRED_SINGLE_ENA ); REG64_FLD( NV_CONFIG2_CREQ_BE_128 , 2 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_CREQ_BE_128 ); REG64_FLD( NV_CONFIG2_DGD_BE_128 , 3 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_DGD_BE_128 ); REG64_FLD( NV_CONFIG2_WR_SPLIT_UT0_ENA , 4 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_WR_SPLIT_UT0_ENA ); REG64_FLD( NV_CONFIG2_WR_SPLIT_UT1_ENA , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_WR_SPLIT_UT1_ENA ); REG64_FLD( NV_CONFIG2_BRICK_DEBUG_MODE , 6 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_BRICK_DEBUG_MODE ); REG64_FLD( NV_CONFIG2_P9_TO_P9_MODE , 7 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_P9_TO_P9_MODE ); REG64_FLD( NV_CONFIG2_RESERVED1 , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( NV_CONFIG2_RESERVED1_LEN , 2 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( NV_CONFIG2_CAM256_MAX_CNT , 10 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_CAM256_MAX_CNT ); REG64_FLD( NV_CONFIG2_CAM256_MAX_CNT_LEN , 6 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_CAM256_MAX_CNT_LEN ); REG64_FLD( NV_CONFIG2_NDL_RX_PARITY_ENA , 16 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NDL_RX_PARITY_ENA ); REG64_FLD( NV_CONFIG2_NDL_TX_PARITY_ENA , 17 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NDL_TX_PARITY_ENA ); REG64_FLD( NV_CONFIG2_NDL_PRI_PARITY_ENA , 18 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NDL_PRI_PARITY_ENA ); REG64_FLD( NV_CONFIG2_RCV_CREDIT_OVERFLOW_ENA , 19 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RCV_CREDIT_OVERFLOW_ENA ); REG64_FLD( NV_CONFIG2_HDR_ARR_ECC_CORR_ENA , 20 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_HDR_ARR_ECC_CORR_ENA ); REG64_FLD( NV_CONFIG2_DAT_ARR_ECC_CORR_ENA , 21 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_DAT_ARR_ECC_CORR_ENA ); REG64_FLD( NV_CONFIG2_TX_DATA_ECC_CORR_ENA , 22 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_TX_DATA_ECC_CORR_ENA ); REG64_FLD( NV_CONFIG2_RESERVED2 , 23 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( NV_CONFIG2_PARITY_ERROR_SUE_ENA , 24 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_PARITY_ERROR_SUE_ENA ); REG64_FLD( NV_CONFIG2_DATA_POISON_SUE_ENA , 25 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_DATA_POISON_SUE_ENA ); REG64_FLD( NV_CONFIG2_HDR_ARR_ECC_SUE_ENA , 26 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_HDR_ARR_ECC_SUE_ENA ); REG64_FLD( NV_CONFIG2_DAT_ARR_ECC_SUE_ENA , 27 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_DAT_ARR_ECC_SUE_ENA ); REG64_FLD( NV_CONFIG2_TX_ECC_DATA_POISON_ENA , 28 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_TX_ECC_DATA_POISON_ENA ); REG64_FLD( NV_CONFIG2_RESERVED3 , 29 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( NV_CONFIG2_RESERVED3_LEN , 3 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( NV_CONFIG2_PRI_STATE_MACHINE_RESET , 32 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_PRI_STATE_MACHINE_RESET ); REG64_FLD( NV_CONFIG2_RESERVED4 , 33 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED4 ); REG64_FLD( NV_CONFIG2_RESERVED4_LEN , 31 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED4_LEN ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_BRICK_ENABLE , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_BRICK_ENABLE ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_RSP_CTL_CRED_SINGLE_ENA , 1 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RSP_CTL_CRED_SINGLE_ENA ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_CREQ_BE_128 , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_CREQ_BE_128 ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_DGD_BE_128 , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_DGD_BE_128 ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_WR_SPLIT_UT0_ENA , 4 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_WR_SPLIT_UT0_ENA ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_WR_SPLIT_UT1_ENA , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_WR_SPLIT_UT1_ENA ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_BRICK_DEBUG_MODE , 6 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_BRICK_DEBUG_MODE ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_P9_TO_P9_MODE , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_P9_TO_P9_MODE ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED1 , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_CAM256_MAX_CNT , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_CAM256_MAX_CNT ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_CAM256_MAX_CNT_LEN , 6 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_CAM256_MAX_CNT_LEN ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_NDL_RX_PARITY_ENA , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NDL_RX_PARITY_ENA ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_NDL_TX_PARITY_ENA , 17 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NDL_TX_PARITY_ENA ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_NDL_PRI_PARITY_ENA , 18 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NDL_PRI_PARITY_ENA ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_RCV_CREDIT_OVERFLOW_ENA , 19 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RCV_CREDIT_OVERFLOW_ENA ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_HDR_ARR_ECC_CORR_ENA , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_HDR_ARR_ECC_CORR_ENA ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_DAT_ARR_ECC_CORR_ENA , 21 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_DAT_ARR_ECC_CORR_ENA ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_TX_DATA_ECC_CORR_ENA , 22 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_TX_DATA_ECC_CORR_ENA ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED2 , 23 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_PARITY_ERROR_SUE_ENA , 24 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_PARITY_ERROR_SUE_ENA ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_DATA_POISON_SUE_ENA , 25 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_DATA_POISON_SUE_ENA ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_HDR_ARR_ECC_SUE_ENA , 26 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_HDR_ARR_ECC_SUE_ENA ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_DAT_ARR_ECC_SUE_ENA , 27 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_DAT_ARR_ECC_SUE_ENA ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_TX_ECC_DATA_POISON_ENA , 28 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_TX_ECC_DATA_POISON_ENA ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED3 , 29 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED3_LEN , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED3_LEN ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_PRI_STATE_MACHINE_RESET , 32 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_PRI_STATE_MACHINE_RESET ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED4 , 33 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED4 ); REG64_FLD( PU_NPU2_NTL1_CONFIG2_RESERVED4_LEN , 31 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED4_LEN ); REG64_FLD( PU_NPU2_NTL0_CONFIG3_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL0_CONFIG3_RESERVED1_LEN , 64 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_CTL_CONFIG3_IDIAL , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU1_CTL_CONFIG3_IDIAL_LEN , 64 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_NPU0_CTL_CONFIG3_IDIAL , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU0_CTL_CONFIG3_IDIAL_LEN , 64 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_NPU2_CTL_CONFIG3_IDIAL , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU2_CTL_CONFIG3_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( NV_CONFIG3_RESERVED1 , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( NV_CONFIG3_RESERVED1_LEN , 64 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL1_CONFIG3_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL1_CONFIG3_RESERVED1_LEN , 64 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_WRENA ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_RDENA ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0 ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_WRENA ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_RDENA ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_WRENA ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_RDENA ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0 ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_WRENA ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_RDENA ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_WRENA ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_RDENA ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0 ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_WRENA ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_RDENA ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_WRENA ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_RDENA ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0 ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_WRENA ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_RDENA ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_WRENA ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_RDENA ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0 ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_WRENA ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_RDENA ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_WRENA ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_RDENA ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0 ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_WRENA ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_RDENA ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_WRENA ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_RDENA ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0 ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_WRENA ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_RDENA ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_WRENA ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_RDENA ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0 ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_WRENA ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_RDENA ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_WRENA ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_RDENA ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0 ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_WRENA ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_RDENA ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_WRENA ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_RDENA ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0 ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_WRENA ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_RDENA ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_WRENA ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_RDENA ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0 ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_WRENA ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_RDENA ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_WRENA , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_WRENA ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_RDENA , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_RDENA ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MATCH_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE0_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE0_MASK_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_RESERVED0 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0 ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_RESERVED0_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED0_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_WRENA , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_WRENA ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_RDENA , 41 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_RDENA ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED0_RELAXED_SOURCE1_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MATCH_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1 ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_WRENA ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_RDENA ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2 ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1 ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_WRENA ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_RDENA ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2 ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1 ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_WRENA ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_RDENA ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2 ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1 ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_WRENA ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_RDENA ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2 ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1 ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_WRENA ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_RDENA ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2 ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1 ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_WRENA ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_RDENA ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2 ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1 ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_WRENA ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_RDENA ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2 ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1 ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_WRENA ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_RDENA ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2 ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1 ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_WRENA ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_RDENA ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2 ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1 ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_WRENA ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_RDENA ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2 ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1 ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_WRENA ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_RDENA ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2 ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE1_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE1_MASK_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_RESERVED1 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1 ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_WRENA , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_WRENA ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_RDENA , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_RDENA ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MATCH_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_SOURCE2_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE2_MASK_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_RESERVED2 , 58 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2 ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED1_RELAXED_RESERVED2_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED2_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_INJ ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_PR_DMA_INJ ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_DMA_PR_W ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_ADD ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_AND ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_OR ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_XOR ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_ADD ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_AND ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_OR ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_XOR ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_WRENA ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_RDENA ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK_LEN ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3 ); REG64_FLD( PU_NPU0_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_INJ ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_PR_DMA_INJ ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_DMA_PR_W ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_ADD ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_AND ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_OR ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_XOR ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_ADD ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_AND ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_OR ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_XOR ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_WRENA ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_RDENA ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK_LEN ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3 ); REG64_FLD( PU_NPU1_SM2_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_INJ ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_PR_DMA_INJ ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_DMA_PR_W ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_ADD ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_AND ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_OR ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_XOR ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_ADD ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_AND ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_OR ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_XOR ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_WRENA ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_RDENA ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK_LEN ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3 ); REG64_FLD( PU_NPU2_SM3_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_INJ ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_PR_DMA_INJ ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_DMA_PR_W ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_ADD ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_AND ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_OR ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_XOR ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_ADD ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_AND ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_OR ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_XOR ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_WRENA ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_RDENA ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK_LEN ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3 ); REG64_FLD( PU_NPU1_SM3_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_INJ ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_PR_DMA_INJ ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_DMA_PR_W ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_ADD ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_AND ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_OR ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_XOR ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_ADD ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_AND ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_OR ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_XOR ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_WRENA ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_RDENA ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK_LEN ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3 ); REG64_FLD( PU_NPU0_SM3_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_INJ ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_PR_DMA_INJ ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_DMA_PR_W ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_ADD ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_AND ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_OR ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_XOR ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_ADD ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_AND ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_OR ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_XOR ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_WRENA ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_RDENA ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK_LEN ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3 ); REG64_FLD( PU_NPU1_SM1_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_INJ ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_PR_DMA_INJ ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_DMA_PR_W ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_ADD ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_AND ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_OR ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_XOR ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_ADD ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_AND ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_OR ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_XOR ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_WRENA ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_RDENA ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK_LEN ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3 ); REG64_FLD( PU_NPU2_SM2_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_INJ ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_PR_DMA_INJ ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_DMA_PR_W ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_ADD ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_AND ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_OR ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_XOR ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_ADD ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_AND ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_OR ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_XOR ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_WRENA ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_RDENA ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK_LEN ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3 ); REG64_FLD( PU_NPU2_SM1_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_INJ ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_PR_DMA_INJ ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_DMA_PR_W ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_ADD ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_AND ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_OR ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_XOR ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_ADD ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_AND ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_OR ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_XOR ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_WRENA ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_RDENA ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK_LEN ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3 ); REG64_FLD( PU_NPU0_SM2_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_INJ ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_PR_DMA_INJ ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_DMA_PR_W ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_ADD ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_AND ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_OR ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_XOR ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_ADD ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_AND ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_OR ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_XOR ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_WRENA ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_RDENA ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK_LEN ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3 ); REG64_FLD( PU_NPU2_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_INJ ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_PR_DMA_INJ ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_DMA_PR_W ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_ADD ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_AND ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_OR ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_XOR ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_ADD ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_AND ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_OR ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_XOR ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_WRENA ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_RDENA ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK_LEN ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3 ); REG64_FLD( PU_NPU0_SM1_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_W_HP , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_W_HP ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_DMA_INJ , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_DMA_INJ ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_U , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_U ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMAX_S , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMAX_S ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_U , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_U ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_CAS_IMIN_S , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_CAS_IMIN_S ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_U , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_U ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMAX_S , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMAX_S ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_U , 9 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_U ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_IMIN_S , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_IMIN_S ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_PR_DMA_INJ , 11 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_PR_DMA_INJ ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_DMA_PR_W , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_DMA_PR_W ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_ADD , 13 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_ADD ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_AND , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_AND ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_OR , 15 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_OR ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMW_XOR , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMW_XOR ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_ADD , 17 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_ADD ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_AND , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_AND ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_OR , 19 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_OR ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_XOR , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_XOR ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_E , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_E ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_ARMWF_CAS_U , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_ARMWF_CAS_U ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_CMD_CL_RD_NC_F0 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_CMD_CL_RD_NC_F0 ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_WRENA , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_WRENA ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_RDENA , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_RDENA ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MATCH_LEN , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MATCH_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK , 44 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_SOURCE3_MASK_LEN , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_SOURCE3_MASK_LEN ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3 , 62 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3 ); REG64_FLD( PU_NPU1_SM0_CONFIG_RELAXED2_RELAXED_RESERVED3_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RELAXED_RESERVED3_LEN ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_WITHSTART_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_WITHADDR_0 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_READCONT_0 , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_READCONT_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_WITHSTOP_0 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_LENGTH_0 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_LENGTH_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_LENGTH_0_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_LENGTH_0_LEN ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_ADDR_0 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_ADDR_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_ADDR_0_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_ADDR_0_LEN ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_BIT_RNW_0 , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_RNW_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_SPEED_0 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_SPEED_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_SPEED_0_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_SPEED_0_LEN ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_PORT_NUMBER_0 , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_PORT_NUMBER_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_PORT_NUMBER_0_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_PORT_NUMBER_0_LEN ); REG64_FLD( PU_CONTROL_REGISTER_B_REG_ADDR_LEN_0 , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_REG_ADDR_LEN_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_REG_ADDR_LEN_0_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_REG_ADDR_LEN_0_LEN ); REG64_FLD( PU_CONTROL_REGISTER_B_ENH_MODE_0 , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENH_MODE_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_ECC_ENABLE_0 , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_ENABLE_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_ECCCHK_DISABLE_0 , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECCCHK_DISABLE_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_UNUSED_0 , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_FAST_MODE_INTERRUPT_STERRING_BITS_0 , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_FAST_MODE_INTERRUPT_STERRING_BITS_0_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_0_LEN ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_1_0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_1_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_1_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_1_0_LEN ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_2_0 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_2_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_2_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_2_0_LEN ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_3_0 , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_3_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_3_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_3_0_LEN ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_4_0 , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_4_0 ); REG64_FLD( PU_CONTROL_REGISTER_B_PIB_CNTR_REG_DATA_4_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_4_0_LEN ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_WITHSTART_1 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_1 ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_WITHADDR_1 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_1 ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_READCONT_1 , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_READCONT_1 ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_WITHSTOP_1 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_1 ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_LENGTH_1 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_LENGTH_1 ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_LENGTH_1_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_LENGTH_1_LEN ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_ADDR_1 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_ADDR_1 ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_ADDR_1_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_ADDR_1_LEN ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_BIT_RNW_1 , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_RNW_1 ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_SPEED_1 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_SPEED_1 ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_SPEED_1_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_SPEED_1_LEN ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_PORT_NUMBER_1 , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_PORT_NUMBER_1 ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_PORT_NUMBER_1_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_PORT_NUMBER_1_LEN ); REG64_FLD( PU_CONTROL_REGISTER_C_REG_ADDR_LEN_1 , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_REG_ADDR_LEN_1 ); REG64_FLD( PU_CONTROL_REGISTER_C_REG_ADDR_LEN_1_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_REG_ADDR_LEN_1_LEN ); REG64_FLD( PU_CONTROL_REGISTER_C_ENH_MODE_1 , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENH_MODE_1 ); REG64_FLD( PU_CONTROL_REGISTER_C_ECC_ENABLE_1 , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_ENABLE_1 ); REG64_FLD( PU_CONTROL_REGISTER_C_ECCCHK_DISABLE_1 , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECCCHK_DISABLE_1 ); REG64_FLD( PU_CONTROL_REGISTER_C_UNUSED_1 , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_1 ); REG64_FLD( PU_CONTROL_REGISTER_C_FAST_MODE_INTERRUPT_STERRING_BITS_1 , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_1 ); REG64_FLD( PU_CONTROL_REGISTER_C_FAST_MODE_INTERRUPT_STERRING_BITS_1_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_1_LEN ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_1_1 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_1_1 ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_1_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_1_1_LEN ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_2_1 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_2_1 ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_2_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_2_1_LEN ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_3_1 , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_3_1 ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_3_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_3_1_LEN ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_4_1 , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_4_1 ); REG64_FLD( PU_CONTROL_REGISTER_C_PIB_CNTR_REG_DATA_4_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_4_1_LEN ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_WITHSTART_2 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_2 ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_WITHADDR_2 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_2 ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_READCONT_2 , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_READCONT_2 ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_WITHSTOP_2 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_2 ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_LENGTH_2 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_LENGTH_2 ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_LENGTH_2_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_LENGTH_2_LEN ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_ADDR_2 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_ADDR_2 ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_ADDR_2_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_ADDR_2_LEN ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_BIT_RNW_2 , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_RNW_2 ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_SPEED_2 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_SPEED_2 ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_SPEED_2_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_SPEED_2_LEN ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_PORT_NUMBER_2 , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_PORT_NUMBER_2 ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_PORT_NUMBER_2_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_PORT_NUMBER_2_LEN ); REG64_FLD( PU_CONTROL_REGISTER_D_REG_ADDR_LEN_2 , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_REG_ADDR_LEN_2 ); REG64_FLD( PU_CONTROL_REGISTER_D_REG_ADDR_LEN_2_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_REG_ADDR_LEN_2_LEN ); REG64_FLD( PU_CONTROL_REGISTER_D_ENH_MODE_2 , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENH_MODE_2 ); REG64_FLD( PU_CONTROL_REGISTER_D_ECC_ENABLE_2 , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_ENABLE_2 ); REG64_FLD( PU_CONTROL_REGISTER_D_ECCCHK_DISABLE_2 , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECCCHK_DISABLE_2 ); REG64_FLD( PU_CONTROL_REGISTER_D_UNUSED_2 , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_2 ); REG64_FLD( PU_CONTROL_REGISTER_D_FAST_MODE_INTERRUPT_STERRING_BITS_2 , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_2 ); REG64_FLD( PU_CONTROL_REGISTER_D_FAST_MODE_INTERRUPT_STERRING_BITS_2_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_2_LEN ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_1_2 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_1_2 ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_1_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_1_2_LEN ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_2_2 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_2_2 ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_2_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_2_2_LEN ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_3_2 , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_3_2 ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_3_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_3_2_LEN ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_4_2 , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_4_2 ); REG64_FLD( PU_CONTROL_REGISTER_D_PIB_CNTR_REG_DATA_4_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_4_2_LEN ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_WITHSTART_3 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_WITHSTART_3 ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_WITHADDR_3 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_WITHADDR_3 ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_READCONT_3 , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_READCONT_3 ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_WITHSTOP_3 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_WITHSTOP_3 ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_LENGTH_3 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_LENGTH_3 ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_LENGTH_3_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_LENGTH_3_LEN ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_ADDR_3 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_ADDR_3 ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_ADDR_3_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_ADDR_3_LEN ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_BIT_RNW_3 , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_BIT_RNW_3 ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_SPEED_3 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_SPEED_3 ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_SPEED_3_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_SPEED_3_LEN ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_PORT_NUMBER_3 , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_PORT_NUMBER_3 ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_PORT_NUMBER_3_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_PORT_NUMBER_3_LEN ); REG64_FLD( PU_CONTROL_REGISTER_E_REG_ADDR_LEN_3 , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_REG_ADDR_LEN_3 ); REG64_FLD( PU_CONTROL_REGISTER_E_REG_ADDR_LEN_3_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_REG_ADDR_LEN_3_LEN ); REG64_FLD( PU_CONTROL_REGISTER_E_ENH_MODE_3 , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENH_MODE_3 ); REG64_FLD( PU_CONTROL_REGISTER_E_ECC_ENABLE_3 , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_ENABLE_3 ); REG64_FLD( PU_CONTROL_REGISTER_E_ECCCHK_DISABLE_3 , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECCCHK_DISABLE_3 ); REG64_FLD( PU_CONTROL_REGISTER_E_UNUSED_3 , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_3 ); REG64_FLD( PU_CONTROL_REGISTER_E_FAST_MODE_INTERRUPT_STERRING_BITS_3 , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_3 ); REG64_FLD( PU_CONTROL_REGISTER_E_FAST_MODE_INTERRUPT_STERRING_BITS_3_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_FAST_MODE_INTERRUPT_STERRING_BITS_3_LEN ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_1_3 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_1_3 ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_1_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_1_3_LEN ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_2_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_2_3 ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_2_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_2_3_LEN ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_3_3 , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_3_3 ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_3_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_3_3_LEN ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_4_3 , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_4_3 ); REG64_FLD( PU_CONTROL_REGISTER_E_PIB_CNTR_REG_DATA_4_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_CNTR_REG_DATA_4_3_LEN ); REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC , 0 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE0_SEL_DC ); REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE0_SEL_DC_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE0_SEL_DC_LEN ); REG64_FLD( PEC_CPLT_CONF0_RESERVED_6C , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_6C ); REG64_FLD( PEC_CPLT_CONF0_RESERVED_7C , 7 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_7C ); REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE1_SEL_DC ); REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE1_SEL_DC_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE1_SEL_DC_LEN ); REG64_FLD( PEC_CPLT_CONF0_RESERVED_14C , 14 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_14C ); REG64_FLD( PEC_CPLT_CONF0_RESERVED_15C , 15 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_15C ); REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC , 16 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE2_SEL_DC ); REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE2_SEL_DC_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE2_SEL_DC_LEN ); REG64_FLD( PEC_CPLT_CONF0_RESERVED_22C , 22 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_22C ); REG64_FLD( PEC_CPLT_CONF0_RESERVED_23C , 23 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_23C ); REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC , 24 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE3_SEL_DC ); REG64_FLD( PEC_CPLT_CONF0_CTRL_MISC_PROBE3_SEL_DC_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_PROBE3_SEL_DC_LEN ); REG64_FLD( PEC_CPLT_CONF0_RESERVED_30C , 30 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_30C ); REG64_FLD( PEC_CPLT_CONF0_RESERVED_31C , 31 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_31C ); REG64_FLD( PEC_CPLT_CONF0_CTRL_CC_OFLOW_FEH_SEL_DC , 32 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_OFLOW_FEH_SEL_DC ); REG64_FLD( PEC_CPLT_CONF0_CTRL_CC_SCAN_PROTECT_DC , 33 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_SCAN_PROTECT_DC ); REG64_FLD( PEC_CPLT_CONF0_CTRL_CC_SDIS_DC_N , 34 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_SDIS_DC_N ); REG64_FLD( PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_35C , 35 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_35C ); REG64_FLD( PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_36C , 36 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_36C ); REG64_FLD( PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_37C , 37 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_37C ); REG64_FLD( PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_38C , 38 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_38C ); REG64_FLD( PEC_CPLT_CONF0_RESERVED_TEST_CONTROL_39C , 39 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_TEST_CONTROL_39C ); REG64_FLD( PEC_CPLT_CONF0_CTRL_EPS_MASK_VITL_PCB_ERR_DC , 40 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_EPS_MASK_VITL_PCB_ERR_DC ); REG64_FLD( PEC_CPLT_CONF0_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC , 41 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_MASK_VITL_SCAN_OPCG_ERR_DC ); REG64_FLD( PEC_CPLT_CONF0_RESERVED_42C , 42 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_42C ); REG64_FLD( PEC_CPLT_CONF0_RESERVED_43C , 43 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_43C ); REG64_FLD( PEC_CPLT_CONF0_FREE_USAGE_44C , 44 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_44C ); REG64_FLD( PEC_CPLT_CONF0_FREE_USAGE_45C , 45 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_45C ); REG64_FLD( PEC_CPLT_CONF0_FREE_USAGE_46C , 46 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_46C ); REG64_FLD( PEC_CPLT_CONF0_FREE_USAGE_47C , 47 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_47C ); REG64_FLD( PEC_CPLT_CONF0_TC_UNIT_GROUP_ID_DC , 48 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_GROUP_ID_DC ); REG64_FLD( PEC_CPLT_CONF0_TC_UNIT_GROUP_ID_DC_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_GROUP_ID_DC_LEN ); REG64_FLD( PEC_CPLT_CONF0_TC_UNIT_CHIP_ID_DC , 52 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_CHIP_ID_DC ); REG64_FLD( PEC_CPLT_CONF0_TC_UNIT_CHIP_ID_DC_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_CHIP_ID_DC_LEN ); REG64_FLD( PEC_CPLT_CONF0_RESERVED_ID_55C , 55 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_55C ); REG64_FLD( PEC_CPLT_CONF0_TC_UNIT_SYS_ID_DC , 56 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_SYS_ID_DC ); REG64_FLD( PEC_CPLT_CONF0_TC_UNIT_SYS_ID_DC_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_SYS_ID_DC_LEN ); REG64_FLD( PEC_CPLT_CONF0_RESERVED_ID_61C , 61 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_61C ); REG64_FLD( PEC_CPLT_CONF0_RESERVED_ID_62C , 62 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_62C ); REG64_FLD( PEC_CPLT_CONF0_RESERVED_ID_63C , 63 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_ID_63C ); REG64_FLD( PEC_CPLT_CONF1_TC_IOX_MUX_VSEL , 0 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_IOX_MUX_VSEL ); REG64_FLD( PEC_CPLT_CONF1_TC_IOX_MUX_VSEL_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_IOX_MUX_VSEL_LEN ); REG64_FLD( PEC_CPLT_CONF1_UNUSED , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED ); REG64_FLD( PEC_CPLT_CONF1_TC_PBE0_IOVALID_DC , 4 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PBE0_IOVALID_DC ); REG64_FLD( PEC_CPLT_CONF1_TC_PBE1_IOVALID_DC , 5 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PBE1_IOVALID_DC ); REG64_FLD( PEC_CPLT_CONF1_TC_PBE2_IOVALID_DC , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PBE2_IOVALID_DC ); REG64_FLD( PEC_CPLT_CONF1_TC_PBE3_IOVALID_DC , 7 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PBE3_IOVALID_DC ); REG64_FLD( PEC_CPLT_CONF1_TC_PBE4_IOVALID_DC , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PBE4_IOVALID_DC ); REG64_FLD( PEC_CPLT_CONF1_TC_PBE5_IOVALID_DC , 9 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PBE5_IOVALID_DC ); REG64_FLD( PEC_CPLT_CONF1_TC_PSI_IOVALID_DC , 10 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PSI_IOVALID_DC ); REG64_FLD( PEC_CPLT_CONF1_IOVALID , 11 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_IOVALID ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_12D , 12 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_12D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_13D , 13 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_13D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_14D , 14 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_14D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_15D , 15 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_15D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_16D , 16 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_16D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_17D , 17 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_17D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_18D , 18 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_18D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_19D , 19 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_19D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_20D , 20 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_20D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_21D , 21 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_21D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_22D , 22 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_22D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_23D , 23 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_23D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_24D , 24 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_24D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_25D , 25 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_25D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_26D , 26 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_26D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_27D , 27 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_27D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_28D , 28 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_28D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_29D , 29 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_29D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_30D , 30 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_30D ); REG64_FLD( PEC_CPLT_CONF1_FREE_USAGE_31D , 31 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_31D ); REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_ABSTCLK_MUXSEL_DC , 0 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_ABSTCLK_MUXSEL_DC ); REG64_FLD( PEC_CPLT_CTRL0_TC_UNIT_SYNCCLK_MUXSEL_DC , 1 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_SYNCCLK_MUXSEL_DC ); REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_FLUSHMODE_INH_DC , 2 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_FLUSHMODE_INH_DC ); REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_FORCE_ALIGN_DC , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_FORCE_ALIGN_DC ); REG64_FLD( PEC_CPLT_CTRL0_TC_UNIT_ARY_WRT_THRU_DC , 4 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_ARY_WRT_THRU_DC ); REG64_FLD( PEC_CPLT_CTRL0_TC_UNIT_AVP_MODE , 5 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_AVP_MODE ); REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_6A , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_6A ); REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_7A , 7 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_7A ); REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_ABIST_RECOV_DISABLE_DC , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_ABIST_RECOV_DISABLE_DC ); REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_9A , 9 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_9A ); REG64_FLD( PEC_CPLT_CTRL0_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC , 10 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_IOBIST_TX_WRAP_ENABLE_DC ); REG64_FLD( PEC_CPLT_CTRL0_RESERVED_11A , 11 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_11A ); REG64_FLD( PEC_CPLT_CTRL0_TC_SKIT_MODE_BIST_DC , 12 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_SKIT_MODE_BIST_DC ); REG64_FLD( PEC_CPLT_CTRL0_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC , 13 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_DETERMINISTIC_TEST_ENABLE_DC ); REG64_FLD( PEC_CPLT_CTRL0_TC_UNIT_CONSTRAIN_SAFESCAN_DC , 14 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_CONSTRAIN_SAFESCAN_DC ); REG64_FLD( PEC_CPLT_CTRL0_TC_UNIT_RRFA_TEST_ENABLE_DC , 15 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_RRFA_TEST_ENABLE_DC ); REG64_FLD( PEC_CPLT_CTRL0_TC_NBTI_HDR_ENABLE_OVR_DC , 16 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_NBTI_HDR_ENABLE_OVR_DC ); REG64_FLD( PEC_CPLT_CTRL0_TC_NBTI_PROBE_GATE_DC , 17 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_NBTI_PROBE_GATE_DC ); REG64_FLD( PEC_CPLT_CTRL0_RESERVED_18A , 18 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_18A ); REG64_FLD( PEC_CPLT_CTRL0_RESERVED_19A , 19 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_19A ); REG64_FLD( PEC_CPLT_CTRL0_TC_PSRO_SEL_DC , 20 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PSRO_SEL_DC ); REG64_FLD( PEC_CPLT_CTRL0_TC_PSRO_SEL_DC_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PSRO_SEL_DC_LEN ); REG64_FLD( PEC_CPLT_CTRL0_TC_BSC_WRAPSEL_DC , 28 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_BSC_WRAPSEL_DC ); REG64_FLD( PEC_CPLT_CTRL0_TC_BSC_INTMODE_DC , 29 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_BSC_INTMODE_DC ); REG64_FLD( PEC_CPLT_CTRL0_TC_BSC_INV_DC , 30 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_BSC_INV_DC ); REG64_FLD( PEC_CPLT_CTRL0_TC_BSC_EXTMODE_DC , 31 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_BSC_EXTMODE_DC ); REG64_FLD( PEC_CPLT_CTRL0_TC_REFCLK_DRVR_EN_DC , 32 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REFCLK_DRVR_EN_DC ); REG64_FLD( PEC_CPLT_CTRL0_RESERVED_33A , 33 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_33A ); REG64_FLD( PEC_CPLT_CTRL0_RESERVED_34A , 34 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_34A ); REG64_FLD( PEC_CPLT_CTRL0_RESERVED_35A , 35 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_35A ); REG64_FLD( PEC_CPLT_CTRL0_TC_OELCC_EDGE_DELAYED_DC , 36 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_OELCC_EDGE_DELAYED_DC ); REG64_FLD( PEC_CPLT_CTRL0_TC_OELCC_ALIGN_FLUSH_DC , 37 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_OELCC_ALIGN_FLUSH_DC ); REG64_FLD( PEC_CPLT_CTRL0_RESERVED_38A , 38 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_38A ); REG64_FLD( PEC_CPLT_CTRL0_RESERVED_39A , 39 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_39A ); REG64_FLD( PEC_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC , 40 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_CLKDIV_SEL_DC ); REG64_FLD( PEC_CPLT_CTRL0_CTRL_MISC_CLKDIV_SEL_DC_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_MISC_CLKDIV_SEL_DC_LEN ); REG64_FLD( PEC_CPLT_CTRL0_RESERVED_42A , 42 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_42A ); REG64_FLD( PEC_CPLT_CTRL0_RESERVED_43A , 43 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED_43A ); REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_DCTEST_DC , 44 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_DCTEST_DC ); REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_OTP_PRGMODE_DC , 45 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_OTP_PRGMODE_DC ); REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_SSS_CALIBRATE_DC , 46 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_SSS_CALIBRATE_DC ); REG64_FLD( PEC_CPLT_CTRL0_CTRL_CC_PIN_LBIST_DC , 47 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_CTRL_CC_PIN_LBIST_DC ); REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_48A , 48 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_48A ); REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_49A , 49 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_49A ); REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_50A , 50 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_50A ); REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_51A , 51 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_51A ); REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_52A , 52 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_52A ); REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_53A , 53 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_53A ); REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_54A , 54 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_54A ); REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_55A , 55 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_55A ); REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_56A , 56 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_56A ); REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_57A , 57 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_57A ); REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_58A , 58 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_58A ); REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_59A , 59 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_59A ); REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_60A , 60 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_60A ); REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_61A , 61 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_61A ); REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_62A , 62 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_62A ); REG64_FLD( PEC_CPLT_CTRL0_FREE_USAGE_63A , 63 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_FREE_USAGE_63A ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_0B , 0 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_0B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_1B , 1 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_1B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_2B , 2 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_2B ); REG64_FLD( PEC_CPLT_CTRL1_TC_VITL_REGION_FENCE , 3 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_VITL_REGION_FENCE ); REG64_FLD( PEC_CPLT_CTRL1_TC_PERV_REGION_FENCE , 4 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_PERV_REGION_FENCE ); REG64_FLD( PEC_CPLT_CTRL1_TC_REGION1_FENCE , 5 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION1_FENCE ); REG64_FLD( PEC_CPLT_CTRL1_TC_REGION2_FENCE , 6 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION2_FENCE ); REG64_FLD( PEC_CPLT_CTRL1_TC_REGION3_FENCE , 7 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION3_FENCE ); REG64_FLD( PEC_CPLT_CTRL1_TC_REGION4_FENCE , 8 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION4_FENCE ); REG64_FLD( PEC_CPLT_CTRL1_TC_REGION5_FENCE , 9 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION5_FENCE ); REG64_FLD( PEC_CPLT_CTRL1_TC_REGION6_FENCE , 10 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION6_FENCE ); REG64_FLD( PEC_CPLT_CTRL1_TC_REGION7_FENCE , 11 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_REGION7_FENCE ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_12B , 12 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_12B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_13B , 13 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_13B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_14B , 14 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_14B ); REG64_FLD( PEC_CPLT_CTRL1_RESERVED , 15 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_RESERVED ); REG64_FLD( PEC_CPLT_CTRL1_TC_UNIT_MULTICYCLE_TEST_FENCE , 16 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_TC_UNIT_MULTICYCLE_TEST_FENCE ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_17B , 17 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_17B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_18B , 18 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_18B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_19B , 19 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_19B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_20B , 20 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_20B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_21B , 21 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_21B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_22B , 22 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_22B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_23B , 23 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_23B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_24B , 24 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_24B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_25B , 25 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_25B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_26B , 26 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_26B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_27B , 27 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_27B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_28B , 28 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_28B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_29B , 29 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_29B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_30B , 30 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_30B ); REG64_FLD( PEC_CPLT_CTRL1_UNUSED_31B , 31 , SH_UNT_PEC , SH_ACS_SCOM2_CLEAR, SH_FLD_UNUSED_31B ); REG64_FLD( PEC_CPLT_MASK0_CPLTMASK0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CPLTMASK0 ); REG64_FLD( PEC_CPLT_MASK0_CPLTMASK0_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CPLTMASK0_LEN ); REG64_FLD( PEC_CPLT_STAT0_SRAM_ABIST_DONE_DC , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SRAM_ABIST_DONE_DC ); REG64_FLD( PEC_CPLT_STAT0_DRAM_ABIST_DONE_DC , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DRAM_ABIST_DONE_DC ); REG64_FLD( PEC_CPLT_STAT0_RESERVED_2E , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESERVED_2E ); REG64_FLD( PEC_CPLT_STAT0_RESERVED_3E , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESERVED_3E ); REG64_FLD( PEC_CPLT_STAT0_TC_DIAG_PORT0_OUT , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TC_DIAG_PORT0_OUT ); REG64_FLD( PEC_CPLT_STAT0_TC_DIAG_PORT1_OUT , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TC_DIAG_PORT1_OUT ); REG64_FLD( PEC_CPLT_STAT0_RESERVED_6E , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESERVED_6E ); REG64_FLD( PEC_CPLT_STAT0_PLL_DESTOUT , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PLL_DESTOUT ); REG64_FLD( PEC_CPLT_STAT0_CC_CTRL_OPCG_DONE_DC , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CC_CTRL_OPCG_DONE_DC ); REG64_FLD( PEC_CPLT_STAT0_CC_CTRL_CHIPLET_IS_ALIGNED_DC , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CC_CTRL_CHIPLET_IS_ALIGNED_DC ); REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_10E , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FREE_USAGE_10E ); REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_11E , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FREE_USAGE_11E ); REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_12E , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FREE_USAGE_12E ); REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_13E , 13 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FREE_USAGE_13E ); REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_14E , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FREE_USAGE_14E ); REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_15E , 15 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FREE_USAGE_15E ); REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_16E , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FREE_USAGE_16E ); REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_17E , 17 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FREE_USAGE_17E ); REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_18E , 18 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FREE_USAGE_18E ); REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_19E , 19 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FREE_USAGE_19E ); REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_20E , 20 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FREE_USAGE_20E ); REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_21E , 21 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FREE_USAGE_21E ); REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_22E , 22 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FREE_USAGE_22E ); REG64_FLD( PEC_CPLT_STAT0_FREE_USAGE_23E , 23 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FREE_USAGE_23E ); REG64_FLD( PEC_STACK2_CQSTAT_REG_PE_INBOUND_ACTIVE , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RO , SH_FLD_PE_INBOUND_ACTIVE ); REG64_FLD( PEC_STACK2_CQSTAT_REG_PE_OUTBOUND_ACTIVE , 1 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RO , SH_FLD_PE_OUTBOUND_ACTIVE ); REG64_FLD( PEC_STACK1_CQSTAT_REG_PE_INBOUND_ACTIVE , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RO , SH_FLD_PE_INBOUND_ACTIVE ); REG64_FLD( PEC_STACK1_CQSTAT_REG_PE_OUTBOUND_ACTIVE , 1 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RO , SH_FLD_PE_OUTBOUND_ACTIVE ); REG64_FLD( PHB_CQSTAT_REG_PE_INBOUND_ACTIVE , 0 , SH_UNT_PHB , SH_ACS_SCOM_RO , SH_FLD_PE_INBOUND_ACTIVE ); REG64_FLD( PHB_CQSTAT_REG_PE_OUTBOUND_ACTIVE , 1 , SH_UNT_PHB , SH_ACS_SCOM_RO , SH_FLD_PE_OUTBOUND_ACTIVE ); REG64_FLD( PEC_STACK0_CQSTAT_REG_PE_INBOUND_ACTIVE , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RO , SH_FLD_PE_INBOUND_ACTIVE ); REG64_FLD( PEC_STACK0_CQSTAT_REG_PE_OUTBOUND_ACTIVE , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RO , SH_FLD_PE_OUTBOUND_ACTIVE ); REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_START , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_START ); REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_START_LEN , 9 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_START_LEN ); REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_RESERVED2_LEN , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_END , 15 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_END ); REG64_FLD( PU_NPU2_NTL0_CREQ_DA_PTR_END_LEN , 9 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_END_LEN ); REG64_FLD( NV_CREQ_DA_PTR_RESERVED1 , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( NV_CREQ_DA_PTR_RESERVED1_LEN , 3 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( NV_CREQ_DA_PTR_START , 3 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_START ); REG64_FLD( NV_CREQ_DA_PTR_START_LEN , 9 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_START_LEN ); REG64_FLD( NV_CREQ_DA_PTR_RESERVED2 , 12 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( NV_CREQ_DA_PTR_RESERVED2_LEN , 3 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( NV_CREQ_DA_PTR_END , 15 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_END ); REG64_FLD( NV_CREQ_DA_PTR_END_LEN , 9 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_END_LEN ); REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_START , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_START ); REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_START_LEN , 9 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_START_LEN ); REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_RESERVED2_LEN , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_END , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_END ); REG64_FLD( PU_NPU2_NTL1_CREQ_DA_PTR_END_LEN , 9 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_END_LEN ); REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_START , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_START ); REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_START_LEN , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_START_LEN ); REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_END , 17 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_END ); REG64_FLD( PU_NPU2_NTL0_CREQ_HA_PTR_END_LEN , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_END_LEN ); REG64_FLD( NV_CREQ_HA_PTR_RESERVED1 , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( NV_CREQ_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( NV_CREQ_HA_PTR_START , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_START ); REG64_FLD( NV_CREQ_HA_PTR_START_LEN , 7 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_START_LEN ); REG64_FLD( NV_CREQ_HA_PTR_RESERVED2 , 12 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( NV_CREQ_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( NV_CREQ_HA_PTR_END , 17 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_END ); REG64_FLD( NV_CREQ_HA_PTR_END_LEN , 7 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_END_LEN ); REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_START , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_START ); REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_START_LEN , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_START_LEN ); REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_END , 17 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_END ); REG64_FLD( PU_NPU2_NTL1_CREQ_HA_PTR_END_LEN , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_END_LEN ); REG64_FLD( PU_CSAR_SRAM_ADDRESS , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_ADDRESS ); REG64_FLD( PU_CSAR_SRAM_ADDRESS_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_ADDRESS_LEN ); REG64_FLD( PU_CSCR_SRAM_ACCESS_MODE , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SRAM_ACCESS_MODE ); REG64_FLD( PU_CSCR_SRAM_SCRUB_ENABLE , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SRAM_SCRUB_ENABLE ); REG64_FLD( PU_CSCR_ECC_CORRECT_DIS , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ECC_CORRECT_DIS ); REG64_FLD( PU_CSCR_ECC_DETECT_DIS , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ECC_DETECT_DIS ); REG64_FLD( PU_CSCR_ECC_INJECT_TYPE , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ECC_INJECT_TYPE ); REG64_FLD( PU_CSCR_ECC_INJECT_ERR , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ECC_INJECT_ERR ); REG64_FLD( PU_CSCR_SPARE_6_7 , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_6_7 ); REG64_FLD( PU_CSCR_SPARE_6_7_LEN , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_6_7_LEN ); REG64_FLD( PU_CSCR_SRAM_SCRUB_INDEX , 47 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SRAM_SCRUB_INDEX ); REG64_FLD( PU_CSCR_SRAM_SCRUB_INDEX_LEN , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SRAM_SCRUB_INDEX_LEN ); REG64_FLD( PU_CSDR_SRAM_DATA , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_DATA ); REG64_FLD( PU_CSDR_SRAM_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_DATA_LEN ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_SM_MMIO0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_SM_MMIO0 ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_SM_MMIO1 , 1 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_SM_MMIO1 ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_SM_MMIO2 , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_SM_MMIO2 ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_SM_MMIO3 , 3 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_SM_MMIO3 ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_MRBGP , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_MRBGP ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_MRBGP_LEN ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_MRBSP , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_MRBSP ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_FENCE0 , 12 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_FENCE0 ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_FENCE1 , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_FENCE1 ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_LPCTH , 20 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_LPCTH ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_LPCTH_LEN , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_LPCTH_LEN ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_PBM_STATE , 22 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PBM_STATE ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_PBM_STATE_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PBM_STATE_LEN ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_BRK0_RLX , 27 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_BRK0_RLX ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_BRK1_RLX , 28 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_BRK1_RLX ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_BRK0_NVL , 29 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_BRK0_NVL ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_BRK1_NVL , 30 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_BRK1_NVL ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_ATS_SYNC , 31 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_ATS_SYNC ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_NMMU , 32 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_NMMU ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_PBLN , 33 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PBLN ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_PBNNG , 34 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PBNNG ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_PBRNVG , 35 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PBRNVG ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_NVREQ0 , 36 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_NVREQ0 ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_NVDGD0 , 37 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_NVDGD0 ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_NVREQ1 , 38 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_NVREQ1 ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_NVDGD1 , 39 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_NVDGD1 ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_ATSREQ , 40 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_ATSREQ ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_MMIO , 41 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_MMIO ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_PBRS , 42 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PBRS ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_NVRS0 , 43 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_NVRS0 ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_NVRS1 , 44 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_NVRS1 ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_XARS , 45 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_XARS ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_ATRR , 46 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_ATRR ); REG64_FLD( PU_NPU1_CTL_CTL_STATUS_RESERVED1 , 47 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_SM_MMIO0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_SM_MMIO0 ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_SM_MMIO1 , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_SM_MMIO1 ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_SM_MMIO2 , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_SM_MMIO2 ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_SM_MMIO3 , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_SM_MMIO3 ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_MRBGP , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_MRBGP ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_MRBGP_LEN ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_MRBSP , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_MRBSP ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_FENCE0 , 12 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_FENCE0 ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_FENCE1 , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_FENCE1 ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_LPCTH , 20 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_LPCTH ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_LPCTH_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_LPCTH_LEN ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_PBM_STATE , 22 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PBM_STATE ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_PBM_STATE_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PBM_STATE_LEN ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_BRK0_RLX , 27 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_BRK0_RLX ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_BRK1_RLX , 28 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_BRK1_RLX ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_BRK0_NVL , 29 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_BRK0_NVL ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_BRK1_NVL , 30 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_BRK1_NVL ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_ATS_SYNC , 31 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_ATS_SYNC ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_NMMU , 32 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_NMMU ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_PBLN , 33 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PBLN ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_PBNNG , 34 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PBNNG ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_PBRNVG , 35 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PBRNVG ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_NVREQ0 , 36 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_NVREQ0 ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_NVDGD0 , 37 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_NVDGD0 ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_NVREQ1 , 38 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_NVREQ1 ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_NVDGD1 , 39 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_NVDGD1 ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_ATSREQ , 40 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_ATSREQ ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_MMIO , 41 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_MMIO ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_PBRS , 42 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PBRS ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_NVRS0 , 43 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_NVRS0 ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_NVRS1 , 44 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_NVRS1 ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_XARS , 45 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_XARS ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_ATRR , 46 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_ATRR ); REG64_FLD( PU_NPU0_CTL_CTL_STATUS_RESERVED1 , 47 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_SM_MMIO0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_SM_MMIO0 ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_SM_MMIO1 , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_SM_MMIO1 ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_SM_MMIO2 , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_SM_MMIO2 ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_SM_MMIO3 , 3 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_SM_MMIO3 ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_MRBGP , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_MRBGP ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_MRBGP_LEN ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_MRBSP , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_MRBSP ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_FENCE0 , 12 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_FENCE0 ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_FENCE1 , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_FENCE1 ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_LPCTH , 20 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_LPCTH ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_LPCTH_LEN , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_LPCTH_LEN ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_PBM_STATE , 22 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PBM_STATE ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_PBM_STATE_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PBM_STATE_LEN ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_BRK0_RLX , 27 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_BRK0_RLX ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_BRK1_RLX , 28 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_BRK1_RLX ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_BRK0_NVL , 29 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_BRK0_NVL ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_BRK1_NVL , 30 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_BRK1_NVL ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_ATS_SYNC , 31 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ATS_SYNC ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_NMMU , 32 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_NMMU ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_PBLN , 33 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PBLN ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_PBNNG , 34 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PBNNG ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_PBRNVG , 35 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PBRNVG ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_NVREQ0 , 36 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_NVREQ0 ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_NVDGD0 , 37 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_NVDGD0 ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_NVREQ1 , 38 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_NVREQ1 ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_NVDGD1 , 39 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_NVDGD1 ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_ATSREQ , 40 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ATSREQ ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_MMIO , 41 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_MMIO ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_PBRS , 42 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PBRS ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_NVRS0 , 43 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_NVRS0 ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_NVRS1 , 44 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_NVRS1 ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_XARS , 45 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_XARS ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_ATRR , 46 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ATRR ); REG64_FLD( PU_NPU2_CTL_CTL_STATUS_RESERVED1 , 47 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PEC_CTRL_ATOMIC_LOCK_REG_ENABLE , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PEC_CTRL_ATOMIC_LOCK_REG_ID , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ID ); REG64_FLD( PEC_CTRL_ATOMIC_LOCK_REG_ID_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ID_LEN ); REG64_FLD( PEC_CTRL_ATOMIC_LOCK_REG_ACTIVITY , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACTIVITY ); REG64_FLD( PEC_CTRL_ATOMIC_LOCK_REG_ACTIVITY_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACTIVITY_LEN ); REG64_FLD( PEC_CTRL_PROTECT_MODE_REG_READ_ENABLE , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_READ_ENABLE ); REG64_FLD( PEC_CTRL_PROTECT_MODE_REG_WRITE_ENABLE , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_WRITE_ENABLE ); REG64_FLD( CAPP_CXA_SNP_ARRAY_ADDR_REG_ADDRESS , 1 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_ADDRESS ); REG64_FLD( CAPP_CXA_SNP_ARRAY_ADDR_REG_ADDRESS_LEN , 15 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_ADDRESS_LEN ); REG64_FLD( CAPP_CXA_SNP_ARRAY_READ_REG_DATA , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_DATA ); REG64_FLD( CAPP_CXA_SNP_ARRAY_READ_REG_DATA_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_DATA_LEN ); REG64_FLD( CAPP_CXA_SNP_ARRAY_WRITE_REG_DATA , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_DATA ); REG64_FLD( CAPP_CXA_SNP_ARRAY_WRITE_REG_DATA_LEN , 64 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_DATA_LEN ); REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG0_0_CANNED_0 , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_0_CANNED_0 ); REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG0_0_CANNED_0_LEN , 32 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_0_CANNED_0_LEN ); REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG0_0_CANNED_1 , 32 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_0_CANNED_1 ); REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG0_0_CANNED_1_LEN , 32 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_0_CANNED_1_LEN ); REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG1_1_CANNED_0 , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_1_CANNED_0 ); REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG1_1_CANNED_0_LEN , 32 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_1_CANNED_0_LEN ); REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG1_1_CANNED_1 , 32 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_1_CANNED_1 ); REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG1_1_CANNED_1_LEN , 32 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_1_CANNED_1_LEN ); REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG2_2_CANNED_0 , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_2_CANNED_0 ); REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG2_2_CANNED_0_LEN , 32 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_2_CANNED_0_LEN ); REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG2_2_CANNED_1 , 32 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_2_CANNED_1 ); REG64_FLD( CAPP_CXA_SNP_CAN_PRESP_REG2_2_CANNED_1_LEN , 32 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_2_CANNED_1_LEN ); REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_ENABLE_TTYPE_DECODE , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_ENABLE_TTYPE_DECODE ); REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_PRECISE_DIR_SIZE , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PRECISE_DIR_SIZE ); REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_PRECISE_DIR_SIZE_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PRECISE_DIR_SIZE_LEN ); REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_COARSE_DIR_ENABLE , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_COARSE_DIR_ENABLE ); REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_COARSE_DIR_SECTORS , 5 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_COARSE_DIR_SECTORS ); REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_MCD_CHICKEN_SWITCH , 6 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_MCD_CHICKEN_SWITCH ); REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_BHR_DIR_STATE , 7 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BHR_DIR_STATE ); REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_BHR_DIR_STATE_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BHR_DIR_STATE_LEN ); REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_LPC_MODE , 12 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_LPC_MODE ); REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_LPC_MODE_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_LPC_MODE_LEN ); REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_CT_COMPARE_VECTOR , 32 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_CT_COMPARE_VECTOR ); REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_CT_COMPARE_VECTOR_LEN , 6 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_CT_COMPARE_VECTOR_LEN ); REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_PHB_FILTER_CNTL , 38 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PHB_FILTER_CNTL ); REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_PHB_FILTER_CNTL_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PHB_FILTER_CNTL_LEN ); REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_EPOCH_TEST_VECTOR , 40 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_EPOCH_TEST_VECTOR ); REG64_FLD( CAPP_CXA_SNP_CAPI_CFG_REG_EPOCH_TEST_VECTOR_LEN , 24 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_EPOCH_TEST_VECTOR_LEN ); REG64_FLD( CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_MODE , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_READ_EPSILON_MODE ); REG64_FLD( CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER0 , 3 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_READ_EPSILON_TIER0 ); REG64_FLD( CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER0_LEN , 9 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_READ_EPSILON_TIER0_LEN ); REG64_FLD( CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER1 , 15 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_READ_EPSILON_TIER1 ); REG64_FLD( CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER1_LEN , 9 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_READ_EPSILON_TIER1_LEN ); REG64_FLD( CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER2 , 25 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_READ_EPSILON_TIER2 ); REG64_FLD( CAPP_CXA_SNP_CNTL_REG_READ_EPSILON_TIER2_LEN , 11 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_READ_EPSILON_TIER2_LEN ); REG64_FLD( CAPP_CXA_SNP_CNTL_REG_ADDRESS_PIPELINE_MASTERWAIT_COUNT , 45 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_ADDRESS_PIPELINE_MASTERWAIT_COUNT ); REG64_FLD( CAPP_CXA_SNP_CNTL_REG_ADDRESS_PIPELINE_MASTERWAIT_COUNT_LEN , 3 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_ADDRESS_PIPELINE_MASTERWAIT_COUNT_LEN ); REG64_FLD( CAPP_CXA_SNP_CNTL_REG_DATA_HANG_POLL_SCALE , 48 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_DATA_HANG_POLL_SCALE ); REG64_FLD( CAPP_CXA_SNP_CNTL_REG_DATA_HANG_POLL_SCALE_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_DATA_HANG_POLL_SCALE_LEN ); REG64_FLD( CAPP_CXA_SNP_ERROR_REPORT_REG_C_ERR_RPT_HOLD_DATA , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_C_ERR_RPT_HOLD_DATA ); REG64_FLD( CAPP_CXA_SNP_ERROR_REPORT_REG_C_ERR_RPT_HOLD_DATA_LEN , 32 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_C_ERR_RPT_HOLD_DATA_LEN ); REG64_FLD( CAPP_CXA_SNP_PHB_TTAG_FILTER_REG_FILTER , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_FILTER ); REG64_FLD( CAPP_CXA_SNP_PHB_TTAG_FILTER_REG_FILTER_LEN , 48 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_FILTER_LEN ); REG64_FLD( CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_GROUP , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_GROUP ); REG64_FLD( CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_GROUP_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_GROUP_LEN ); REG64_FLD( CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_FSMJ_EVENT , 6 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_FSMJ_EVENT ); REG64_FLD( CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_FSMJ_EVENT_LEN , 6 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_FSMJ_EVENT_LEN ); REG64_FLD( CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_FSMJ_FSM , 14 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_FSMJ_FSM ); REG64_FLD( CAPP_CXA_SNP_PMU_EVENTS_SELECT_REG_FSMJ_FSM_LEN , 6 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_FSMJ_FSM_LEN ); REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG_EN , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_EN ); REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG_SIZE , 1 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SIZE ); REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG_SIZE_LEN , 18 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SIZE_LEN ); REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG_STARTING_ADDRESS , 19 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_STARTING_ADDRESS ); REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG_STARTING_ADDRESS_LEN , 27 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_STARTING_ADDRESS_LEN ); REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG_SYSTEM , 50 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SYSTEM ); REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG_SYSTEM_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SYSTEM_LEN ); REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1_BAR1_EN , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BAR1_EN ); REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1_BAR1_SIZE , 1 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BAR1_SIZE ); REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1_BAR1_SIZE_LEN , 18 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BAR1_SIZE_LEN ); REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1_BAR1_STARTING_ADDRESS , 19 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BAR1_STARTING_ADDRESS ); REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1_BAR1_STARTING_ADDRESS_LEN , 27 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BAR1_STARTING_ADDRESS_LEN ); REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1_BAR1_SYSTEM , 50 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BAR1_SYSTEM ); REG64_FLD( CAPP_CXA_SNP_REMOTE_ADDR_BAR_BARM_REG1_BAR1_SYSTEM_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BAR1_SYSTEM_LEN ); REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG_EN , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_EN ); REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG_MS_GROUP_CHIP , 13 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_MS_GROUP_CHIP ); REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG_MS_GROUP_CHIP_LEN , 9 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_MS_GROUP_CHIP_LEN ); REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG_STARTING_ADDRESS , 22 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_STARTING_ADDRESS ); REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG_STARTING_ADDRESS_LEN , 31 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_STARTING_ADDRESS_LEN ); REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1_BAR1_EN , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BAR1_EN ); REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1_BAR1_MS_GROUP_CHIP , 13 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BAR1_MS_GROUP_CHIP ); REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1_BAR1_MS_GROUP_CHIP_LEN , 9 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BAR1_MS_GROUP_CHIP_LEN ); REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1_BAR1_STARTING_ADDRESS , 22 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BAR1_STARTING_ADDRESS ); REG64_FLD( CAPP_CXA_SNP_REMOTE_MMIO_BAR_BARM_REG1_BAR1_STARTING_ADDRESS_LEN , 31 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BAR1_STARTING_ADDRESS_LEN ); REG64_FLD( CAPP_CXA_TRIGCTL_PORTSEL , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PORTSEL ); REG64_FLD( CAPP_CXA_TRIGCTL_PORTSEL_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PORTSEL_LEN ); REG64_FLD( CAPP_CXA_TRIGCTL_APC0_ENABLE , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APC0_ENABLE ); REG64_FLD( CAPP_CXA_TRIGCTL_APC1_ENABLE , 5 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APC1_ENABLE ); REG64_FLD( CAPP_CXA_TRIGCTL_SNPFE_TRIGGER_ENABLE , 6 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SNPFE_TRIGGER_ENABLE ); REG64_FLD( CAPP_CXA_TRIGCTL_SNPFE_DIR_TRIGGER_ENABLE , 7 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SNPFE_DIR_TRIGGER_ENABLE ); REG64_FLD( CAPP_CXA_TRIGCTL_SNPBE_TRIGGER_ENABLE , 8 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SNPBE_TRIGGER_ENABLE ); REG64_FLD( CAPP_CXA_TRIGCTL_SNPBE_UOP_TRIGGER_ENABLE , 9 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SNPBE_UOP_TRIGGER_ENABLE ); REG64_FLD( CAPP_CXA_TRIGCTL_SNP_MUX_PORT_SEL , 12 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SNP_MUX_PORT_SEL ); REG64_FLD( CAPP_CXA_TRIGCTL_SNP_MUX_PORT_SEL_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SNP_MUX_PORT_SEL_LEN ); REG64_FLD( PU_DATA0TO7_REGISTER_B_PIB_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_0 ); REG64_FLD( PU_DATA0TO7_REGISTER_B_PIB_0_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_0_LEN ); REG64_FLD( PU_DATA0TO7_REGISTER_C_PIB_1 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_1 ); REG64_FLD( PU_DATA0TO7_REGISTER_C_PIB_1_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_1_LEN ); REG64_FLD( PU_DATA0TO7_REGISTER_D_PIB_2 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_2 ); REG64_FLD( PU_DATA0TO7_REGISTER_D_PIB_2_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_2_LEN ); REG64_FLD( PU_DATA0TO7_REGISTER_E_PIB_3 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_3 ); REG64_FLD( PU_DATA0TO7_REGISTER_E_PIB_3_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_3_LEN ); REG64_FLD( PU_DATA8TO15_REGISTER_B_PIB_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_0 ); REG64_FLD( PU_DATA8TO15_REGISTER_B_PIB_0_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_0_LEN ); REG64_FLD( PU_DATA8TO15_REGISTER_C_PIB_1 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_1 ); REG64_FLD( PU_DATA8TO15_REGISTER_C_PIB_1_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_1_LEN ); REG64_FLD( PU_DATA8TO15_REGISTER_D_PIB_2 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_2 ); REG64_FLD( PU_DATA8TO15_REGISTER_D_PIB_2_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_2_LEN ); REG64_FLD( PU_DATA8TO15_REGISTER_E_PIB_3 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_3 ); REG64_FLD( PU_DATA8TO15_REGISTER_E_PIB_3_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_3_LEN ); REG64_FLD( PU_DATATAG_0_HASH_FUNCTION_REG_FUNCTION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FUNCTION ); REG64_FLD( PU_DATATAG_0_HASH_FUNCTION_REG_FUNCTION_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FUNCTION_LEN ); REG64_FLD( PU_DATATAG_1_HASH_FUNCTION_REG_FUNCTION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FUNCTION ); REG64_FLD( PU_DATATAG_1_HASH_FUNCTION_REG_FUNCTION_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FUNCTION_LEN ); REG64_FLD( PU_DATATAG_2_HASH_FUNCTION_REG_FUNCTION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FUNCTION ); REG64_FLD( PU_DATATAG_2_HASH_FUNCTION_REG_FUNCTION_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FUNCTION_LEN ); REG64_FLD( PU_DATATAG_3_HASH_FUNCTION_REG_FUNCTION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FUNCTION ); REG64_FLD( PU_DATATAG_3_HASH_FUNCTION_REG_FUNCTION_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FUNCTION_LEN ); REG64_FLD( PU_DATATAG_4_HASH_FUNCTION_REG_FUNCTION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FUNCTION ); REG64_FLD( PU_DATATAG_4_HASH_FUNCTION_REG_FUNCTION_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FUNCTION_LEN ); REG64_FLD( PU_DATATAG_5_HASH_FUNCTION_REG_FUNCTION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FUNCTION ); REG64_FLD( PU_DATATAG_5_HASH_FUNCTION_REG_FUNCTION_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FUNCTION_LEN ); REG64_FLD( PU_DATA_REGISTER_OTP , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_OTP ); REG64_FLD( PU_DATA_REGISTER_OTP_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_OTP_LEN ); REG64_FLD( PU_NPU_CTL_DA_ADDR_MISC , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC ); REG64_FLD( PU_NPU_CTL_DA_ADDR_MISC_LEN , 24 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_LEN ); REG64_FLD( PU_NPU_CTL_DA_ADDR_MISC_LENGTH , 24 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_LENGTH ); REG64_FLD( PU_NPU_CTL_DA_ADDR_MISC_LENGTH_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_LENGTH_LEN ); REG64_FLD( PU_NPU_CTL_DA_ADDR_MISC_RSVD , 26 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_RSVD ); REG64_FLD( PU_NPU_CTL_DA_ADDR_MISC_RSVD_LEN , 38 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_RSVD_LEN ); REG64_FLD( PEC_DBG_CBS_CC_RESET_EP , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESET_EP ); REG64_FLD( PEC_DBG_CBS_CC_OPCG_IP , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_OPCG_IP ); REG64_FLD( PEC_DBG_CBS_CC_VITL_CLKOFF , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_VITL_CLKOFF ); REG64_FLD( PEC_DBG_CBS_CC_TEST_ENABLE , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TEST_ENABLE ); REG64_FLD( PEC_DBG_CBS_CC_REQ , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_REQ ); REG64_FLD( PEC_DBG_CBS_CC_CMD , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CMD ); REG64_FLD( PEC_DBG_CBS_CC_CMD_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CMD_LEN ); REG64_FLD( PEC_DBG_CBS_CC_STATE , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATE ); REG64_FLD( PEC_DBG_CBS_CC_STATE_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STATE_LEN ); REG64_FLD( PEC_DBG_CBS_CC_SECURITY_DEBUG_MODE , 13 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SECURITY_DEBUG_MODE ); REG64_FLD( PEC_DBG_CBS_CC_PROTOCOL_ERROR , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PROTOCOL_ERROR ); REG64_FLD( PEC_DBG_CBS_CC_PCB_IDLE , 15 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PCB_IDLE ); REG64_FLD( PEC_DBG_CBS_CC_CURRENT_OPCG_MODE , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CURRENT_OPCG_MODE ); REG64_FLD( PEC_DBG_CBS_CC_CURRENT_OPCG_MODE_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CURRENT_OPCG_MODE_LEN ); REG64_FLD( PEC_DBG_CBS_CC_LAST_OPCG_MODE , 20 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_LAST_OPCG_MODE ); REG64_FLD( PEC_DBG_CBS_CC_LAST_OPCG_MODE_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_LAST_OPCG_MODE_LEN ); REG64_FLD( PEC_DBG_CBS_CC_PCB_ERROR , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PCB_ERROR ); REG64_FLD( PEC_DBG_CBS_CC_PARITY_ERROR , 25 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PARITY_ERROR ); REG64_FLD( PEC_DBG_CBS_CC_ERROR , 26 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ERROR ); REG64_FLD( PEC_DBG_CBS_CC_CHIPLET_IS_ALIGNED , 27 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CHIPLET_IS_ALIGNED ); REG64_FLD( PEC_DBG_CBS_CC_PCB_REQUEST_SINCE_RESET , 28 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PCB_REQUEST_SINCE_RESET ); REG64_FLD( PEC_DBG_CBS_CC_PARANOIA_TEST_ENABLE_CHANGE , 29 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PARANOIA_TEST_ENABLE_CHANGE ); REG64_FLD( PEC_DBG_CBS_CC_PARANOIA_VITL_CLKOFF_CHANGE , 30 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PARANOIA_VITL_CLKOFF_CHANGE ); REG64_FLD( PEC_DBG_CBS_CC_TP_TPFSI_ACK , 31 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TP_TPFSI_ACK ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_UNUSED , 36 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_UNUSED_2 , 43 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_UNUSED_2 ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_UNUSED_2_LEN ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_UNUSED , 36 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_UNUSED_2 , 43 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_UNUSED_2 ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_UNUSED_2_LEN ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_UNUSED , 36 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_UNUSED_2 , 43 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_UNUSED_2 ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_UNUSED_2_LEN ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_UNUSED , 36 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_UNUSED_2 , 43 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED_2 ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED_2_LEN ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( PEC_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_UNUSED , 36 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_UNUSED_2 , 43 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_UNUSED_2 ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_UNUSED_2_LEN ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TO_CMP_LT ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TO_CMP_LT_LEN ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TO_CMP_LT ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TO_CMP_LT_LEN ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TO_CMP_LT ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TO_CMP_LT_LEN ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A ); REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( PEC_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); REG64_FLD( PEC_DBG_INST1_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TO_CMP_LT ); REG64_FLD( PEC_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TO_CMP_LT_LEN ); REG64_FLD( PEC_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TO_CMP_LT ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TO_CMP_LT_LEN ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT ); REG64_FLD( PU_N3_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT_LEN ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT ); REG64_FLD( PU_N1_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT_LEN ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT ); REG64_FLD( PU_N2_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT_LEN ); REG64_FLD( PEC_DBG_INST1_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT ); REG64_FLD( PEC_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT_LEN ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT ); REG64_FLD( PU_N0_DBG_INST1_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT_LEN ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_UNUSED , 36 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_UNUSED_2 , 43 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_UNUSED_2 ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_UNUSED_2_LEN ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_UNUSED , 36 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_UNUSED_2 , 43 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_UNUSED_2 ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_UNUSED_2_LEN ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_UNUSED , 36 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_UNUSED_2 , 43 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_UNUSED_2 ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_UNUSED_2_LEN ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_UNUSED , 36 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_UNUSED_2 , 43 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED_2 ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED_2_LEN ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( PEC_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_A , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_A_LEN , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND1_SEL_A_LEN ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_B , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND1_SEL_B_LEN , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND1_SEL_B_LEN ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_A , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_A_LEN , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND2_SEL_A_LEN ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_B , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND2_SEL_B_LEN , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND2_SEL_B_LEN ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C1_INAROW_MODE , 32 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C1_INAROW_MODE ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE1 , 33 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE1 ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE1 , 34 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE1 ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE1 , 35 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE1 ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_UNUSED , 36 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_UNUSED_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C2_INAROW_MODE , 39 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C2_INAROW_MODE ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_AND_TRIGGER_MODE2 , 40 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_AND_TRIGGER_MODE2 ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_NOT_TRIGGER_MODE2 , 41 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_NOT_TRIGGER_MODE2 ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_EDGE_TRIGGER_MODE2 , 42 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_EDGE_TRIGGER_MODE2 ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_UNUSED_2 , 43 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_UNUSED_2 ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_UNUSED_2_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_UNUSED_2_LEN ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_COND3_ENABLE_RESET , 46 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_COND3_ENABLE_RESET ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_EXACT_TO_MODE , 47 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_EXACT_TO_MODE ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_RESET_C2TIMER_ON_C1 , 48 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RESET_C2TIMER_ON_C1 ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_RESET_C3_ON_C0 , 49 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RESET_C3_ON_C0 ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_SLOW_TO_MODE , 50 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_SLOW_TO_MODE ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_EXACT_RESET_C3_ON_TO , 51 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_EXACT_RESET_C3_ON_TO ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C1_COUNT_LT , 52 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C1_COUNT_LT_LEN , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C1_COUNT_LT_LEN ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C2_COUNT_LT , 56 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_C2_COUNT_LT_LEN , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_C2_COUNT_LT_LEN ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_RESET_C3_SELECT , 60 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_1_RESET_C3_SELECT_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RESET_C3_SELECT_LEN ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TO_CMP_LT ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TO_CMP_LT_LEN ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TO_CMP_LT ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TO_CMP_LT_LEN ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TO_CMP_LT ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TO_CMP_LT_LEN ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A ); REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( PEC_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); REG64_FLD( PEC_DBG_INST2_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TO_CMP_LT ); REG64_FLD( PEC_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TO_CMP_LT_LEN ); REG64_FLD( PEC_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_A_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_A_LEN ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_1_B_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_1_B_LEN ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A , 10 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_A_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_A_LEN ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B , 15 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_CROSS_COUPLE_SELECT_B_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CROSS_COUPLE_SELECT_B_LEN ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_TO_CMP_LT , 20 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TO_CMP_LT ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_TO_CMP_LT_LEN , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TO_CMP_LT_LEN ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_2_FORCE_TEST_MODE , 44 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_FORCE_TEST_MODE ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT ); REG64_FLD( PU_N3_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT_LEN ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT ); REG64_FLD( PU_N1_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT_LEN ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT ); REG64_FLD( PU_N2_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT_LEN ); REG64_FLD( PEC_DBG_INST2_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT ); REG64_FLD( PEC_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT_LEN ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_3_SP_COUNT_LT , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT ); REG64_FLD( PU_N0_DBG_INST2_COND_REG_3_SP_COUNT_LT_LEN , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_SP_COUNT_LT_LEN ); REG64_FLD( PU_N3_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( PU_N3_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); REG64_FLD( PU_N3_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); REG64_FLD( PU_N3_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); REG64_FLD( PU_N3_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( PU_N3_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_STOP_ON_RECOV_ERR_SELECTION ); REG64_FLD( PU_N3_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( PU_N3_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); REG64_FLD( PU_N1_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( PU_N1_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); REG64_FLD( PU_N1_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); REG64_FLD( PU_N1_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); REG64_FLD( PU_N1_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( PU_N1_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_STOP_ON_RECOV_ERR_SELECTION ); REG64_FLD( PU_N1_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( PU_N1_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); REG64_FLD( PU_N2_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( PU_N2_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); REG64_FLD( PU_N2_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); REG64_FLD( PU_N2_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); REG64_FLD( PU_N2_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( PU_N2_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_STOP_ON_RECOV_ERR_SELECTION ); REG64_FLD( PU_N2_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( PU_N2_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); REG64_FLD( PEC_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( PEC_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); REG64_FLD( PEC_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); REG64_FLD( PEC_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); REG64_FLD( PEC_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( PEC_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STOP_ON_RECOV_ERR_SELECTION ); REG64_FLD( PEC_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( PEC_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); REG64_FLD( PU_N0_DBG_MODE_REG_GLB_BRCST , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_GLB_BRCST ); REG64_FLD( PU_N0_DBG_MODE_REG_GLB_BRCST_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_GLB_BRCST_LEN ); REG64_FLD( PU_N0_DBG_MODE_REG_TRACE_SEL , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); REG64_FLD( PU_N0_DBG_MODE_REG_TRIG_SEL , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRIG_SEL ); REG64_FLD( PU_N0_DBG_MODE_REG_STOP_ON_XSTOP_SELECTION , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_STOP_ON_XSTOP_SELECTION ); REG64_FLD( PU_N0_DBG_MODE_REG_STOP_ON_RECOV_ERR_SELECTION , 9 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_STOP_ON_RECOV_ERR_SELECTION ); REG64_FLD( PU_N0_DBG_MODE_REG_STOP_ON_SPATTN_SELECTION , 10 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_STOP_ON_SPATTN_SELECTION ); REG64_FLD( PU_N0_DBG_MODE_REG_FREEZE_SEL , 11 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_FREEZE_SEL ); REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE ); REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN ); REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_IMM_FREEZE , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_IMM_FREEZE ); REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_STOP_ON_ERR , 17 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_STOP_ON_ERR ); REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH , 18 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_BANK_ON_RUNN_MATCH ); REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_FORCE_TEST , 19 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_FORCE_TEST ); REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_ACCUM_HIST , 20 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ACCUM_HIST ); REG64_FLD( PU_N3_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ , 21 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_FRZ_COUNT_ON_FRZ ); REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE ); REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN ); REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_IMM_FREEZE , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_IMM_FREEZE ); REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_STOP_ON_ERR , 17 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_STOP_ON_ERR ); REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH , 18 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_BANK_ON_RUNN_MATCH ); REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_FORCE_TEST , 19 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_FORCE_TEST ); REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_ACCUM_HIST , 20 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ACCUM_HIST ); REG64_FLD( PU_N1_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ , 21 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_FRZ_COUNT_ON_FRZ ); REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE ); REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN ); REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_IMM_FREEZE , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_IMM_FREEZE ); REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_STOP_ON_ERR , 17 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_STOP_ON_ERR ); REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH , 18 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_BANK_ON_RUNN_MATCH ); REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_FORCE_TEST , 19 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_FORCE_TEST ); REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_ACCUM_HIST , 20 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ACCUM_HIST ); REG64_FLD( PU_N2_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ , 21 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_FRZ_COUNT_ON_FRZ ); REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE ); REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN ); REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_IMM_FREEZE , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IMM_FREEZE ); REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_STOP_ON_ERR , 17 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STOP_ON_ERR ); REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH , 18 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_BANK_ON_RUNN_MATCH ); REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_FORCE_TEST , 19 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FORCE_TEST ); REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_ACCUM_HIST , 20 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACCUM_HIST ); REG64_FLD( PEC_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ , 21 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FRZ_COUNT_ON_FRZ ); REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE ); REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_RUNN_COUNT_COMPARE_VALUE_LEN , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RUNN_COUNT_COMPARE_VALUE_LEN ); REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_IMM_FREEZE , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_IMM_FREEZE ); REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_STOP_ON_ERR , 17 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_STOP_ON_ERR ); REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_BANK_ON_RUNN_MATCH , 18 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_BANK_ON_RUNN_MATCH ); REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_FORCE_TEST , 19 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_FORCE_TEST ); REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_ACCUM_HIST , 20 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ACCUM_HIST ); REG64_FLD( PU_N0_DBG_TRACE_MODE_REG_2_FRZ_COUNT_ON_FRZ , 21 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_FRZ_COUNT_ON_FRZ ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_COND3_ENABLE , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_COND3_ENABLE ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_COND3_ENABLE , 1 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_COND3_ENABLE ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST3_COND3_ENABLE , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST3_COND3_ENABLE ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST4_COND3_ENABLE , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST4_COND3_ENABLE ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_SLOW_LFSR_MODE ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_SLOW_LFSR_MODE ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE , 6 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST3_SLOW_LFSR_MODE ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST4_SLOW_LFSR_MODE ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_TRIG_SEL ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL , 10 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_TRIG_SEL ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL , 12 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL , 14 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_TRIG_SEL ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_TRIG_SEL ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL , 18 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP , 32 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_EXT_TRIG_ON_STOP ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE , 33 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_EXT_TRIG_ON_FREEZE ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL , 34 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CORE_RAS0_TRIG_SEL ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CORE_RAS0_TRIG_SEL_LEN ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL , 39 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CORE_RAS1_TRIG_SEL ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_CORE_RAS1_TRIG_SEL_LEN ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_PC_TP_TRIG_SEL , 44 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_PC_TP_TRIG_SEL ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_PC_TP_TRIG_SEL_LEN ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_ARM_SEL , 46 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ARM_SEL ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_ARM_SEL_LEN , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ARM_SEL_LEN ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL , 50 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRIG0_LEVEL_SEL ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRIG0_LEVEL_SEL_LEN ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL , 54 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRIG1_LEVEL_SEL ); REG64_FLD( PU_N3_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRIG1_LEVEL_SEL_LEN ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_COND3_ENABLE , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_COND3_ENABLE ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_COND3_ENABLE , 1 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_COND3_ENABLE ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST3_COND3_ENABLE , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST3_COND3_ENABLE ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST4_COND3_ENABLE , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST4_COND3_ENABLE ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_SLOW_LFSR_MODE ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_SLOW_LFSR_MODE ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE , 6 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST3_SLOW_LFSR_MODE ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST4_SLOW_LFSR_MODE ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_TRIG_SEL ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL , 10 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_TRIG_SEL ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL , 12 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL , 14 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_TRIG_SEL ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_TRIG_SEL ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL , 18 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP , 32 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_EXT_TRIG_ON_STOP ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE , 33 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_EXT_TRIG_ON_FREEZE ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL , 34 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CORE_RAS0_TRIG_SEL ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CORE_RAS0_TRIG_SEL_LEN ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL , 39 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CORE_RAS1_TRIG_SEL ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_CORE_RAS1_TRIG_SEL_LEN ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_PC_TP_TRIG_SEL , 44 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_PC_TP_TRIG_SEL ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_PC_TP_TRIG_SEL_LEN ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_ARM_SEL , 46 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ARM_SEL ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_ARM_SEL_LEN , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ARM_SEL_LEN ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL , 50 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRIG0_LEVEL_SEL ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRIG0_LEVEL_SEL_LEN ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL , 54 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRIG1_LEVEL_SEL ); REG64_FLD( PU_N1_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRIG1_LEVEL_SEL_LEN ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_COND3_ENABLE , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_COND3_ENABLE ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_COND3_ENABLE , 1 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_COND3_ENABLE ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST3_COND3_ENABLE , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST3_COND3_ENABLE ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST4_COND3_ENABLE , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST4_COND3_ENABLE ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_SLOW_LFSR_MODE ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_SLOW_LFSR_MODE ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE , 6 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST3_SLOW_LFSR_MODE ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST4_SLOW_LFSR_MODE ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_TRIG_SEL ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL , 10 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_TRIG_SEL ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL , 12 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL , 14 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_TRIG_SEL ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_TRIG_SEL ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL , 18 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP , 32 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_EXT_TRIG_ON_STOP ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE , 33 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_EXT_TRIG_ON_FREEZE ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL , 34 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CORE_RAS0_TRIG_SEL ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CORE_RAS0_TRIG_SEL_LEN ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL , 39 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CORE_RAS1_TRIG_SEL ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_CORE_RAS1_TRIG_SEL_LEN ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_PC_TP_TRIG_SEL , 44 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_PC_TP_TRIG_SEL ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_PC_TP_TRIG_SEL_LEN ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_ARM_SEL , 46 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ARM_SEL ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_ARM_SEL_LEN , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ARM_SEL_LEN ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL , 50 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRIG0_LEVEL_SEL ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRIG0_LEVEL_SEL_LEN ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL , 54 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRIG1_LEVEL_SEL ); REG64_FLD( PU_N2_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRIG1_LEVEL_SEL_LEN ); REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_COND3_ENABLE , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_COND3_ENABLE ); REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_COND3_ENABLE , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_COND3_ENABLE ); REG64_FLD( PEC_DBG_TRACE_REG_0_INST3_COND3_ENABLE , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST3_COND3_ENABLE ); REG64_FLD( PEC_DBG_TRACE_REG_0_INST4_COND3_ENABLE , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST4_COND3_ENABLE ); REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_SLOW_LFSR_MODE ); REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_SLOW_LFSR_MODE ); REG64_FLD( PEC_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST3_SLOW_LFSR_MODE ); REG64_FLD( PEC_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST4_SLOW_LFSR_MODE ); REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_TRIG_SEL ); REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN ); REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_TRIG_SEL ); REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN ); REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL ); REG64_FLD( PEC_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN ); REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_TRIG_SEL ); REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN ); REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_TRIG_SEL ); REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN ); REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL , 18 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL ); REG64_FLD( PEC_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN ); REG64_FLD( PEC_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP , 32 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_EXT_TRIG_ON_STOP ); REG64_FLD( PEC_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE , 33 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_EXT_TRIG_ON_FREEZE ); REG64_FLD( PEC_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL , 34 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CORE_RAS0_TRIG_SEL ); REG64_FLD( PEC_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CORE_RAS0_TRIG_SEL_LEN ); REG64_FLD( PEC_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL , 39 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CORE_RAS1_TRIG_SEL ); REG64_FLD( PEC_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CORE_RAS1_TRIG_SEL_LEN ); REG64_FLD( PEC_DBG_TRACE_REG_0_PC_TP_TRIG_SEL , 44 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PC_TP_TRIG_SEL ); REG64_FLD( PEC_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PC_TP_TRIG_SEL_LEN ); REG64_FLD( PEC_DBG_TRACE_REG_0_ARM_SEL , 46 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ARM_SEL ); REG64_FLD( PEC_DBG_TRACE_REG_0_ARM_SEL_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ARM_SEL_LEN ); REG64_FLD( PEC_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL , 50 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIG0_LEVEL_SEL ); REG64_FLD( PEC_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIG0_LEVEL_SEL_LEN ); REG64_FLD( PEC_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL , 54 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIG1_LEVEL_SEL ); REG64_FLD( PEC_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIG1_LEVEL_SEL_LEN ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_COND3_ENABLE , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_COND3_ENABLE ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_COND3_ENABLE , 1 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_COND3_ENABLE ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST3_COND3_ENABLE , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST3_COND3_ENABLE ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST4_COND3_ENABLE , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST4_COND3_ENABLE ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_SLOW_LFSR_MODE , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_SLOW_LFSR_MODE ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_SLOW_LFSR_MODE , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_SLOW_LFSR_MODE ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST3_SLOW_LFSR_MODE , 6 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST3_SLOW_LFSR_MODE ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST4_SLOW_LFSR_MODE , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST4_SLOW_LFSR_MODE ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_TRIG_SEL ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_TRIG_SEL_LEN ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL , 10 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_TRIG_SEL ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_TRIG_SEL_LEN ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL , 12 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST1_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_TRIG_SEL_LEN ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL , 14 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_TRIG_SEL ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_CONDITION1_TRIG_SEL_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_TRIG_SEL_LEN ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_TRIG_SEL ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_CONDITION2_TRIG_SEL_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_TRIG_SEL_LEN ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL , 18 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_INST2_C2_TIMEOUT_TRIG_SEL_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_TRIG_SEL_LEN ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_EXT_TRIG_ON_STOP , 32 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_EXT_TRIG_ON_STOP ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_EXT_TRIG_ON_FREEZE , 33 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_EXT_TRIG_ON_FREEZE ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL , 34 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CORE_RAS0_TRIG_SEL ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_CORE_RAS0_TRIG_SEL_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CORE_RAS0_TRIG_SEL_LEN ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL , 39 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CORE_RAS1_TRIG_SEL ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_CORE_RAS1_TRIG_SEL_LEN , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_CORE_RAS1_TRIG_SEL_LEN ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_PC_TP_TRIG_SEL , 44 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_PC_TP_TRIG_SEL ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_PC_TP_TRIG_SEL_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_PC_TP_TRIG_SEL_LEN ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_ARM_SEL , 46 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ARM_SEL ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_ARM_SEL_LEN , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ARM_SEL_LEN ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL , 50 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRIG0_LEVEL_SEL ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_TRIG0_LEVEL_SEL_LEN , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRIG0_LEVEL_SEL_LEN ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL , 54 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRIG1_LEVEL_SEL ); REG64_FLD( PU_N0_DBG_TRACE_REG_0_TRIG1_LEVEL_SEL_LEN , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRIG1_LEVEL_SEL_LEN ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_DO ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_DO_LEN ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_DO ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_DO_LEN ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_DO ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO , 6 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_DO ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_DO_LEN ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_DO ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_DO_LEN ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO , 10 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_DO ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_WAITN ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN , 25 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_WAITN ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN , 26 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN , 27 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_WAITN ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN , 28 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_WAITN ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN , 29 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK , 36 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_BANK ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK , 37 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_BANK ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK , 38 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK , 39 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_BANK ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK , 40 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_BANK ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK , 41 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT , 48 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_LT ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR , 51 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT , 52 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_LT ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN ); REG64_FLD( PU_N3_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_DO ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_DO_LEN ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_DO ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_DO_LEN ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_DO ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO , 6 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_DO ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_DO_LEN ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_DO ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_DO_LEN ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO , 10 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_DO ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_WAITN ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN , 25 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_WAITN ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN , 26 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN , 27 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_WAITN ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN , 28 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_WAITN ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN , 29 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK , 36 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_BANK ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK , 37 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_BANK ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK , 38 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK , 39 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_BANK ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK , 40 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_BANK ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK , 41 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT , 48 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_LT ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR , 51 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT , 52 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_LT ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN ); REG64_FLD( PU_N1_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_DO ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_DO_LEN ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_DO ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_DO_LEN ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_DO ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO , 6 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_DO ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_DO_LEN ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_DO ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_DO_LEN ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO , 10 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_DO ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_WAITN ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN , 25 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_WAITN ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN , 26 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN , 27 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_WAITN ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN , 28 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_WAITN ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN , 29 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK , 36 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_BANK ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK , 37 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_BANK ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK , 38 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK , 39 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_BANK ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK , 40 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_BANK ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK , 41 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT , 48 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_LT ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR , 51 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT , 52 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_LT ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN ); REG64_FLD( PU_N2_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_DO ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_DO_LEN ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_DO ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_DO_LEN ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_DO ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_DO ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_DO_LEN ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_DO ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_DO_LEN ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_DO ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_WAITN ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN , 25 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_WAITN ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN , 26 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN , 27 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_WAITN ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN , 28 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_WAITN ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN , 29 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK , 36 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_BANK ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK , 37 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_BANK ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK , 38 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK , 39 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_BANK ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK , 40 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_BANK ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK , 41 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT , 48 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_LT ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR , 51 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT , 52 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_LT ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN ); REG64_FLD( PEC_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_DO ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_DO_LEN ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_DO ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_DO_LEN ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_DO ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_DO_LEN ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO , 6 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_DO ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_DO_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_DO_LEN ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_DO ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_DO_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_DO_LEN ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO , 10 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_DO ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_DO_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_DO_LEN ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_WAITN , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_WAITN ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_WAITN , 25 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_WAITN ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_WAITN , 26 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_WAITN ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_WAITN , 27 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_WAITN ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_WAITN , 28 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_WAITN ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_WAITN , 29 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_WAITN ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION1_ACTION_BANK , 36 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION1_ACTION_BANK ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CONDITION2_ACTION_BANK , 37 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_CONDITION2_ACTION_BANK ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_C2_TIMEOUT_ACTION_BANK , 38 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_C2_TIMEOUT_ACTION_BANK ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION1_ACTION_BANK , 39 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION1_ACTION_BANK ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CONDITION2_ACTION_BANK , 40 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_CONDITION2_ACTION_BANK ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_C2_TIMEOUT_ACTION_BANK , 41 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_C2_TIMEOUT_ACTION_BANK ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT , 48 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_LT ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_LT_LEN ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST1_CHECKSTOP_MODE_SELECTOR , 51 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST1_CHECKSTOP_MODE_SELECTOR ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT , 52 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_LT ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_LT_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_LT_LEN ); REG64_FLD( PU_N0_DBG_TRACE_REG_1_INST2_CHECKSTOP_MODE_SELECTOR , 55 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_INST2_CHECKSTOP_MODE_SELECTOR ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD0_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD1 ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD1_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD2 ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD2_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD3 ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD3_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD4 ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD4_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD5 ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD5_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD6 ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD6_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD7 ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD7_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD8 ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD8_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD9 ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD9_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD10 ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD10_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD0_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD1 ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD1_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD2 ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD2_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD3 ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD3_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD4 ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD4_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD5 ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD5_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD6 ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD6_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD7 ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD7_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD8 ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD8_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD9 ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD9_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD10 ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD10_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD0_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD1 ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD1_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD2 ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD2_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD3 ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD3_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD4 ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD4_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD5 ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD5_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD6 ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD6_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD7 ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD7_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD8 ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD8_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD9 ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD9_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD10 ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD10_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD0_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD1 ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD1_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD2 ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD2_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD3 ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD3_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD4 ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD4_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD5 ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD5_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD6 ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD6_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD7 ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD7_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD8 ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD8_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD9 ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD9_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD10 ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD10_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD0_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD1 ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD1_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD2 ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD2_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD3 ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD3_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD4 ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD4_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD5 ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD5_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD6 ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD6_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD7 ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD7_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD8 ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD8_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD9 ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD9_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD10 ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD10_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( NV_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( NV_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD0_LEN ); REG64_FLD( NV_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD1 ); REG64_FLD( NV_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD1_LEN ); REG64_FLD( NV_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD2 ); REG64_FLD( NV_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD2_LEN ); REG64_FLD( NV_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD3 ); REG64_FLD( NV_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD3_LEN ); REG64_FLD( NV_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD4 ); REG64_FLD( NV_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD4_LEN ); REG64_FLD( NV_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD5 ); REG64_FLD( NV_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD5_LEN ); REG64_FLD( NV_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD6 ); REG64_FLD( NV_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD6_LEN ); REG64_FLD( NV_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD7 ); REG64_FLD( NV_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD7_LEN ); REG64_FLD( NV_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD8 ); REG64_FLD( NV_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD8_LEN ); REG64_FLD( NV_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD9 ); REG64_FLD( NV_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD9_LEN ); REG64_FLD( NV_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD10 ); REG64_FLD( NV_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD10_LEN ); REG64_FLD( NV_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( NV_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( NV_DEBUG0_CONFIG_ACT , 63 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD0_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD1 ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD1_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD2 ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD2_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD3 ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD3_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD4 ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD4_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD5 ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD5_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD6 ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD6_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD7 ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD7_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD8 ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD8_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD9 ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD9_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD10 ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD10_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD0_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD1 ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD1_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD2 ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD2_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD3 ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD3_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD4 ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD4_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD5 ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD5_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD6 ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD6_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD7 ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD7_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD8 ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD8_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD9 ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD9_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD10 ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD10_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD0_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD1 ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD1_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD2 ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD2_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD3 ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD3_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD4 ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD4_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD5 ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD5_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD6 ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD6_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD7 ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD7_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD8 ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD8_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD9 ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD9_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD10 ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD10_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD0_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD1 , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD1 ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD1_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD2 , 10 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD2 ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD2_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD3 , 15 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD3 ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD3_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD4 , 20 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD4 ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD4_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD5 , 25 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD5 ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD5_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD6 , 30 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD6 ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD6_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD7 , 35 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD7 ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD7_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD8 , 40 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD8 ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD8_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD9 , 45 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD9 ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD9_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD10 , 50 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD10 ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD10_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG0_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD0_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD1 ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD1_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD2 ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD2_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD3 ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD3_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD4 ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD4_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD5 ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD5_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD6 ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD6_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD7 ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD7_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD8 ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD8_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD9 ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD9_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD10 ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_POD10_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL0_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD0_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD1 ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD1_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD2 ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD2_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD3 ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD3_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD4 ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD4_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD5 ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD5_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD6 ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD6_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD7 ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD7_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD8 ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD8_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD9 ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD9_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD10 ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_POD10_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL1_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD0_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD1 ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD1_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD2 ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD2_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD3 ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD3_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD4 ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD4_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD5 ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD5_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD6 ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD6_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD7 ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD7_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD8 ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD8_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD9 ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD9_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD10 ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_POD10_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU_SM2_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD0_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD1 ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD1_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD2 ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD2_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD3 ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD3_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD4 ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD4_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD5 ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD5_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD6 ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD6_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD7 ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD7_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD8 ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD8_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD9 ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD9_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD10 ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_POD10_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_CTL_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD0_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD1 ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD1_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD2 ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD2_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD3 ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD3_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD4 ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD4_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD5 ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD5_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD6 ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD6_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD7 ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD7_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD8 ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD8_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD9 ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD9_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD10 ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_POD10_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_CTL_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( NV_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( NV_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD0_LEN ); REG64_FLD( NV_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD1 ); REG64_FLD( NV_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD1_LEN ); REG64_FLD( NV_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD2 ); REG64_FLD( NV_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD2_LEN ); REG64_FLD( NV_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD3 ); REG64_FLD( NV_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD3_LEN ); REG64_FLD( NV_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD4 ); REG64_FLD( NV_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD4_LEN ); REG64_FLD( NV_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD5 ); REG64_FLD( NV_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD5_LEN ); REG64_FLD( NV_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD6 ); REG64_FLD( NV_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD6_LEN ); REG64_FLD( NV_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD7 ); REG64_FLD( NV_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD7_LEN ); REG64_FLD( NV_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD8 ); REG64_FLD( NV_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD8_LEN ); REG64_FLD( NV_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD9 ); REG64_FLD( NV_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD9_LEN ); REG64_FLD( NV_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD10 ); REG64_FLD( NV_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_POD10_LEN ); REG64_FLD( NV_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( NV_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( NV_DEBUG1_CONFIG_ACT , 63 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD0_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD1 ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD1_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD2 ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD2_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD3 ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD3_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD4 ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD4_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD5 ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD5_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD6 ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD6_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD7 ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD7_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD8 ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD8_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD9 ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD9_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD10 ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_POD10_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_CTL_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD0_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD1 ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD1_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD2 ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD2_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD3 ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD3_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD4 ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD4_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD5 ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD5_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD6 ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD6_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD7 ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD7_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD8 ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD8_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD9 ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD9_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD10 ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_POD10_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_DAT_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD0_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD1 ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD1_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD2 ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD2_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD3 ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD3_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD4 ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD4_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD5 ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD5_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD6 ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD6_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD7 ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD7_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD8 ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD8_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD9 ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD9_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD10 ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_POD10_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_DAT_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD0 , 0 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD0 ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD0_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD0_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD1 , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD1 ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD1_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD1_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD2 , 10 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD2 ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD2_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD2_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD3 , 15 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD3 ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD3_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD3_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD4 , 20 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD4 ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD4_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD4_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD5 , 25 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD5 ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD5_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD5_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD6 , 30 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD6 ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD6_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD6_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD7 , 35 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD7 ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD7_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD7_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD8 , 40 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD8 ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD8_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD8_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD9 , 45 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD9 ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD9_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD9_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD10 , 50 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD10 ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_POD10_LEN , 5 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_POD10_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_RESERVED1 , 55 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_RESERVED1_LEN , 8 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_DAT_DEBUG1_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE0 , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE0 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE0_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE0_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE1 , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE1 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE1_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE1_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE2 , 4 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE2 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE2_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE2_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE3 , 6 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE3 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE3_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE3_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE4 , 8 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE4 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE4_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE4_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE5 , 10 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE5 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE5_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE5_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE6 , 12 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE6 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE6_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE6_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE7 , 14 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE7 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE7_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE7_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE8 , 16 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE8 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE8_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE8_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE9 , 18 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE9 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE9_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE9_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE10 , 20 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE10 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS0BYTE10_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS0BYTE10_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE0 , 22 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE0 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE0_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE0_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE1 , 24 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE1 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE1_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE1_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE2 , 26 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE2 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE2_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE2_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE3 , 28 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE3 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE3_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE3_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE4 , 30 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE4 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE4_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE4_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE5 , 32 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE5 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE5_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE5_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE6 , 34 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE6 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE6_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE6_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE7 , 36 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE7 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE7_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE7_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE8 , 38 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE8 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE8_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE8_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE9 , 40 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE9 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE9_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE9_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE10 , 42 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE10 ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_MISC_BUS1BYTE10_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_BUS1BYTE10_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_RESERVED , 44 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_RESERVED_LEN , 19 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU_CTL_DEBUG_CONFIG_ACT , 63 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( CAPP_DEBUG_CONTROL_BLOCK_MUX_PORT_SEL , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BLOCK_MUX_PORT_SEL ); REG64_FLD( CAPP_DEBUG_CONTROL_BLOCK_MUX_PORT_SEL_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BLOCK_MUX_PORT_SEL_LEN ); REG64_FLD( CAPP_DEBUG_CONTROL_BLOCK_SEL , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BLOCK_SEL ); REG64_FLD( CAPP_DEBUG_CONTROL_BLOCK_SEL_LEN , 8 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BLOCK_SEL_LEN ); REG64_FLD( CAPP_DFSUOP1_WORD , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_WORD ); REG64_FLD( CAPP_DFSUOP1_WORD_LEN , 56 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_WORD_LEN ); REG64_FLD( PU_DISABLE_FORCE_PFET_OFF_REG , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_REG ); REG64_FLD( PU_DISABLE_FORCE_PFET_OFF_REG_LEN , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_REG_LEN ); REG64_FLD( PU_DISABLE_FORCE_PFET_OFF_RESERVED , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_DISABLE_FORCE_PFET_OFF_RESERVED_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU_SM1_DMA_SYNC_START_READ , 0 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_START_READ ); REG64_FLD( PU_NPU_SM1_DMA_SYNC_READ_COMPLETE , 1 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_READ_COMPLETE ); REG64_FLD( PU_NPU_SM1_DMA_SYNC_START_WRITE , 2 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_START_WRITE ); REG64_FLD( PU_NPU_SM1_DMA_SYNC_WRITE_COMPLETE , 3 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_WRITE_COMPLETE ); REG64_FLD( PU_DMA_UP_ADDR_BASE_UPPER_BITS , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_BASE_UPPER_BITS ); REG64_FLD( PU_DMA_UP_ADDR_BASE_UPPER_BITS_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_BASE_UPPER_BITS_LEN ); REG64_FLD( PU_DMA_UP_ADDR_ESCAPE_ADDRESS , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_ESCAPE_ADDRESS ); REG64_FLD( PU_DMA_UP_ADDR_ESCAPE_ADDRESS_LEN , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_ESCAPE_ADDRESS_LEN ); REG64_FLD( PU_DMA_VAS_MMIO_BAR_BAR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BAR ); REG64_FLD( PU_DMA_VAS_MMIO_BAR_BAR_LEN , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BAR_LEN ); REG64_FLD( PEC_DRPPRICTL_REG_PE_DROPPRIORITYMASK , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DROPPRIORITYMASK ); REG64_FLD( PEC_DRPPRICTL_REG_PE_DROPPRIORITYMASK_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DROPPRIORITYMASK_LEN ); REG64_FLD( PEC_DRPPRICTL_REG_PE_ENABLE_CTAG_DROP_PRIORITY , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_ENABLE_CTAG_DROP_PRIORITY ); REG64_FLD( PEC_DRPPRICTL_REG_PE_ENABLE_IO_CMD_PACING , 7 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_ENABLE_IO_CMD_PACING ); REG64_FLD( PEC_DRPPRICTL_REG_PE_DROPPACECOUNT , 8 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DROPPACECOUNT ); REG64_FLD( PEC_DRPPRICTL_REG_PE_DROPPACECOUNT_LEN , 9 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DROPPACECOUNT_LEN ); REG64_FLD( PEC_DRPPRICTL_REG_PE_DROPPACEINC , 17 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DROPPACEINC ); REG64_FLD( PEC_DRPPRICTL_REG_PE_DROPPACEINC_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DROPPACEINC_LEN ); REG64_FLD( PEC_DRPPRICTL_REG_PE_RTYDROPDIVIDER , 23 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_RTYDROPDIVIDER ); REG64_FLD( PEC_DRPPRICTL_REG_PE_RTYDROPDIVIDER_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_RTYDROPDIVIDER_LEN ); REG64_FLD( PEC_DTS_RESULT0_0_RESULT , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_0_RESULT ); REG64_FLD( PEC_DTS_RESULT0_0_RESULT_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_0_RESULT_LEN ); REG64_FLD( PEC_DTS_RESULT0_1_RESULT , 16 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_1_RESULT ); REG64_FLD( PEC_DTS_RESULT0_1_RESULT_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_1_RESULT_LEN ); REG64_FLD( PEC_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_TIMESTAMP_COUNTER_VALUE ); REG64_FLD( PEC_DTS_TRC_RESULT_TIMESTAMP_COUNTER_VALUE_LEN , 44 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_TIMESTAMP_COUNTER_VALUE_LEN ); REG64_FLD( PEC_DTS_TRC_RESULT_TIMESTAMP_COUNTER_OVERFLOW_ERR , 44 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_TIMESTAMP_COUNTER_OVERFLOW_ERR ); REG64_FLD( PEC_DTS_TRC_RESULT_1 , 48 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_1 ); REG64_FLD( PEC_DTS_TRC_RESULT_1_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_1_LEN ); REG64_FLD( PU_NPU0_ECC_CONFIG_PBTX_AMO_IGNORE_XUE , 0 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_PBTX_AMO_IGNORE_XUE ); REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_BR_PERR , 1 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_SUE_DIS_BR_PERR ); REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_IR_PERR , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_SUE_DIS_IR_PERR ); REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_OR_PERR , 3 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_SUE_DIS_OR_PERR ); REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_PT , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_CORR_DIS_PT ); REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_PR , 5 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_CORR_DIS_PR ); REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_BR , 6 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_CORR_DIS_BR ); REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_IR , 7 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_CORR_DIS_IR ); REG64_FLD( PU_NPU0_ECC_CONFIG_CORR_DIS_OR , 8 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_CORR_DIS_OR ); REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_PT , 9 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_SUE_DIS_PT ); REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_PR , 10 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_SUE_DIS_PR ); REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_BR , 11 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_SUE_DIS_BR ); REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_IR , 12 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_SUE_DIS_IR ); REG64_FLD( PU_NPU0_ECC_CONFIG_SUE_DIS_OR , 13 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_SUE_DIS_OR ); REG64_FLD( PU_NPU0_ECC_CONFIG_RESERVED , 14 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU0_ECC_CONFIG_RESERVED_LEN , 18 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU1_ECC_CONFIG_PBTX_AMO_IGNORE_XUE , 0 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_PBTX_AMO_IGNORE_XUE ); REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_BR_PERR , 1 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_SUE_DIS_BR_PERR ); REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_IR_PERR , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_SUE_DIS_IR_PERR ); REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_OR_PERR , 3 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_SUE_DIS_OR_PERR ); REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_PT , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_CORR_DIS_PT ); REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_PR , 5 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_CORR_DIS_PR ); REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_BR , 6 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_CORR_DIS_BR ); REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_IR , 7 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_CORR_DIS_IR ); REG64_FLD( PU_NPU1_ECC_CONFIG_CORR_DIS_OR , 8 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_CORR_DIS_OR ); REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_PT , 9 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_SUE_DIS_PT ); REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_PR , 10 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_SUE_DIS_PR ); REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_BR , 11 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_SUE_DIS_BR ); REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_IR , 12 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_SUE_DIS_IR ); REG64_FLD( PU_NPU1_ECC_CONFIG_SUE_DIS_OR , 13 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_SUE_DIS_OR ); REG64_FLD( PU_NPU1_ECC_CONFIG_RESERVED , 14 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU1_ECC_CONFIG_RESERVED_LEN , 18 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_ECC_CONFIG_PBTX_AMO_IGNORE_XUE , 0 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_PBTX_AMO_IGNORE_XUE ); REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_BR_PERR , 1 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_SUE_DIS_BR_PERR ); REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_IR_PERR , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_SUE_DIS_IR_PERR ); REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_OR_PERR , 3 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_SUE_DIS_OR_PERR ); REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_PT , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_CORR_DIS_PT ); REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_PR , 5 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_CORR_DIS_PR ); REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_BR , 6 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_CORR_DIS_BR ); REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_IR , 7 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_CORR_DIS_IR ); REG64_FLD( PU_NPU2_ECC_CONFIG_CORR_DIS_OR , 8 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_CORR_DIS_OR ); REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_PT , 9 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_SUE_DIS_PT ); REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_PR , 10 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_SUE_DIS_PR ); REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_BR , 11 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_SUE_DIS_BR ); REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_IR , 12 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_SUE_DIS_IR ); REG64_FLD( PU_NPU2_ECC_CONFIG_SUE_DIS_OR , 13 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_SUE_DIS_OR ); REG64_FLD( PU_NPU2_ECC_CONFIG_RESERVED , 14 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU2_ECC_CONFIG_RESERVED_LEN , 18 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART0_REGISTER_PART_0 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_0 ); REG64_FLD( PU_OTPROM0_ECID_PART0_REGISTER_PART_0_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_0_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART0_REGISTER_PART_0 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_0 ); REG64_FLD( PU_OTPROM1_ECID_PART0_REGISTER_PART_0_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_0_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART10_REGISTER_PART_10 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_10 ); REG64_FLD( PU_OTPROM0_ECID_PART10_REGISTER_PART_10_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_10_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART10_REGISTER_PART_10 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_10 ); REG64_FLD( PU_OTPROM1_ECID_PART10_REGISTER_PART_10_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_10_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART11_REGISTER_PART_11 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_11 ); REG64_FLD( PU_OTPROM0_ECID_PART11_REGISTER_PART_11_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_11_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART11_REGISTER_PART_11 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_11 ); REG64_FLD( PU_OTPROM1_ECID_PART11_REGISTER_PART_11_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_11_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART12_REGISTER_PART_12 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_12 ); REG64_FLD( PU_OTPROM0_ECID_PART12_REGISTER_PART_12_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_12_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART12_REGISTER_PART_12 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_12 ); REG64_FLD( PU_OTPROM1_ECID_PART12_REGISTER_PART_12_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_12_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART13_REGISTER_PART_13 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_13 ); REG64_FLD( PU_OTPROM0_ECID_PART13_REGISTER_PART_13_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_13_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART13_REGISTER_PART_13 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_13 ); REG64_FLD( PU_OTPROM1_ECID_PART13_REGISTER_PART_13_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_13_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART14_REGISTER_PART_14 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_14 ); REG64_FLD( PU_OTPROM0_ECID_PART14_REGISTER_PART_14_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_14_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART14_REGISTER_PART_14 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_14 ); REG64_FLD( PU_OTPROM1_ECID_PART14_REGISTER_PART_14_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_14_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART15_REGISTER_PART_15 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_15 ); REG64_FLD( PU_OTPROM0_ECID_PART15_REGISTER_PART_15_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_15_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART15_REGISTER_PART_15 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_15 ); REG64_FLD( PU_OTPROM1_ECID_PART15_REGISTER_PART_15_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_15_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART16_REGISTER_PART_16 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_16 ); REG64_FLD( PU_OTPROM0_ECID_PART16_REGISTER_PART_16_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_16_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART16_REGISTER_PART_16 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_16 ); REG64_FLD( PU_OTPROM1_ECID_PART16_REGISTER_PART_16_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_16_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART17_REGISTER_PART_17 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_17 ); REG64_FLD( PU_OTPROM0_ECID_PART17_REGISTER_PART_17_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_17_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART17_REGISTER_PART_17 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_17 ); REG64_FLD( PU_OTPROM1_ECID_PART17_REGISTER_PART_17_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_17_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART18_REGISTER_PART_18 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_18 ); REG64_FLD( PU_OTPROM0_ECID_PART18_REGISTER_PART_18_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_18_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART18_REGISTER_PART_18 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_18 ); REG64_FLD( PU_OTPROM1_ECID_PART18_REGISTER_PART_18_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_18_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART19_REGISTER_PART_19 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_19 ); REG64_FLD( PU_OTPROM0_ECID_PART19_REGISTER_PART_19_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_19_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART19_REGISTER_PART_19 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_19 ); REG64_FLD( PU_OTPROM1_ECID_PART19_REGISTER_PART_19_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_19_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART1_REGISTER_PART_1 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_1 ); REG64_FLD( PU_OTPROM0_ECID_PART1_REGISTER_PART_1_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_1_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART1_REGISTER_PART_1 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_1 ); REG64_FLD( PU_OTPROM1_ECID_PART1_REGISTER_PART_1_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_1_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART20_REGISTER_PART_20 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_20 ); REG64_FLD( PU_OTPROM0_ECID_PART20_REGISTER_PART_20_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_20_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART20_REGISTER_PART_20 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_20 ); REG64_FLD( PU_OTPROM1_ECID_PART20_REGISTER_PART_20_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_20_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART21_REGISTER_PART_21 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_21 ); REG64_FLD( PU_OTPROM0_ECID_PART21_REGISTER_PART_21_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_21_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART21_REGISTER_PART_21 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_21 ); REG64_FLD( PU_OTPROM1_ECID_PART21_REGISTER_PART_21_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_21_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART22_REGISTER_PART_22 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_22 ); REG64_FLD( PU_OTPROM0_ECID_PART22_REGISTER_PART_22_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_22_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART22_REGISTER_PART_22 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_22 ); REG64_FLD( PU_OTPROM1_ECID_PART22_REGISTER_PART_22_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_22_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART23_REGISTER_PART_23 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_23 ); REG64_FLD( PU_OTPROM0_ECID_PART23_REGISTER_PART_23_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_23_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART23_REGISTER_PART_23 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_23 ); REG64_FLD( PU_OTPROM1_ECID_PART23_REGISTER_PART_23_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_23_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART24_REGISTER_PART_24 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_24 ); REG64_FLD( PU_OTPROM0_ECID_PART24_REGISTER_PART_24_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_24_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART24_REGISTER_PART_24 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_24 ); REG64_FLD( PU_OTPROM1_ECID_PART24_REGISTER_PART_24_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_24_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART25_REGISTER_PART_25 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_25 ); REG64_FLD( PU_OTPROM0_ECID_PART25_REGISTER_PART_25_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_25_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART25_REGISTER_PART_25 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_25 ); REG64_FLD( PU_OTPROM1_ECID_PART25_REGISTER_PART_25_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_25_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART26_REGISTER_PART_26 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_26 ); REG64_FLD( PU_OTPROM0_ECID_PART26_REGISTER_PART_26_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_26_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART26_REGISTER_PART_26 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_26 ); REG64_FLD( PU_OTPROM1_ECID_PART26_REGISTER_PART_26_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_26_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART27_REGISTER_PART_27 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_27 ); REG64_FLD( PU_OTPROM0_ECID_PART27_REGISTER_PART_27_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_27_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART27_REGISTER_PART_27 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_27 ); REG64_FLD( PU_OTPROM1_ECID_PART27_REGISTER_PART_27_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_27_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART28_REGISTER_PART_28 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_28 ); REG64_FLD( PU_OTPROM0_ECID_PART28_REGISTER_PART_28_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_28_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART28_REGISTER_PART_28 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_28 ); REG64_FLD( PU_OTPROM1_ECID_PART28_REGISTER_PART_28_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_28_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART29_REGISTER_PART_29 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_29 ); REG64_FLD( PU_OTPROM0_ECID_PART29_REGISTER_PART_29_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_29_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART29_REGISTER_PART_29 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_29 ); REG64_FLD( PU_OTPROM1_ECID_PART29_REGISTER_PART_29_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_29_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART2_REGISTER_PART_2 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_2 ); REG64_FLD( PU_OTPROM0_ECID_PART2_REGISTER_PART_2_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_2_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART2_REGISTER_PART_2 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_2 ); REG64_FLD( PU_OTPROM1_ECID_PART2_REGISTER_PART_2_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_2_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART30_REGISTER_PART_30 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_30 ); REG64_FLD( PU_OTPROM0_ECID_PART30_REGISTER_PART_30_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_30_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART30_REGISTER_PART_30 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_30 ); REG64_FLD( PU_OTPROM1_ECID_PART30_REGISTER_PART_30_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_30_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART31_REGISTER_PART_31 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_31 ); REG64_FLD( PU_OTPROM0_ECID_PART31_REGISTER_PART_31_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_31_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART31_REGISTER_PART_31 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_31 ); REG64_FLD( PU_OTPROM1_ECID_PART31_REGISTER_PART_31_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_31_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART32_REGISTER_PART_32 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_32 ); REG64_FLD( PU_OTPROM0_ECID_PART32_REGISTER_PART_32_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_32_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART32_REGISTER_PART_32 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_32 ); REG64_FLD( PU_OTPROM1_ECID_PART32_REGISTER_PART_32_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_32_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART33_REGISTER_PART_33 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_33 ); REG64_FLD( PU_OTPROM0_ECID_PART33_REGISTER_PART_33_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_33_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART33_REGISTER_PART_33 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_33 ); REG64_FLD( PU_OTPROM1_ECID_PART33_REGISTER_PART_33_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_33_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART34_REGISTER_PART_34 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_34 ); REG64_FLD( PU_OTPROM0_ECID_PART34_REGISTER_PART_34_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_34_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART34_REGISTER_PART_34 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_34 ); REG64_FLD( PU_OTPROM1_ECID_PART34_REGISTER_PART_34_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_34_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART35_REGISTER_PART_35 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_35 ); REG64_FLD( PU_OTPROM0_ECID_PART35_REGISTER_PART_35_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_35_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART35_REGISTER_PART_35 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_35 ); REG64_FLD( PU_OTPROM1_ECID_PART35_REGISTER_PART_35_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_35_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART36_REGISTER_PART_36 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_36 ); REG64_FLD( PU_OTPROM0_ECID_PART36_REGISTER_PART_36_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_36_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART36_REGISTER_PART_36 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_36 ); REG64_FLD( PU_OTPROM1_ECID_PART36_REGISTER_PART_36_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_36_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART37_REGISTER_PART_37 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_37 ); REG64_FLD( PU_OTPROM0_ECID_PART37_REGISTER_PART_37_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_37_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART37_REGISTER_PART_37 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_37 ); REG64_FLD( PU_OTPROM1_ECID_PART37_REGISTER_PART_37_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_37_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART38_REGISTER_PART_38 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_38 ); REG64_FLD( PU_OTPROM0_ECID_PART38_REGISTER_PART_38_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_38_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART38_REGISTER_PART_38 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_38 ); REG64_FLD( PU_OTPROM1_ECID_PART38_REGISTER_PART_38_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_38_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART39_REGISTER_PART_39 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_39 ); REG64_FLD( PU_OTPROM0_ECID_PART39_REGISTER_PART_39_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_39_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART39_REGISTER_PART_39 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_39 ); REG64_FLD( PU_OTPROM1_ECID_PART39_REGISTER_PART_39_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_39_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART3_REGISTER_PART_3 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_3 ); REG64_FLD( PU_OTPROM0_ECID_PART3_REGISTER_PART_3_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_3_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART3_REGISTER_PART_3 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_3 ); REG64_FLD( PU_OTPROM1_ECID_PART3_REGISTER_PART_3_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_3_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART40_REGISTER_PART_40 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_40 ); REG64_FLD( PU_OTPROM0_ECID_PART40_REGISTER_PART_40_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_40_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART40_REGISTER_PART_40 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_40 ); REG64_FLD( PU_OTPROM1_ECID_PART40_REGISTER_PART_40_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_40_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART41_REGISTER_PART_41 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_41 ); REG64_FLD( PU_OTPROM0_ECID_PART41_REGISTER_PART_41_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_41_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART41_REGISTER_PART_41 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_41 ); REG64_FLD( PU_OTPROM1_ECID_PART41_REGISTER_PART_41_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_41_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART42_REGISTER_PART_42 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_42 ); REG64_FLD( PU_OTPROM0_ECID_PART42_REGISTER_PART_42_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_42_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART42_REGISTER_PART_42 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_42 ); REG64_FLD( PU_OTPROM1_ECID_PART42_REGISTER_PART_42_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_42_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART43_REGISTER_PART_43 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_43 ); REG64_FLD( PU_OTPROM0_ECID_PART43_REGISTER_PART_43_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_43_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART43_REGISTER_PART_43 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_43 ); REG64_FLD( PU_OTPROM1_ECID_PART43_REGISTER_PART_43_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_43_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART44_REGISTER_PART_44 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_44 ); REG64_FLD( PU_OTPROM0_ECID_PART44_REGISTER_PART_44_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_44_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART44_REGISTER_PART_44 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_44 ); REG64_FLD( PU_OTPROM1_ECID_PART44_REGISTER_PART_44_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_44_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART45_REGISTER_PART_45 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_45 ); REG64_FLD( PU_OTPROM0_ECID_PART45_REGISTER_PART_45_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_45_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART45_REGISTER_PART_45 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_45 ); REG64_FLD( PU_OTPROM1_ECID_PART45_REGISTER_PART_45_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_45_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART46_REGISTER_PART_46 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_46 ); REG64_FLD( PU_OTPROM0_ECID_PART46_REGISTER_PART_46_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_46_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART46_REGISTER_PART_46 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_46 ); REG64_FLD( PU_OTPROM1_ECID_PART46_REGISTER_PART_46_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_46_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART47_REGISTER_PART_47 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_47 ); REG64_FLD( PU_OTPROM0_ECID_PART47_REGISTER_PART_47_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_47_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART47_REGISTER_PART_47 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_47 ); REG64_FLD( PU_OTPROM1_ECID_PART47_REGISTER_PART_47_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_47_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART48_REGISTER_PART_48 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_48 ); REG64_FLD( PU_OTPROM0_ECID_PART48_REGISTER_PART_48_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_48_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART48_REGISTER_PART_48 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_48 ); REG64_FLD( PU_OTPROM1_ECID_PART48_REGISTER_PART_48_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_48_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART49_REGISTER_PART_49 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_49 ); REG64_FLD( PU_OTPROM0_ECID_PART49_REGISTER_PART_49_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_49_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART49_REGISTER_PART_49 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_49 ); REG64_FLD( PU_OTPROM1_ECID_PART49_REGISTER_PART_49_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_49_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART4_REGISTER_PART_4 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_4 ); REG64_FLD( PU_OTPROM0_ECID_PART4_REGISTER_PART_4_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_4_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART4_REGISTER_PART_4 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_4 ); REG64_FLD( PU_OTPROM1_ECID_PART4_REGISTER_PART_4_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_4_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART50_REGISTER_PART_50 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_50 ); REG64_FLD( PU_OTPROM0_ECID_PART50_REGISTER_PART_50_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_50_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART50_REGISTER_PART_50 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_50 ); REG64_FLD( PU_OTPROM1_ECID_PART50_REGISTER_PART_50_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_50_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART51_REGISTER_PART_51 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_51 ); REG64_FLD( PU_OTPROM0_ECID_PART51_REGISTER_PART_51_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_51_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART51_REGISTER_PART_51 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_51 ); REG64_FLD( PU_OTPROM1_ECID_PART51_REGISTER_PART_51_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_51_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART52_REGISTER_PART_52 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_52 ); REG64_FLD( PU_OTPROM0_ECID_PART52_REGISTER_PART_52_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_52_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART52_REGISTER_PART_52 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_52 ); REG64_FLD( PU_OTPROM1_ECID_PART52_REGISTER_PART_52_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_52_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART53_REGISTER_PART_53 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_53 ); REG64_FLD( PU_OTPROM0_ECID_PART53_REGISTER_PART_53_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_53_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART53_REGISTER_PART_53 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_53 ); REG64_FLD( PU_OTPROM1_ECID_PART53_REGISTER_PART_53_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_53_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART54_REGISTER_PART_54 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_54 ); REG64_FLD( PU_OTPROM0_ECID_PART54_REGISTER_PART_54_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_54_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART54_REGISTER_PART_54 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_54 ); REG64_FLD( PU_OTPROM1_ECID_PART54_REGISTER_PART_54_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_54_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART55_REGISTER_PART_55 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_55 ); REG64_FLD( PU_OTPROM0_ECID_PART55_REGISTER_PART_55_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_55_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART55_REGISTER_PART_55 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_55 ); REG64_FLD( PU_OTPROM1_ECID_PART55_REGISTER_PART_55_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_55_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART56_REGISTER_PART_56 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_56 ); REG64_FLD( PU_OTPROM0_ECID_PART56_REGISTER_PART_56_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_56_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART56_REGISTER_PART_56 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_56 ); REG64_FLD( PU_OTPROM1_ECID_PART56_REGISTER_PART_56_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_56_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART57_REGISTER_PART_57 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_57 ); REG64_FLD( PU_OTPROM0_ECID_PART57_REGISTER_PART_57_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_57_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART57_REGISTER_PART_57 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_57 ); REG64_FLD( PU_OTPROM1_ECID_PART57_REGISTER_PART_57_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_57_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART58_REGISTER_PART_58 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_58 ); REG64_FLD( PU_OTPROM0_ECID_PART58_REGISTER_PART_58_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_58_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART58_REGISTER_PART_58 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_58 ); REG64_FLD( PU_OTPROM1_ECID_PART58_REGISTER_PART_58_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_58_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART59_REGISTER_PART_59 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_59 ); REG64_FLD( PU_OTPROM0_ECID_PART59_REGISTER_PART_59_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_59_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART59_REGISTER_PART_59 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_59 ); REG64_FLD( PU_OTPROM1_ECID_PART59_REGISTER_PART_59_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_59_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART5_REGISTER_PART_5 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_5 ); REG64_FLD( PU_OTPROM0_ECID_PART5_REGISTER_PART_5_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_5_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART5_REGISTER_PART_5 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_5 ); REG64_FLD( PU_OTPROM1_ECID_PART5_REGISTER_PART_5_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_5_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART60_REGISTER_PART_60 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_60 ); REG64_FLD( PU_OTPROM0_ECID_PART60_REGISTER_PART_60_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_60_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART60_REGISTER_PART_60 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_60 ); REG64_FLD( PU_OTPROM1_ECID_PART60_REGISTER_PART_60_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_60_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART61_REGISTER_PART_61 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_61 ); REG64_FLD( PU_OTPROM0_ECID_PART61_REGISTER_PART_61_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_61_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART61_REGISTER_PART_61 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_61 ); REG64_FLD( PU_OTPROM1_ECID_PART61_REGISTER_PART_61_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_61_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART62_REGISTER_PART_62 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_62 ); REG64_FLD( PU_OTPROM0_ECID_PART62_REGISTER_PART_62_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_62_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART62_REGISTER_PART_62 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_62 ); REG64_FLD( PU_OTPROM1_ECID_PART62_REGISTER_PART_62_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_62_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART63_REGISTER_PART_63 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_63 ); REG64_FLD( PU_OTPROM0_ECID_PART63_REGISTER_PART_63_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_63_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART63_REGISTER_PART_63 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_63 ); REG64_FLD( PU_OTPROM1_ECID_PART63_REGISTER_PART_63_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_63_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART6_REGISTER_PART_6 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_6 ); REG64_FLD( PU_OTPROM0_ECID_PART6_REGISTER_PART_6_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_6_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART6_REGISTER_PART_6 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_6 ); REG64_FLD( PU_OTPROM1_ECID_PART6_REGISTER_PART_6_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_6_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART7_REGISTER_PART_7 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_7 ); REG64_FLD( PU_OTPROM0_ECID_PART7_REGISTER_PART_7_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_7_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART7_REGISTER_PART_7 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_7 ); REG64_FLD( PU_OTPROM1_ECID_PART7_REGISTER_PART_7_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_7_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART8_REGISTER_PART_8 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_8 ); REG64_FLD( PU_OTPROM0_ECID_PART8_REGISTER_PART_8_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_8_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART8_REGISTER_PART_8 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_8 ); REG64_FLD( PU_OTPROM1_ECID_PART8_REGISTER_PART_8_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_8_LEN ); REG64_FLD( PU_OTPROM0_ECID_PART9_REGISTER_PART_9 , 0 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_9 ); REG64_FLD( PU_OTPROM0_ECID_PART9_REGISTER_PART_9_LEN , 64 , SH_UNT_PU_OTPROM0, SH_ACS_SCOM , SH_FLD_PART_9_LEN ); REG64_FLD( PU_OTPROM1_ECID_PART9_REGISTER_PART_9 , 0 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_9 ); REG64_FLD( PU_OTPROM1_ECID_PART9_REGISTER_PART_9_LEN , 64 , SH_UNT_PU_OTPROM1, SH_ACS_SCOM , SH_FLD_PART_9_LEN ); REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LPID ); REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LPID_LEN ); REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_PID ); REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_PID_LEN ); REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_TID ); REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_TID_LEN ); REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_ENABLE ); REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_BAR_PRIORITY , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY ); REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LEN ); REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE , 54 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_SIZE ); REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_SIZE_LEN ); REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_READ_OFFSET ); REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_READ_OFFSET_LEN ); REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_QUEUED ); REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_QUEUED_LEN ); REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_PRIMAX ); REG64_FLD( PU_EFT_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX_LEN , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_PRIMAX_LEN ); REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LPID ); REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LPID_LEN ); REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_PID ); REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_PID_LEN ); REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_TID ); REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_TID_LEN ); REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_ENABLE ); REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_BAR_PRIORITY , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY ); REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LEN ); REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE , 54 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_SIZE ); REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_SIZE_LEN ); REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_READ_OFFSET ); REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_READ_OFFSET_LEN ); REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_QUEUED ); REG64_FLD( PU_EFT_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_QUEUED_LEN ); REG64_FLD( PU_EFT_MAX_BYTE_CNT_LIMIT , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LIMIT ); REG64_FLD( PU_EFT_MAX_BYTE_CNT_LIMIT_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LIMIT_LEN ); REG64_FLD( PU_EFT_MAX_BYTE_CNT_SRC_DDE , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRC_DDE ); REG64_FLD( PU_EFT_MAX_BYTE_CNT_SRC_DDE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRC_DDE_LEN ); REG64_FLD( PU_EFT_MAX_BYTE_CNT_TARGET_DDE , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_TARGET_DDE ); REG64_FLD( PU_EFT_MAX_BYTE_CNT_TARGET_DDE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_TARGET_DDE_LEN ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_0_OUT , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE1_0_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_0_OUT , 1 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE2_0_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_0_OUT , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE1_0_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_0_OUT , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE2_0_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_1_OUT , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE1_1_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_1_OUT , 5 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE2_1_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_1_OUT , 6 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE1_1_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_1_OUT , 7 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE2_1_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_2_OUT , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE1_2_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_2_OUT , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE2_2_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_2_OUT , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE1_2_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_2_OUT , 11 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE2_2_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_3_OUT , 12 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE1_3_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_3_OUT , 13 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE2_3_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_3_OUT , 14 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE1_3_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_3_OUT , 15 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE2_3_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_4_OUT , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE1_4_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_4_OUT , 17 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE2_4_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_4_OUT , 18 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE1_4_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_4_OUT , 19 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE2_4_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_5_OUT , 20 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE1_5_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_5_OUT , 21 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE2_5_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_5_OUT , 22 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE1_5_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_5_OUT , 23 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE2_5_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_6_OUT , 24 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE1_6_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_6_OUT , 25 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE2_6_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_6_OUT , 26 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE1_6_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_6_OUT , 27 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE2_6_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE1_7_OUT , 28 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE1_7_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_CE2_7_OUT , 29 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE2_7_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE1_7_OUT , 30 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE1_7_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_UE2_7_OUT , 31 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE2_7_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_DROP_COUNTER_FULL , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DROP_COUNTER_FULL ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_INTERNAL_ERROR , 33 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INTERNAL_ERROR ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_SCOM_ERROR , 34 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SCOM_ERROR ); REG64_FLD( PU_EHHCA_FIR_ACTION0_REG_PARITY_ERROR , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PARITY_ERROR ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_0_OUT , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE1_0_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_0_OUT , 1 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE2_0_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_0_OUT , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE1_0_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_0_OUT , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE2_0_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_1_OUT , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE1_1_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_1_OUT , 5 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE2_1_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_1_OUT , 6 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE1_1_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_1_OUT , 7 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE2_1_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_2_OUT , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE1_2_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_2_OUT , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE2_2_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_2_OUT , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE1_2_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_2_OUT , 11 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE2_2_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_3_OUT , 12 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE1_3_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_3_OUT , 13 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE2_3_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_3_OUT , 14 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE1_3_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_3_OUT , 15 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE2_3_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_4_OUT , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE1_4_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_4_OUT , 17 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE2_4_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_4_OUT , 18 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE1_4_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_4_OUT , 19 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE2_4_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_5_OUT , 20 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE1_5_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_5_OUT , 21 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE2_5_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_5_OUT , 22 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE1_5_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_5_OUT , 23 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE2_5_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_6_OUT , 24 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE1_6_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_6_OUT , 25 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE2_6_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_6_OUT , 26 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE1_6_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_6_OUT , 27 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE2_6_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE1_7_OUT , 28 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE1_7_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_CE2_7_OUT , 29 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CE2_7_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE1_7_OUT , 30 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE1_7_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_UE2_7_OUT , 31 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UE2_7_OUT ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_DROP_COUNTER_FULL , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DROP_COUNTER_FULL ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_INTERNAL_ERROR , 33 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INTERNAL_ERROR ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_SCOM_ERROR , 34 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SCOM_ERROR ); REG64_FLD( PU_EHHCA_FIR_ACTION1_REG_PARITY_ERROR , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PARITY_ERROR ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_0_OUT , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE1_0_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_0_OUT , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE2_0_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_0_OUT , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE1_0_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_0_OUT , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE2_0_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_1_OUT , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE1_1_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_1_OUT , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE2_1_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_1_OUT , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE1_1_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_1_OUT , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE2_1_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_2_OUT , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE1_2_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_2_OUT , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE2_2_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_2_OUT , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE1_2_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_2_OUT , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE2_2_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_3_OUT , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE1_3_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_3_OUT , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE2_3_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_3_OUT , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE1_3_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_3_OUT , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE2_3_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_4_OUT , 16 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE1_4_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_4_OUT , 17 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE2_4_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_4_OUT , 18 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE1_4_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_4_OUT , 19 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE2_4_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_5_OUT , 20 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE1_5_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_5_OUT , 21 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE2_5_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_5_OUT , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE1_5_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_5_OUT , 23 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE2_5_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_6_OUT , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE1_6_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_6_OUT , 25 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE2_6_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_6_OUT , 26 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE1_6_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_6_OUT , 27 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE2_6_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE1_7_OUT , 28 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE1_7_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_CE2_7_OUT , 29 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE2_7_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE1_7_OUT , 30 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE1_7_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_UE2_7_OUT , 31 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE2_7_OUT ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_DROP_COUNTER_FULL , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DROP_COUNTER_FULL ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_INTERNAL_ERROR , 33 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_ERROR ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_SCOM_ERROR , 34 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERROR ); REG64_FLD( PU_EHHCA_FIR_MASK_REG_PARITY_ERROR , 35 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERROR ); REG64_FLD( PU_EHHCA_FIR_REG_CE1_0_OUT , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE1_0_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_CE2_0_OUT , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE2_0_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_UE1_0_OUT , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE1_0_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_UE2_0_OUT , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE2_0_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_CE1_1_OUT , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE1_1_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_CE2_1_OUT , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE2_1_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_UE1_1_OUT , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE1_1_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_UE2_1_OUT , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE2_1_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_CE1_2_OUT , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE1_2_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_CE2_2_OUT , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE2_2_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_UE1_2_OUT , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE1_2_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_UE2_2_OUT , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE2_2_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_CE1_3_OUT , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE1_3_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_CE2_3_OUT , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE2_3_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_UE1_3_OUT , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE1_3_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_UE2_3_OUT , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE2_3_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_CE1_4_OUT , 16 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE1_4_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_CE2_4_OUT , 17 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE2_4_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_UE1_4_OUT , 18 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE1_4_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_UE2_4_OUT , 19 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE2_4_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_CE1_5_OUT , 20 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE1_5_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_CE2_5_OUT , 21 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE2_5_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_UE1_5_OUT , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE1_5_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_UE2_5_OUT , 23 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE2_5_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_CE1_6_OUT , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE1_6_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_CE2_6_OUT , 25 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE2_6_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_UE1_6_OUT , 26 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE1_6_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_UE2_6_OUT , 27 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE2_6_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_CE1_7_OUT , 28 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE1_7_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_CE2_7_OUT , 29 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CE2_7_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_UE1_7_OUT , 30 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE1_7_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_UE2_7_OUT , 31 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UE2_7_OUT ); REG64_FLD( PU_EHHCA_FIR_REG_DROP_COUNTER_FULL , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DROP_COUNTER_FULL ); REG64_FLD( PU_EHHCA_FIR_REG_INTERNAL_ERROR , 33 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_ERROR ); REG64_FLD( PU_EHHCA_FIR_REG_SCOM_ERROR , 34 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERROR ); REG64_FLD( PU_EHHCA_FIR_REG_PARITY_ERROR , 35 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERROR ); REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_RATE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RATE ); REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_RATE_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RATE_LEN ); REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_W0_COUNT , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_W0_COUNT ); REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_W0_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_W0_COUNT_LEN ); REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_W1_COUNT , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_W1_COUNT ); REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_W1_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_W1_COUNT_LEN ); REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_R0_COUNT , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_R0_COUNT ); REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_R0_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_R0_COUNT_LEN ); REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_R1_COUNT , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_R1_COUNT ); REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_R1_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_R1_COUNT_LEN ); REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_R2_COUNT , 52 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_R2_COUNT ); REG64_FLD( PU_NPU0_SM0_EPSILON_CONFIG_R2_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_R2_COUNT_LEN ); REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_RATE , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RATE ); REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_RATE_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RATE_LEN ); REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_W0_COUNT , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_W0_COUNT ); REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_W0_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_W0_COUNT_LEN ); REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_W1_COUNT , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_W1_COUNT ); REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_W1_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_W1_COUNT_LEN ); REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_R0_COUNT , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_R0_COUNT ); REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_R0_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_R0_COUNT_LEN ); REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_R1_COUNT , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_R1_COUNT ); REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_R1_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_R1_COUNT_LEN ); REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_R2_COUNT , 52 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_R2_COUNT ); REG64_FLD( PU_NPU1_SM2_EPSILON_CONFIG_R2_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_R2_COUNT_LEN ); REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_RATE , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RATE ); REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_RATE_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RATE_LEN ); REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_W0_COUNT , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_W0_COUNT ); REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_W0_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_W0_COUNT_LEN ); REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_W1_COUNT , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_W1_COUNT ); REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_W1_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_W1_COUNT_LEN ); REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_R0_COUNT , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_R0_COUNT ); REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_R0_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_R0_COUNT_LEN ); REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_R1_COUNT , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_R1_COUNT ); REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_R1_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_R1_COUNT_LEN ); REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_R2_COUNT , 52 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_R2_COUNT ); REG64_FLD( PU_NPU2_SM3_EPSILON_CONFIG_R2_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_R2_COUNT_LEN ); REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_RATE , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RATE ); REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_RATE_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RATE_LEN ); REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_W0_COUNT , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_W0_COUNT ); REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_W0_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_W0_COUNT_LEN ); REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_W1_COUNT , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_W1_COUNT ); REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_W1_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_W1_COUNT_LEN ); REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_R0_COUNT , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_R0_COUNT ); REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_R0_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_R0_COUNT_LEN ); REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_R1_COUNT , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_R1_COUNT ); REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_R1_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_R1_COUNT_LEN ); REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_R2_COUNT , 52 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_R2_COUNT ); REG64_FLD( PU_NPU1_SM3_EPSILON_CONFIG_R2_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_R2_COUNT_LEN ); REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_RATE , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RATE ); REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_RATE_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RATE_LEN ); REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_W0_COUNT , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_W0_COUNT ); REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_W0_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_W0_COUNT_LEN ); REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_W1_COUNT , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_W1_COUNT ); REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_W1_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_W1_COUNT_LEN ); REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_R0_COUNT , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_R0_COUNT ); REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_R0_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_R0_COUNT_LEN ); REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_R1_COUNT , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_R1_COUNT ); REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_R1_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_R1_COUNT_LEN ); REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_R2_COUNT , 52 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_R2_COUNT ); REG64_FLD( PU_NPU0_SM3_EPSILON_CONFIG_R2_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_R2_COUNT_LEN ); REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_RATE , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RATE ); REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_RATE_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RATE_LEN ); REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_W0_COUNT , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_W0_COUNT ); REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_W0_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_W0_COUNT_LEN ); REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_W1_COUNT , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_W1_COUNT ); REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_W1_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_W1_COUNT_LEN ); REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_R0_COUNT , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_R0_COUNT ); REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_R0_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_R0_COUNT_LEN ); REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_R1_COUNT , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_R1_COUNT ); REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_R1_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_R1_COUNT_LEN ); REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_R2_COUNT , 52 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_R2_COUNT ); REG64_FLD( PU_NPU1_SM1_EPSILON_CONFIG_R2_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_R2_COUNT_LEN ); REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_RATE , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RATE ); REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_RATE_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RATE_LEN ); REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_W0_COUNT , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_W0_COUNT ); REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_W0_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_W0_COUNT_LEN ); REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_W1_COUNT , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_W1_COUNT ); REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_W1_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_W1_COUNT_LEN ); REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_R0_COUNT , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_R0_COUNT ); REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_R0_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_R0_COUNT_LEN ); REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_R1_COUNT , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_R1_COUNT ); REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_R1_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_R1_COUNT_LEN ); REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_R2_COUNT , 52 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_R2_COUNT ); REG64_FLD( PU_NPU2_SM2_EPSILON_CONFIG_R2_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_R2_COUNT_LEN ); REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_RATE , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RATE ); REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_RATE_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RATE_LEN ); REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_W0_COUNT , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_W0_COUNT ); REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_W0_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_W0_COUNT_LEN ); REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_W1_COUNT , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_W1_COUNT ); REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_W1_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_W1_COUNT_LEN ); REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_R0_COUNT , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_R0_COUNT ); REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_R0_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_R0_COUNT_LEN ); REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_R1_COUNT , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_R1_COUNT ); REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_R1_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_R1_COUNT_LEN ); REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_R2_COUNT , 52 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_R2_COUNT ); REG64_FLD( PU_NPU2_SM1_EPSILON_CONFIG_R2_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_R2_COUNT_LEN ); REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_RATE , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RATE ); REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_RATE_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RATE_LEN ); REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_W0_COUNT , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_W0_COUNT ); REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_W0_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_W0_COUNT_LEN ); REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_W1_COUNT , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_W1_COUNT ); REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_W1_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_W1_COUNT_LEN ); REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_R0_COUNT , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_R0_COUNT ); REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_R0_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_R0_COUNT_LEN ); REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_R1_COUNT , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_R1_COUNT ); REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_R1_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_R1_COUNT_LEN ); REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_R2_COUNT , 52 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_R2_COUNT ); REG64_FLD( PU_NPU0_SM2_EPSILON_CONFIG_R2_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_R2_COUNT_LEN ); REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_RATE , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RATE ); REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_RATE_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RATE_LEN ); REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_W0_COUNT , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_W0_COUNT ); REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_W0_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_W0_COUNT_LEN ); REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_W1_COUNT , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_W1_COUNT ); REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_W1_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_W1_COUNT_LEN ); REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_R0_COUNT , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_R0_COUNT ); REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_R0_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_R0_COUNT_LEN ); REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_R1_COUNT , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_R1_COUNT ); REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_R1_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_R1_COUNT_LEN ); REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_R2_COUNT , 52 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_R2_COUNT ); REG64_FLD( PU_NPU2_SM0_EPSILON_CONFIG_R2_COUNT_LEN , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_R2_COUNT_LEN ); REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_RATE , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RATE ); REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_RATE_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RATE_LEN ); REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_W0_COUNT , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_W0_COUNT ); REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_W0_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_W0_COUNT_LEN ); REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_W1_COUNT , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_W1_COUNT ); REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_W1_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_W1_COUNT_LEN ); REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_R0_COUNT , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_R0_COUNT ); REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_R0_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_R0_COUNT_LEN ); REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_R1_COUNT , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_R1_COUNT ); REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_R1_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_R1_COUNT_LEN ); REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_R2_COUNT , 52 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_R2_COUNT ); REG64_FLD( PU_NPU0_SM1_EPSILON_CONFIG_R2_COUNT_LEN , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_R2_COUNT_LEN ); REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_RATE , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RATE ); REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_RATE_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RATE_LEN ); REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_W0_COUNT , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_W0_COUNT ); REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_W0_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_W0_COUNT_LEN ); REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_W1_COUNT , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_W1_COUNT ); REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_W1_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_W1_COUNT_LEN ); REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_R0_COUNT , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_R0_COUNT ); REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_R0_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_R0_COUNT_LEN ); REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_R1_COUNT , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_R1_COUNT ); REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_R1_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_R1_COUNT_LEN ); REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_R2_COUNT , 52 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_R2_COUNT ); REG64_FLD( PU_NPU1_SM0_EPSILON_CONFIG_R2_COUNT_LEN , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_R2_COUNT_LEN ); REG64_FLD( PU_ERAT_STATUS_CONTROL_FORCE_BYPASS , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_FORCE_BYPASS ); REG64_FLD( PU_ERAT_STATUS_CONTROL_IDLE , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_IDLE ); REG64_FLD( PU_ERAT_STATUS_CONTROL_VALID_ENTRY , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_VALID_ENTRY ); REG64_FLD( PU_ERAT_STATUS_CONTROL_DISABLE_HIT_UNDER_BARRIER , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_HIT_UNDER_BARRIER ); REG64_FLD( PU_ERAT_STATUS_CONTROL_DISABLE_PROMOTE , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_PROMOTE ); REG64_FLD( PU_ERAT_STATUS_CONTROL_DISABLE_CHECKIN_HANG_TIMER , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_CHECKIN_HANG_TIMER ); REG64_FLD( PU_ERAT_STATUS_CONTROL_DISABLE_CHECKOUT_HANG_TIMER , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_CHECKOUT_HANG_TIMER ); REG64_FLD( PU_ERAT_STATUS_CONTROL_SPECULATIVE_CHECKIN_COUNT , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPECULATIVE_CHECKIN_COUNT ); REG64_FLD( PU_ERAT_STATUS_CONTROL_SPECULATIVE_CHECKIN_COUNT_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPECULATIVE_CHECKIN_COUNT_LEN ); REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK0 , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_ERR_BRK0 ); REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK0_LEN , 6 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_ERR_BRK0_LEN ); REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK1 , 6 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_ERR_BRK1 ); REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK1_LEN , 6 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_ERR_BRK1_LEN ); REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK2 , 12 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_ERR_BRK2 ); REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK2_LEN , 6 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_ERR_BRK2_LEN ); REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK3 , 18 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_ERR_BRK3 ); REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK3_LEN , 6 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_ERR_BRK3_LEN ); REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK4 , 24 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_ERR_BRK4 ); REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK4_LEN , 6 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_ERR_BRK4_LEN ); REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK5 , 30 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_ERR_BRK5 ); REG64_FLD( PU_NPU_CTL_ERROR_BRICK_GROUP_CONFIG_ERR_BRK5_LEN , 6 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_ERR_BRK5_LEN ); REG64_FLD( PEC_ERROR_REG_CE , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CE ); REG64_FLD( PEC_ERROR_REG_CHIPLET_ERRORS , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CHIPLET_ERRORS ); REG64_FLD( PEC_ERROR_REG_CHIPLET_ERRORS_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CHIPLET_ERRORS_LEN ); REG64_FLD( PEC_ERROR_REG_PARITY , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PARITY ); REG64_FLD( PEC_ERROR_REG_DATA_BUFFER , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DATA_BUFFER ); REG64_FLD( PEC_ERROR_REG_ADDR_BUFFER , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ADDR_BUFFER ); REG64_FLD( PEC_ERROR_REG_PCB_FSM , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PCB_FSM ); REG64_FLD( PEC_ERROR_REG_CL_FSM , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CL_FSM ); REG64_FLD( PEC_ERROR_REG_INT_RX_FSM , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INT_RX_FSM ); REG64_FLD( PEC_ERROR_REG_INT_TX_FSM , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INT_TX_FSM ); REG64_FLD( PEC_ERROR_REG_INT_TYPE , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INT_TYPE ); REG64_FLD( PEC_ERROR_REG_CL_DATA , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CL_DATA ); REG64_FLD( PEC_ERROR_REG_INFO , 13 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INFO ); REG64_FLD( PEC_ERROR_REG_UNUSED_0 , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED_0 ); REG64_FLD( PEC_ERROR_REG_CHIPLET_ATOMIC_LOCK , 15 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CHIPLET_ATOMIC_LOCK ); REG64_FLD( PEC_ERROR_REG_PCB_INTERFACE , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PCB_INTERFACE ); REG64_FLD( PEC_ERROR_REG_CHIPLET_OFFLINE , 17 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CHIPLET_OFFLINE ); REG64_FLD( PEC_ERROR_REG_CHIPLET_GRID_SKITTER , 18 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CHIPLET_GRID_SKITTER ); REG64_FLD( PEC_ERROR_REG_CTRL_PARITY , 19 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CTRL_PARITY ); REG64_FLD( PEC_ERROR_REG_ADDRESS_PARITY , 20 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ADDRESS_PARITY ); REG64_FLD( PEC_ERROR_REG_TIMEOUT_PARITY , 21 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TIMEOUT_PARITY ); REG64_FLD( PEC_ERROR_REG_CONFIG_PARITY , 22 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CONFIG_PARITY ); REG64_FLD( PEC_ERROR_REG_UNUSED_1 , 23 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED_1 ); REG64_FLD( PEC_ERROR_REG_DIV_PARITY , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DIV_PARITY ); REG64_FLD( PEC_ERROR_REG_PLL_UNLOCK , 25 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PLL_UNLOCK ); REG64_FLD( PEC_ERROR_REG_PLL_UNLOCK_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PLL_UNLOCK_LEN ); REG64_FLD( PEC_ERROR_STATUS_ERRORS , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ERRORS ); REG64_FLD( PEC_ERROR_STATUS_ERRORS_LEN , 32 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ERRORS_LEN ); REG64_FLD( PU_NPU_SM2_ERR_FIRST_BITS , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU_SM2_ERR_FIRST_BITS_LEN , 64 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_BITS_LEN ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_DEBUG0_CONFIG_P , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_DEBUG0_CONFIG_P ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_DEBUG1_CONFIG_P , 1 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_DEBUG1_CONFIG_P ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_XTS_CONFIG_P , 2 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_XTS_CONFIG_P ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED1 , 3 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED1 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED1_LEN , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED1_LEN ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_SNP_REG_ERR0 , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_SNP_REG_ERR0 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_SNP_REG_ERR1 , 9 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_SNP_REG_ERR1 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_SNP_REG_ERR2 , 10 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_SNP_REG_ERR2 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_SNP_REG_ERR3 , 11 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_SNP_REG_ERR3 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_SNP_REG_ERR4 , 12 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_SNP_REG_ERR4 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_SNP_REG_ERR5 , 13 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_SNP_REG_ERR5 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_SNP_REG_ERR6 , 14 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_SNP_REG_ERR6 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_ATR_SM_STATE , 15 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATR_SM_STATE ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_ATSD_SM_STATE , 16 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATSD_SM_STATE ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_ATR_TIMEOUT , 17 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATR_TIMEOUT ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_ATSD_TIMEOUT , 18 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATSD_TIMEOUT ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_ATSD_BAD_TAG , 19 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATSD_BAD_TAG ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_MAP_REG_ERR2 , 20 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_MAP_REG_ERR2 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_MAP_REG_ERR3 , 21 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_MAP_REG_ERR3 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_MAP_REG_ERR4 , 22 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_MAP_REG_ERR4 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_ATR_ARBSTATE , 23 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATR_ARBSTATE ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED2 , 24 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED2 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED2_LEN , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED2_LEN ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_CERR0 , 32 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_IFC_REG_CERR0 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_CERR1 , 33 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_IFC_REG_CERR1 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_CERR2 , 34 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_IFC_REG_CERR2 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_MAP_REG_CERR0 , 35 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_MAP_REG_CERR0 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_MAP_REG_CERR1 , 36 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_MAP_REG_CERR1 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED3 , 37 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED3 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED3_LEN , 11 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED3_LEN ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_ERR0 , 48 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_IFC_REG_ERR0 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_ERR1 , 49 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_IFC_REG_ERR1 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_ERR2 , 50 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_IFC_REG_ERR2 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_ERR3 , 51 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_IFC_REG_ERR3 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_ERR4 , 52 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_IFC_REG_ERR4 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_ERR5 , 53 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_IFC_REG_ERR5 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_ERR6 , 54 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_IFC_REG_ERR6 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_ERR7 , 55 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_IFC_REG_ERR7 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_IFC_REG_ERR8 , 56 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_IFC_REG_ERR8 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_MAP_REG_ERR0 , 57 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_MAP_REG_ERR0 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_MAP_REG_ERR1 , 58 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_MAP_REG_ERR1 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED4 , 59 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED4 ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_UNUSED4_LEN , 4 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED4_LEN ); REG64_FLD( PU_NPU_SM2_ERR_HOLD_ATR_MISS_IRQ , 63 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATR_MISS_IRQ ); REG64_FLD( PU_NPU_CTL_ERR_INFO_NPU_RING_ADDR_MISC , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC ); REG64_FLD( PU_NPU_CTL_ERR_INFO_NPU_RING_ADDR_MISC_LEN , 24 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_LEN ); REG64_FLD( PU_NPU_CTL_ERR_INFO_NPU_RING_ADDR_MISC_LENR , 24 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_LENR ); REG64_FLD( PU_NPU_CTL_ERR_INFO_NPU_RING_ADDR_MISC_LENR_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_LENR_LEN ); REG64_FLD( PU_NPU_CTL_ERR_INFO_NPU_RING_ADDR_MISC_RNW , 26 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_RNW ); REG64_FLD( PU_NPU_CTL_ERR_INFO_NPU_RING_ADDR_MISC_DA_OP , 27 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MISC_DA_OP ); REG64_FLD( PU_NPU_SM2_ERR_MASK_BITS , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_NPU_SM2_ERR_MASK_BITS_LEN , 64 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_BITS_LEN ); REG64_FLD( PU_NPU_CTL_ERR_SCOPE_CTL_CONFIG_CTL , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_CTL ); REG64_FLD( PU_NPU_CTL_ERR_SCOPE_CTL_CONFIG_CTL_LEN , 16 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_CTL_LEN ); REG64_FLD( PEC_ERR_STATUS_REG_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK , 16 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_SERIAL_SHIFTCNT_MODEREG_PARITY_MASK ); REG64_FLD( PEC_ERR_STATUS_REG_THERM_MODEREG_PARITY_MASK , 17 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_THERM_MODEREG_PARITY_MASK ); REG64_FLD( PEC_ERR_STATUS_REG_SKITTER_MODEREG_PARITY_MASK , 18 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_SKITTER_MODEREG_PARITY_MASK ); REG64_FLD( PEC_ERR_STATUS_REG_SKITTER_FORCEREG_PARITY_MASK , 19 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_SKITTER_FORCEREG_PARITY_MASK ); REG64_FLD( PEC_ERR_STATUS_REG_SCAN_INIT_VERSION_PARITY_MASK , 20 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_SCAN_INIT_VERSION_PARITY_MASK ); REG64_FLD( PEC_ERR_STATUS_REG_VOLT_MODEREG_PARITY_MASK , 21 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_VOLT_MODEREG_PARITY_MASK ); REG64_FLD( PEC_ERR_STATUS_REG_COUNT_STATE_MASK , 23 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_COUNT_STATE_MASK ); REG64_FLD( PEC_ERR_STATUS_REG_RUN_STATE_MASK , 24 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_RUN_STATE_MASK ); REG64_FLD( PEC_ERR_STATUS_REG_THRES_STATE_MASK , 25 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_THRES_STATE_MASK ); REG64_FLD( PEC_ERR_STATUS_REG_OVERFLOW_MASK , 26 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_OVERFLOW_MASK ); REG64_FLD( PEC_ERR_STATUS_REG_SHIFTER_PARITY_MASK , 27 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_SHIFTER_PARITY_MASK ); REG64_FLD( PEC_ERR_STATUS_REG_SHIFTER_VALID_MASK , 28 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_SHIFTER_VALID_MASK ); REG64_FLD( PEC_ERR_STATUS_REG_TIMEOUT_MASK , 29 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_TIMEOUT_MASK ); REG64_FLD( PEC_ERR_STATUS_REG_F_SKITTER_READ_MASK , 30 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_F_SKITTER_READ_MASK ); REG64_FLD( PEC_ERR_STATUS_REG_PCB_MASK , 31 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_PCB_MASK ); REG64_FLD( PU_ESB_CI_BASE_BASE , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_BASE ); REG64_FLD( PU_ESB_CI_BASE_BASE_LEN , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_BASE_LEN ); REG64_FLD( PU_ESB_CI_BASE_VALID , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_VALID ); REG64_FLD( PU_ESB_NOTIFY_ADDR , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDR ); REG64_FLD( PU_ESB_NOTIFY_ADDR_LEN , 53 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDR_LEN ); REG64_FLD( PU_ESB_NOTIFY_VALID , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_VALID ); REG64_FLD( PU_EXPORT_REGL_CTRL_TP_NX_ALLOW_CRYPTO_DC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_TP_NX_ALLOW_CRYPTO_DC ); REG64_FLD( PU_EXPORT_REGL_CTRL_TP_EX_FUSE_VMX_CRYPTO_DIS_DC , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_TP_EX_FUSE_VMX_CRYPTO_DIS_DC ); REG64_FLD( PU_EXPORT_REGL_CTRL_TP_EX_FUSE_FP_THROTTLE_EN_DC , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_TP_EX_FUSE_FP_THROTTLE_EN_DC ); REG64_FLD( PU_EXPORT_REGL_CTRL_TP_PB_FUSE_TOPOLOGY_2CHIP , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_TP_PB_FUSE_TOPOLOGY_2CHIP ); REG64_FLD( PU_EXPORT_REGL_CTRL_TP_PB_FUSE_TOPOLOGY_GROUP , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TP_PB_FUSE_TOPOLOGY_GROUP ); REG64_FLD( PU_EXPORT_REGL_CTRL_TP_PB_FUSE_TOPOLOGY_GROUP_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_TP_PB_FUSE_TOPOLOGY_GROUP_LEN ); REG64_FLD( PU_EXPORT_REGL_CTRL_TP_PB_FUSE_SPARE , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_TP_PB_FUSE_SPARE ); REG64_FLD( PU_EXTENDED_STATUS_B_MSM_CURR_STATE_0 , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_MSM_CURR_STATE_0 ); REG64_FLD( PU_EXTENDED_STATUS_B_MSM_CURR_STATE_0_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MSM_CURR_STATE_0_LEN ); REG64_FLD( PU_EXTENDED_STATUS_B_SELF_BUSY_0 , 25 , SH_UNT , SH_ACS_SCOM , SH_FLD_SELF_BUSY_0 ); REG64_FLD( PU_EXTENDED_STATUS_B_PEEK_DATA1_0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0 ); REG64_FLD( PU_EXTENDED_STATUS_B_PEEK_DATA1_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0_LEN ); REG64_FLD( PU_EXTENDED_STATUS_B_LBUS_PARITY_ERR1_0 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_0 ); REG64_FLD( PU_EXTENDED_STATUS_C_MSM_CURR_STATE_1 , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_MSM_CURR_STATE_1 ); REG64_FLD( PU_EXTENDED_STATUS_C_MSM_CURR_STATE_1_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MSM_CURR_STATE_1_LEN ); REG64_FLD( PU_EXTENDED_STATUS_C_SELF_BUSY_1 , 25 , SH_UNT , SH_ACS_SCOM , SH_FLD_SELF_BUSY_1 ); REG64_FLD( PU_EXTENDED_STATUS_C_PEEK_DATA1_1 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1 ); REG64_FLD( PU_EXTENDED_STATUS_C_PEEK_DATA1_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1_LEN ); REG64_FLD( PU_EXTENDED_STATUS_C_LBUS_PARITY_ERR1_1 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_1 ); REG64_FLD( PU_EXTENDED_STATUS_D_MSM_CURR_STATE_2 , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_MSM_CURR_STATE_2 ); REG64_FLD( PU_EXTENDED_STATUS_D_MSM_CURR_STATE_2_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MSM_CURR_STATE_2_LEN ); REG64_FLD( PU_EXTENDED_STATUS_D_SELF_BUSY_2 , 25 , SH_UNT , SH_ACS_SCOM , SH_FLD_SELF_BUSY_2 ); REG64_FLD( PU_EXTENDED_STATUS_D_PEEK_DATA1_2 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2 ); REG64_FLD( PU_EXTENDED_STATUS_D_PEEK_DATA1_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2_LEN ); REG64_FLD( PU_EXTENDED_STATUS_D_LBUS_PARITY_ERR1_2 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_2 ); REG64_FLD( PU_EXTENDED_STATUS_E_MSM_CURR_STATE_3 , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_MSM_CURR_STATE_3 ); REG64_FLD( PU_EXTENDED_STATUS_E_MSM_CURR_STATE_3_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MSM_CURR_STATE_3_LEN ); REG64_FLD( PU_EXTENDED_STATUS_E_SELF_BUSY_3 , 25 , SH_UNT , SH_ACS_SCOM , SH_FLD_SELF_BUSY_3 ); REG64_FLD( PU_EXTENDED_STATUS_E_PEEK_DATA1_3 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3 ); REG64_FLD( PU_EXTENDED_STATUS_E_PEEK_DATA1_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3_LEN ); REG64_FLD( PU_EXTENDED_STATUS_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); REG64_FLD( PU_PB_CENT_SM1_EXTFIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM_RO , SH_FLD_ACTION0 ); REG64_FLD( PU_PB_CENT_SM1_EXTFIR_ACTION0_REG_ACTION0_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM_RO , SH_FLD_ACTION0_LEN ); REG64_FLD( PU_PB_CENT_SM1_EXTFIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM_RO , SH_FLD_ACTION1 ); REG64_FLD( PU_PB_CENT_SM1_EXTFIR_ACTION1_REG_ACTION1_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM_RO , SH_FLD_ACTION1_LEN ); REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X0_FIR_ERR , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , SH_FLD_PB_X0_FIR_ERR ); REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X1_FIR_ERR , 1 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , SH_FLD_PB_X1_FIR_ERR ); REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X2_FIR_ERR , 2 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , SH_FLD_PB_X2_FIR_ERR ); REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X3_FIR_ERR , 3 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , SH_FLD_PB_X3_FIR_ERR ); REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X4_FIR_ERR , 4 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , SH_FLD_PB_X4_FIR_ERR ); REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X5_FIR_ERR , 5 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , SH_FLD_PB_X5_FIR_ERR ); REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X6_FIR_ERR , 6 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , SH_FLD_PB_X6_FIR_ERR ); REG64_FLD( PU_PB_CENT_SM1_EXTFIR_MASK_REG_SCOM_ERROR , 7 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERROR ); REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_PB_X0_FIR_ERR , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , SH_FLD_PB_X0_FIR_ERR ); REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_PB_X1_FIR_ERR , 1 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , SH_FLD_PB_X1_FIR_ERR ); REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_PB_X2_FIR_ERR , 2 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , SH_FLD_PB_X2_FIR_ERR ); REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_PB_X3_FIR_ERR , 3 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , SH_FLD_PB_X3_FIR_ERR ); REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_PB_X4_FIR_ERR , 4 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , SH_FLD_PB_X4_FIR_ERR ); REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_PB_X5_FIR_ERR , 5 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , SH_FLD_PB_X5_FIR_ERR ); REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_PB_X6_FIR_ERR , 6 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , SH_FLD_PB_X6_FIR_ERR ); REG64_FLD( PU_PB_CENT_SM1_EXTFIR_REG_SCOM_ERROR , 7 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERROR ); REG64_FLD( PU_NPU_CTL_FENCE_0_CONFIG_0 , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( PU_NPU_CTL_FENCE_0_CONFIG_0_LEN , 64 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_0_LEN ); REG64_FLD( PU_NPU_CTL_FENCE_1_CONFIG_1 , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_1 ); REG64_FLD( PU_NPU_CTL_FENCE_1_CONFIG_1_LEN , 64 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_1_LEN ); REG64_FLD( PU_NPU_CTL_FENCE_STATE_BRK0 , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BRK0 ); REG64_FLD( PU_NPU_CTL_FENCE_STATE_BRK1 , 1 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BRK1 ); REG64_FLD( PU_NPU_CTL_FENCE_STATE_BRK2 , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BRK2 ); REG64_FLD( PU_NPU_CTL_FENCE_STATE_BRK3 , 3 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BRK3 ); REG64_FLD( PU_NPU_CTL_FENCE_STATE_BRK4 , 4 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BRK4 ); REG64_FLD( PU_NPU_CTL_FENCE_STATE_BRK5 , 5 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BRK5 ); REG64_FLD( PU_FI2C_CFG_PIBI2CM_PIB_SLAVE_ID , 0 , SH_UNT , SH_ACS_PPE2 , SH_FLD_PIBI2CM_PIB_SLAVE_ID ); REG64_FLD( PU_FI2C_CFG_PIBI2CM_PIB_SLAVE_ID_LEN , 16 , SH_UNT , SH_ACS_PPE2 , SH_FLD_PIBI2CM_PIB_SLAVE_ID_LEN ); REG64_FLD( PU_FI2C_CFG_ECC_ENABLE , 16 , SH_UNT , SH_ACS_PPE2 , SH_FLD_ECC_ENABLE ); REG64_FLD( PU_FI2C_CFG_DISABLE_ECC_CHK , 17 , SH_UNT , SH_ACS_PPE2 , SH_FLD_DISABLE_ECC_CHK ); REG64_FLD( PU_FI2C_CFG_I2C_SPEED_MUX , 18 , SH_UNT , SH_ACS_PPE2 , SH_FLD_I2C_SPEED_MUX ); REG64_FLD( PU_FI2C_CFG_I2C_SPEED_MUX_LEN , 2 , SH_UNT , SH_ACS_PPE2 , SH_FLD_I2C_SPEED_MUX_LEN ); REG64_FLD( PU_FI2C_CFG_BIT_RATE_DIVISOR_VALUE , 20 , SH_UNT , SH_ACS_PPE2 , SH_FLD_BIT_RATE_DIVISOR_VALUE ); REG64_FLD( PU_FI2C_CFG_BIT_RATE_DIVISOR_VALUE_LEN , 16 , SH_UNT , SH_ACS_PPE2 , SH_FLD_BIT_RATE_DIVISOR_VALUE_LEN ); REG64_FLD( PU_FI2C_CFG_I2C_BUS_HELD_MODE_ENABLE , 36 , SH_UNT , SH_ACS_PPE2 , SH_FLD_I2C_BUS_HELD_MODE_ENABLE ); REG64_FLD( PU_FI2C_CFG_PIPELINE_ENABLE , 37 , SH_UNT , SH_ACS_PPE2 , SH_FLD_PIPELINE_ENABLE ); REG64_FLD( PU_FI2C_CFG_BACKUP_SEEPROM_SELECT , 38 , SH_UNT , SH_ACS_PPE2 , SH_FLD_BACKUP_SEEPROM_SELECT ); REG64_FLD( PU_FI2C_CFG_FORCE_RESET , 39 , SH_UNT , SH_ACS_PPE2 , SH_FLD_FORCE_RESET ); REG64_FLD( PU_FI2C_CFG_RESET_PIB , 40 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESET_PIB ); REG64_FLD( PU_FI2C_CFG_DISABLE_TIMEOUT , 41 , SH_UNT , SH_ACS_PPE2 , SH_FLD_DISABLE_TIMEOUT ); REG64_FLD( PU_FI2C_CFG_RESERVED_FOR_CONFIGS , 42 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_FOR_CONFIGS ); REG64_FLD( PU_FI2C_CFG_RESERVED_FOR_CONFIGS_LEN , 18 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_FOR_CONFIGS_LEN ); REG64_FLD( PU_FI2C_SCFG0_REGISTER_VALID , 0 , SH_UNT , SH_ACS_PPE2 , SH_FLD_REGISTER_VALID ); REG64_FLD( PU_FI2C_SCFG0_RESERVED_3 , 1 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_3 ); REG64_FLD( PU_FI2C_SCFG0_RESERVED_4 , 2 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_4 ); REG64_FLD( PU_FI2C_SCFG0_RESERVED_4_LEN , 2 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_4_LEN ); REG64_FLD( PU_FI2C_SCFG0_RESERVED_5 , 4 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_5 ); REG64_FLD( PU_FI2C_SCFG0_RESERVED_5_LEN , 4 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_5_LEN ); REG64_FLD( PU_FI2C_SCFG0_DEVICE_ID , 8 , SH_UNT , SH_ACS_PPE2 , SH_FLD_DEVICE_ID ); REG64_FLD( PU_FI2C_SCFG0_DEVICE_ID_LEN , 7 , SH_UNT , SH_ACS_PPE2 , SH_FLD_DEVICE_ID_LEN ); REG64_FLD( PU_FI2C_SCFG0_ECC_ENABLE , 15 , SH_UNT , SH_ACS_PPE2 , SH_FLD_ECC_ENABLE ); REG64_FLD( PU_FI2C_SCFG0_MEMORY_SIZE_IN_PPE_ADDR_MAP , 16 , SH_UNT , SH_ACS_PPE2 , SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP ); REG64_FLD( PU_FI2C_SCFG0_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN , 16 , SH_UNT , SH_ACS_PPE2 , SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN ); REG64_FLD( PU_FI2C_SCFG0_START_SEEPROM_ADDRESS , 32 , SH_UNT , SH_ACS_PPE2 , SH_FLD_START_SEEPROM_ADDRESS ); REG64_FLD( PU_FI2C_SCFG0_START_SEEPROM_ADDRESS_LEN , 16 , SH_UNT , SH_ACS_PPE2 , SH_FLD_START_SEEPROM_ADDRESS_LEN ); REG64_FLD( PU_FI2C_SCFG0_START_PPE_ADDR , 48 , SH_UNT , SH_ACS_PPE2 , SH_FLD_START_PPE_ADDR ); REG64_FLD( PU_FI2C_SCFG0_START_PPE_ADDR_LEN , 16 , SH_UNT , SH_ACS_PPE2 , SH_FLD_START_PPE_ADDR_LEN ); REG64_FLD( PU_FI2C_SCFG1_REGISTER_VALID , 0 , SH_UNT , SH_ACS_PPE2 , SH_FLD_REGISTER_VALID ); REG64_FLD( PU_FI2C_SCFG1_RESERVED_6 , 1 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_6 ); REG64_FLD( PU_FI2C_SCFG1_RESERVED_7 , 2 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_7 ); REG64_FLD( PU_FI2C_SCFG1_RESERVED_7_LEN , 2 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_7_LEN ); REG64_FLD( PU_FI2C_SCFG1_RESERVED_8 , 4 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_8 ); REG64_FLD( PU_FI2C_SCFG1_RESERVED_8_LEN , 4 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_8_LEN ); REG64_FLD( PU_FI2C_SCFG1_DEVICE_ID , 8 , SH_UNT , SH_ACS_PPE2 , SH_FLD_DEVICE_ID ); REG64_FLD( PU_FI2C_SCFG1_DEVICE_ID_LEN , 7 , SH_UNT , SH_ACS_PPE2 , SH_FLD_DEVICE_ID_LEN ); REG64_FLD( PU_FI2C_SCFG1_ECC_ENABLE , 15 , SH_UNT , SH_ACS_PPE2 , SH_FLD_ECC_ENABLE ); REG64_FLD( PU_FI2C_SCFG1_MEMORY_SIZE_IN_PPE_ADDR_MAP , 16 , SH_UNT , SH_ACS_PPE2 , SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP ); REG64_FLD( PU_FI2C_SCFG1_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN , 16 , SH_UNT , SH_ACS_PPE2 , SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN ); REG64_FLD( PU_FI2C_SCFG1_START_SEEPROM_ADDRESS , 32 , SH_UNT , SH_ACS_PPE2 , SH_FLD_START_SEEPROM_ADDRESS ); REG64_FLD( PU_FI2C_SCFG1_START_SEEPROM_ADDRESS_LEN , 16 , SH_UNT , SH_ACS_PPE2 , SH_FLD_START_SEEPROM_ADDRESS_LEN ); REG64_FLD( PU_FI2C_SCFG1_START_PPE_ADDR , 48 , SH_UNT , SH_ACS_PPE2 , SH_FLD_START_PPE_ADDR ); REG64_FLD( PU_FI2C_SCFG1_START_PPE_ADDR_LEN , 16 , SH_UNT , SH_ACS_PPE2 , SH_FLD_START_PPE_ADDR_LEN ); REG64_FLD( PU_FI2C_SCFG2_REGISTER_VALID , 0 , SH_UNT , SH_ACS_PPE2 , SH_FLD_REGISTER_VALID ); REG64_FLD( PU_FI2C_SCFG2_RESERVED_9 , 1 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_9 ); REG64_FLD( PU_FI2C_SCFG2_RESERVED_10 , 2 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_10 ); REG64_FLD( PU_FI2C_SCFG2_RESERVED_10_LEN , 2 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_10_LEN ); REG64_FLD( PU_FI2C_SCFG2_RESERVED_11 , 4 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_11 ); REG64_FLD( PU_FI2C_SCFG2_RESERVED_11_LEN , 4 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_11_LEN ); REG64_FLD( PU_FI2C_SCFG2_DEVICE_ID , 8 , SH_UNT , SH_ACS_PPE2 , SH_FLD_DEVICE_ID ); REG64_FLD( PU_FI2C_SCFG2_DEVICE_ID_LEN , 7 , SH_UNT , SH_ACS_PPE2 , SH_FLD_DEVICE_ID_LEN ); REG64_FLD( PU_FI2C_SCFG2_ECC_ENABLE , 15 , SH_UNT , SH_ACS_PPE2 , SH_FLD_ECC_ENABLE ); REG64_FLD( PU_FI2C_SCFG2_MEMORY_SIZE_IN_PPE_ADDR_MAP , 16 , SH_UNT , SH_ACS_PPE2 , SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP ); REG64_FLD( PU_FI2C_SCFG2_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN , 16 , SH_UNT , SH_ACS_PPE2 , SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN ); REG64_FLD( PU_FI2C_SCFG2_START_SEEPROM_ADDRESS , 32 , SH_UNT , SH_ACS_PPE2 , SH_FLD_START_SEEPROM_ADDRESS ); REG64_FLD( PU_FI2C_SCFG2_START_SEEPROM_ADDRESS_LEN , 16 , SH_UNT , SH_ACS_PPE2 , SH_FLD_START_SEEPROM_ADDRESS_LEN ); REG64_FLD( PU_FI2C_SCFG2_START_PPE_ADDR , 48 , SH_UNT , SH_ACS_PPE2 , SH_FLD_START_PPE_ADDR ); REG64_FLD( PU_FI2C_SCFG2_START_PPE_ADDR_LEN , 16 , SH_UNT , SH_ACS_PPE2 , SH_FLD_START_PPE_ADDR_LEN ); REG64_FLD( PU_FI2C_SCFG3_REGISTER_VALID , 0 , SH_UNT , SH_ACS_PPE2 , SH_FLD_REGISTER_VALID ); REG64_FLD( PU_FI2C_SCFG3_RESERVED_12 , 1 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_12 ); REG64_FLD( PU_FI2C_SCFG3_RESERVED_13 , 2 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_13 ); REG64_FLD( PU_FI2C_SCFG3_RESERVED_13_LEN , 2 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_13_LEN ); REG64_FLD( PU_FI2C_SCFG3_RESERVED_14 , 4 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_14 ); REG64_FLD( PU_FI2C_SCFG3_RESERVED_14_LEN , 4 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_14_LEN ); REG64_FLD( PU_FI2C_SCFG3_DEVICE_ID , 8 , SH_UNT , SH_ACS_PPE2 , SH_FLD_DEVICE_ID ); REG64_FLD( PU_FI2C_SCFG3_DEVICE_ID_LEN , 7 , SH_UNT , SH_ACS_PPE2 , SH_FLD_DEVICE_ID_LEN ); REG64_FLD( PU_FI2C_SCFG3_ECC_ENABLE , 15 , SH_UNT , SH_ACS_PPE2 , SH_FLD_ECC_ENABLE ); REG64_FLD( PU_FI2C_SCFG3_MEMORY_SIZE_IN_PPE_ADDR_MAP , 16 , SH_UNT , SH_ACS_PPE2 , SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP ); REG64_FLD( PU_FI2C_SCFG3_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN , 16 , SH_UNT , SH_ACS_PPE2 , SH_FLD_MEMORY_SIZE_IN_PPE_ADDR_MAP_LEN ); REG64_FLD( PU_FI2C_SCFG3_START_SEEPROM_ADDRESS , 32 , SH_UNT , SH_ACS_PPE2 , SH_FLD_START_SEEPROM_ADDRESS ); REG64_FLD( PU_FI2C_SCFG3_START_SEEPROM_ADDRESS_LEN , 16 , SH_UNT , SH_ACS_PPE2 , SH_FLD_START_SEEPROM_ADDRESS_LEN ); REG64_FLD( PU_FI2C_SCFG3_START_PPE_ADDR , 48 , SH_UNT , SH_ACS_PPE2 , SH_FLD_START_PPE_ADDR ); REG64_FLD( PU_FI2C_SCFG3_START_PPE_ADDR_LEN , 16 , SH_UNT , SH_ACS_PPE2 , SH_FLD_START_PPE_ADDR_LEN ); REG64_FLD( PU_FI2C_STAT_PIB_RESPONSE_INFO , 0 , SH_UNT , SH_ACS_PPE , SH_FLD_PIB_RESPONSE_INFO ); REG64_FLD( PU_FI2C_STAT_PIB_RESPONSE_INFO_LEN , 3 , SH_UNT , SH_ACS_PPE , SH_FLD_PIB_RESPONSE_INFO_LEN ); REG64_FLD( PU_FI2C_STAT_I2CM_PIB_ERRORS , 3 , SH_UNT , SH_ACS_PPE , SH_FLD_I2CM_PIB_ERRORS ); REG64_FLD( PU_FI2C_STAT_I2CM_PIB_ERRORS_LEN , 6 , SH_UNT , SH_ACS_PPE , SH_FLD_I2CM_PIB_ERRORS_LEN ); REG64_FLD( PU_FI2C_STAT_I2CM_ECC_ERRORS , 9 , SH_UNT , SH_ACS_PPE , SH_FLD_I2CM_ECC_ERRORS ); REG64_FLD( PU_FI2C_STAT_I2CM_ECC_ERRORS_LEN , 3 , SH_UNT , SH_ACS_PPE , SH_FLD_I2CM_ECC_ERRORS_LEN ); REG64_FLD( PU_FI2C_STAT_I2CM_I2C_ERRORS , 12 , SH_UNT , SH_ACS_PPE , SH_FLD_I2CM_I2C_ERRORS ); REG64_FLD( PU_FI2C_STAT_I2CM_I2C_ERRORS_LEN , 7 , SH_UNT , SH_ACS_PPE , SH_FLD_I2CM_I2C_ERRORS_LEN ); REG64_FLD( PU_FI2C_STAT_ERR_ADDR_BEYOND_RANGE , 19 , SH_UNT , SH_ACS_PPE , SH_FLD_ERR_ADDR_BEYOND_RANGE ); REG64_FLD( PU_FI2C_STAT_ERR_ADDR_OVERLAP , 20 , SH_UNT , SH_ACS_PPE , SH_FLD_ERR_ADDR_OVERLAP ); REG64_FLD( PU_FI2C_STAT_PIB_ABORT , 21 , SH_UNT , SH_ACS_PPE , SH_FLD_PIB_ABORT ); REG64_FLD( PU_FI2C_STAT_TIMEOUT_ON_I2C_STATUS_RD , 22 , SH_UNT , SH_ACS_PPE , SH_FLD_TIMEOUT_ON_I2C_STATUS_RD ); REG64_FLD( PU_FI2C_STAT_RESERVED_FOR_ERRS , 23 , SH_UNT , SH_ACS_PPE , SH_FLD_RESERVED_FOR_ERRS ); REG64_FLD( PU_FI2C_STAT_RESERVED_FOR_ERRS_LEN , 9 , SH_UNT , SH_ACS_PPE , SH_FLD_RESERVED_FOR_ERRS_LEN ); REG64_FLD( PU_FI2C_STAT_LOCKED_PIBM_ADDR , 32 , SH_UNT , SH_ACS_PPE , SH_FLD_LOCKED_PIBM_ADDR ); REG64_FLD( PU_FI2C_STAT_LOCKED_PIBM_ADDR_LEN , 8 , SH_UNT , SH_ACS_PPE , SH_FLD_LOCKED_PIBM_ADDR_LEN ); REG64_FLD( PU_FI2C_STAT_LOCKED_FSM_RESET_ONGOING , 40 , SH_UNT , SH_ACS_PPE , SH_FLD_LOCKED_FSM_RESET_ONGOING ); REG64_FLD( PU_FI2C_STAT_RESERVED_FOR_ADDRESS , 41 , SH_UNT , SH_ACS_PPE , SH_FLD_RESERVED_FOR_ADDRESS ); REG64_FLD( PU_FI2C_STAT_RESERVED_FOR_ADDRESS_LEN , 2 , SH_UNT , SH_ACS_PPE , SH_FLD_RESERVED_FOR_ADDRESS_LEN ); REG64_FLD( PU_FI2C_STAT_LOCKED_FSM_STATE , 43 , SH_UNT , SH_ACS_PPE , SH_FLD_LOCKED_FSM_STATE ); REG64_FLD( PU_FI2C_STAT_LOCKED_FSM_STATE_LEN , 5 , SH_UNT , SH_ACS_PPE , SH_FLD_LOCKED_FSM_STATE_LEN ); REG64_FLD( PU_FI2C_STAT_LOCKED_SEEPROM_ADDRESS , 48 , SH_UNT , SH_ACS_PPE , SH_FLD_LOCKED_SEEPROM_ADDRESS ); REG64_FLD( PU_FI2C_STAT_LOCKED_SEEPROM_ADDRESS_LEN , 16 , SH_UNT , SH_ACS_PPE , SH_FLD_LOCKED_SEEPROM_ADDRESS_LEN ); REG64_FLD( PU_FIFO1_REGISTER_READ_B_FIFO_BITS_READ0_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_0 ); REG64_FLD( PU_FIFO1_REGISTER_READ_B_FIFO_BITS_READ0_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_0_LEN ); REG64_FLD( PU_FIFO1_REGISTER_READ_B_PEEK_DATA1_0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0 ); REG64_FLD( PU_FIFO1_REGISTER_READ_B_PEEK_DATA1_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0_LEN ); REG64_FLD( PU_FIFO1_REGISTER_READ_B_LBUS_PARITY_ERR1_0 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_0 ); REG64_FLD( PU_FIFO1_REGISTER_READ_C_FIFO_BITS_READ0_1 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_1 ); REG64_FLD( PU_FIFO1_REGISTER_READ_C_FIFO_BITS_READ0_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_1_LEN ); REG64_FLD( PU_FIFO1_REGISTER_READ_C_PEEK_DATA1_1 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1 ); REG64_FLD( PU_FIFO1_REGISTER_READ_C_PEEK_DATA1_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1_LEN ); REG64_FLD( PU_FIFO1_REGISTER_READ_C_LBUS_PARITY_ERR1_1 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_1 ); REG64_FLD( PU_FIFO1_REGISTER_READ_D_FIFO_BITS_READ0_2 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_2 ); REG64_FLD( PU_FIFO1_REGISTER_READ_D_FIFO_BITS_READ0_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_2_LEN ); REG64_FLD( PU_FIFO1_REGISTER_READ_D_PEEK_DATA1_2 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2 ); REG64_FLD( PU_FIFO1_REGISTER_READ_D_PEEK_DATA1_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2_LEN ); REG64_FLD( PU_FIFO1_REGISTER_READ_D_LBUS_PARITY_ERR1_2 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_2 ); REG64_FLD( PU_FIFO1_REGISTER_READ_E_FIFO_BITS_READ0_3 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_3 ); REG64_FLD( PU_FIFO1_REGISTER_READ_E_FIFO_BITS_READ0_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_3_LEN ); REG64_FLD( PU_FIFO1_REGISTER_READ_E_PEEK_DATA1_3 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3 ); REG64_FLD( PU_FIFO1_REGISTER_READ_E_PEEK_DATA1_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3_LEN ); REG64_FLD( PU_FIFO1_REGISTER_READ_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ0_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_0 ); REG64_FLD( PU_FIFO4_REGISTER_READ_B_FIFO_BITS_READ0_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_0_LEN ); REG64_FLD( PU_FIFO4_REGISTER_READ_B_PEEK_DATA1_0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0 ); REG64_FLD( PU_FIFO4_REGISTER_READ_B_PEEK_DATA1_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0_LEN ); REG64_FLD( PU_FIFO4_REGISTER_READ_B_LBUS_PARITY_ERR1_0 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_0 ); REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ0_1 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_1 ); REG64_FLD( PU_FIFO4_REGISTER_READ_C_FIFO_BITS_READ0_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_1_LEN ); REG64_FLD( PU_FIFO4_REGISTER_READ_C_PEEK_DATA1_1 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1 ); REG64_FLD( PU_FIFO4_REGISTER_READ_C_PEEK_DATA1_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1_LEN ); REG64_FLD( PU_FIFO4_REGISTER_READ_C_LBUS_PARITY_ERR1_1 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_1 ); REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ0_2 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_2 ); REG64_FLD( PU_FIFO4_REGISTER_READ_D_FIFO_BITS_READ0_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_2_LEN ); REG64_FLD( PU_FIFO4_REGISTER_READ_D_PEEK_DATA1_2 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2 ); REG64_FLD( PU_FIFO4_REGISTER_READ_D_PEEK_DATA1_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2_LEN ); REG64_FLD( PU_FIFO4_REGISTER_READ_D_LBUS_PARITY_ERR1_2 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_2 ); REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ0_3 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_3 ); REG64_FLD( PU_FIFO4_REGISTER_READ_E_FIFO_BITS_READ0_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_BITS_READ0_3_LEN ); REG64_FLD( PU_FIFO4_REGISTER_READ_E_PEEK_DATA1_3 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3 ); REG64_FLD( PU_FIFO4_REGISTER_READ_E_PEEK_DATA1_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3_LEN ); REG64_FLD( PU_FIFO4_REGISTER_READ_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); REG64_FLD( CAPP_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_CAPP , SH_ACS_SCOM_RO , SH_FLD_ACTION0 ); REG64_FLD( CAPP_FIR_ACTION0_REG_ACTION0_LEN , 52 , SH_UNT_CAPP , SH_ACS_SCOM_RO , SH_FLD_ACTION0_LEN ); REG64_FLD( PEC_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_ACTION0 ); REG64_FLD( PEC_FIR_ACTION0_REG_ACTION0_LEN , 37 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_ACTION0_LEN ); REG64_FLD( PU_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( PU_FIR_ACTION0_REG_ACTION0_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); REG64_FLD( PU_NPU_MSC_SM0_FIR_ACTION0_REG_0_0 , 0 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_RW , SH_FLD_0 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_ACTION0_REG_0_0_LEN , 64 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_RW , SH_FLD_0_LEN ); REG64_FLD( PU_NPU_MSC_SM2_FIR_ACTION0_REG_1_1 , 0 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM_RW , SH_FLD_1 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_ACTION0_REG_1_1_LEN , 64 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM_RW , SH_FLD_1_LEN ); REG64_FLD( CAPP_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_CAPP , SH_ACS_SCOM_RO , SH_FLD_ACTION1 ); REG64_FLD( CAPP_FIR_ACTION1_REG_ACTION1_LEN , 52 , SH_UNT_CAPP , SH_ACS_SCOM_RO , SH_FLD_ACTION1_LEN ); REG64_FLD( PEC_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_ACTION1 ); REG64_FLD( PEC_FIR_ACTION1_REG_ACTION1_LEN , 37 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_ACTION1_LEN ); REG64_FLD( PU_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); REG64_FLD( PU_FIR_ACTION1_REG_ACTION1_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); REG64_FLD( PU_NPU_MSC_SM0_FIR_ACTION1_REG_0_0 , 0 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_RW , SH_FLD_0 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_ACTION1_REG_0_0_LEN , 64 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_RW , SH_FLD_0_LEN ); REG64_FLD( PU_NPU_MSC_SM2_FIR_ACTION1_REG_1_1 , 0 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM_RW , SH_FLD_1 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_ACTION1_REG_1_1_LEN , 64 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM_RW , SH_FLD_1_LEN ); REG64_FLD( PEC_FIR_MASK_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN0 ); REG64_FLD( PEC_FIR_MASK_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN1 ); REG64_FLD( PEC_FIR_MASK_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN2 ); REG64_FLD( PEC_FIR_MASK_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN3 ); REG64_FLD( PEC_FIR_MASK_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN4 ); REG64_FLD( PEC_FIR_MASK_IN5 , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN5 ); REG64_FLD( PEC_FIR_MASK_IN6 , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN6 ); REG64_FLD( PEC_FIR_MASK_IN6_LEN , 20 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN6_LEN ); REG64_FLD( PEC_FIR_MASK_IN26 , 26 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN26 ); REG64_FLD( CAPP_FIR_MASK_REG_BAR_PE , 0 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_BAR_PE ); REG64_FLD( CAPP_FIR_MASK_REG_REGISTER_PE , 1 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_REGISTER_PE ); REG64_FLD( CAPP_FIR_MASK_REG_MASTER_ARRAY_CE , 2 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_MASTER_ARRAY_CE ); REG64_FLD( CAPP_FIR_MASK_REG_MASTER_ARRAY_UE , 3 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_MASTER_ARRAY_UE ); REG64_FLD( CAPP_FIR_MASK_REG_TIMER_EXPIRED_RECOV_ERROR , 4 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_TIMER_EXPIRED_RECOV_ERROR ); REG64_FLD( CAPP_FIR_MASK_REG_TIMER_EXPIRED_XSTOP_ERROR , 5 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_TIMER_EXPIRED_XSTOP_ERROR ); REG64_FLD( CAPP_FIR_MASK_REG_PSL_CMD_UE , 6 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_PSL_CMD_UE ); REG64_FLD( CAPP_FIR_MASK_REG_PSL_CMD_SUE , 7 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_PSL_CMD_SUE ); REG64_FLD( CAPP_FIR_MASK_REG_SNOOP_ARRAY_CE , 8 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SNOOP_ARRAY_CE ); REG64_FLD( CAPP_FIR_MASK_REG_SNOOP_ARRAY_UE , 9 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SNOOP_ARRAY_UE ); REG64_FLD( CAPP_FIR_MASK_REG_RECOVERY_FAILED , 10 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_RECOVERY_FAILED ); REG64_FLD( CAPP_FIR_MASK_REG_ILLEGAL_LPC_BAR_ACCESS , 11 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_ILLEGAL_LPC_BAR_ACCESS ); REG64_FLD( CAPP_FIR_MASK_REG_XPT_RECOVERABLE_ERROR , 12 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_XPT_RECOVERABLE_ERROR ); REG64_FLD( CAPP_FIR_MASK_REG_MASTER_RECOVERABLE_ERROR , 13 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_MASTER_RECOVERABLE_ERROR ); REG64_FLD( CAPP_FIR_MASK_REG_SNOOPER_RECOVERABLE_ERROR , 14 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SNOOPER_RECOVERABLE_ERROR ); REG64_FLD( CAPP_FIR_MASK_REG_SECURE_SCOM_ERROR , 15 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SECURE_SCOM_ERROR ); REG64_FLD( CAPP_FIR_MASK_REG_MASTER_SYS_XSTOP_ERROR , 16 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_MASTER_SYS_XSTOP_ERROR ); REG64_FLD( CAPP_FIR_MASK_REG_SNOOPER_SYS_XSTOP_ERROR , 17 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SNOOPER_SYS_XSTOP_ERROR ); REG64_FLD( CAPP_FIR_MASK_REG_XPT_SYS_XSTOP_ERROR , 18 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_XPT_SYS_XSTOP_ERROR ); REG64_FLD( CAPP_FIR_MASK_REG_MUOP_ERROR_1 , 19 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_MUOP_ERROR_1 ); REG64_FLD( CAPP_FIR_MASK_REG_MUOP_ERROR_2 , 20 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_MUOP_ERROR_2 ); REG64_FLD( CAPP_FIR_MASK_REG_MUOP_ERROR_3 , 21 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_MUOP_ERROR_3 ); REG64_FLD( CAPP_FIR_MASK_REG_SUOP_ERROR_1 , 22 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SUOP_ERROR_1 ); REG64_FLD( CAPP_FIR_MASK_REG_SUOP_ERROR_2 , 23 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SUOP_ERROR_2 ); REG64_FLD( CAPP_FIR_MASK_REG_SUOP_ERROR_3 , 24 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SUOP_ERROR_3 ); REG64_FLD( CAPP_FIR_MASK_REG_POWERBUS_MISC_ERROR , 25 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_POWERBUS_MISC_ERROR ); REG64_FLD( CAPP_FIR_MASK_REG_POWERBUS_INTERFACE_PE , 26 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_POWERBUS_INTERFACE_PE ); REG64_FLD( CAPP_FIR_MASK_REG_POWERBUS_DATA_HANG_ERROR , 27 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_POWERBUS_DATA_HANG_ERROR ); REG64_FLD( CAPP_FIR_MASK_REG_POWERBUS_HANG_ERROR , 28 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_POWERBUS_HANG_ERROR ); REG64_FLD( CAPP_FIR_MASK_REG_LD_CLASS_CMD_ADDR_ERR , 29 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_LD_CLASS_CMD_ADDR_ERR ); REG64_FLD( CAPP_FIR_MASK_REG_ST_CLASS_CMD_ADDR_ERR , 30 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_ST_CLASS_CMD_ADDR_ERR ); REG64_FLD( CAPP_FIR_MASK_REG_PHB_LINK_DOWN , 31 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_PHB_LINK_DOWN ); REG64_FLD( CAPP_FIR_MASK_REG_LD_CLASS_CMD_FOREIGN_LINK_FAIL , 32 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_LD_CLASS_CMD_FOREIGN_LINK_FAIL ); REG64_FLD( CAPP_FIR_MASK_REG_FOREIGN_LINK_HANG_ERROR , 33 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_FOREIGN_LINK_HANG_ERROR ); REG64_FLD( CAPP_FIR_MASK_REG_XPT_POWERBUS_CE , 34 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_XPT_POWERBUS_CE ); REG64_FLD( CAPP_FIR_MASK_REG_XPT_POWERBUS_UE , 35 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_XPT_POWERBUS_UE ); REG64_FLD( CAPP_FIR_MASK_REG_XPT_POWERBUS_SUE , 36 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_XPT_POWERBUS_SUE ); REG64_FLD( CAPP_FIR_MASK_REG_TLBI_TIMEOUT , 37 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_TLBI_TIMEOUT ); REG64_FLD( CAPP_FIR_MASK_REG_TLBI_SOT_ERR , 38 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_TLBI_SOT_ERR ); REG64_FLD( CAPP_FIR_MASK_REG_TLBI_BAD_OP_ERR , 39 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_TLBI_BAD_OP_ERR ); REG64_FLD( CAPP_FIR_MASK_REG_TLBI_SEQ_NUM_PARITY_ERR , 40 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_TLBI_SEQ_NUM_PARITY_ERR ); REG64_FLD( CAPP_FIR_MASK_REG_ST_CLASS_CMD_FOREIGN_LINK_FAIL , 41 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_ST_CLASS_CMD_FOREIGN_LINK_FAIL ); REG64_FLD( CAPP_FIR_MASK_REG_TIME_BASE_ERR , 42 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_TIME_BASE_ERR ); REG64_FLD( CAPP_FIR_MASK_REG_TRANSPORT_INFORMATIONAL_ERR , 43 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_TRANSPORT_INFORMATIONAL_ERR ); REG64_FLD( CAPP_FIR_MASK_REG_APC_ARRAY_CMD_CE_ERPT , 44 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_APC_ARRAY_CMD_CE_ERPT ); REG64_FLD( CAPP_FIR_MASK_REG_APC_ARRAY_CMD_UE_ERPT , 45 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_APC_ARRAY_CMD_UE_ERPT ); REG64_FLD( CAPP_FIR_MASK_REG_PSL_CREDIT_TIMEOUT_ERR , 46 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_PSL_CREDIT_TIMEOUT_ERR ); REG64_FLD( CAPP_FIR_MASK_REG_SPARE_2 , 47 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SPARE_2 ); REG64_FLD( CAPP_FIR_MASK_REG_SPARE_3 , 48 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SPARE_3 ); REG64_FLD( CAPP_FIR_MASK_REG_HYPERVISOR , 49 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_HYPERVISOR ); REG64_FLD( CAPP_FIR_MASK_REG_SCOM_ERR2 , 50 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR2 ); REG64_FLD( CAPP_FIR_MASK_REG_SCOM_ERR , 51 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); REG64_FLD( PEC_FIR_MASK_REG_HSSCALERR , 0 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_HSSCALERR ); REG64_FLD( PEC_FIR_MASK_REG_HSSPLLAERR , 1 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_HSSPLLAERR ); REG64_FLD( PEC_FIR_MASK_REG_HSSPLLBERR , 2 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_HSSPLLBERR ); REG64_FLD( PEC_FIR_MASK_REG_TXAERR , 3 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXAERR ); REG64_FLD( PEC_FIR_MASK_REG_TXBERR , 4 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXBERR ); REG64_FLD( PEC_FIR_MASK_REG_TXCERR , 5 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXCERR ); REG64_FLD( PEC_FIR_MASK_REG_TXDERR , 6 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXDERR ); REG64_FLD( PEC_FIR_MASK_REG_TXEERR , 7 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXEERR ); REG64_FLD( PEC_FIR_MASK_REG_TXFERR , 8 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXFERR ); REG64_FLD( PEC_FIR_MASK_REG_TXGERR , 9 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXGERR ); REG64_FLD( PEC_FIR_MASK_REG_TXHERR , 10 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXHERR ); REG64_FLD( PEC_FIR_MASK_REG_TXIERR , 11 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXIERR ); REG64_FLD( PEC_FIR_MASK_REG_TXJERR , 12 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXJERR ); REG64_FLD( PEC_FIR_MASK_REG_TXKERR , 13 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXKERR ); REG64_FLD( PEC_FIR_MASK_REG_TXLERR , 14 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXLERR ); REG64_FLD( PEC_FIR_MASK_REG_TXMERR , 15 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXMERR ); REG64_FLD( PEC_FIR_MASK_REG_TXNERR , 16 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXNERR ); REG64_FLD( PEC_FIR_MASK_REG_TXOERR , 17 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXOERR ); REG64_FLD( PEC_FIR_MASK_REG_TXPERR , 18 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXPERR ); REG64_FLD( PEC_FIR_MASK_REG_RXAERR , 19 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXAERR ); REG64_FLD( PEC_FIR_MASK_REG_RXBERR , 20 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXBERR ); REG64_FLD( PEC_FIR_MASK_REG_RXCERR , 21 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXCERR ); REG64_FLD( PEC_FIR_MASK_REG_RXDERR , 22 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXDERR ); REG64_FLD( PEC_FIR_MASK_REG_RXEERR , 23 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXEERR ); REG64_FLD( PEC_FIR_MASK_REG_RXFERR , 24 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXFERR ); REG64_FLD( PEC_FIR_MASK_REG_RXGERR , 25 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXGERR ); REG64_FLD( PEC_FIR_MASK_REG_RXHERR , 26 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXHERR ); REG64_FLD( PEC_FIR_MASK_REG_RXIERR , 27 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXIERR ); REG64_FLD( PEC_FIR_MASK_REG_RXJERR , 28 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXJERR ); REG64_FLD( PEC_FIR_MASK_REG_RXKERR , 29 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXKERR ); REG64_FLD( PEC_FIR_MASK_REG_RXLERR , 30 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXLERR ); REG64_FLD( PEC_FIR_MASK_REG_RXMERR , 31 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXMERR ); REG64_FLD( PEC_FIR_MASK_REG_RXNERR , 32 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXNERR ); REG64_FLD( PEC_FIR_MASK_REG_RXOERR , 33 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXOERR ); REG64_FLD( PEC_FIR_MASK_REG_RXPERR , 34 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXPERR ); REG64_FLD( PEC_FIR_MASK_REG_SCOM_PERR0 , 35 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PERR0 ); REG64_FLD( PEC_FIR_MASK_REG_SCOM_PERR1 , 36 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PERR1 ); REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED0 , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PSI_RESERVED0 ); REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED1 , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PSI_RESERVED1 ); REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED2 , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PSI_RESERVED2 ); REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED3 , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PSI_RESERVED3 ); REG64_FLD( PU_FIR_MASK_REG_PSI_RESERVED4 , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PSI_RESERVED4 ); REG64_FLD( PU_FIR_MASK_REG_INTERNAL_SCOM_ERROR , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_SCOM_ERROR ); REG64_FLD( PU_FIR_MASK_REG_INTERNAL_SCOM_ERROR_CLONE , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); REG64_FLD( PU_FIR_MASK_REGISTER_ECC_UNCORRECTED_ERR_PIB , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_UNCORRECTED_ERR_PIB ); REG64_FLD( PU_FIR_MASK_REGISTER_BAD_ARRAY_ADDR_PIB , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAD_ARRAY_ADDR_PIB ); REG64_FLD( PU_FIR_MASK_REGISTER_WRT_RST_INTRPT_PIB , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_WRT_RST_INTRPT_PIB ); REG64_FLD( PU_FIR_MASK_REGISTER_RD_RST_INTRPT_PIB , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_RD_RST_INTRPT_PIB ); REG64_FLD( PU_FIR_MASK_REGISTER_ECC_UNCORRECTED_ERR_FACES , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_UNCORRECTED_ERR_FACES ); REG64_FLD( PU_FIR_MASK_REGISTER_BAD_ARRAY_ADDR_FACES , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAD_ARRAY_ADDR_FACES ); REG64_FLD( PU_FIR_MASK_REGISTER_WRT_RST_INTRPT_FACES , 25 , SH_UNT , SH_ACS_SCOM , SH_FLD_WRT_RST_INTRPT_FACES ); REG64_FLD( PU_FIR_MASK_REGISTER_RD_RST_INTRPT_FACES , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_RD_RST_INTRPT_FACES ); REG64_FLD( PU_NPU_MSC_SM0_FIR_MASK_REG_0_0 , 0 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_0 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_MASK_REG_0_0_LEN , 64 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_0_LEN ); REG64_FLD( PU_NPU_MSC_SM2_FIR_MASK_REG_1_1 , 0 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_1 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_MASK_REG_1_1_LEN , 64 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_1_LEN ); REG64_FLD( CAPP_FIR_REG_BAR_PE , 0 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_BAR_PE ); REG64_FLD( CAPP_FIR_REG_REGISTER_PE , 1 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_REGISTER_PE ); REG64_FLD( CAPP_FIR_REG_MASTER_ARRAY_CE , 2 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_MASTER_ARRAY_CE ); REG64_FLD( CAPP_FIR_REG_MASTER_ARRAY_UE , 3 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_MASTER_ARRAY_UE ); REG64_FLD( CAPP_FIR_REG_TIMER_EXPIRED_RECOV_ERROR , 4 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_TIMER_EXPIRED_RECOV_ERROR ); REG64_FLD( CAPP_FIR_REG_TIMER_EXPIRED_XSTOP_ERROR , 5 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_TIMER_EXPIRED_XSTOP_ERROR ); REG64_FLD( CAPP_FIR_REG_PSL_CMD_UE , 6 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_PSL_CMD_UE ); REG64_FLD( CAPP_FIR_REG_PSL_CMD_SUE , 7 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_PSL_CMD_SUE ); REG64_FLD( CAPP_FIR_REG_SNOOP_ARRAY_CE , 8 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SNOOP_ARRAY_CE ); REG64_FLD( CAPP_FIR_REG_SNOOP_ARRAY_UE , 9 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SNOOP_ARRAY_UE ); REG64_FLD( CAPP_FIR_REG_RECOVERY_FAILED , 10 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_RECOVERY_FAILED ); REG64_FLD( CAPP_FIR_REG_ILLEGAL_LPC_BAR_ACCESS , 11 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_ILLEGAL_LPC_BAR_ACCESS ); REG64_FLD( CAPP_FIR_REG_XPT_RECOVERABLE_ERROR , 12 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_XPT_RECOVERABLE_ERROR ); REG64_FLD( CAPP_FIR_REG_MASTER_RECOVERABLE_ERROR , 13 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_MASTER_RECOVERABLE_ERROR ); REG64_FLD( CAPP_FIR_REG_SNOOPER_RECOVERABLE_ERROR , 14 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SNOOPER_RECOVERABLE_ERROR ); REG64_FLD( CAPP_FIR_REG_SECURE_SCOM_ERROR , 15 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SECURE_SCOM_ERROR ); REG64_FLD( CAPP_FIR_REG_MASTER_SYS_XSTOP_ERROR , 16 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_MASTER_SYS_XSTOP_ERROR ); REG64_FLD( CAPP_FIR_REG_SNOOPER_SYS_XSTOP_ERROR , 17 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SNOOPER_SYS_XSTOP_ERROR ); REG64_FLD( CAPP_FIR_REG_XPT_SYS_XSTOP_ERROR , 18 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_XPT_SYS_XSTOP_ERROR ); REG64_FLD( CAPP_FIR_REG_MUOP_ERROR_1 , 19 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_MUOP_ERROR_1 ); REG64_FLD( CAPP_FIR_REG_MUOP_ERROR_2 , 20 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_MUOP_ERROR_2 ); REG64_FLD( CAPP_FIR_REG_MUOP_ERROR_3 , 21 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_MUOP_ERROR_3 ); REG64_FLD( CAPP_FIR_REG_SUOP_ERROR_1 , 22 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SUOP_ERROR_1 ); REG64_FLD( CAPP_FIR_REG_SUOP_ERROR_2 , 23 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SUOP_ERROR_2 ); REG64_FLD( CAPP_FIR_REG_SUOP_ERROR_3 , 24 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SUOP_ERROR_3 ); REG64_FLD( CAPP_FIR_REG_POWERBUS_MISC_ERROR , 25 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_POWERBUS_MISC_ERROR ); REG64_FLD( CAPP_FIR_REG_POWERBUS_INTERFACE_PE , 26 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_POWERBUS_INTERFACE_PE ); REG64_FLD( CAPP_FIR_REG_POWERBUS_DATA_HANG_ERROR , 27 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_POWERBUS_DATA_HANG_ERROR ); REG64_FLD( CAPP_FIR_REG_POWERBUS_HANG_ERROR , 28 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_POWERBUS_HANG_ERROR ); REG64_FLD( CAPP_FIR_REG_LD_CLASS_CMD_ADDR_ERR , 29 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_LD_CLASS_CMD_ADDR_ERR ); REG64_FLD( CAPP_FIR_REG_ST_CLASS_CMD_ADDR_ERR , 30 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_ST_CLASS_CMD_ADDR_ERR ); REG64_FLD( CAPP_FIR_REG_PHB_LINK_DOWN , 31 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_PHB_LINK_DOWN ); REG64_FLD( CAPP_FIR_REG_LD_CLASS_CMD_FOREIGN_LINK_FAIL , 32 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_LD_CLASS_CMD_FOREIGN_LINK_FAIL ); REG64_FLD( CAPP_FIR_REG_FOREIGN_LINK_HANG_ERROR , 33 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_FOREIGN_LINK_HANG_ERROR ); REG64_FLD( CAPP_FIR_REG_XPT_POWERBUS_CE , 34 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_XPT_POWERBUS_CE ); REG64_FLD( CAPP_FIR_REG_XPT_POWERBUS_UE , 35 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_XPT_POWERBUS_UE ); REG64_FLD( CAPP_FIR_REG_XPT_POWERBUS_SUE , 36 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_XPT_POWERBUS_SUE ); REG64_FLD( CAPP_FIR_REG_TLBI_TIMEOUT , 37 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_TLBI_TIMEOUT ); REG64_FLD( CAPP_FIR_REG_TLBI_SOT_ERR , 38 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_TLBI_SOT_ERR ); REG64_FLD( CAPP_FIR_REG_TLBI_BAD_OP_ERR , 39 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_TLBI_BAD_OP_ERR ); REG64_FLD( CAPP_FIR_REG_TLBI_SEQ_NUM_PARITY_ERR , 40 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_TLBI_SEQ_NUM_PARITY_ERR ); REG64_FLD( CAPP_FIR_REG_ST_CLASS_CMD_FOREIGN_LINK_FAIL , 41 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_ST_CLASS_CMD_FOREIGN_LINK_FAIL ); REG64_FLD( CAPP_FIR_REG_TIME_BASE_ERR , 42 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_TIME_BASE_ERR ); REG64_FLD( CAPP_FIR_REG_TRANSPORT_INFORMATIONAL_ERR , 43 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_TRANSPORT_INFORMATIONAL_ERR ); REG64_FLD( CAPP_FIR_REG_APC_ARRAY_CMD_CE_ERPT , 44 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_APC_ARRAY_CMD_CE_ERPT ); REG64_FLD( CAPP_FIR_REG_APC_ARRAY_CMD_UE_ERPT , 45 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_APC_ARRAY_CMD_UE_ERPT ); REG64_FLD( CAPP_FIR_REG_PSL_CREDIT_TIMEOUT_ERR , 46 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_PSL_CREDIT_TIMEOUT_ERR ); REG64_FLD( CAPP_FIR_REG_SPARE_2 , 47 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SPARE_2 ); REG64_FLD( CAPP_FIR_REG_HYPERVISOR , 48 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_HYPERVISOR ); REG64_FLD( CAPP_FIR_REG_SPARE_3 , 49 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SPARE_3 ); REG64_FLD( CAPP_FIR_REG_SCOM_ERR2 , 50 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR2 ); REG64_FLD( CAPP_FIR_REG_SCOM_ERR , 51 , SH_UNT_CAPP , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); REG64_FLD( PU_FIR_REG_PSI_RESERVED0 , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PSI_RESERVED0 ); REG64_FLD( PU_FIR_REG_PSI_RESERVED1 , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PSI_RESERVED1 ); REG64_FLD( PU_FIR_REG_PSI_RESERVED2 , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PSI_RESERVED2 ); REG64_FLD( PU_FIR_REG_PSI_RESERVED3 , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PSI_RESERVED3 ); REG64_FLD( PU_FIR_REG_PSI_RESERVED4 , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PSI_RESERVED4 ); REG64_FLD( PU_FIR_REG_INTERNAL_SCOM_ERROR , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_SCOM_ERROR ); REG64_FLD( PU_FIR_REG_INTERNAL_SCOM_ERROR_CLONE , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_SCOM_ERROR_CLONE ); REG64_FLD( PHB_FIR_REG_AIB_COMMAND_INVALID , 0 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_AIB_COMMAND_INVALID ); REG64_FLD( PHB_FIR_REG_AIB_ADDRESS_INVALID , 1 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_AIB_ADDRESS_INVALID ); REG64_FLD( PHB_FIR_REG_AIB_ACCESS_ERROR , 2 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_AIB_ACCESS_ERROR ); REG64_FLD( PHB_FIR_REG_PAPR_OUTBOUND_INJECT_ERROR , 3 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_PAPR_OUTBOUND_INJECT_ERROR ); REG64_FLD( PHB_FIR_REG_AIB_FATAL_CLASS_ERROR , 4 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_AIB_FATAL_CLASS_ERROR ); REG64_FLD( PHB_FIR_REG_AIB_INF_CLASS_ERROR , 6 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_AIB_INF_CLASS_ERROR ); REG64_FLD( PHB_FIR_REG_PE_STOP_STATE_SIGNALED , 7 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_PE_STOP_STATE_SIGNALED ); REG64_FLD( PHB_FIR_REG_OUT_COMMON_ARRAY_FATAL_ERROR , 8 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_OUT_COMMON_ARRAY_FATAL_ERROR ); REG64_FLD( PHB_FIR_REG_OUT_COMMON_LATCH_FATAL_ERROR , 9 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_OUT_COMMON_LATCH_FATAL_ERROR ); REG64_FLD( PHB_FIR_REG_OUT_COMMON_LOGIC_FATAL_ERROR , 10 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_OUT_COMMON_LOGIC_FATAL_ERROR ); REG64_FLD( PHB_FIR_REG_BLIF_OUT_INTERFACE_PARITY_ERROR , 11 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_BLIF_OUT_INTERFACE_PARITY_ERROR ); REG64_FLD( PHB_FIR_REG_CFG_WRITE_CA_OR_UR_RESPONSE , 12 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_CFG_WRITE_CA_OR_UR_RESPONSE ); REG64_FLD( PHB_FIR_REG_MMIO_REQUEST_TIMEOUT , 13 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_MMIO_REQUEST_TIMEOUT ); REG64_FLD( PHB_FIR_REG_OUT_RRB_SOURCED_ERROR , 14 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_OUT_RRB_SOURCED_ERROR ); REG64_FLD( PHB_FIR_REG_CFG_LOGIC_SIGNALED_ERROR , 15 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_CFG_LOGIC_SIGNALED_ERROR ); REG64_FLD( PHB_FIR_REG_RSB_REQUEST_ADDRESS_ERROR , 16 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_RSB_REQUEST_ADDRESS_ERROR ); REG64_FLD( PHB_FIR_REG_RSB_FDA_FATAL_ERROR , 17 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_RSB_FDA_FATAL_ERROR ); REG64_FLD( PHB_FIR_REG_RSB_FDA_INF_ERROR , 18 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_RSB_FDA_INF_ERROR ); REG64_FLD( PHB_FIR_REG_RSB_FDB_FATAL_ERROR , 19 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_RSB_FDB_FATAL_ERROR ); REG64_FLD( PHB_FIR_REG_RSB_FDB_INF_ERROR , 20 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_RSB_FDB_INF_ERROR ); REG64_FLD( PHB_FIR_REG_RSB_ERR_FATAL_ERROR , 21 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_RSB_ERR_FATAL_ERROR ); REG64_FLD( PHB_FIR_REG_RSB_ERR_INF_ERROR , 22 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_RSB_ERR_INF_ERROR ); REG64_FLD( PHB_FIR_REG_RSB_DBG_FATAL_ERROR , 23 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_RSB_DBG_FATAL_ERROR ); REG64_FLD( PHB_FIR_REG_RSB_DBG_INF_ERROR , 24 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_RSB_DBG_INF_ERROR ); REG64_FLD( PHB_FIR_REG_PCIE_REQUEST_ACCESS_ERROR , 25 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_PCIE_REQUEST_ACCESS_ERROR ); REG64_FLD( PHB_FIR_REG_RSB_BUS_LOGIC_ERROR , 26 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_RSB_BUS_LOGIC_ERROR ); REG64_FLD( PHB_FIR_REG_RSB_UVI_FATAL_ERROR , 27 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_RSB_UVI_FATAL_ERROR ); REG64_FLD( PHB_FIR_REG_RSB_UVI_INF_ERROR , 28 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_RSB_UVI_INF_ERROR ); REG64_FLD( PHB_FIR_REG_SCOM_FATAL_ERROR , 29 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_SCOM_FATAL_ERROR ); REG64_FLD( PHB_FIR_REG_SCOM_INF_ERROR , 30 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_SCOM_INF_ERROR ); REG64_FLD( PHB_FIR_REG_PCIE_MACRO_ERROR_ACTIVE_STATUS , 31 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_PCIE_MACRO_ERROR_ACTIVE_STATUS ); REG64_FLD( PHB_FIR_REG_ARB_IODA_FATAL_ERROR , 32 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_ARB_IODA_FATAL_ERROR ); REG64_FLD( PHB_FIR_REG_ARB_MSI_PE_MATCH_ERROR , 33 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_ARB_MSI_PE_MATCH_ERROR ); REG64_FLD( PHB_FIR_REG_ARB_MSI_ADDRESS_ERROR , 34 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_ARB_MSI_ADDRESS_ERROR ); REG64_FLD( PHB_FIR_REG_ARB_TVT_ERROR , 35 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_ARB_TVT_ERROR ); REG64_FLD( PHB_FIR_REG_ARB_RCVD_FATAL_ERROR_MSG , 36 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_ARB_RCVD_FATAL_ERROR_MSG ); REG64_FLD( PHB_FIR_REG_ARB_RCVD_NONFATAL_ERROR_MSG , 37 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_ARB_RCVD_NONFATAL_ERROR_MSG ); REG64_FLD( PHB_FIR_REG_ARB_RCVD_CORRECTIBLE_ERROR_MSG , 38 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_ARB_RCVD_CORRECTIBLE_ERROR_MSG ); REG64_FLD( PHB_FIR_REG_PAPR_INBOUND_INJECT_ERROR , 39 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_PAPR_INBOUND_INJECT_ERROR ); REG64_FLD( PHB_FIR_REG_ARB_COMMON_FATAL_ERROR , 40 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_ARB_COMMON_FATAL_ERROR ); REG64_FLD( PHB_FIR_REG_ARB_TABLE_BAR_DISABLED_ERROR , 41 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_ARB_TABLE_BAR_DISABLED_ERROR ); REG64_FLD( PHB_FIR_REG_ARB_BLIF_COMPLETION_ERROR , 42 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_ARB_BLIF_COMPLETION_ERROR ); REG64_FLD( PHB_FIR_REG_ARB_PCT_TIMEOUT_ERROR , 43 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_ARB_PCT_TIMEOUT_ERROR ); REG64_FLD( PHB_FIR_REG_ARB_ECC_CORRECTABLE_ERROR , 44 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_ARB_ECC_CORRECTABLE_ERROR ); REG64_FLD( PHB_FIR_REG_ARB_ECC_UNCORRECTABLE_ERROR , 45 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_ARB_ECC_UNCORRECTABLE_ERROR ); REG64_FLD( PHB_FIR_REG_ARB_TLP_POISON_SIGNALED , 46 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_ARB_TLP_POISON_SIGNALED ); REG64_FLD( PHB_FIR_REG_ARB_RTT_PENUM_INVALID_ERROR , 47 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_ARB_RTT_PENUM_INVALID_ERROR ); REG64_FLD( PHB_FIR_REG_MRG_COMMON_FATAL_ERROR , 48 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_MRG_COMMON_FATAL_ERROR ); REG64_FLD( PHB_FIR_REG_MRG_TABLE_BAR_DISABLED_ERROR , 49 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_MRG_TABLE_BAR_DISABLED_ERROR ); REG64_FLD( PHB_FIR_REG_MRG_ECC_CORRECTABLE_ERROR , 50 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_MRG_ECC_CORRECTABLE_ERROR ); REG64_FLD( PHB_FIR_REG_MRG_ECC_UNCORRECTABLE_ERROR , 51 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_MRG_ECC_UNCORRECTABLE_ERROR ); REG64_FLD( PHB_FIR_REG_MRG_AIB2_TX_TIMEOUT_ERROR , 52 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_MRG_AIB2_TX_TIMEOUT_ERROR ); REG64_FLD( PHB_FIR_REG_MRG_MRT_ERROR , 53 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_MRG_MRT_ERROR ); REG64_FLD( PHB_FIR_REG_TCE_IODA_PAGE_ACCESS_ERROR , 56 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_TCE_IODA_PAGE_ACCESS_ERROR ); REG64_FLD( PHB_FIR_REG_TCE_REQUEST_TIMEOUT_ERROR , 57 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_TCE_REQUEST_TIMEOUT_ERROR ); REG64_FLD( PHB_FIR_REG_TCE_UNEXPECTED_RESPONSE_ERROR , 58 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_TCE_UNEXPECTED_RESPONSE_ERROR ); REG64_FLD( PHB_FIR_REG_TCE_COMMON_FATAL_ERROR , 59 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_TCE_COMMON_FATAL_ERROR ); REG64_FLD( PHB_FIR_REG_TCE_ECC_CORRECTABLE_ERROR , 60 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_TCE_ECC_CORRECTABLE_ERROR ); REG64_FLD( PHB_FIR_REG_TCE_ECC_UNCORRECTABLE_ERROR , 61 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_TCE_ECC_UNCORRECTABLE_ERROR ); REG64_FLD( PHB_FIR_REG_INTERNAL_PARITY_ERROR , 63 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_PARITY_ERROR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_ARRAY_CE , 0 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_ARRAY_CE ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_ARRAY_HDR_UE , 1 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_ARRAY_HDR_UE ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_ARRAY_DATA_UE , 2 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_ARRAY_DATA_UE ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_NVL_FLIT_PERR , 3 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_NVL_FLIT_PERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_NVL_DATA_PERR , 4 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_NVL_DATA_PERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_NVL_PKT_MALFOR , 5 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_NVL_PKT_MALFOR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_NVL_PKT_UNSUPPORTED , 6 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_NVL_PKT_UNSUPPORTED ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_NVL_CONFIG_ERR , 7 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_NVL_CONFIG_ERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_NVL_CRC_ERR , 8 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_NVL_CRC_ERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_PRI_ERR , 9 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_PRI_ERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_LOGIC_ERR , 10 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_LOGIC_ERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_LMD_POISON , 11 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_LMD_POISON ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_NTL_ARRAY_DATA_SUE , 12 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_NTL_ARRAY_DATA_SUE ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_ARRAY_CE , 13 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_ARRAY_CE ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_PBUS_RECOV_ERR , 14 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_PBUS_RECOV_ERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_RING_ERR , 15 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_RING_ERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_MMIO_ST_DATA_UE , 16 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_MMIO_ST_DATA_UE ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_PEF , 17 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_PEF ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_NVL_CFG_ERR , 18 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_NVL_CFG_ERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_NVL_FATAL_ERR , 19 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_NVL_FATAL_ERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_RESERVED_1 , 20 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_RESERVED_1 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_ARRAY_UE , 21 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_ARRAY_UE ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_PBUS_PERR , 22 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_PBUS_PERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_PBUS_FATAL_ERR , 23 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_PBUS_FATAL_ERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_PBUS_CONFIG_ERR , 24 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_PBUS_CONFIG_ERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_FWD_PROGRESS_ERR , 25 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_FWD_PROGRESS_ERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_LOGIC_ERR , 26 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_LOGIC_ERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_PEST_DIS , 27 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_PEST_DIS ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_CTL_RSVD_15 , 28 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_CTL_RSVD_15 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_DATA_BE_UE , 29 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_DATA_BE_UE ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_DATA_BE_CE , 30 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_DATA_BE_CE ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_DATA_BE_PERR , 31 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_DATA_BE_PERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_CREG_PERR , 32 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_CREG_PERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_RTAG_PERR , 33 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_RTAG_PERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_STATE_PERR , 34 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_STATE_PERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_LOGIC_ERR , 35 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_LOGIC_ERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_DATA_BE_SUE , 36 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_DATA_BE_SUE ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_PBRX_SUE , 37 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_PBRX_SUE ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_RSVD_9 , 38 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_RSVD_9 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_DAT_RSVD_10 , 39 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_DAT_RSVD_10 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_INT , 40 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_INT ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_SRAM_CE , 41 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_SRAM_CE ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_SRAM_UE , 42 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_SRAM_UE ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_PROTOCOL_CE , 43 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_PROTOCOL_CE ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_PROTOCOL_UE , 44 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_PROTOCOL_UE ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_PBUS_PROTOCOL , 45 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_PBUS_PROTOCOL ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_6 , 46 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_6 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_7 , 47 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_7 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_8 , 48 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_8 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_9 , 49 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_9 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_10 , 50 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_10 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_11 , 51 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_11 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_12 , 52 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_12 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_13 , 53 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_13 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_14 , 54 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_14 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_15 , 55 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_15 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_16 , 56 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_16 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_17 , 57 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_17 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_18 , 58 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_18 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_XTS_RSVD_19 , 59 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_XTS_RSVD_19 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_SCOMSAT00_ERR , 60 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOMSAT00_ERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_SCOMSAT01_ERR , 61 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOMSAT01_ERR ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_PARITY_ERR2 , 62 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERR2 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_REG_0_PARITY_ERR , 63 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERR ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK0_STALL , 0 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK0_STALL ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK0_NOSTALL , 1 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK0_NOSTALL ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK1_STALL , 2 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK1_STALL ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK1_NOSTALL , 3 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK1_NOSTALL ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK2_STALL , 4 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK2_STALL ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK2_NOSTALL , 5 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK2_NOSTALL ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK3_STALL , 6 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK3_STALL ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK3_NOSTALL , 7 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK3_NOSTALL ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK4_STALL , 8 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK4_STALL ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK4_NOSTALL , 9 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK4_NOSTALL ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK5_STALL , 10 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK5_STALL ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_NDL_BRK5_NOSTALL , 11 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_NDL_BRK5_NOSTALL ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_MISC_RING_ERR , 12 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_MISC_RING_ERR ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_MISC_INT_RA_PERR , 13 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_MISC_INT_RA_PERR ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_MISC_DA_ADDR_PERR , 14 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_MISC_DA_ADDR_PERR ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_MISC_CTRL_PERR , 15 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_MISC_CTRL_PERR ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_MISC_NMMU_ERR , 16 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_MISC_NMMU_ERR ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TVT_ENTRY_INVALID , 17 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_TVT_ENTRY_INVALID ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TVT_ADDR_RANGE_ERR , 18 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_TVT_ADDR_RANGE_ERR ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TCE_PAGE_ACCESS_CA_ERR , 19 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_TCE_PAGE_ACCESS_CA_ERR ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TCE_CACHE_MULT_HIT_ERR , 20 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_TCE_CACHE_MULT_HIT_ERR ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TCE_PAGE_ACCESS_TW_ERR , 21 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_TCE_PAGE_ACCESS_TW_ERR ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TCE_REQ_TO_ERR , 22 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_TCE_REQ_TO_ERR ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TCD_PERR , 23 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_TCD_PERR ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TDR_PERR , 24 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_TDR_PERR ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_AT_EA_UE , 25 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_AT_EA_UE ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_AT_EA_CE , 26 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_AT_EA_CE ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_AT_TDRMEM_UE , 27 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_AT_TDRMEM_UE ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_AT_TDRMEM_CE , 28 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_AT_TDRMEM_CE ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_AT_RSPOUT_UE , 29 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_AT_RSPOUT_UE ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_AT_RSPOUT_CE , 30 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_AT_RSPOUT_CE ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_TVT_PERR , 31 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_TVT_PERR ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_IODA_ADDR_PERR , 32 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_IODA_ADDR_PERR ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_NPU_CTRL_PERR , 33 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_NPU_CTRL_PERR ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_NPU_TOR_PERR , 34 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_NPU_TOR_PERR ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_INVAL_IODA_TBL_SEL , 35 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_INVAL_IODA_TBL_SEL ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_ATS_RSVD_19 , 36 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_ATS_RSVD_19 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_37 , 37 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_37 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_38 , 38 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_38 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_39 , 39 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_39 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_40 , 40 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_40 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_41 , 41 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_41 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_42 , 42 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_42 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_43 , 43 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_43 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_44 , 44 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_44 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_45 , 45 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_45 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_46 , 46 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_46 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_47 , 47 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_47 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_48 , 48 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_48 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_49 , 49 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_49 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_50 , 50 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_50 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_51 , 51 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_51 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_52 , 52 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_52 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_53 , 53 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_53 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_54 , 54 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_54 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_55 , 55 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_55 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_56 , 56 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_56 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_57 , 57 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_57 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_58 , 58 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_58 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_59 , 59 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_59 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_60 , 60 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_60 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_FIR1_RSVD_61 , 61 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_FIR1_RSVD_61 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_PARITY_ERR2 , 62 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERR2 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_REG_1_PARITY_ERR , 63 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERR ); REG64_FLD( PEC_FIR_STATUS_REG_HSSCALERR , 0 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_HSSCALERR ); REG64_FLD( PEC_FIR_STATUS_REG_HSSPLLAERR , 1 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_HSSPLLAERR ); REG64_FLD( PEC_FIR_STATUS_REG_HSSPLLBERR , 2 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_HSSPLLBERR ); REG64_FLD( PEC_FIR_STATUS_REG_TXAERR , 3 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXAERR ); REG64_FLD( PEC_FIR_STATUS_REG_TXBERR , 4 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXBERR ); REG64_FLD( PEC_FIR_STATUS_REG_TXCERR , 5 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXCERR ); REG64_FLD( PEC_FIR_STATUS_REG_TXDERR , 6 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXDERR ); REG64_FLD( PEC_FIR_STATUS_REG_TXEERR , 7 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXEERR ); REG64_FLD( PEC_FIR_STATUS_REG_TXFERR , 8 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXFERR ); REG64_FLD( PEC_FIR_STATUS_REG_TXGERR , 9 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXGERR ); REG64_FLD( PEC_FIR_STATUS_REG_TXHERR , 10 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXHERR ); REG64_FLD( PEC_FIR_STATUS_REG_TXIERR , 11 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXIERR ); REG64_FLD( PEC_FIR_STATUS_REG_TXJERR , 12 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXJERR ); REG64_FLD( PEC_FIR_STATUS_REG_TXKERR , 13 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXKERR ); REG64_FLD( PEC_FIR_STATUS_REG_TXLERR , 14 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXLERR ); REG64_FLD( PEC_FIR_STATUS_REG_TXMERR , 15 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXMERR ); REG64_FLD( PEC_FIR_STATUS_REG_TXNERR , 16 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXNERR ); REG64_FLD( PEC_FIR_STATUS_REG_TXOERR , 17 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXOERR ); REG64_FLD( PEC_FIR_STATUS_REG_TXPERR , 18 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_TXPERR ); REG64_FLD( PEC_FIR_STATUS_REG_RXAERR , 19 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXAERR ); REG64_FLD( PEC_FIR_STATUS_REG_RXBERR , 20 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXBERR ); REG64_FLD( PEC_FIR_STATUS_REG_RXCERR , 21 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXCERR ); REG64_FLD( PEC_FIR_STATUS_REG_RXDERR , 22 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXDERR ); REG64_FLD( PEC_FIR_STATUS_REG_RXEERR , 23 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXEERR ); REG64_FLD( PEC_FIR_STATUS_REG_RXFERR , 24 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXFERR ); REG64_FLD( PEC_FIR_STATUS_REG_RXGERR , 25 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXGERR ); REG64_FLD( PEC_FIR_STATUS_REG_RXHERR , 26 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXHERR ); REG64_FLD( PEC_FIR_STATUS_REG_RXIERR , 27 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXIERR ); REG64_FLD( PEC_FIR_STATUS_REG_RXJERR , 28 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXJERR ); REG64_FLD( PEC_FIR_STATUS_REG_RXKERR , 29 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXKERR ); REG64_FLD( PEC_FIR_STATUS_REG_RXLERR , 30 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXLERR ); REG64_FLD( PEC_FIR_STATUS_REG_RXMERR , 31 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXMERR ); REG64_FLD( PEC_FIR_STATUS_REG_RXNERR , 32 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXNERR ); REG64_FLD( PEC_FIR_STATUS_REG_RXOERR , 33 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXOERR ); REG64_FLD( PEC_FIR_STATUS_REG_RXPERR , 34 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_RXPERR ); REG64_FLD( PEC_FIR_STATUS_REG_SCOM_PERR0 , 35 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PERR0 ); REG64_FLD( PEC_FIR_STATUS_REG_SCOM_PERR1 , 36 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PERR1 ); REG64_FLD( PEC_FIR_WOF_REG_WOF , 0 , SH_UNT_PEC , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF ); REG64_FLD( PEC_FIR_WOF_REG_WOF_LEN , 37 , SH_UNT_PEC , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LEN ); REG64_FLD( PU_NPU_MSC_SM0_FIR_WOF_REG_0_0 , 0 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_0 ); REG64_FLD( PU_NPU_MSC_SM0_FIR_WOF_REG_0_0_LEN , 64 , SH_UNT_PU_NPU_MSC_SM0, SH_ACS_SCOM_WCLRREG, SH_FLD_0_LEN ); REG64_FLD( PU_NPU_MSC_SM2_FIR_WOF_REG_1_1 , 0 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM_WCLRREG, SH_FLD_1 ); REG64_FLD( PU_NPU_MSC_SM2_FIR_WOF_REG_1_1_LEN , 64 , SH_UNT_PU_NPU_MSC_SM2, SH_ACS_SCOM_WCLRREG, SH_FLD_1_LEN ); REG64_FLD( CAPP_FLUSHCPIG_FLUSH_CP_IG_STATE_MAP , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_FLUSH_CP_IG_STATE_MAP ); REG64_FLD( CAPP_FLUSHCPIG_FLUSH_CP_IG_STATE_MAP_LEN , 32 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_FLUSH_CP_IG_STATE_MAP_LEN ); REG64_FLD( CAPP_FLUSHSHUE_FLUSH_SUE_STATE_MAP , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_FLUSH_SUE_STATE_MAP ); REG64_FLD( CAPP_FLUSHSHUE_FLUSH_SUE_STATE_MAP_LEN , 32 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_FLUSH_SUE_STATE_MAP_LEN ); REG64_FLD( PU_FORCE_ECC_REG_ALTD_DATA_ITAG , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ALTD_DATA_ITAG ); REG64_FLD( PU_FORCE_ECC_REG_ALTD_DATA_TX , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ALTD_DATA_TX ); REG64_FLD( PU_FORCE_ECC_REG_ALTD_DATA_TX_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ALTD_DATA_TX_LEN ); REG64_FLD( PU_FORCE_ECC_REG_ALTD_DATA_TX_OVERWRITE , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ALTD_DATA_TX_OVERWRITE ); REG64_FLD( PU_NPU_CTL_FREEZE_0_CONFIG_0 , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( PU_NPU_CTL_FREEZE_0_CONFIG_0_LEN , 64 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_0_LEN ); REG64_FLD( PU_NPU_CTL_FREEZE_1_CONFIG_1 , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_1 ); REG64_FLD( PU_NPU_CTL_FREEZE_1_CONFIG_1_LEN , 64 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_1_LEN ); REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_00 , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BDF2PE_00 ); REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_01 , 1 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BDF2PE_01 ); REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_02 , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BDF2PE_02 ); REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_10 , 3 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BDF2PE_10 ); REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_11 , 4 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BDF2PE_11 ); REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_12 , 5 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BDF2PE_12 ); REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_20 , 6 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BDF2PE_20 ); REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_21 , 7 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BDF2PE_21 ); REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_22 , 8 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BDF2PE_22 ); REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_30 , 9 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BDF2PE_30 ); REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_31 , 10 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BDF2PE_31 ); REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_32 , 11 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BDF2PE_32 ); REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_40 , 12 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BDF2PE_40 ); REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_41 , 13 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BDF2PE_41 ); REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_42 , 14 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BDF2PE_42 ); REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_50 , 15 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BDF2PE_50 ); REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_51 , 16 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BDF2PE_51 ); REG64_FLD( PU_NPU_CTL_FREEZE_STATE_BDF2PE_52 , 17 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BDF2PE_52 ); REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SBE , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_REQ_RESET_FR_SBE ); REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_REQ_RESET_FR_SP , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_REQ_RESET_FR_SP ); REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_DEQUEUED_EOT_FLAG , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_DEQUEUED_EOT_FLAG ); REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_FULL , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_FULL ); REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EMPTY , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_EMPTY ); REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_ENTRY_COUNT ); REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_ENTRY_COUNT_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_ENTRY_COUNT_LEN ); REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_VALID_FLAGS ); REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_VALID_FLAGS_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_VALID_FLAGS_LEN ); REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_EOT_FLAGS ); REG64_FLD( PU_FSB_DOWNFIFO_STATUS_DNFIFO_FIFO_EOT_FLAGS_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_DNFIFO_FIFO_EOT_FLAGS_LEN ); REG64_FLD( PU_FSB_UPFIFO_STATUS_REQ_RESET_FR_SP , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_REQ_RESET_FR_SP ); REG64_FLD( PU_FSB_UPFIFO_STATUS_REQ_RESET_FR_SBE , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_REQ_RESET_FR_SBE ); REG64_FLD( PU_FSB_UPFIFO_STATUS_DEQUEUED_EOT_FLAG , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_DEQUEUED_EOT_FLAG ); REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_FULL , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_FULL ); REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_EMPTY , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_EMPTY ); REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_ENTRY_COUNT ); REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_ENTRY_COUNT_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_ENTRY_COUNT_LEN ); REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_VALID_FLAGS ); REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_VALID_FLAGS_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_VALID_FLAGS_LEN ); REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_EOT_FLAGS ); REG64_FLD( PU_FSB_UPFIFO_STATUS_FIFO_EOT_FLAGS_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_EOT_FLAGS_LEN ); REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU0_SM0_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM0_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU0_SM0_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU0_SM0_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU1_SM2_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM2_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU1_SM2_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU1_SM2_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU2_SM3_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM3_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU2_SM3_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU2_SM3_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU1_SM3_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM3_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU1_SM3_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU1_SM3_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU0_SM3_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM3_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU0_SM3_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU0_SM3_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU1_SM1_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM1_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU1_SM1_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU1_SM1_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU2_SM2_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM2_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU2_SM2_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU2_SM2_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU2_SM1_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM1_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU2_SM1_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU2_SM1_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU0_SM2_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM2_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU0_SM2_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU0_SM2_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU2_SM0_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM0_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU2_SM0_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU2_SM0_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU0_SM1_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM1_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU0_SM1_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU0_SM1_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU1_SM0_GENID_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM0_GENID_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU1_SM0_GENID_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU1_SM0_GENID_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_GPE0_GPEDBG_EN_DBG , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_DBG ); REG64_FLD( PU_GPE0_GPEDBG_HALT_ON_XSTOP , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_GPE0_GPEDBG_HALT_ON_TRIG , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_HALT_ON_TRIG ); REG64_FLD( PU_GPE0_GPEDBG_RESERVED3 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( PU_GPE0_GPEDBG_EN_INTR_ADDR , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_INTR_ADDR ); REG64_FLD( PU_GPE0_GPEDBG_EN_TRACE_EXTRA , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_TRACE_EXTRA ); REG64_FLD( PU_GPE0_GPEDBG_EN_TRACE_STALL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_TRACE_STALL ); REG64_FLD( PU_GPE0_GPEDBG_EN_WAIT_CYCLES , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_WAIT_CYCLES ); REG64_FLD( PU_GPE0_GPEDBG_EN_FULL_SPEED , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_FULL_SPEED ); REG64_FLD( PU_GPE0_GPEDBG_RESERVED9 , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED9 ); REG64_FLD( PU_GPE0_GPEDBG_TRACE_MODE_SEL , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_GPE0_GPEDBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_MODE_SEL_LEN ); REG64_FLD( PU_GPE0_GPEDBG_RESERVED12_15 , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED12_15 ); REG64_FLD( PU_GPE0_GPEDBG_RESERVED12_15_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_GPE0_GPEDBG_FIR_TRIGGER , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_GPE0_GPEDBG_SPARE , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE ); REG64_FLD( PU_GPE0_GPEDBG_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); REG64_FLD( PU_GPE0_GPEDBG_TRACE_DATA_SEL , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_GPE0_GPEDBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_GPE0_GPEIVPR_IVPR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IVPR ); REG64_FLD( PU_GPE0_GPEIVPR_IVPR_LEN , 23 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IVPR_LEN ); REG64_FLD( PU_GPE0_GPEMACR_MEM_LOW_PRIORITY , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MEM_LOW_PRIORITY ); REG64_FLD( PU_GPE0_GPEMACR_MEM_LOW_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MEM_LOW_PRIORITY_LEN ); REG64_FLD( PU_GPE0_GPEMACR_MEM_HIGH_PRIORITY , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MEM_HIGH_PRIORITY ); REG64_FLD( PU_GPE0_GPEMACR_MEM_HIGH_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MEM_HIGH_PRIORITY_LEN ); REG64_FLD( PU_GPE0_GPEMACR_LOCAL_LOW_PRIORITY , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LOCAL_LOW_PRIORITY ); REG64_FLD( PU_GPE0_GPEMACR_LOCAL_LOW_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LOCAL_LOW_PRIORITY_LEN ); REG64_FLD( PU_GPE0_GPEMACR_LOCAL_HIGH_PRIORITY , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LOCAL_HIGH_PRIORITY ); REG64_FLD( PU_GPE0_GPEMACR_LOCAL_HIGH_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LOCAL_HIGH_PRIORITY_LEN ); REG64_FLD( PU_GPE0_GPEMACR_SRAM_LOW_PRIORITY , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_LOW_PRIORITY ); REG64_FLD( PU_GPE0_GPEMACR_SRAM_LOW_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_LOW_PRIORITY_LEN ); REG64_FLD( PU_GPE0_GPEMACR_SRAM_HIGH_PRIORITY , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_HIGH_PRIORITY ); REG64_FLD( PU_GPE0_GPEMACR_SRAM_HIGH_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_HIGH_PRIORITY_LEN ); REG64_FLD( PU_GPE0_GPENXIXCR_PPE_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR ); REG64_FLD( PU_GPE0_GPENXIXCR_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR_LEN ); REG64_FLD( PU_GPE0_GPESTR_PBASE , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBASE ); REG64_FLD( PU_GPE0_GPESTR_PBASE_LEN , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBASE_LEN ); REG64_FLD( PU_GPE0_GPESTR_SIZE , 29 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SIZE ); REG64_FLD( PU_GPE0_GPESTR_SIZE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SIZE_LEN ); REG64_FLD( PU_GPE0_GPETSEL_FIT_SEL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FIT_SEL ); REG64_FLD( PU_GPE0_GPETSEL_FIT_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FIT_SEL_LEN ); REG64_FLD( PU_GPE0_GPETSEL_WATCHDOG_SEL , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WATCHDOG_SEL ); REG64_FLD( PU_GPE0_GPETSEL_WATCHDOG_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WATCHDOG_SEL_LEN ); REG64_FLD( PU_GPE0_GPEXIEDR_PPE_XIRAMEDR_EDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PPE_XIRAMEDR_EDR ); REG64_FLD( PU_GPE0_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PPE_XIRAMEDR_EDR_LEN ); REG64_FLD( PU_GPE0_GPEXIIR_PPE_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMGA_IR ); REG64_FLD( PU_GPE0_GPEXIIR_PPE_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMGA_IR_LEN ); REG64_FLD( PU_GPE0_GPEXISPRG0_PPE_XIRAMRA_SPRG0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMRA_SPRG0 ); REG64_FLD( PU_GPE0_GPEXISPRG0_PPE_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMRA_SPRG0_LEN ); REG64_FLD( PU_GPE0_GPEXIXCR_PPE_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR ); REG64_FLD( PU_GPE0_GPEXIXCR_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR_LEN ); REG64_FLD( PU_GPE0_GPEXIXSR_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE0_GPEXIXSR_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC_LEN ); REG64_FLD( PU_GPE0_GPEXIXSR_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_WE ); REG64_FLD( PU_GPE0_GPEXIXSR_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_LP ); REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_TAG_ADDR ); REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN , 27 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE0_MIB_XIDCAC_DCACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_ERR ); REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR ); REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); REG64_FLD( PU_GPE0_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID ); REG64_FLD( PU_GPE0_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID_LEN ); REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_ADDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR_LEN ); REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_R_NW , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_R_NW ); REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_BUSY , 33 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_BUSY ); REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_IMPRECISE_ERROR_PENDING ); REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_BYTE_ENABLE , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_BYTE_ENABLE ); REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_BYTE_ENABLE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_BYTE_ENABLE_LEN ); REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_LINE_MODE , 43 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_LINE_MODE ); REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_ERROR , 49 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ERROR ); REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_ERROR_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ERROR_LEN ); REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_IFETCH_PENDING , 62 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_IFETCH_PENDING ); REG64_FLD( PU_GPE0_MIB_XIMEM_MEM_DATAOP_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_DATAOP_PENDING ); REG64_FLD( PU_GPE0_MIB_XISGB_STORE_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_STORE_ADDRESS ); REG64_FLD( PU_GPE0_MIB_XISGB_STORE_ADDRESS_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_STORE_ADDRESS_LEN ); REG64_FLD( PU_GPE0_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING ); REG64_FLD( PU_GPE0_MIB_XISGB_SGB_BYTE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_BYTE_VALID ); REG64_FLD( PU_GPE0_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_BYTE_VALID_LEN ); REG64_FLD( PU_GPE0_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); REG64_FLD( PU_GPE0_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); REG64_FLD( PU_GPE0_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE0_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); REG64_FLD( PU_GPE0_PPE_XIRAMDBG_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); REG64_FLD( PU_GPE0_PPE_XIRAMDBG_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( PU_GPE0_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0_LEN ); REG64_FLD( PU_GPE0_PPE_XIRAMEDR_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMGA_IR ); REG64_FLD( PU_GPE0_PPE_XIRAMEDR_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMGA_IR_LEN ); REG64_FLD( PU_GPE0_PPE_XIRAMEDR_EDR , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_EDR ); REG64_FLD( PU_GPE0_PPE_XIRAMEDR_EDR_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_EDR_LEN ); REG64_FLD( PU_GPE0_PPE_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_IR ); REG64_FLD( PU_GPE0_PPE_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_IR_LEN ); REG64_FLD( PU_GPE0_PPE_XIRAMGA_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( PU_GPE0_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIRAMRA_SPRG0_LEN ); REG64_FLD( PU_GPE0_PPE_XIRAMRA_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIXCR_XCR ); REG64_FLD( PU_GPE0_PPE_XIRAMRA_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIXCR_XCR_LEN ); REG64_FLD( PU_GPE0_PPE_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_SPRG0 ); REG64_FLD( PU_GPE0_PPE_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_SPRG0_LEN ); REG64_FLD( PU_GPE0_PPE_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XCR ); REG64_FLD( PU_GPE0_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XCR_LEN ); REG64_FLD( PU_GPE1_GPEDBG_EN_DBG , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_DBG ); REG64_FLD( PU_GPE1_GPEDBG_HALT_ON_XSTOP , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_GPE1_GPEDBG_HALT_ON_TRIG , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_HALT_ON_TRIG ); REG64_FLD( PU_GPE1_GPEDBG_RESERVED3 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( PU_GPE1_GPEDBG_EN_INTR_ADDR , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_INTR_ADDR ); REG64_FLD( PU_GPE1_GPEDBG_EN_TRACE_EXTRA , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_TRACE_EXTRA ); REG64_FLD( PU_GPE1_GPEDBG_EN_TRACE_STALL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_TRACE_STALL ); REG64_FLD( PU_GPE1_GPEDBG_EN_WAIT_CYCLES , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_WAIT_CYCLES ); REG64_FLD( PU_GPE1_GPEDBG_EN_FULL_SPEED , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_FULL_SPEED ); REG64_FLD( PU_GPE1_GPEDBG_RESERVED9 , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED9 ); REG64_FLD( PU_GPE1_GPEDBG_TRACE_MODE_SEL , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_GPE1_GPEDBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_MODE_SEL_LEN ); REG64_FLD( PU_GPE1_GPEDBG_RESERVED12_15 , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED12_15 ); REG64_FLD( PU_GPE1_GPEDBG_RESERVED12_15_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_GPE1_GPEDBG_FIR_TRIGGER , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_GPE1_GPEDBG_SPARE , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE ); REG64_FLD( PU_GPE1_GPEDBG_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); REG64_FLD( PU_GPE1_GPEDBG_TRACE_DATA_SEL , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_GPE1_GPEDBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_GPE1_GPEIVPR_IVPR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IVPR ); REG64_FLD( PU_GPE1_GPEIVPR_IVPR_LEN , 23 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IVPR_LEN ); REG64_FLD( PU_GPE1_GPEMACR_MEM_LOW_PRIORITY , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MEM_LOW_PRIORITY ); REG64_FLD( PU_GPE1_GPEMACR_MEM_LOW_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MEM_LOW_PRIORITY_LEN ); REG64_FLD( PU_GPE1_GPEMACR_MEM_HIGH_PRIORITY , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MEM_HIGH_PRIORITY ); REG64_FLD( PU_GPE1_GPEMACR_MEM_HIGH_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MEM_HIGH_PRIORITY_LEN ); REG64_FLD( PU_GPE1_GPEMACR_LOCAL_LOW_PRIORITY , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LOCAL_LOW_PRIORITY ); REG64_FLD( PU_GPE1_GPEMACR_LOCAL_LOW_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LOCAL_LOW_PRIORITY_LEN ); REG64_FLD( PU_GPE1_GPEMACR_LOCAL_HIGH_PRIORITY , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LOCAL_HIGH_PRIORITY ); REG64_FLD( PU_GPE1_GPEMACR_LOCAL_HIGH_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LOCAL_HIGH_PRIORITY_LEN ); REG64_FLD( PU_GPE1_GPEMACR_SRAM_LOW_PRIORITY , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_LOW_PRIORITY ); REG64_FLD( PU_GPE1_GPEMACR_SRAM_LOW_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_LOW_PRIORITY_LEN ); REG64_FLD( PU_GPE1_GPEMACR_SRAM_HIGH_PRIORITY , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_HIGH_PRIORITY ); REG64_FLD( PU_GPE1_GPEMACR_SRAM_HIGH_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_HIGH_PRIORITY_LEN ); REG64_FLD( PU_GPE1_GPENXIXCR_PPE_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR ); REG64_FLD( PU_GPE1_GPENXIXCR_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR_LEN ); REG64_FLD( PU_GPE1_GPESTR_PBASE , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBASE ); REG64_FLD( PU_GPE1_GPESTR_PBASE_LEN , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBASE_LEN ); REG64_FLD( PU_GPE1_GPESTR_SIZE , 29 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SIZE ); REG64_FLD( PU_GPE1_GPESTR_SIZE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SIZE_LEN ); REG64_FLD( PU_GPE1_GPETSEL_FIT_SEL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FIT_SEL ); REG64_FLD( PU_GPE1_GPETSEL_FIT_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FIT_SEL_LEN ); REG64_FLD( PU_GPE1_GPETSEL_WATCHDOG_SEL , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WATCHDOG_SEL ); REG64_FLD( PU_GPE1_GPETSEL_WATCHDOG_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WATCHDOG_SEL_LEN ); REG64_FLD( PU_GPE1_GPEXIEDR_PPE_XIRAMEDR_EDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PPE_XIRAMEDR_EDR ); REG64_FLD( PU_GPE1_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PPE_XIRAMEDR_EDR_LEN ); REG64_FLD( PU_GPE1_GPEXIIR_PPE_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMGA_IR ); REG64_FLD( PU_GPE1_GPEXIIR_PPE_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMGA_IR_LEN ); REG64_FLD( PU_GPE1_GPEXISPRG0_PPE_XIRAMRA_SPRG0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMRA_SPRG0 ); REG64_FLD( PU_GPE1_GPEXISPRG0_PPE_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMRA_SPRG0_LEN ); REG64_FLD( PU_GPE1_GPEXIXCR_PPE_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR ); REG64_FLD( PU_GPE1_GPEXIXCR_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR_LEN ); REG64_FLD( PU_GPE1_GPEXIXSR_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE1_GPEXIXSR_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC_LEN ); REG64_FLD( PU_GPE1_GPEXIXSR_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_WE ); REG64_FLD( PU_GPE1_GPEXIXSR_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_LP ); REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_TAG_ADDR ); REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN , 27 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE1_MIB_XIDCAC_DCACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_ERR ); REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR ); REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); REG64_FLD( PU_GPE1_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID ); REG64_FLD( PU_GPE1_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID_LEN ); REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_ADDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR_LEN ); REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_R_NW , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_R_NW ); REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_BUSY , 33 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_BUSY ); REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_IMPRECISE_ERROR_PENDING ); REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_BYTE_ENABLE , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_BYTE_ENABLE ); REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_BYTE_ENABLE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_BYTE_ENABLE_LEN ); REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_LINE_MODE , 43 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_LINE_MODE ); REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_ERROR , 49 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ERROR ); REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_ERROR_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ERROR_LEN ); REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_IFETCH_PENDING , 62 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_IFETCH_PENDING ); REG64_FLD( PU_GPE1_MIB_XIMEM_MEM_DATAOP_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_DATAOP_PENDING ); REG64_FLD( PU_GPE1_MIB_XISGB_STORE_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_STORE_ADDRESS ); REG64_FLD( PU_GPE1_MIB_XISGB_STORE_ADDRESS_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_STORE_ADDRESS_LEN ); REG64_FLD( PU_GPE1_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING ); REG64_FLD( PU_GPE1_MIB_XISGB_SGB_BYTE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_BYTE_VALID ); REG64_FLD( PU_GPE1_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_BYTE_VALID_LEN ); REG64_FLD( PU_GPE1_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); REG64_FLD( PU_GPE1_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); REG64_FLD( PU_GPE1_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE1_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); REG64_FLD( PU_GPE1_PPE_XIRAMDBG_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); REG64_FLD( PU_GPE1_PPE_XIRAMDBG_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( PU_GPE1_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0_LEN ); REG64_FLD( PU_GPE1_PPE_XIRAMEDR_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMGA_IR ); REG64_FLD( PU_GPE1_PPE_XIRAMEDR_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMGA_IR_LEN ); REG64_FLD( PU_GPE1_PPE_XIRAMEDR_EDR , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_EDR ); REG64_FLD( PU_GPE1_PPE_XIRAMEDR_EDR_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_EDR_LEN ); REG64_FLD( PU_GPE1_PPE_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_IR ); REG64_FLD( PU_GPE1_PPE_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_IR_LEN ); REG64_FLD( PU_GPE1_PPE_XIRAMGA_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( PU_GPE1_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIRAMRA_SPRG0_LEN ); REG64_FLD( PU_GPE1_PPE_XIRAMRA_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIXCR_XCR ); REG64_FLD( PU_GPE1_PPE_XIRAMRA_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIXCR_XCR_LEN ); REG64_FLD( PU_GPE1_PPE_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_SPRG0 ); REG64_FLD( PU_GPE1_PPE_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_SPRG0_LEN ); REG64_FLD( PU_GPE1_PPE_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XCR ); REG64_FLD( PU_GPE1_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XCR_LEN ); REG64_FLD( PU_GPE2_GPEDBG_EN_DBG , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_DBG ); REG64_FLD( PU_GPE2_GPEDBG_HALT_ON_XSTOP , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_GPE2_GPEDBG_HALT_ON_TRIG , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_HALT_ON_TRIG ); REG64_FLD( PU_GPE2_GPEDBG_RESERVED3 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( PU_GPE2_GPEDBG_EN_INTR_ADDR , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_INTR_ADDR ); REG64_FLD( PU_GPE2_GPEDBG_EN_TRACE_EXTRA , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_TRACE_EXTRA ); REG64_FLD( PU_GPE2_GPEDBG_EN_TRACE_STALL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_TRACE_STALL ); REG64_FLD( PU_GPE2_GPEDBG_EN_WAIT_CYCLES , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_WAIT_CYCLES ); REG64_FLD( PU_GPE2_GPEDBG_EN_FULL_SPEED , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_FULL_SPEED ); REG64_FLD( PU_GPE2_GPEDBG_RESERVED9 , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED9 ); REG64_FLD( PU_GPE2_GPEDBG_TRACE_MODE_SEL , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_GPE2_GPEDBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_MODE_SEL_LEN ); REG64_FLD( PU_GPE2_GPEDBG_RESERVED12_15 , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED12_15 ); REG64_FLD( PU_GPE2_GPEDBG_RESERVED12_15_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_GPE2_GPEDBG_FIR_TRIGGER , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_GPE2_GPEDBG_SPARE , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE ); REG64_FLD( PU_GPE2_GPEDBG_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); REG64_FLD( PU_GPE2_GPEDBG_TRACE_DATA_SEL , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_GPE2_GPEDBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_GPE2_GPEIVPR_IVPR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IVPR ); REG64_FLD( PU_GPE2_GPEIVPR_IVPR_LEN , 23 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IVPR_LEN ); REG64_FLD( PU_GPE2_GPEMACR_MEM_LOW_PRIORITY , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MEM_LOW_PRIORITY ); REG64_FLD( PU_GPE2_GPEMACR_MEM_LOW_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MEM_LOW_PRIORITY_LEN ); REG64_FLD( PU_GPE2_GPEMACR_MEM_HIGH_PRIORITY , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MEM_HIGH_PRIORITY ); REG64_FLD( PU_GPE2_GPEMACR_MEM_HIGH_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MEM_HIGH_PRIORITY_LEN ); REG64_FLD( PU_GPE2_GPEMACR_LOCAL_LOW_PRIORITY , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LOCAL_LOW_PRIORITY ); REG64_FLD( PU_GPE2_GPEMACR_LOCAL_LOW_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LOCAL_LOW_PRIORITY_LEN ); REG64_FLD( PU_GPE2_GPEMACR_LOCAL_HIGH_PRIORITY , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LOCAL_HIGH_PRIORITY ); REG64_FLD( PU_GPE2_GPEMACR_LOCAL_HIGH_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LOCAL_HIGH_PRIORITY_LEN ); REG64_FLD( PU_GPE2_GPEMACR_SRAM_LOW_PRIORITY , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_LOW_PRIORITY ); REG64_FLD( PU_GPE2_GPEMACR_SRAM_LOW_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_LOW_PRIORITY_LEN ); REG64_FLD( PU_GPE2_GPEMACR_SRAM_HIGH_PRIORITY , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_HIGH_PRIORITY ); REG64_FLD( PU_GPE2_GPEMACR_SRAM_HIGH_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_HIGH_PRIORITY_LEN ); REG64_FLD( PU_GPE2_GPENXIXCR_PPE_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR ); REG64_FLD( PU_GPE2_GPENXIXCR_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR_LEN ); REG64_FLD( PU_GPE2_GPESTR_PBASE , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBASE ); REG64_FLD( PU_GPE2_GPESTR_PBASE_LEN , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBASE_LEN ); REG64_FLD( PU_GPE2_GPESTR_SIZE , 29 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SIZE ); REG64_FLD( PU_GPE2_GPESTR_SIZE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SIZE_LEN ); REG64_FLD( PU_GPE2_GPETSEL_FIT_SEL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FIT_SEL ); REG64_FLD( PU_GPE2_GPETSEL_FIT_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FIT_SEL_LEN ); REG64_FLD( PU_GPE2_GPETSEL_WATCHDOG_SEL , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WATCHDOG_SEL ); REG64_FLD( PU_GPE2_GPETSEL_WATCHDOG_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WATCHDOG_SEL_LEN ); REG64_FLD( PU_GPE2_GPEXIEDR_PPE_XIRAMEDR_EDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PPE_XIRAMEDR_EDR ); REG64_FLD( PU_GPE2_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PPE_XIRAMEDR_EDR_LEN ); REG64_FLD( PU_GPE2_GPEXIIR_PPE_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMGA_IR ); REG64_FLD( PU_GPE2_GPEXIIR_PPE_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMGA_IR_LEN ); REG64_FLD( PU_GPE2_GPEXISPRG0_PPE_XIRAMRA_SPRG0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMRA_SPRG0 ); REG64_FLD( PU_GPE2_GPEXISPRG0_PPE_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMRA_SPRG0_LEN ); REG64_FLD( PU_GPE2_GPEXIXCR_PPE_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR ); REG64_FLD( PU_GPE2_GPEXIXCR_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR_LEN ); REG64_FLD( PU_GPE2_GPEXIXSR_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE2_GPEXIXSR_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC_LEN ); REG64_FLD( PU_GPE2_GPEXIXSR_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_WE ); REG64_FLD( PU_GPE2_GPEXIXSR_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_LP ); REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_TAG_ADDR ); REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN , 27 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE2_MIB_XIDCAC_DCACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_ERR ); REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR ); REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); REG64_FLD( PU_GPE2_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID ); REG64_FLD( PU_GPE2_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID_LEN ); REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_ADDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR_LEN ); REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_R_NW , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_R_NW ); REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_BUSY , 33 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_BUSY ); REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_IMPRECISE_ERROR_PENDING ); REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_BYTE_ENABLE , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_BYTE_ENABLE ); REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_BYTE_ENABLE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_BYTE_ENABLE_LEN ); REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_LINE_MODE , 43 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_LINE_MODE ); REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_ERROR , 49 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ERROR ); REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_ERROR_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ERROR_LEN ); REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_IFETCH_PENDING , 62 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_IFETCH_PENDING ); REG64_FLD( PU_GPE2_MIB_XIMEM_MEM_DATAOP_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_DATAOP_PENDING ); REG64_FLD( PU_GPE2_MIB_XISGB_STORE_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_STORE_ADDRESS ); REG64_FLD( PU_GPE2_MIB_XISGB_STORE_ADDRESS_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_STORE_ADDRESS_LEN ); REG64_FLD( PU_GPE2_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING ); REG64_FLD( PU_GPE2_MIB_XISGB_SGB_BYTE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_BYTE_VALID ); REG64_FLD( PU_GPE2_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_BYTE_VALID_LEN ); REG64_FLD( PU_GPE2_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); REG64_FLD( PU_GPE2_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); REG64_FLD( PU_GPE2_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE2_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); REG64_FLD( PU_GPE2_PPE_XIRAMDBG_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); REG64_FLD( PU_GPE2_PPE_XIRAMDBG_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( PU_GPE2_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0_LEN ); REG64_FLD( PU_GPE2_PPE_XIRAMEDR_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMGA_IR ); REG64_FLD( PU_GPE2_PPE_XIRAMEDR_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMGA_IR_LEN ); REG64_FLD( PU_GPE2_PPE_XIRAMEDR_EDR , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_EDR ); REG64_FLD( PU_GPE2_PPE_XIRAMEDR_EDR_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_EDR_LEN ); REG64_FLD( PU_GPE2_PPE_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_IR ); REG64_FLD( PU_GPE2_PPE_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_IR_LEN ); REG64_FLD( PU_GPE2_PPE_XIRAMGA_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( PU_GPE2_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIRAMRA_SPRG0_LEN ); REG64_FLD( PU_GPE2_PPE_XIRAMRA_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIXCR_XCR ); REG64_FLD( PU_GPE2_PPE_XIRAMRA_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIXCR_XCR_LEN ); REG64_FLD( PU_GPE2_PPE_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_SPRG0 ); REG64_FLD( PU_GPE2_PPE_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_SPRG0_LEN ); REG64_FLD( PU_GPE2_PPE_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XCR ); REG64_FLD( PU_GPE2_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XCR_LEN ); REG64_FLD( PU_GPE3_GPEDBG_EN_DBG , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_DBG ); REG64_FLD( PU_GPE3_GPEDBG_HALT_ON_XSTOP , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_HALT_ON_XSTOP ); REG64_FLD( PU_GPE3_GPEDBG_HALT_ON_TRIG , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_HALT_ON_TRIG ); REG64_FLD( PU_GPE3_GPEDBG_RESERVED3 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED3 ); REG64_FLD( PU_GPE3_GPEDBG_EN_INTR_ADDR , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_INTR_ADDR ); REG64_FLD( PU_GPE3_GPEDBG_EN_TRACE_EXTRA , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_TRACE_EXTRA ); REG64_FLD( PU_GPE3_GPEDBG_EN_TRACE_STALL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_TRACE_STALL ); REG64_FLD( PU_GPE3_GPEDBG_EN_WAIT_CYCLES , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_WAIT_CYCLES ); REG64_FLD( PU_GPE3_GPEDBG_EN_FULL_SPEED , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_FULL_SPEED ); REG64_FLD( PU_GPE3_GPEDBG_RESERVED9 , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED9 ); REG64_FLD( PU_GPE3_GPEDBG_TRACE_MODE_SEL , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_MODE_SEL ); REG64_FLD( PU_GPE3_GPEDBG_TRACE_MODE_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_MODE_SEL_LEN ); REG64_FLD( PU_GPE3_GPEDBG_RESERVED12_15 , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED12_15 ); REG64_FLD( PU_GPE3_GPEDBG_RESERVED12_15_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED12_15_LEN ); REG64_FLD( PU_GPE3_GPEDBG_FIR_TRIGGER , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIR_TRIGGER ); REG64_FLD( PU_GPE3_GPEDBG_SPARE , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE ); REG64_FLD( PU_GPE3_GPEDBG_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); REG64_FLD( PU_GPE3_GPEDBG_TRACE_DATA_SEL , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_DATA_SEL ); REG64_FLD( PU_GPE3_GPEDBG_TRACE_DATA_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_DATA_SEL_LEN ); REG64_FLD( PU_GPE3_GPEIVPR_IVPR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IVPR ); REG64_FLD( PU_GPE3_GPEIVPR_IVPR_LEN , 23 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IVPR_LEN ); REG64_FLD( PU_GPE3_GPEMACR_MEM_LOW_PRIORITY , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MEM_LOW_PRIORITY ); REG64_FLD( PU_GPE3_GPEMACR_MEM_LOW_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MEM_LOW_PRIORITY_LEN ); REG64_FLD( PU_GPE3_GPEMACR_MEM_HIGH_PRIORITY , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MEM_HIGH_PRIORITY ); REG64_FLD( PU_GPE3_GPEMACR_MEM_HIGH_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MEM_HIGH_PRIORITY_LEN ); REG64_FLD( PU_GPE3_GPEMACR_LOCAL_LOW_PRIORITY , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LOCAL_LOW_PRIORITY ); REG64_FLD( PU_GPE3_GPEMACR_LOCAL_LOW_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LOCAL_LOW_PRIORITY_LEN ); REG64_FLD( PU_GPE3_GPEMACR_LOCAL_HIGH_PRIORITY , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LOCAL_HIGH_PRIORITY ); REG64_FLD( PU_GPE3_GPEMACR_LOCAL_HIGH_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LOCAL_HIGH_PRIORITY_LEN ); REG64_FLD( PU_GPE3_GPEMACR_SRAM_LOW_PRIORITY , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_LOW_PRIORITY ); REG64_FLD( PU_GPE3_GPEMACR_SRAM_LOW_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_LOW_PRIORITY_LEN ); REG64_FLD( PU_GPE3_GPEMACR_SRAM_HIGH_PRIORITY , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_HIGH_PRIORITY ); REG64_FLD( PU_GPE3_GPEMACR_SRAM_HIGH_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRAM_HIGH_PRIORITY_LEN ); REG64_FLD( PU_GPE3_GPENXIXCR_PPE_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR ); REG64_FLD( PU_GPE3_GPENXIXCR_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR_LEN ); REG64_FLD( PU_GPE3_GPESTR_PBASE , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBASE ); REG64_FLD( PU_GPE3_GPESTR_PBASE_LEN , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBASE_LEN ); REG64_FLD( PU_GPE3_GPESTR_SIZE , 29 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SIZE ); REG64_FLD( PU_GPE3_GPESTR_SIZE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SIZE_LEN ); REG64_FLD( PU_GPE3_GPETSEL_FIT_SEL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FIT_SEL ); REG64_FLD( PU_GPE3_GPETSEL_FIT_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FIT_SEL_LEN ); REG64_FLD( PU_GPE3_GPETSEL_WATCHDOG_SEL , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WATCHDOG_SEL ); REG64_FLD( PU_GPE3_GPETSEL_WATCHDOG_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WATCHDOG_SEL_LEN ); REG64_FLD( PU_GPE3_GPEXIEDR_PPE_XIRAMEDR_EDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PPE_XIRAMEDR_EDR ); REG64_FLD( PU_GPE3_GPEXIEDR_PPE_XIRAMEDR_EDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PPE_XIRAMEDR_EDR_LEN ); REG64_FLD( PU_GPE3_GPEXIIR_PPE_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMGA_IR ); REG64_FLD( PU_GPE3_GPEXIIR_PPE_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMGA_IR_LEN ); REG64_FLD( PU_GPE3_GPEXISPRG0_PPE_XIRAMRA_SPRG0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMRA_SPRG0 ); REG64_FLD( PU_GPE3_GPEXISPRG0_PPE_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PPE_XIRAMRA_SPRG0_LEN ); REG64_FLD( PU_GPE3_GPEXIXCR_PPE_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR ); REG64_FLD( PU_GPE3_GPEXIXCR_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_PPE_XIXCR_XCR_LEN ); REG64_FLD( PU_GPE3_GPEXIXSR_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE3_GPEXIXSR_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_SIBRC_LEN ); REG64_FLD( PU_GPE3_GPEXIXSR_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_WE ); REG64_FLD( PU_GPE3_GPEXIXSR_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_NULL_MSR_LP ); REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_TAG_ADDR ); REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_TAG_ADDR_LEN , 27 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE3_MIB_XIDCAC_DCACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DCACHE_ERR ); REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR ); REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); REG64_FLD( PU_GPE3_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID ); REG64_FLD( PU_GPE3_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID_LEN ); REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_ADDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR_LEN ); REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_R_NW , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_R_NW ); REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_BUSY , 33 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_BUSY ); REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_IMPRECISE_ERROR_PENDING ); REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_BYTE_ENABLE , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_BYTE_ENABLE ); REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_BYTE_ENABLE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_BYTE_ENABLE_LEN ); REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_LINE_MODE , 43 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_LINE_MODE ); REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_ERROR , 49 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ERROR ); REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_ERROR_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ERROR_LEN ); REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_IFETCH_PENDING , 62 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_IFETCH_PENDING ); REG64_FLD( PU_GPE3_MIB_XIMEM_MEM_DATAOP_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_DATAOP_PENDING ); REG64_FLD( PU_GPE3_MIB_XISGB_STORE_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_STORE_ADDRESS ); REG64_FLD( PU_GPE3_MIB_XISGB_STORE_ADDRESS_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_STORE_ADDRESS_LEN ); REG64_FLD( PU_GPE3_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING ); REG64_FLD( PU_GPE3_MIB_XISGB_SGB_BYTE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_BYTE_VALID ); REG64_FLD( PU_GPE3_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_BYTE_VALID_LEN ); REG64_FLD( PU_GPE3_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); REG64_FLD( PU_GPE3_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); REG64_FLD( PU_GPE3_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_GPE3_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); REG64_FLD( PU_GPE3_PPE_XIRAMDBG_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); REG64_FLD( PU_GPE3_PPE_XIRAMDBG_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( PU_GPE3_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0_LEN ); REG64_FLD( PU_GPE3_PPE_XIRAMEDR_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMGA_IR ); REG64_FLD( PU_GPE3_PPE_XIRAMEDR_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMGA_IR_LEN ); REG64_FLD( PU_GPE3_PPE_XIRAMEDR_EDR , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_EDR ); REG64_FLD( PU_GPE3_PPE_XIRAMEDR_EDR_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_EDR_LEN ); REG64_FLD( PU_GPE3_PPE_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_IR ); REG64_FLD( PU_GPE3_PPE_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_IR_LEN ); REG64_FLD( PU_GPE3_PPE_XIRAMGA_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( PU_GPE3_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIRAMRA_SPRG0_LEN ); REG64_FLD( PU_GPE3_PPE_XIRAMRA_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIXCR_XCR ); REG64_FLD( PU_GPE3_PPE_XIRAMRA_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIXCR_XCR_LEN ); REG64_FLD( PU_GPE3_PPE_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_SPRG0 ); REG64_FLD( PU_GPE3_PPE_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_SPRG0_LEN ); REG64_FLD( PU_GPE3_PPE_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XCR ); REG64_FLD( PU_GPE3_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XCR_LEN ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP_LEN ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP_LEN ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_RESERVED ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GRANULE ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP_LEN ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP_LEN ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_RESERVED ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GRANULE ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU0_SM0_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP_LEN ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP_LEN ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_RESERVED ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GRANULE ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP_LEN ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP_LEN ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_RESERVED ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GRANULE ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU1_SM2_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP_LEN ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP_LEN ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_RESERVED ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GRANULE ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP_LEN ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP_LEN ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_RESERVED ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GRANULE ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU2_SM3_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP_LEN ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP_LEN ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_RESERVED ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GRANULE ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP_LEN ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP_LEN ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_RESERVED ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GRANULE ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU1_SM3_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP_LEN ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP_LEN ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_RESERVED ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GRANULE ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP_LEN ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP_LEN ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_RESERVED ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GRANULE ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU0_SM3_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP_LEN ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP_LEN ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_RESERVED ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GRANULE ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP_LEN ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP_LEN ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_RESERVED ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GRANULE ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU1_SM1_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP_LEN ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP_LEN ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_RESERVED ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GRANULE ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP_LEN ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP_LEN ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_RESERVED ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GRANULE ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU2_SM2_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP_LEN ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP_LEN ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_RESERVED ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GRANULE ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP_LEN ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP_LEN ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_RESERVED ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GRANULE ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU2_SM1_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP_LEN ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP_LEN ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_RESERVED ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GRANULE ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP_LEN ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP_LEN ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_RESERVED ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GRANULE ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU0_SM2_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP_LEN ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP_LEN ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_RESERVED ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GRANULE ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP_LEN ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP_LEN ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_RESERVED ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GRANULE ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU2_SM0_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP_LEN ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP_LEN ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_RESERVED ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GRANULE ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP_LEN ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP_LEN ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_RESERVED ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GRANULE ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU0_SM1_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_ENABLE , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ENABLE ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MEMTYPE_LEN ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_GROUP , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GROUP_LEN ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_CHIP , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_CHIP_LEN ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_ADDR , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_ADDR_LEN ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_RESERVED , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_RESERVED ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_GRANULE , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_GRANULE ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_SIZE , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_SIZE_LEN ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_MODE , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU0_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU0_MODE_LEN ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_ENABLE , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ENABLE ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_MEMTYPE_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MEMTYPE_LEN ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_GROUP , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GROUP_LEN ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_CHIP , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_CHIP_LEN ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_ADDR , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_ADDR_LEN , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_ADDR_LEN ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_RESERVED , 54 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_RESERVED ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_GRANULE , 55 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_GRANULE ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_SIZE , 56 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_SIZE_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_SIZE_LEN ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_MODE , 60 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE ); REG64_FLD( PU_NPU1_SM0_GPU_BAR_CONFIG_GPU1_MODE_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GPU1_MODE_LEN ); REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN0 ); REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN1 ); REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN2 ); REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN3 ); REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN4 ); REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN5 , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN5 ); REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN6 , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN6 ); REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN7 , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN7 ); REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN8 , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN8 ); REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN9 , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN9 ); REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN10 , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN10 ); REG64_FLD( PEC_GXSTOP0_MASK_REG_GXSTP0_TRIG_IN11 , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP0_TRIG_IN11 ); REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN0 ); REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN1 ); REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN2 ); REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN3 ); REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN4 ); REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN5 , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN5 ); REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN6 , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN6 ); REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN7 , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN7 ); REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN8 , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN8 ); REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN9 , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN9 ); REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN10 , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN10 ); REG64_FLD( PEC_GXSTOP1_MASK_REG_GXSTP1_TRIG_IN11 , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP1_TRIG_IN11 ); REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN0 ); REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN1 ); REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN2 ); REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN3 ); REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN4 ); REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN5 , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN5 ); REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN6 , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN6 ); REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN7 , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN7 ); REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN8 , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN8 ); REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN9 , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN9 ); REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN10 , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN10 ); REG64_FLD( PEC_GXSTOP2_MASK_REG_GXSTP2_TRIG_IN11 , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP2_TRIG_IN11 ); REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP_IN0 ); REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP_IN1 ); REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP_IN2 ); REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP_IN3 ); REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP_IN4 ); REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN5 , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP_IN5 ); REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN6 , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP_IN6 ); REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN7 , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP_IN7 ); REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN8 , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP_IN8 ); REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN9 , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP_IN9 ); REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN10 , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP_IN10 ); REG64_FLD( PEC_GXSTOP_TRIG_REG_GXSTP_IN11 , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GXSTP_IN11 ); REG64_FLD( PU_GZIP_CONTROL_REG_DISABLE_NEAR_HISTORY , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_NEAR_HISTORY ); REG64_FLD( PU_GZIP_CONTROL_REG_DISABLE_FAR_HISTORY , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_FAR_HISTORY ); REG64_FLD( PU_GZIP_CONTROL_REG_DISABLE_EXTRA_HASH_ACCESSES , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_EXTRA_HASH_ACCESSES ); REG64_FLD( PU_GZIP_CONTROL_REG_DISABLE_EXTRA_FIFO_ACCESSES , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_EXTRA_FIFO_ACCESSES ); REG64_FLD( PU_GZIP_CONTROL_REG_HASH_SIZE_MASK , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_HASH_SIZE_MASK ); REG64_FLD( PU_GZIP_CONTROL_REG_HASH_SIZE_MASK_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_HASH_SIZE_MASK_LEN ); REG64_FLD( PU_GZIP_ERRRPT_HOLD_REG_HOLD , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HOLD ); REG64_FLD( PU_GZIP_ERRRPT_HOLD_REG_HOLD_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_HOLD_LEN ); REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LPID ); REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LPID_LEN ); REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_PID ); REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_PID_LEN ); REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_TID ); REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_TID_LEN ); REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_ENABLE ); REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_BAR_PRIORITY , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY ); REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LEN ); REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE , 54 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_SIZE ); REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_SIZE_LEN ); REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_READ_OFFSET ); REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_READ_OFFSET_LEN ); REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_QUEUED ); REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_QUEUED_LEN ); REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_PRIMAX ); REG64_FLD( PU_GZIP_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX_LEN , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_PRIMAX_LEN ); REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LPID ); REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LPID_LEN ); REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_PID ); REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_PID_LEN ); REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_TID ); REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_TID_LEN ); REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_ENABLE ); REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_BAR_PRIORITY , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY ); REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LEN ); REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE , 54 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_SIZE ); REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_SIZE_LEN ); REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_READ_OFFSET ); REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_READ_OFFSET_LEN ); REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_QUEUED ); REG64_FLD( PU_GZIP_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_QUEUED_LEN ); REG64_FLD( PU_GZIP_MAX_BYTE_CNT_LOW , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LOW ); REG64_FLD( PU_GZIP_MAX_BYTE_CNT_LOW_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LOW_LEN ); REG64_FLD( PU_GZIP_MAX_BYTE_CNT_HIGH , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HIGH ); REG64_FLD( PU_GZIP_MAX_BYTE_CNT_HIGH_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HIGH_LEN ); REG64_FLD( PU_GZIP_MAX_BYTE_CNT_THRESHOLD , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_THRESHOLD ); REG64_FLD( PU_GZIP_MAX_BYTE_CNT_SRC_DDE , 11 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRC_DDE ); REG64_FLD( PU_GZIP_MAX_BYTE_CNT_SRC_DDE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRC_DDE_LEN ); REG64_FLD( PU_GZIP_MAX_BYTE_CNT_TARGET_DDE , 19 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_TARGET_DDE ); REG64_FLD( PU_GZIP_MAX_BYTE_CNT_TARGET_DDE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_TARGET_DDE_LEN ); REG64_FLD( PEC_HANG_PULSE_0_REG_0 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_0 ); REG64_FLD( PEC_HANG_PULSE_0_REG_0_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_0_LEN ); REG64_FLD( PEC_HANG_PULSE_0_REG_SUPPRESS , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( PEC_HANG_PULSE_1_REG_1 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_1 ); REG64_FLD( PEC_HANG_PULSE_1_REG_1_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_1_LEN ); REG64_FLD( PEC_HANG_PULSE_1_REG_SUPPRESS , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( PEC_HANG_PULSE_2_REG_2 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_2 ); REG64_FLD( PEC_HANG_PULSE_2_REG_2_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_2_LEN ); REG64_FLD( PEC_HANG_PULSE_2_REG_SUPPRESS , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( PEC_HANG_PULSE_3_REG_3 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_3 ); REG64_FLD( PEC_HANG_PULSE_3_REG_3_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_3_LEN ); REG64_FLD( PEC_HANG_PULSE_3_REG_SUPPRESS , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( PEC_HANG_PULSE_4_REG_4 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_4 ); REG64_FLD( PEC_HANG_PULSE_4_REG_4_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_4_LEN ); REG64_FLD( PEC_HANG_PULSE_4_REG_SUPPRESS , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( PEC_HANG_PULSE_5_REG_5 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_5 ); REG64_FLD( PEC_HANG_PULSE_5_REG_5_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_5_LEN ); REG64_FLD( PEC_HANG_PULSE_5_REG_SUPPRESS , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( PEC_HANG_PULSE_6_REG_6 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_6 ); REG64_FLD( PEC_HANG_PULSE_6_REG_6_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_6_LEN ); REG64_FLD( PEC_HANG_PULSE_6_REG_SUPPRESS , 6 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_SUPPRESS ); REG64_FLD( PU_HCA_BAR_ADDR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR ); REG64_FLD( PU_HCA_BAR_ADDR_LEN , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_LEN ); REG64_FLD( PU_HCA_BAR_RANGE , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RANGE ); REG64_FLD( PU_HCA_BAR_RANGE_LEN , 11 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RANGE_LEN ); REG64_FLD( PU_HCA_BAR_PAGE_SIZE_64K , 62 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PAGE_SIZE_64K ); REG64_FLD( PU_HCA_BAR_VALID , 63 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_HCA_COUNT_BAR_ADDR , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR ); REG64_FLD( PU_HCA_COUNT_BAR_ADDR_LEN , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_LEN ); REG64_FLD( PU_HCA_COUNT_BAR_VALID , 63 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_HCA_DROP_PIPE_COUNTER , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PIPE_COUNTER ); REG64_FLD( PU_HCA_DROP_PIPE_COUNTER_LEN , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PIPE_COUNTER_LEN ); REG64_FLD( PU_HCA_DROP_WRITE_COUNTER , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_COUNTER ); REG64_FLD( PU_HCA_DROP_WRITE_COUNTER_LEN , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_COUNTER_LEN ); REG64_FLD( PU_HCA_FLUSH_INDEX , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INDEX ); REG64_FLD( PU_HCA_FLUSH_INDEX_LEN , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INDEX_LEN ); REG64_FLD( PU_HCA_FLUSH_CONG , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CONG ); REG64_FLD( PU_HCA_FLUSH_CONG_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CONG_LEN ); REG64_FLD( PU_HCA_FLUSH_COUNT , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_COUNT ); REG64_FLD( PU_HCA_FLUSH_COUNT_LEN , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_COUNT_LEN ); REG64_FLD( PU_HCA_MIRROR_BAR_ADDR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR ); REG64_FLD( PU_HCA_MIRROR_BAR_ADDR_LEN , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_LEN ); REG64_FLD( PU_HCA_MIRROR_BAR_VALID , 63 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_HCA_MODES_FULLMASK , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FULLMASK ); REG64_FLD( PU_HCA_MODES_FULLMASK_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FULLMASK_LEN ); REG64_FLD( PU_HCA_MODES_ERROR_INJECT , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJECT ); REG64_FLD( PU_HCA_MODES_ERROR_INJECT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJECT_LEN ); REG64_FLD( PU_HCA_REF_BAR_ADDR , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR ); REG64_FLD( PU_HCA_REF_BAR_ADDR_LEN , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_LEN ); REG64_FLD( PU_HCA_REF_BAR_VALID , 63 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PEC_HEARTBEAT_REG_DEAD , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DEAD ); REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU0_SM0_HIGH_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU0_SM0_HIGH_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM0_HIGH_WATER_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU1_SM2_HIGH_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU1_SM2_HIGH_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM2_HIGH_WATER_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU2_SM3_HIGH_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU2_SM3_HIGH_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM3_HIGH_WATER_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU1_SM3_HIGH_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU1_SM3_HIGH_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM3_HIGH_WATER_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU0_SM3_HIGH_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU0_SM3_HIGH_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM3_HIGH_WATER_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU1_SM1_HIGH_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU1_SM1_HIGH_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM1_HIGH_WATER_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU2_SM2_HIGH_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU2_SM2_HIGH_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM2_HIGH_WATER_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU2_SM1_HIGH_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU2_SM1_HIGH_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM1_HIGH_WATER_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU0_SM2_HIGH_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU0_SM2_HIGH_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM2_HIGH_WATER_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU2_SM0_HIGH_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU2_SM0_HIGH_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM0_HIGH_WATER_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU0_SM1_HIGH_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU0_SM1_HIGH_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM1_HIGH_WATER_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU1_SM0_HIGH_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU1_SM0_HIGH_WATER_RESERVED1 , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM0_HIGH_WATER_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PEC_HOSTATTN_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN0 ); REG64_FLD( PEC_HOSTATTN_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN1 ); REG64_FLD( PEC_HOSTATTN_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN2 ); REG64_FLD( PEC_HOSTATTN_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN3 ); REG64_FLD( PEC_HOSTATTN_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN4 ); REG64_FLD( PEC_HOSTATTN_IN5 , 5 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN5 ); REG64_FLD( PEC_HOSTATTN_IN6 , 6 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN6 ); REG64_FLD( PEC_HOSTATTN_IN7 , 7 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN7 ); REG64_FLD( PEC_HOSTATTN_IN8 , 8 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN8 ); REG64_FLD( PEC_HOSTATTN_IN9 , 9 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN9 ); REG64_FLD( PEC_HOSTATTN_IN10 , 10 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN10 ); REG64_FLD( PEC_HOSTATTN_IN11 , 11 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN11 ); REG64_FLD( PEC_HOSTATTN_IN12 , 12 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN12 ); REG64_FLD( PEC_HOSTATTN_IN13 , 13 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN13 ); REG64_FLD( PEC_HOSTATTN_IN14 , 14 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN14 ); REG64_FLD( PEC_HOSTATTN_IN15 , 15 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN15 ); REG64_FLD( PEC_HOSTATTN_IN16 , 16 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN16 ); REG64_FLD( PEC_HOSTATTN_IN17 , 17 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN17 ); REG64_FLD( PEC_HOSTATTN_IN18 , 18 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN18 ); REG64_FLD( PEC_HOSTATTN_IN19 , 19 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN19 ); REG64_FLD( PEC_HOSTATTN_IN20 , 20 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN20 ); REG64_FLD( PEC_HOSTATTN_IN21 , 21 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN21 ); REG64_FLD( PEC_HOSTATTN_IN22 , 22 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN22 ); REG64_FLD( PEC_HOSTATTN_MASK_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( PEC_HOSTATTN_MASK_IN_LEN , 22 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO , 0 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_OPER_HANG_DIV_RATIO ); REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO_LEN , 5 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_OPER_HANG_DIV_RATIO_LEN ); REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_RTY_DRP_COUNT , 5 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_RTY_DRP_COUNT ); REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_RTY_DRP_COUNT_LEN , 4 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_RTY_DRP_COUNT_LEN ); REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_DIS_DRP_PRIORITY_INCR , 9 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DIS_DRP_PRIORITY_INCR ); REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_DIS_RETRY_BACKOFF , 10 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DIS_RETRY_BACKOFF ); REG64_FLD( PU_HTM0_HTM_CFG_HTMSC_DIS_OPER_HANG , 11 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DIS_OPER_HANG ); REG64_FLD( PU_HTM1_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO , 0 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_OPER_HANG_DIV_RATIO ); REG64_FLD( PU_HTM1_HTM_CFG_HTMSC_OPER_HANG_DIV_RATIO_LEN , 5 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_OPER_HANG_DIV_RATIO_LEN ); REG64_FLD( PU_HTM1_HTM_CFG_HTMSC_RTY_DRP_COUNT , 5 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_RTY_DRP_COUNT ); REG64_FLD( PU_HTM1_HTM_CFG_HTMSC_RTY_DRP_COUNT_LEN , 4 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_RTY_DRP_COUNT_LEN ); REG64_FLD( PU_HTM1_HTM_CFG_HTMSC_DIS_DRP_PRIORITY_INCR , 9 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DIS_DRP_PRIORITY_INCR ); REG64_FLD( PU_HTM1_HTM_CFG_HTMSC_DIS_RETRY_BACKOFF , 10 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DIS_RETRY_BACKOFF ); REG64_FLD( PU_HTM1_HTM_CFG_HTMSC_DIS_OPER_HANG , 11 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DIS_OPER_HANG ); REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_TRIG , 0 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_TRIG ); REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_TRIG_LEN , 2 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_TRIG_LEN ); REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_MARK , 4 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARK ); REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_MARK_LEN , 2 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARK_LEN ); REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_DBG0_STOP , 6 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DBG0_STOP ); REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_DBG1_STOP , 7 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DBG1_STOP ); REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_RUN_STOP , 8 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_RUN_STOP ); REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_OTHER_DBG0_STOP , 9 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_OTHER_DBG0_STOP ); REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_SPARE1012 , 10 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE1012 ); REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_SPARE1012_LEN , 3 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE1012_LEN ); REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_XSTOP_STOP , 13 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_XSTOP_STOP ); REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_SPARE1415 , 14 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE1415 ); REG64_FLD( PU_HTM0_HTM_CTRL_HTMSC_SPARE1415_LEN , 2 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE1415_LEN ); REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_TRIG , 0 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_TRIG ); REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_TRIG_LEN , 2 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_TRIG_LEN ); REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_MARK , 4 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARK ); REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_MARK_LEN , 2 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARK_LEN ); REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_DBG0_STOP , 6 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DBG0_STOP ); REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_DBG1_STOP , 7 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DBG1_STOP ); REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_RUN_STOP , 8 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_RUN_STOP ); REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_OTHER_DBG0_STOP , 9 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_OTHER_DBG0_STOP ); REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_SPARE1012 , 10 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE1012 ); REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_SPARE1012_LEN , 3 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE1012_LEN ); REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_XSTOP_STOP , 13 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_XSTOP_STOP ); REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_SPARE1415 , 14 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE1415 ); REG64_FLD( PU_HTM1_HTM_CTRL_HTMSC_SPARE1415_LEN , 2 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE1415_LEN ); REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_PAT , 0 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_PAT ); REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_PAT_LEN , 23 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_PAT_LEN ); REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_CRESP_PAT , 27 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CRESP_PAT ); REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_CRESP_PAT_LEN , 5 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CRESP_PAT_LEN ); REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_MASK , 32 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MASK ); REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_MASK_LEN , 23 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MASK_LEN ); REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_CRESP_MASK , 59 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CRESP_MASK ); REG64_FLD( PU_HTM0_HTM_FILT_HTMSC_CRESP_MASK_LEN , 5 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CRESP_MASK_LEN ); REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_PAT , 0 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_PAT ); REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_PAT_LEN , 23 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_PAT_LEN ); REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_CRESP_PAT , 27 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CRESP_PAT ); REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_CRESP_PAT_LEN , 5 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CRESP_PAT_LEN ); REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_MASK , 32 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MASK ); REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_MASK_LEN , 23 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MASK_LEN ); REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_CRESP_MASK , 59 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CRESP_MASK ); REG64_FLD( PU_HTM1_HTM_FILT_HTMSC_CRESP_MASK_LEN , 5 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CRESP_MASK_LEN ); REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL0 , 0 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL0 ); REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL0_LEN , 4 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL0_LEN ); REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL1 , 4 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL1 ); REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL1_LEN , 4 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL1_LEN ); REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL2 , 8 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL2 ); REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL2_LEN , 4 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL2_LEN ); REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL3 , 12 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL3 ); REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL3_LEN , 4 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL3_LEN ); REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL4 , 16 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL4 ); REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL4_LEN , 4 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL4_LEN ); REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL5 , 20 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL5 ); REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_RGRPSEL5_LEN , 4 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL5_LEN ); REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL0 , 24 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_CGRPSEL0 ); REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL0_LEN , 4 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_CGRPSEL0_LEN ); REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL1 , 28 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_CGRPSEL1 ); REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL1_LEN , 4 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_CGRPSEL1_LEN ); REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL2 , 32 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_CGRPSEL2 ); REG64_FLD( PU_HTM0_HTM_FLEX_HTMSC_FMUX_CGRPSEL2_LEN , 4 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_CGRPSEL2_LEN ); REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL0 , 0 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL0 ); REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL0_LEN , 4 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL0_LEN ); REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL1 , 4 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL1 ); REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL1_LEN , 4 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL1_LEN ); REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL2 , 8 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL2 ); REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL2_LEN , 4 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL2_LEN ); REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL3 , 12 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL3 ); REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL3_LEN , 4 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL3_LEN ); REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL4 , 16 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL4 ); REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL4_LEN , 4 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL4_LEN ); REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL5 , 20 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL5 ); REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_RGRPSEL5_LEN , 4 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_RGRPSEL5_LEN ); REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL0 , 24 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_CGRPSEL0 ); REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL0_LEN , 4 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_CGRPSEL0_LEN ); REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL1 , 28 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_CGRPSEL1 ); REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL1_LEN , 4 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_CGRPSEL1_LEN ); REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL2 , 32 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_CGRPSEL2 ); REG64_FLD( PU_HTM1_HTM_FLEX_HTMSC_FMUX_CGRPSEL2_LEN , 4 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_FMUX_CGRPSEL2_LEN ); REG64_FLD( PU_HTM0_HTM_LAST_ADDRESS , 8 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_HTM0_HTM_LAST_ADDRESS_LEN , 49 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_HTM1_HTM_LAST_ADDRESS , 8 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_HTM1_HTM_LAST_ADDRESS_LEN , 49 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_ALLOC , 0 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_ALLOC ); REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_SCOPE , 1 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SCOPE ); REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_SCOPE_LEN , 3 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SCOPE_LEN ); REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_PRIORITY , 4 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_PRIORITY ); REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_SIZE_SMALL , 5 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SIZE_SMALL ); REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_SPARE67 , 6 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE67 ); REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_SPARE67_LEN , 2 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE67_LEN ); REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_BASE , 8 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_BASE ); REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_BASE_LEN , 32 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_BASE_LEN ); REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_SIZE , 40 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SIZE ); REG64_FLD( PU_HTM0_HTM_MEM_HTMSC_SIZE_LEN , 9 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SIZE_LEN ); REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_ALLOC , 0 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_ALLOC ); REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_SCOPE , 1 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SCOPE ); REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_SCOPE_LEN , 3 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SCOPE_LEN ); REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_PRIORITY , 4 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_PRIORITY ); REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_SIZE_SMALL , 5 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SIZE_SMALL ); REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_SPARE67 , 6 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE67 ); REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_SPARE67_LEN , 2 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE67_LEN ); REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_BASE , 8 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_BASE ); REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_BASE_LEN , 32 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_BASE_LEN ); REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_SIZE , 40 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SIZE ); REG64_FLD( PU_HTM1_HTM_MEM_HTMSC_SIZE_LEN , 9 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SIZE_LEN ); REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_ENABLE , 0 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_ENABLE ); REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_CONTENT_SEL , 1 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CONTENT_SEL ); REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_CONTENT_SEL_LEN , 2 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CONTENT_SEL_LEN ); REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SPARE3 , 3 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE3 ); REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_CAPTURE , 4 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CAPTURE ); REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_CAPTURE_LEN , 9 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CAPTURE_LEN ); REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_WRAP , 13 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_WRAP ); REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_DIS_TSTAMP , 14 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DIS_TSTAMP ); REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SINGLE_TSTAMP , 15 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SINGLE_TSTAMP ); REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SPARE16 , 16 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE16 ); REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_MARKERS_ONLY , 17 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARKERS_ONLY ); REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_DIS_FORCE_GROUP_SCOPE , 18 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DIS_FORCE_GROUP_SCOPE ); REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SYNC_STAMP_FORCE , 19 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SYNC_STAMP_FORCE ); REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SYNC_STAMP_FORCE_LEN , 3 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SYNC_STAMP_FORCE_LEN ); REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_WRITETOIO , 22 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_WRITETOIO ); REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SPARE23 , 23 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE23 ); REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_VGTARGET , 24 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_VGTARGET ); REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_VGTARGET_LEN , 16 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_VGTARGET_LEN ); REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SPARE4043 , 40 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE4043 ); REG64_FLD( PU_HTM0_HTM_MODE_HTMSC_SPARE4043_LEN , 4 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE4043_LEN ); REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_ENABLE , 0 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_ENABLE ); REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_CONTENT_SEL , 1 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CONTENT_SEL ); REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_CONTENT_SEL_LEN , 2 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CONTENT_SEL_LEN ); REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SPARE3 , 3 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE3 ); REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_CAPTURE , 4 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CAPTURE ); REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_CAPTURE_LEN , 9 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CAPTURE_LEN ); REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_WRAP , 13 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_WRAP ); REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_DIS_TSTAMP , 14 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DIS_TSTAMP ); REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SINGLE_TSTAMP , 15 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SINGLE_TSTAMP ); REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SPARE16 , 16 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE16 ); REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_MARKERS_ONLY , 17 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARKERS_ONLY ); REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_DIS_FORCE_GROUP_SCOPE , 18 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_DIS_FORCE_GROUP_SCOPE ); REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SYNC_STAMP_FORCE , 19 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SYNC_STAMP_FORCE ); REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SYNC_STAMP_FORCE_LEN , 3 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SYNC_STAMP_FORCE_LEN ); REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_WRITETOIO , 22 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_WRITETOIO ); REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SPARE23 , 23 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE23 ); REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_VGTARGET , 24 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_VGTARGET ); REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_VGTARGET_LEN , 16 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_VGTARGET_LEN ); REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SPARE4043 , 40 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE4043 ); REG64_FLD( PU_HTM1_HTM_MODE_HTMSC_SPARE4043_LEN , 4 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_SPARE4043_LEN ); REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_SPARE , 0 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_SPARE ); REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_SPARE_LEN , 2 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_SPARE_LEN ); REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_CRESP_OV , 2 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_CRESP_OV ); REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_REPAIR , 3 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_REPAIR ); REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_BUF_WAIT , 4 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_BUF_WAIT ); REG64_FLD( PU_HTM0_HTM_STAT_STATUS_TRIG_DROPPED_Q , 5 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_STATUS_TRIG_DROPPED_Q ); REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_ADDR_ERROR , 6 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_ADDR_ERROR ); REG64_FLD( PU_HTM0_HTM_STAT_STATUS_REC_DROPPED_Q , 7 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_STATUS_REC_DROPPED_Q ); REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_INIT , 8 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_INIT ); REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_PREREQ , 9 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_PREREQ ); REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_READY , 10 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_READY ); REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_TRACING , 11 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_TRACING ); REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_PAUSED , 12 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_PAUSED ); REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_FLUSH , 13 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_FLUSH ); REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_COMPLETE , 14 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_COMPLETE ); REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_ENABLE , 15 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_ENABLE ); REG64_FLD( PU_HTM0_HTM_STAT_HTMCO_STATUS_STAMP , 16 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_STAMP ); REG64_FLD( PU_HTM0_HTM_STAT_STATUS_SCOM_ERROR , 17 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_STATUS_SCOM_ERROR ); REG64_FLD( PU_HTM0_HTM_STAT_STATUS_PARITY_ERROR , 18 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_STATUS_PARITY_ERROR ); REG64_FLD( PU_HTM0_HTM_STAT_STATUS_INVALID_CRESP , 19 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RO , SH_FLD_STATUS_INVALID_CRESP ); REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_SPARE , 0 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_SPARE ); REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_SPARE_LEN , 2 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_SPARE_LEN ); REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_CRESP_OV , 2 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_CRESP_OV ); REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_REPAIR , 3 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_REPAIR ); REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_BUF_WAIT , 4 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_BUF_WAIT ); REG64_FLD( PU_HTM1_HTM_STAT_STATUS_TRIG_DROPPED_Q , 5 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_STATUS_TRIG_DROPPED_Q ); REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_ADDR_ERROR , 6 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_ADDR_ERROR ); REG64_FLD( PU_HTM1_HTM_STAT_STATUS_REC_DROPPED_Q , 7 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_STATUS_REC_DROPPED_Q ); REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_INIT , 8 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_INIT ); REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_PREREQ , 9 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_PREREQ ); REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_READY , 10 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_READY ); REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_TRACING , 11 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_TRACING ); REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_PAUSED , 12 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_PAUSED ); REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_FLUSH , 13 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_FLUSH ); REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_COMPLETE , 14 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_COMPLETE ); REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_ENABLE , 15 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_ENABLE ); REG64_FLD( PU_HTM1_HTM_STAT_HTMCO_STATUS_STAMP , 16 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_HTMCO_STATUS_STAMP ); REG64_FLD( PU_HTM1_HTM_STAT_STATUS_SCOM_ERROR , 17 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_STATUS_SCOM_ERROR ); REG64_FLD( PU_HTM1_HTM_STAT_STATUS_PARITY_ERROR , 18 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_STATUS_PARITY_ERROR ); REG64_FLD( PU_HTM1_HTM_STAT_STATUS_INVALID_CRESP , 19 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RO , SH_FLD_STATUS_INVALID_CRESP ); REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_START , 0 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_START ); REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_STOP , 1 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_STOP ); REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_PAUSE , 2 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_PAUSE ); REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_STOP_ALT , 3 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_STOP_ALT ); REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_RESET , 4 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_RESET ); REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_MARK_VALID , 5 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARK_VALID ); REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_MARK_TYPE , 6 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARK_TYPE ); REG64_FLD( PU_HTM0_HTM_TRIG_HTMSC_MARK_TYPE_LEN , 10 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARK_TYPE_LEN ); REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_START , 0 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_START ); REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_STOP , 1 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_STOP ); REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_PAUSE , 2 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_PAUSE ); REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_STOP_ALT , 3 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_STOP_ALT ); REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_RESET , 4 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_RESET ); REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_MARK_VALID , 5 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARK_VALID ); REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_MARK_TYPE , 6 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARK_TYPE ); REG64_FLD( PU_HTM1_HTM_TRIG_HTMSC_MARK_TYPE_LEN , 10 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MARK_TYPE_LEN ); REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_PAT , 1 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_PAT ); REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_PAT_LEN , 7 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_PAT_LEN ); REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT , 8 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_TSIZEFILT_PAT ); REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT_LEN , 8 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_TSIZEFILT_PAT_LEN ); REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_MASK , 17 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MASK ); REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_MASK_LEN , 7 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MASK_LEN ); REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK , 24 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_TSIZEFILT_MASK ); REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK_LEN , 8 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_TSIZEFILT_MASK_LEN ); REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_INVERT , 32 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_INVERT ); REG64_FLD( PU_HTM0_HTM_TTYPEFILT_HTMSC_CRESPFILT_INVERT , 33 , SH_UNT_PU_HTM0 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CRESPFILT_INVERT ); REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_PAT , 1 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_PAT ); REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_PAT_LEN , 7 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_PAT_LEN ); REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT , 8 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_TSIZEFILT_PAT ); REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_TSIZEFILT_PAT_LEN , 8 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_TSIZEFILT_PAT_LEN ); REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_MASK , 17 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MASK ); REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_MASK_LEN , 7 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_MASK_LEN ); REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK , 24 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_TSIZEFILT_MASK ); REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_TSIZEFILT_MASK_LEN , 8 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_TSIZEFILT_MASK_LEN ); REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_INVERT , 32 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_INVERT ); REG64_FLD( PU_HTM1_HTM_TTYPEFILT_HTMSC_CRESPFILT_INVERT , 33 , SH_UNT_PU_HTM1 , SH_ACS_SCOM_RW , SH_FLD_HTMSC_CRESPFILT_INVERT ); REG64_FLD( PU_I2C_BUSY_REGISTER_B_PEEK_DATA1_0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0 ); REG64_FLD( PU_I2C_BUSY_REGISTER_B_PEEK_DATA1_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0_LEN ); REG64_FLD( PU_I2C_BUSY_REGISTER_B_LBUS_PARITY_ERR1_0 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_0 ); REG64_FLD( PU_I2C_BUSY_REGISTER_C_PEEK_DATA1_1 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1 ); REG64_FLD( PU_I2C_BUSY_REGISTER_C_PEEK_DATA1_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1_LEN ); REG64_FLD( PU_I2C_BUSY_REGISTER_C_LBUS_PARITY_ERR1_1 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_1 ); REG64_FLD( PU_I2C_BUSY_REGISTER_D_PEEK_DATA1_2 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2 ); REG64_FLD( PU_I2C_BUSY_REGISTER_D_PEEK_DATA1_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2_LEN ); REG64_FLD( PU_I2C_BUSY_REGISTER_D_LBUS_PARITY_ERR1_2 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_2 ); REG64_FLD( PU_I2C_BUSY_REGISTER_E_PEEK_DATA1_3 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3 ); REG64_FLD( PU_I2C_BUSY_REGISTER_E_PEEK_DATA1_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3_LEN ); REG64_FLD( PU_I2C_BUSY_REGISTER_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); REG64_FLD( PU_NPU_CTL_INHIBIT_CONFIG_LFREQ , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_LFREQ ); REG64_FLD( PU_NPU_CTL_INHIBIT_CONFIG_LFREQ_LEN , 4 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_LFREQ_LEN ); REG64_FLD( PU_NPU_CTL_INHIBIT_CONFIG_IFREQ , 4 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IFREQ ); REG64_FLD( PU_NPU_CTL_INHIBIT_CONFIG_DEST , 5 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_DEST ); REG64_FLD( PU_NPU_CTL_INHIBIT_CONFIG_DEST_LEN , 3 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_DEST_LEN ); REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_LFREQ0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_LFREQ0 ); REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_LFREQ0_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_LFREQ0_LEN ); REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_PFREQ0 , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_PFREQ0 ); REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_PFREQ0_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_PFREQ0_LEN ); REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_BLOCKY0 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_BLOCKY0 ); REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_ONESHOT0 , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_ONESHOT0 ); REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_DEST0 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_DEST0 ); REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_DEST0_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_DEST0_LEN ); REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_LFREQ1 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_LFREQ1 ); REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_LFREQ1_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_LFREQ1_LEN ); REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_PFREQ1 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_PFREQ1 ); REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_PFREQ1_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_PFREQ1_LEN ); REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_BLOCKY1 , 22 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_BLOCKY1 ); REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_ONESHOT1 , 23 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_ONESHOT1 ); REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_DEST1 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_DEST1 ); REG64_FLD( PU_NPU1_SM2_INHIBIT_CONFIG_DEST1_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_DEST1_LEN ); REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_LFREQ0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_LFREQ0 ); REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_LFREQ0_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_LFREQ0_LEN ); REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_PFREQ0 , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_PFREQ0 ); REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_PFREQ0_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_PFREQ0_LEN ); REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_BLOCKY0 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_BLOCKY0 ); REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_ONESHOT0 , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_ONESHOT0 ); REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_DEST0 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_DEST0 ); REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_DEST0_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_DEST0_LEN ); REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_LFREQ1 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_LFREQ1 ); REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_LFREQ1_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_LFREQ1_LEN ); REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_PFREQ1 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_PFREQ1 ); REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_PFREQ1_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_PFREQ1_LEN ); REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_BLOCKY1 , 22 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_BLOCKY1 ); REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_ONESHOT1 , 23 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_ONESHOT1 ); REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_DEST1 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_DEST1 ); REG64_FLD( PU_NPU1_SM3_INHIBIT_CONFIG_DEST1_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_DEST1_LEN ); REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_LFREQ0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_LFREQ0 ); REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_LFREQ0_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_LFREQ0_LEN ); REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_PFREQ0 , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_PFREQ0 ); REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_PFREQ0_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_PFREQ0_LEN ); REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_BLOCKY0 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_BLOCKY0 ); REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_ONESHOT0 , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_ONESHOT0 ); REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_DEST0 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_DEST0 ); REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_DEST0_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_DEST0_LEN ); REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_LFREQ1 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_LFREQ1 ); REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_LFREQ1_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_LFREQ1_LEN ); REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_PFREQ1 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_PFREQ1 ); REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_PFREQ1_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_PFREQ1_LEN ); REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_BLOCKY1 , 22 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_BLOCKY1 ); REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_ONESHOT1 , 23 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_ONESHOT1 ); REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_DEST1 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_DEST1 ); REG64_FLD( PU_NPU1_SM1_INHIBIT_CONFIG_DEST1_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_DEST1_LEN ); REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_LFREQ0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_LFREQ0 ); REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_LFREQ0_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_LFREQ0_LEN ); REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_PFREQ0 , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_PFREQ0 ); REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_PFREQ0_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_PFREQ0_LEN ); REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_BLOCKY0 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_BLOCKY0 ); REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_ONESHOT0 , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_ONESHOT0 ); REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_DEST0 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_DEST0 ); REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_DEST0_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_DEST0_LEN ); REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_LFREQ1 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_LFREQ1 ); REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_LFREQ1_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_LFREQ1_LEN ); REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_PFREQ1 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_PFREQ1 ); REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_PFREQ1_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_PFREQ1_LEN ); REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_BLOCKY1 , 22 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_BLOCKY1 ); REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_ONESHOT1 , 23 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_ONESHOT1 ); REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_DEST1 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_DEST1 ); REG64_FLD( PU_NPU0_SM2_INHIBIT_CONFIG_DEST1_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_DEST1_LEN ); REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_LFREQ0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_LFREQ0 ); REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_LFREQ0_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_LFREQ0_LEN ); REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_PFREQ0 , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PFREQ0 ); REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_PFREQ0_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PFREQ0_LEN ); REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_BLOCKY0 , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_BLOCKY0 ); REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_ONESHOT0 , 7 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_ONESHOT0 ); REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_DEST0 , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_DEST0 ); REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_DEST0_LEN , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_DEST0_LEN ); REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_LFREQ1 , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_LFREQ1 ); REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_LFREQ1_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_LFREQ1_LEN ); REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_PFREQ1 , 20 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PFREQ1 ); REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_PFREQ1_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PFREQ1_LEN ); REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_BLOCKY1 , 22 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_BLOCKY1 ); REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_ONESHOT1 , 23 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_ONESHOT1 ); REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_DEST1 , 24 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_DEST1 ); REG64_FLD( PU_NPU0_CTL_INHIBIT_CONFIG_DEST1_LEN , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_DEST1_LEN ); REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_LFREQ0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_LFREQ0 ); REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_LFREQ0_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_LFREQ0_LEN ); REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_PFREQ0 , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_PFREQ0 ); REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_PFREQ0_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_PFREQ0_LEN ); REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_BLOCKY0 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_BLOCKY0 ); REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_ONESHOT0 , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_ONESHOT0 ); REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_DEST0 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_DEST0 ); REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_DEST0_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_DEST0_LEN ); REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_LFREQ1 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_LFREQ1 ); REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_LFREQ1_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_LFREQ1_LEN ); REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_PFREQ1 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_PFREQ1 ); REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_PFREQ1_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_PFREQ1_LEN ); REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_BLOCKY1 , 22 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_BLOCKY1 ); REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_ONESHOT1 , 23 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_ONESHOT1 ); REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_DEST1 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_DEST1 ); REG64_FLD( PU_NPU0_SM1_INHIBIT_CONFIG_DEST1_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_DEST1_LEN ); REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_LFREQ0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_LFREQ0 ); REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_LFREQ0_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_LFREQ0_LEN ); REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_PFREQ0 , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_PFREQ0 ); REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_PFREQ0_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_PFREQ0_LEN ); REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_BLOCKY0 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_BLOCKY0 ); REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_ONESHOT0 , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_ONESHOT0 ); REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_DEST0 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_DEST0 ); REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_DEST0_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_DEST0_LEN ); REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_LFREQ1 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_LFREQ1 ); REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_LFREQ1_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_LFREQ1_LEN ); REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_PFREQ1 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_PFREQ1 ); REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_PFREQ1_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_PFREQ1_LEN ); REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_BLOCKY1 , 22 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_BLOCKY1 ); REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_ONESHOT1 , 23 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_ONESHOT1 ); REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_DEST1 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_DEST1 ); REG64_FLD( PU_NPU0_SM0_INHIBIT_CONFIG_DEST1_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_DEST1_LEN ); REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_LFREQ0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_LFREQ0 ); REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_LFREQ0_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_LFREQ0_LEN ); REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_PFREQ0 , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_PFREQ0 ); REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_PFREQ0_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_PFREQ0_LEN ); REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_BLOCKY0 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_BLOCKY0 ); REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_ONESHOT0 , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_ONESHOT0 ); REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_DEST0 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_DEST0 ); REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_DEST0_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_DEST0_LEN ); REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_LFREQ1 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_LFREQ1 ); REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_LFREQ1_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_LFREQ1_LEN ); REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_PFREQ1 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_PFREQ1 ); REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_PFREQ1_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_PFREQ1_LEN ); REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_BLOCKY1 , 22 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_BLOCKY1 ); REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_ONESHOT1 , 23 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_ONESHOT1 ); REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_DEST1 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_DEST1 ); REG64_FLD( PU_NPU0_SM3_INHIBIT_CONFIG_DEST1_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_DEST1_LEN ); REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_LFREQ0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_LFREQ0 ); REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_LFREQ0_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_LFREQ0_LEN ); REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_PFREQ0 , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_PFREQ0 ); REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_PFREQ0_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_PFREQ0_LEN ); REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_BLOCKY0 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_BLOCKY0 ); REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_ONESHOT0 , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_ONESHOT0 ); REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_DEST0 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_DEST0 ); REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_DEST0_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_DEST0_LEN ); REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_LFREQ1 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_LFREQ1 ); REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_LFREQ1_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_LFREQ1_LEN ); REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_PFREQ1 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_PFREQ1 ); REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_PFREQ1_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_PFREQ1_LEN ); REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_BLOCKY1 , 22 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_BLOCKY1 ); REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_ONESHOT1 , 23 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_ONESHOT1 ); REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_DEST1 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_DEST1 ); REG64_FLD( PU_NPU2_SM3_INHIBIT_CONFIG_DEST1_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_DEST1_LEN ); REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_LFREQ0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_LFREQ0 ); REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_LFREQ0_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_LFREQ0_LEN ); REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_PFREQ0 , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_PFREQ0 ); REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_PFREQ0_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_PFREQ0_LEN ); REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_BLOCKY0 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_BLOCKY0 ); REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_ONESHOT0 , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_ONESHOT0 ); REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_DEST0 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_DEST0 ); REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_DEST0_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_DEST0_LEN ); REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_LFREQ1 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_LFREQ1 ); REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_LFREQ1_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_LFREQ1_LEN ); REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_PFREQ1 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_PFREQ1 ); REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_PFREQ1_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_PFREQ1_LEN ); REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_BLOCKY1 , 22 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_BLOCKY1 ); REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_ONESHOT1 , 23 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_ONESHOT1 ); REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_DEST1 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_DEST1 ); REG64_FLD( PU_NPU2_SM2_INHIBIT_CONFIG_DEST1_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_DEST1_LEN ); REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_LFREQ0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_LFREQ0 ); REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_LFREQ0_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_LFREQ0_LEN ); REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_PFREQ0 , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PFREQ0 ); REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_PFREQ0_LEN , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PFREQ0_LEN ); REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_BLOCKY0 , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_BLOCKY0 ); REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_ONESHOT0 , 7 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_ONESHOT0 ); REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_DEST0 , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_DEST0 ); REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_DEST0_LEN , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_DEST0_LEN ); REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_LFREQ1 , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_LFREQ1 ); REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_LFREQ1_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_LFREQ1_LEN ); REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_PFREQ1 , 20 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PFREQ1 ); REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_PFREQ1_LEN , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PFREQ1_LEN ); REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_BLOCKY1 , 22 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_BLOCKY1 ); REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_ONESHOT1 , 23 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_ONESHOT1 ); REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_DEST1 , 24 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_DEST1 ); REG64_FLD( PU_NPU1_CTL_INHIBIT_CONFIG_DEST1_LEN , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_DEST1_LEN ); REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_LFREQ0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_LFREQ0 ); REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_LFREQ0_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_LFREQ0_LEN ); REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_PFREQ0 , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_PFREQ0 ); REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_PFREQ0_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_PFREQ0_LEN ); REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_BLOCKY0 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_BLOCKY0 ); REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_ONESHOT0 , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_ONESHOT0 ); REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_DEST0 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_DEST0 ); REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_DEST0_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_DEST0_LEN ); REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_LFREQ1 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_LFREQ1 ); REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_LFREQ1_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_LFREQ1_LEN ); REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_PFREQ1 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_PFREQ1 ); REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_PFREQ1_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_PFREQ1_LEN ); REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_BLOCKY1 , 22 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_BLOCKY1 ); REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_ONESHOT1 , 23 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_ONESHOT1 ); REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_DEST1 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_DEST1 ); REG64_FLD( PU_NPU2_SM1_INHIBIT_CONFIG_DEST1_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_DEST1_LEN ); REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_LFREQ0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_LFREQ0 ); REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_LFREQ0_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_LFREQ0_LEN ); REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_PFREQ0 , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_PFREQ0 ); REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_PFREQ0_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_PFREQ0_LEN ); REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_BLOCKY0 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_BLOCKY0 ); REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_ONESHOT0 , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_ONESHOT0 ); REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_DEST0 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_DEST0 ); REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_DEST0_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_DEST0_LEN ); REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_LFREQ1 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_LFREQ1 ); REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_LFREQ1_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_LFREQ1_LEN ); REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_PFREQ1 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_PFREQ1 ); REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_PFREQ1_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_PFREQ1_LEN ); REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_BLOCKY1 , 22 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_BLOCKY1 ); REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_ONESHOT1 , 23 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_ONESHOT1 ); REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_DEST1 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_DEST1 ); REG64_FLD( PU_NPU2_SM0_INHIBIT_CONFIG_DEST1_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_DEST1_LEN ); REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_LFREQ0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_LFREQ0 ); REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_LFREQ0_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_LFREQ0_LEN ); REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_PFREQ0 , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PFREQ0 ); REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_PFREQ0_LEN , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PFREQ0_LEN ); REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_BLOCKY0 , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_BLOCKY0 ); REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_ONESHOT0 , 7 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ONESHOT0 ); REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_DEST0 , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_DEST0 ); REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_DEST0_LEN , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_DEST0_LEN ); REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_LFREQ1 , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_LFREQ1 ); REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_LFREQ1_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_LFREQ1_LEN ); REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_PFREQ1 , 20 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PFREQ1 ); REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_PFREQ1_LEN , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PFREQ1_LEN ); REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_BLOCKY1 , 22 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_BLOCKY1 ); REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_ONESHOT1 , 23 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ONESHOT1 ); REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_DEST1 , 24 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_DEST1 ); REG64_FLD( PU_NPU2_CTL_INHIBIT_CONFIG_DEST1_LEN , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_DEST1_LEN ); REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_LFREQ0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_LFREQ0 ); REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_LFREQ0_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_LFREQ0_LEN ); REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_PFREQ0 , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_PFREQ0 ); REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_PFREQ0_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_PFREQ0_LEN ); REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_BLOCKY0 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_BLOCKY0 ); REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_ONESHOT0 , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_ONESHOT0 ); REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_DEST0 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_DEST0 ); REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_DEST0_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_DEST0_LEN ); REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_LFREQ1 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_LFREQ1 ); REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_LFREQ1_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_LFREQ1_LEN ); REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_PFREQ1 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_PFREQ1 ); REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_PFREQ1_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_PFREQ1_LEN ); REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_BLOCKY1 , 22 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_BLOCKY1 ); REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_ONESHOT1 , 23 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_ONESHOT1 ); REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_DEST1 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_DEST1 ); REG64_FLD( PU_NPU1_SM0_INHIBIT_CONFIG_DEST1_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_DEST1_LEN ); REG64_FLD( PEC_INJECT_REG_THERM_TRIP , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_THERM_TRIP ); REG64_FLD( PEC_INJECT_REG_THERM_TRIP_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_THERM_TRIP_LEN ); REG64_FLD( PEC_INJECT_REG_THERM_MODE , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_THERM_MODE ); REG64_FLD( PEC_INJECT_REG_THERM_MODE_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_THERM_MODE_LEN ); REG64_FLD( PEC_STACK2_INTBAR_REG_PE_INT_BAR , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , SH_FLD_PE_INT_BAR ); REG64_FLD( PEC_STACK2_INTBAR_REG_PE_INT_BAR_LEN , 28 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , SH_FLD_PE_INT_BAR_LEN ); REG64_FLD( PEC_STACK1_INTBAR_REG_PE_INT_BAR , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , SH_FLD_PE_INT_BAR ); REG64_FLD( PEC_STACK1_INTBAR_REG_PE_INT_BAR_LEN , 28 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , SH_FLD_PE_INT_BAR_LEN ); REG64_FLD( PHB_INTBAR_REG_PE_INT_BAR , 0 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_INT_BAR ); REG64_FLD( PHB_INTBAR_REG_PE_INT_BAR_LEN , 28 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_INT_BAR_LEN ); REG64_FLD( PEC_STACK0_INTBAR_REG_PE_INT_BAR , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , SH_FLD_PE_INT_BAR ); REG64_FLD( PEC_STACK0_INTBAR_REG_PE_INT_BAR_LEN , 28 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , SH_FLD_PE_INT_BAR_LEN ); REG64_FLD( PU_INTERRUPTS_B_PEEK_DATA1_0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0 ); REG64_FLD( PU_INTERRUPTS_B_PEEK_DATA1_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0_LEN ); REG64_FLD( PU_INTERRUPTS_B_LBUS_PARITY_ERR1_0 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_0 ); REG64_FLD( PU_INTERRUPTS_C_PEEK_DATA1_1 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1 ); REG64_FLD( PU_INTERRUPTS_C_PEEK_DATA1_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1_LEN ); REG64_FLD( PU_INTERRUPTS_C_LBUS_PARITY_ERR1_1 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_1 ); REG64_FLD( PU_INTERRUPTS_D_PEEK_DATA1_2 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2 ); REG64_FLD( PU_INTERRUPTS_D_PEEK_DATA1_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2_LEN ); REG64_FLD( PU_INTERRUPTS_D_LBUS_PARITY_ERR1_2 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_2 ); REG64_FLD( PU_INTERRUPTS_E_PEEK_DATA1_3 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3 ); REG64_FLD( PU_INTERRUPTS_E_PEEK_DATA1_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3_LEN ); REG64_FLD( PU_INTERRUPTS_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); REG64_FLD( PU_INTERRUPT_COND_B_INVALID_CMD_0 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_INVALID_CMD_0 ); REG64_FLD( PU_INTERRUPT_COND_B_LBUS_PARITY_ERROR_0 , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERROR_0 ); REG64_FLD( PU_INTERRUPT_COND_B_BE_OV_ERROR_0 , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_BE_OV_ERROR_0 ); REG64_FLD( PU_INTERRUPT_COND_B_BE_ACC_ERROR_0 , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_BE_ACC_ERROR_0 ); REG64_FLD( PU_INTERRUPT_COND_B_ARBITRATION_LOST_ERROR_0 , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_ARBITRATION_LOST_ERROR_0 ); REG64_FLD( PU_INTERRUPT_COND_B_NACK_RECEIVED_ERROR_0 , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_NACK_RECEIVED_ERROR_0 ); REG64_FLD( PU_INTERRUPT_COND_B_DATA_REQUEST_0 , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_REQUEST_0 ); REG64_FLD( PU_INTERRUPT_COND_B_STOP_ERROR_0 , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_STOP_ERROR_0 ); REG64_FLD( PU_INTERRUPT_COND_B_PEEK_DATA1_0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0 ); REG64_FLD( PU_INTERRUPT_COND_B_PEEK_DATA1_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0_LEN ); REG64_FLD( PU_INTERRUPT_COND_B_LBUS_PARITY_ERR1_0 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_0 ); REG64_FLD( PU_INTERRUPT_COND_C_INVALID_CMD_1 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_INVALID_CMD_1 ); REG64_FLD( PU_INTERRUPT_COND_C_LBUS_PARITY_ERROR_1 , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERROR_1 ); REG64_FLD( PU_INTERRUPT_COND_C_BE_OV_ERROR_1 , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_BE_OV_ERROR_1 ); REG64_FLD( PU_INTERRUPT_COND_C_BE_ACC_ERROR_1 , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_BE_ACC_ERROR_1 ); REG64_FLD( PU_INTERRUPT_COND_C_ARBITRATION_LOST_ERROR_1 , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_ARBITRATION_LOST_ERROR_1 ); REG64_FLD( PU_INTERRUPT_COND_C_NACK_RECEIVED_ERROR_1 , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_NACK_RECEIVED_ERROR_1 ); REG64_FLD( PU_INTERRUPT_COND_C_DATA_REQUEST_1 , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_REQUEST_1 ); REG64_FLD( PU_INTERRUPT_COND_C_STOP_ERROR_1 , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_STOP_ERROR_1 ); REG64_FLD( PU_INTERRUPT_COND_C_PEEK_DATA1_1 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1 ); REG64_FLD( PU_INTERRUPT_COND_C_PEEK_DATA1_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1_LEN ); REG64_FLD( PU_INTERRUPT_COND_C_LBUS_PARITY_ERR1_1 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_1 ); REG64_FLD( PU_INTERRUPT_COND_D_INVALID_CMD_2 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_INVALID_CMD_2 ); REG64_FLD( PU_INTERRUPT_COND_D_LBUS_PARITY_ERROR_2 , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERROR_2 ); REG64_FLD( PU_INTERRUPT_COND_D_BE_OV_ERROR_2 , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_BE_OV_ERROR_2 ); REG64_FLD( PU_INTERRUPT_COND_D_BE_ACC_ERROR_2 , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_BE_ACC_ERROR_2 ); REG64_FLD( PU_INTERRUPT_COND_D_ARBITRATION_LOST_ERROR_2 , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_ARBITRATION_LOST_ERROR_2 ); REG64_FLD( PU_INTERRUPT_COND_D_NACK_RECEIVED_ERROR_2 , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_NACK_RECEIVED_ERROR_2 ); REG64_FLD( PU_INTERRUPT_COND_D_DATA_REQUEST_2 , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_REQUEST_2 ); REG64_FLD( PU_INTERRUPT_COND_D_STOP_ERROR_2 , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_STOP_ERROR_2 ); REG64_FLD( PU_INTERRUPT_COND_D_PEEK_DATA1_2 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2 ); REG64_FLD( PU_INTERRUPT_COND_D_PEEK_DATA1_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2_LEN ); REG64_FLD( PU_INTERRUPT_COND_D_LBUS_PARITY_ERR1_2 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_2 ); REG64_FLD( PU_INTERRUPT_COND_E_INVALID_CMD_3 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_INVALID_CMD_3 ); REG64_FLD( PU_INTERRUPT_COND_E_LBUS_PARITY_ERROR_3 , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERROR_3 ); REG64_FLD( PU_INTERRUPT_COND_E_BE_OV_ERROR_3 , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_BE_OV_ERROR_3 ); REG64_FLD( PU_INTERRUPT_COND_E_BE_ACC_ERROR_3 , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_BE_ACC_ERROR_3 ); REG64_FLD( PU_INTERRUPT_COND_E_ARBITRATION_LOST_ERROR_3 , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_ARBITRATION_LOST_ERROR_3 ); REG64_FLD( PU_INTERRUPT_COND_E_NACK_RECEIVED_ERROR_3 , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_NACK_RECEIVED_ERROR_3 ); REG64_FLD( PU_INTERRUPT_COND_E_DATA_REQUEST_3 , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_REQUEST_3 ); REG64_FLD( PU_INTERRUPT_COND_E_STOP_ERROR_3 , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_STOP_ERROR_3 ); REG64_FLD( PU_INTERRUPT_COND_E_PEEK_DATA1_3 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3 ); REG64_FLD( PU_INTERRUPT_COND_E_PEEK_DATA1_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3_LEN ); REG64_FLD( PU_INTERRUPT_COND_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_B_INT_0 , 16 , SH_UNT , SH_ACS_SCOM2_AND, SH_FLD_INT_0 ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_B_INT_0_LEN , 16 , SH_UNT , SH_ACS_SCOM2_AND, SH_FLD_INT_0_LEN ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_C_INT_1 , 16 , SH_UNT , SH_ACS_SCOM2_AND, SH_FLD_INT_1 ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_C_INT_1_LEN , 16 , SH_UNT , SH_ACS_SCOM2_AND, SH_FLD_INT_1_LEN ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_D_INT_2 , 16 , SH_UNT , SH_ACS_SCOM2_AND, SH_FLD_INT_2 ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_D_INT_2_LEN , 16 , SH_UNT , SH_ACS_SCOM2_AND, SH_FLD_INT_2_LEN ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_E_INT_3 , 16 , SH_UNT , SH_ACS_SCOM2_AND, SH_FLD_INT_3 ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_E_INT_3_LEN , 16 , SH_UNT , SH_ACS_SCOM2_AND, SH_FLD_INT_3_LEN ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_B_INT_0 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_INT_0 ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_B_INT_0_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_INT_0_LEN ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_B_PEEK_DATA1_0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0 ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_B_PEEK_DATA1_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0_LEN ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_B_LBUS_PARITY_ERR1_0 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_0 ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_C_INT_1 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_INT_1 ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_C_INT_1_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_INT_1_LEN ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_C_PEEK_DATA1_1 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1 ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_C_PEEK_DATA1_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1_LEN ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_C_LBUS_PARITY_ERR1_1 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_1 ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_D_INT_2 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_INT_2 ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_D_INT_2_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_INT_2_LEN ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_D_PEEK_DATA1_2 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2 ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_D_PEEK_DATA1_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2_LEN ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_D_LBUS_PARITY_ERR1_2 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_2 ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_E_INT_3 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_INT_3 ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_E_INT_3_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_INT_3_LEN ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_E_PEEK_DATA1_3 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3 ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_E_PEEK_DATA1_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3_LEN ); REG64_FLD( PU_INTERRUPT_MASK_REGISTER_READ_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); REG64_FLD( PU_NPU_CTL_INT_0_CONFIG_0 , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( PU_NPU_CTL_INT_0_CONFIG_0_LEN , 64 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_0_LEN ); REG64_FLD( PU_NPU_CTL_INT_1_CONFIG_1 , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_1 ); REG64_FLD( PU_NPU_CTL_INT_1_CONFIG_1_LEN , 64 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_1_LEN ); REG64_FLD( PU_NPU_CTL_INT_BAR_CONFIG , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_CONFIG ); REG64_FLD( PU_NPU_CTL_INT_BAR_CONFIG_LEN , 39 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_CONFIG_LEN ); REG64_FLD( PU_INT_CQ_ACTION0_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( PU_INT_CQ_ACTION0_ACTION0_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); REG64_FLD( PU_INT_CQ_ACTION1_ACTION1 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); REG64_FLD( PU_INT_CQ_ACTION1_ACTION1_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); REG64_FLD( PU_INT_CQ_AIB_CTL_DIS_ECCCHK_IN , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DIS_ECCCHK_IN ); REG64_FLD( PU_INT_CQ_AIB_CTL_EXTRA_CMD_SPACING_0_2 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_EXTRA_CMD_SPACING_0_2 ); REG64_FLD( PU_INT_CQ_AIB_CTL_EXTRA_CMD_SPACING_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_EXTRA_CMD_SPACING_0_2_LEN ); REG64_FLD( PU_INT_CQ_AIB_CTL_EXTRA_DAT_SPACING_0_3 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_EXTRA_DAT_SPACING_0_3 ); REG64_FLD( PU_INT_CQ_AIB_CTL_EXTRA_DAT_SPACING_0_3_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_EXTRA_DAT_SPACING_0_3_LEN ); REG64_FLD( PU_INT_CQ_AIB_CTL_PC_PRIORITY_LIMIT_0_3 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PC_PRIORITY_LIMIT_0_3 ); REG64_FLD( PU_INT_CQ_AIB_CTL_PC_PRIORITY_LIMIT_0_3_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PC_PRIORITY_LIMIT_0_3_LEN ); REG64_FLD( PU_INT_CQ_AIB_CTL_VC_PRIORITY_LIMIT_0_3 , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_VC_PRIORITY_LIMIT_0_3 ); REG64_FLD( PU_INT_CQ_AIB_CTL_VC_PRIORITY_LIMIT_0_3_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_VC_PRIORITY_LIMIT_0_3_LEN ); REG64_FLD( PU_INT_CQ_AIB_CTL_PRIORITY_LIMIT_0_3 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LIMIT_0_3 ); REG64_FLD( PU_INT_CQ_AIB_CTL_PRIORITY_LIMIT_0_3_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LIMIT_0_3_LEN ); REG64_FLD( PU_INT_CQ_AIB_CTL_BLOCK_CMD_OVERLAP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_BLOCK_CMD_OVERLAP ); REG64_FLD( PU_INT_CQ_AIB_CTL_RESERVED_21_31 , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_21_31 ); REG64_FLD( PU_INT_CQ_AIB_CTL_RESERVED_21_31_LEN , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_21_31_LEN ); REG64_FLD( PU_INT_CQ_AIB_CTL_CH0_CMD_CREDITS_0_5 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_CH0_CMD_CREDITS_0_5 ); REG64_FLD( PU_INT_CQ_AIB_CTL_CH0_CMD_CREDITS_0_5_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_CH0_CMD_CREDITS_0_5_LEN ); REG64_FLD( PU_INT_CQ_AIB_CTL_CH1_CMD_CREDITS_0_5 , 38 , SH_UNT , SH_ACS_SCOM , SH_FLD_CH1_CMD_CREDITS_0_5 ); REG64_FLD( PU_INT_CQ_AIB_CTL_CH1_CMD_CREDITS_0_5_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_CH1_CMD_CREDITS_0_5_LEN ); REG64_FLD( PU_INT_CQ_AIB_CTL_CH1_DAT_CREDITS_0_5 , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_CH1_DAT_CREDITS_0_5 ); REG64_FLD( PU_INT_CQ_AIB_CTL_CH1_DAT_CREDITS_0_5_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_CH1_DAT_CREDITS_0_5_LEN ); REG64_FLD( PU_INT_CQ_AIB_CTL_CH2_CMD_CREDITS_PC_0_5 , 50 , SH_UNT , SH_ACS_SCOM , SH_FLD_CH2_CMD_CREDITS_PC_0_5 ); REG64_FLD( PU_INT_CQ_AIB_CTL_CH2_CMD_CREDITS_PC_0_5_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_CH2_CMD_CREDITS_PC_0_5_LEN ); REG64_FLD( PU_INT_CQ_AIB_CTL_CH2_CMD_CREDITS_VC_0_5 , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_CH2_CMD_CREDITS_VC_0_5 ); REG64_FLD( PU_INT_CQ_AIB_CTL_CH2_CMD_CREDITS_VC_0_5_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_CH2_CMD_CREDITS_VC_0_5_LEN ); REG64_FLD( PU_INT_CQ_AIB_CTL_RESERVED_62 , 62 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_62 ); REG64_FLD( PU_INT_CQ_AIB_CTL_REINIT_CREDITS , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_REINIT_CREDITS ); REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_IVE_MIN_0_4 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_IVE_MIN_0_4 ); REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_IVE_MIN_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_IVE_MIN_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_IVE_MAX_0_4 , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_IVE_MAX_0_4 ); REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_IVE_MAX_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_IVE_MAX_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_EQD_MIN_0_4 , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_EQD_MIN_0_4 ); REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_EQD_MIN_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_EQD_MIN_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_EQD_MAX_0_4 , 15 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_EQD_MAX_0_4 ); REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_EQD_MAX_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_EQD_MAX_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_THR_MIN_0_4 , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_THR_MIN_0_4 ); REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_THR_MIN_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_THR_MIN_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_THR_MAX_0_4 , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_THR_MAX_0_4 ); REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_THR_MAX_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_THR_MAX_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_VPC_MIN_0_4 , 30 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_VPC_MIN_0_4 ); REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_VPC_MIN_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_VPC_MIN_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_VPC_MAX_0_4 , 35 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_VPC_MAX_0_4 ); REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_VPC_MAX_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_VPC_MAX_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_REG_MIN_0_4 , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_REG_MIN_0_4 ); REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_REG_MIN_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_REG_MIN_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_REG_MAX_0_4 , 45 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_REG_MAX_0_4 ); REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_REG_MAX_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_REG_MAX_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_LDQ_LDQ_REG_ORDER_ALL , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_REG_ORDER_ALL ); REG64_FLD( PU_INT_CQ_CFG_LDQ_RESERVED_51_63 , 51 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_51_63 ); REG64_FLD( PU_INT_CQ_CFG_LDQ_RESERVED_51_63_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_51_63_LEN ); REG64_FLD( PU_INT_CQ_CFG_PB_GEN_ADDR_BAR_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDR_BAR_MODE ); REG64_FLD( PU_INT_CQ_CFG_PB_GEN_PUMP_MODE , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUMP_MODE ); REG64_FLD( PU_INT_CQ_CFG_PB_GEN_PHYP_SCOPE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PHYP_SCOPE ); REG64_FLD( PU_INT_CQ_CFG_PB_GEN_INIT , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_INIT ); REG64_FLD( PU_INT_CQ_CFG_PB_GEN_MODE_128K_VP , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MODE_128K_VP ); REG64_FLD( PU_INT_CQ_CFG_PB_GEN_RESERVED_5_15 , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_5_15 ); REG64_FLD( PU_INT_CQ_CFG_PB_GEN_RESERVED_5_15_LEN , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_5_15_LEN ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_IPI_MIN_0_4 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_IPI_MIN_0_4 ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_IPI_MIN_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_IPI_MIN_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_IPI_MAX_0_4 , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_IPI_MAX_0_4 ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_IPI_MAX_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_IPI_MAX_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_HW_MIN_0_4 , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_HW_MIN_0_4 ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_HW_MIN_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_HW_MIN_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_HW_MAX_0_4 , 15 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_HW_MAX_0_4 ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_HW_MAX_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_HW_MAX_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_OS_MIN_0_4 , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_OS_MIN_0_4 ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_OS_MIN_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_OS_MIN_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_OS_MAX_0_4 , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_OS_MAX_0_4 ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_OS_MAX_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_OS_MAX_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_HYP_MIN_0_4 , 30 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_HYP_MIN_0_4 ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_HYP_MIN_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_HYP_MIN_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_HYP_MAX_0_4 , 35 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_HYP_MAX_0_4 ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_HYP_MAX_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_HYP_MAX_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_RDI_MIN_0_4 , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_RDI_MIN_0_4 ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_RDI_MIN_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_RDI_MIN_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_RDI_MAX_0_4 , 45 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_RDI_MAX_0_4 ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_RDI_MAX_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_RDI_MAX_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_THR_MIN_0_4 , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_THR_MIN_0_4 ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_THR_MIN_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_THR_MIN_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_THR_MAX_0_4 , 55 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_THR_MAX_0_4 ); REG64_FLD( PU_INT_CQ_CFG_STQ1_STQ_THR_MAX_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_THR_MAX_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_STQ1_RESERVED_60_63 , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_60_63 ); REG64_FLD( PU_INT_CQ_CFG_STQ1_RESERVED_60_63_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_60_63_LEN ); REG64_FLD( PU_INT_CQ_CFG_STQ2_STQ_VPC_MIN_0_4 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_VPC_MIN_0_4 ); REG64_FLD( PU_INT_CQ_CFG_STQ2_STQ_VPC_MIN_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_VPC_MIN_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_STQ2_STQ_VPC_MAX_0_4 , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_VPC_MAX_0_4 ); REG64_FLD( PU_INT_CQ_CFG_STQ2_STQ_VPC_MAX_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_VPC_MAX_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_STQ2_STQ_REG_MIN_0_4 , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_REG_MIN_0_4 ); REG64_FLD( PU_INT_CQ_CFG_STQ2_STQ_REG_MIN_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_REG_MIN_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_STQ2_STQ_REG_MAX_0_4 , 15 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_REG_MAX_0_4 ); REG64_FLD( PU_INT_CQ_CFG_STQ2_STQ_REG_MAX_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_REG_MAX_0_4_LEN ); REG64_FLD( PU_INT_CQ_CFG_STQ2_RESERVED_20_31 , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_20_31 ); REG64_FLD( PU_INT_CQ_CFG_STQ2_RESERVED_20_31_LEN , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_20_31_LEN ); REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE0_0_2 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMON_MUX_BYTE0_0_2 ); REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE0_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMON_MUX_BYTE0_0_2_LEN ); REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE1_0_2 , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMON_MUX_BYTE1_0_2 ); REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE1_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMON_MUX_BYTE1_0_2_LEN ); REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE2_0_2 , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMON_MUX_BYTE2_0_2 ); REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE2_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMON_MUX_BYTE2_0_2_LEN ); REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE3_0_2 , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMON_MUX_BYTE3_0_2 ); REG64_FLD( PU_INT_CQ_CNPM_SEL_PMON_MUX_BYTE3_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMON_MUX_BYTE3_0_2_LEN ); REG64_FLD( PU_INT_CQ_CNPM_SEL_RESERVED_12_23 , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_12_23 ); REG64_FLD( PU_INT_CQ_CNPM_SEL_RESERVED_12_23_LEN , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_12_23_LEN ); REG64_FLD( PU_INT_CQ_CNPM_SEL_EBUS_ENABLE_0_15 , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EBUS_ENABLE_0_15 ); REG64_FLD( PU_INT_CQ_CNPM_SEL_EBUS_ENABLE_0_15_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EBUS_ENABLE_0_15_LEN ); REG64_FLD( PU_INT_CQ_ERR_INFO0_INFO_CAPTURED , 0 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_INFO_CAPTURED ); REG64_FLD( PU_INT_CQ_ERR_INFO0_RCMD0_ADDR_PERR , 1 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_RCMD0_ADDR_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO0_RCMD1_ADDR_PERR , 2 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_RCMD1_ADDR_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO0_RCMD2_ADDR_PERR , 3 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_RCMD2_ADDR_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO0_RCMD3_ADDR_PERR , 4 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_RCMD3_ADDR_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO0_RCMD0_TTAG_PERR , 5 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_RCMD0_TTAG_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO0_RCMD1_TTAG_PERR , 6 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_RCMD1_TTAG_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO0_RCMD2_TTAG_PERR , 7 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_RCMD2_TTAG_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO0_RCMD3_TTAG_PERR , 8 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_RCMD3_TTAG_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO0_CR0_TTAG_PERR , 9 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CR0_TTAG_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO0_CR1_TTAG_PERR , 10 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CR1_TTAG_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO0_CR2_TTAG_PERR , 11 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CR2_TTAG_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO0_CR3_TTAG_PERR , 12 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CR3_TTAG_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO0_CR0_ATAG_PERR , 13 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CR0_ATAG_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO0_CR1_ATAG_PERR , 14 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CR1_ATAG_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO0_CR2_ATAG_PERR , 15 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CR2_ATAG_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO0_CR3_ATAG_PERR , 16 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CR3_ATAG_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO0_RTAG_PERR , 17 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_RTAG_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO1_INFO_CAPTURED , 0 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_INFO_CAPTURED ); REG64_FLD( PU_INT_CQ_ERR_INFO1_CI_WRITE , 1 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CI_WRITE ); REG64_FLD( PU_INT_CQ_ERR_INFO1_CI_READ , 2 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CI_READ ); REG64_FLD( PU_INT_CQ_ERR_INFO1_DMA_WRITE , 3 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_DMA_WRITE ); REG64_FLD( PU_INT_CQ_ERR_INFO1_TSIZE_4_6 , 4 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_TSIZE_4_6 ); REG64_FLD( PU_INT_CQ_ERR_INFO1_TSIZE_4_6_LEN , 3 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_TSIZE_4_6_LEN ); REG64_FLD( PU_INT_CQ_ERR_INFO1_RESERVED_7 , 7 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_RESERVED_7 ); REG64_FLD( PU_INT_CQ_ERR_INFO1_ADDRESS_8_63 , 8 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_ADDRESS_8_63 ); REG64_FLD( PU_INT_CQ_ERR_INFO1_ADDRESS_8_63_LEN , 56 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_ADDRESS_8_63_LEN ); REG64_FLD( PU_INT_CQ_ERR_INFO2_INFO_CAPTURED , 0 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_INFO_CAPTURED ); REG64_FLD( PU_INT_CQ_ERR_INFO2_RESERVED_1_5 , 1 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_RESERVED_1_5 ); REG64_FLD( PU_INT_CQ_ERR_INFO2_RESERVED_1_5_LEN , 5 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_RESERVED_1_5_LEN ); REG64_FLD( PU_INT_CQ_ERR_INFO2_HI , 6 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_HI ); REG64_FLD( PU_INT_CQ_ERR_INFO2_LO , 7 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_LO ); REG64_FLD( PU_INT_CQ_ERR_INFO2_RD_ADDR_0_7 , 8 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_RD_ADDR_0_7 ); REG64_FLD( PU_INT_CQ_ERR_INFO2_RD_ADDR_0_7_LEN , 8 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_RD_ADDR_0_7_LEN ); REG64_FLD( PU_INT_CQ_ERR_INFO2_SYN_HI_0_7 , 16 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_SYN_HI_0_7 ); REG64_FLD( PU_INT_CQ_ERR_INFO2_SYN_HI_0_7_LEN , 8 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_SYN_HI_0_7_LEN ); REG64_FLD( PU_INT_CQ_ERR_INFO2_SYN_LO_0_7 , 24 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_SYN_LO_0_7 ); REG64_FLD( PU_INT_CQ_ERR_INFO2_SYN_LO_0_7_LEN , 8 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_SYN_LO_0_7_LEN ); REG64_FLD( PU_INT_CQ_ERR_INFO3_INFO_CAPTURED , 0 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_INFO_CAPTURED ); REG64_FLD( PU_INT_CQ_ERR_INFO3_STQ_FSM_PERR , 1 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_STQ_FSM_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO3_LDQ_FSM_PERR , 2 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_LDQ_FSM_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO3_WRQ_FSM_PERR , 3 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_WRQ_FSM_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO3_RDQ_FSM_PERR , 4 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_RDQ_FSM_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO3_INTQ_FSM_PERR , 5 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_INTQ_FSM_PERR ); REG64_FLD( PU_INT_CQ_ERR_INFO3_WRQ_OVERFLOW , 6 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_WRQ_OVERFLOW ); REG64_FLD( PU_INT_CQ_ERR_INFO3_RDQ_OVERFLOW , 7 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_RDQ_OVERFLOW ); REG64_FLD( PU_INT_CQ_ERR_INFO3_INTQ_OVERFLOW , 8 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_INTQ_OVERFLOW ); REG64_FLD( PU_INT_CQ_ERR_RPT_HOLD_HOLD_0_48 , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_0_48 ); REG64_FLD( PU_INT_CQ_ERR_RPT_HOLD_HOLD_0_48_LEN , 49 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_0_48_LEN ); REG64_FLD( PU_INT_CQ_FIR_PI_ECC_CE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PI_ECC_CE ); REG64_FLD( PU_INT_CQ_FIR_PI_ECC_UE , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PI_ECC_UE ); REG64_FLD( PU_INT_CQ_FIR_PI_ECC_SUE , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PI_ECC_SUE ); REG64_FLD( PU_INT_CQ_FIR_ST_ECC_CE , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ST_ECC_CE ); REG64_FLD( PU_INT_CQ_FIR_ST_ECC_UE , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ST_ECC_UE ); REG64_FLD( PU_INT_CQ_FIR_LD_ECC_CE , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LD_ECC_CE ); REG64_FLD( PU_INT_CQ_FIR_LD_ECC_UE , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LD_ECC_UE ); REG64_FLD( PU_INT_CQ_FIR_CL_ECC_CE , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CL_ECC_CE ); REG64_FLD( PU_INT_CQ_FIR_CL_ECC_UE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CL_ECC_UE ); REG64_FLD( PU_INT_CQ_FIR_WR_ECC_CE , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WR_ECC_CE ); REG64_FLD( PU_INT_CQ_FIR_WR_ECC_UE , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WR_ECC_UE ); REG64_FLD( PU_INT_CQ_FIR_RD_ECC_CE , 11 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RD_ECC_CE ); REG64_FLD( PU_INT_CQ_FIR_RD_ECC_UE , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RD_ECC_UE ); REG64_FLD( PU_INT_CQ_FIR_AI_ECC_CE , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_AI_ECC_CE ); REG64_FLD( PU_INT_CQ_FIR_AI_ECC_UE , 14 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_AI_ECC_UE ); REG64_FLD( PU_INT_CQ_FIR_AIB_IN_CMD_CTL_PERR , 15 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_AIB_IN_CMD_CTL_PERR ); REG64_FLD( PU_INT_CQ_FIR_AIB_IN_CMD_PERR , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_AIB_IN_CMD_PERR ); REG64_FLD( PU_INT_CQ_FIR_AIB_IN_DAT_CTL_PERR , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_AIB_IN_DAT_CTL_PERR ); REG64_FLD( PU_INT_CQ_FIR_PB_PARITY_ERROR , 18 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PB_PARITY_ERROR ); REG64_FLD( PU_INT_CQ_FIR_PB_RCMDX_CI_ERR1 , 19 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PB_RCMDX_CI_ERR1 ); REG64_FLD( PU_INT_CQ_FIR_PB_RCMDX_CI_ERR2 , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PB_RCMDX_CI_ERR2 ); REG64_FLD( PU_INT_CQ_FIR_PB_RCMDX_CI_ERR3 , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PB_RCMDX_CI_ERR3 ); REG64_FLD( PU_INT_CQ_FIR_RCVD_POISONED_CIST_DATA , 22 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RCVD_POISONED_CIST_DATA ); REG64_FLD( PU_INT_CQ_FIR_MRT_ERR_NOT_VALID , 23 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MRT_ERR_NOT_VALID ); REG64_FLD( PU_INT_CQ_FIR_MRT_ERR_PSIZE , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MRT_ERR_PSIZE ); REG64_FLD( PU_INT_CQ_FIR_SCOM_S_ERR , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SCOM_S_ERR ); REG64_FLD( PU_INT_CQ_FIR_TCTXT_PRESP_ERROR , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_TCTXT_PRESP_ERROR ); REG64_FLD( PU_INT_CQ_FIR_WRQ_OP_HANG , 27 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRQ_OP_HANG ); REG64_FLD( PU_INT_CQ_FIR_RDQ_OP_HANG , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RDQ_OP_HANG ); REG64_FLD( PU_INT_CQ_FIR_INTQ_OP_HANG , 29 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INTQ_OP_HANG ); REG64_FLD( PU_INT_CQ_FIR_RDQ_DATA_HANG , 30 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RDQ_DATA_HANG ); REG64_FLD( PU_INT_CQ_FIR_STQ_DATA_HANG , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_STQ_DATA_HANG ); REG64_FLD( PU_INT_CQ_FIR_LDQ_DATA_HANG , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LDQ_DATA_HANG ); REG64_FLD( PU_INT_CQ_FIR_WRQ_BAD_CRESP , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRQ_BAD_CRESP ); REG64_FLD( PU_INT_CQ_FIR_RDQ_BAD_CRESP , 34 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RDQ_BAD_CRESP ); REG64_FLD( PU_INT_CQ_FIR_INTQ_BAD_CRESP , 35 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INTQ_BAD_CRESP ); REG64_FLD( PU_INT_CQ_FIR_BAD_128K_VP_OP , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BAD_128K_VP_OP ); REG64_FLD( PU_INT_CQ_FIR_RDQ_ABORT_OP , 37 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RDQ_ABORT_OP ); REG64_FLD( PU_INT_CQ_FIR_PC_CRD_PERR , 38 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PC_CRD_PERR ); REG64_FLD( PU_INT_CQ_FIR_PC_CRD_AVAIL_PERR , 39 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PC_CRD_AVAIL_PERR ); REG64_FLD( PU_INT_CQ_FIR_VC_CRD_PERR , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VC_CRD_PERR ); REG64_FLD( PU_INT_CQ_FIR_VC_CRD_AVAIL_PERR , 41 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VC_CRD_AVAIL_PERR ); REG64_FLD( PU_INT_CQ_FIR_CMD_QX_SEVERE_ERR , 42 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CMD_QX_SEVERE_ERR ); REG64_FLD( PU_INT_CQ_FIR_RDQ_ABORT_TRM , 43 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RDQ_ABORT_TRM ); REG64_FLD( PU_INT_CQ_FIR_UNSOLICITED_CRESP , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_UNSOLICITED_CRESP ); REG64_FLD( PU_INT_CQ_FIR_UNSOLICITED_PBDATA , 45 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_UNSOLICITED_PBDATA ); REG64_FLD( PU_INT_CQ_FIR_FIR_PARITY_ERR , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FIR_PARITY_ERR ); REG64_FLD( PU_INT_CQ_FIR_RESERVED_47 , 47 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_47 ); REG64_FLD( PU_INT_CQ_FIR_RESERVED_48 , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_48 ); REG64_FLD( PU_INT_CQ_FIR_PC_FATAL_ERROR_0_2 , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PC_FATAL_ERROR_0_2 ); REG64_FLD( PU_INT_CQ_FIR_PC_FATAL_ERROR_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PC_FATAL_ERROR_0_2_LEN ); REG64_FLD( PU_INT_CQ_FIR_PC_RECOV_ERROR_0_2 , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PC_RECOV_ERROR_0_2 ); REG64_FLD( PU_INT_CQ_FIR_PC_RECOV_ERROR_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PC_RECOV_ERROR_0_2_LEN ); REG64_FLD( PU_INT_CQ_FIR_PC_INFO_ERROR_0_2 , 55 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PC_INFO_ERROR_0_2 ); REG64_FLD( PU_INT_CQ_FIR_PC_INFO_ERROR_0_2_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PC_INFO_ERROR_0_2_LEN ); REG64_FLD( PU_INT_CQ_FIR_VC_FATAL_ERROR_0_1 , 58 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VC_FATAL_ERROR_0_1 ); REG64_FLD( PU_INT_CQ_FIR_VC_FATAL_ERROR_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VC_FATAL_ERROR_0_1_LEN ); REG64_FLD( PU_INT_CQ_FIR_VC_RECOV_ERROR_0_1 , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VC_RECOV_ERROR_0_1 ); REG64_FLD( PU_INT_CQ_FIR_VC_RECOV_ERROR_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VC_RECOV_ERROR_0_1_LEN ); REG64_FLD( PU_INT_CQ_FIR_VC_INFO_ERROR_0_1 , 62 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VC_INFO_ERROR_0_1 ); REG64_FLD( PU_INT_CQ_FIR_VC_INFO_ERROR_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VC_INFO_ERROR_0_1_LEN ); REG64_FLD( PU_INT_CQ_FIRMASK_FIR_MASK , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FIR_MASK ); REG64_FLD( PU_INT_CQ_FIRMASK_FIR_MASK_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FIR_MASK_LEN ); REG64_FLD( PU_INT_CQ_IC_BAR_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_INT_CQ_IC_BAR_PAGE_SIZE_64K , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PAGE_SIZE_64K ); REG64_FLD( PU_INT_CQ_IC_BAR_ADDR_8_48 , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_8_48 ); REG64_FLD( PU_INT_CQ_IC_BAR_ADDR_8_48_LEN , 41 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_8_48_LEN ); REG64_FLD( PU_INT_CQ_MSGSND_CORES_ENABLED_0_23 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CORES_ENABLED_0_23 ); REG64_FLD( PU_INT_CQ_MSGSND_CORES_ENABLED_0_23_LEN , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CORES_ENABLED_0_23_LEN ); REG64_FLD( PU_INT_CQ_PBI_CTL_DIS_ECCCHK , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DIS_ECCCHK ); REG64_FLD( PU_INT_CQ_PBI_CTL_DIS_ECCCHK_STO , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_DIS_ECCCHK_STO ); REG64_FLD( PU_INT_CQ_PBI_CTL_RESERVED_2 , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_2 ); REG64_FLD( PU_INT_CQ_PBI_CTL_RESERVED_3 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_3 ); REG64_FLD( PU_INT_CQ_PBI_CTL_RESERVED_4 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_4 ); REG64_FLD( PU_INT_CQ_PBI_CTL_PAGE_SIZE_64K_PC , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PAGE_SIZE_64K_PC ); REG64_FLD( PU_INT_CQ_PBI_CTL_PAGE_SIZE_64K_VC , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PAGE_SIZE_64K_VC ); REG64_FLD( PU_INT_CQ_PBI_CTL_LINUX_TRIG_MODE , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_LINUX_TRIG_MODE ); REG64_FLD( PU_INT_CQ_PBI_CTL_TRACE_BUS_SEL_0_1 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_BUS_SEL_0_1 ); REG64_FLD( PU_INT_CQ_PBI_CTL_TRACE_BUS_SEL_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_BUS_SEL_0_1_LEN ); REG64_FLD( PU_INT_CQ_PBI_CTL_TRACE_SEL_0_1 , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_SEL_0_1 ); REG64_FLD( PU_INT_CQ_PBI_CTL_TRACE_SEL_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_SEL_0_1_LEN ); REG64_FLD( PU_INT_CQ_PBI_CTL_DIS_DMA_W , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_DIS_DMA_W ); REG64_FLD( PU_INT_CQ_PBI_CTL_STRICT_IPI_RULES , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_STRICT_IPI_RULES ); REG64_FLD( PU_INT_CQ_PBI_CTL_FORCE_ECC_CE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_FORCE_ECC_CE ); REG64_FLD( PU_INT_CQ_PBI_CTL_FORCE_ECC_UE , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_FORCE_ECC_UE ); REG64_FLD( PU_INT_CQ_PBI_CTL_FORCE_ECC_SEL , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_FORCE_ECC_SEL ); REG64_FLD( PU_INT_CQ_PBI_CTL_SPEC_CILD_G , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPEC_CILD_G ); REG64_FLD( PU_INT_CQ_PBI_CTL_EN_SPEC_CILD_IVE , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_SPEC_CILD_IVE ); REG64_FLD( PU_INT_CQ_PBI_CTL_EN_SPEC_CILD_EQD , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_SPEC_CILD_EQD ); REG64_FLD( PU_INT_CQ_PBI_CTL_EN_SPEC_CILD_VPC_HW , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_SPEC_CILD_VPC_HW ); REG64_FLD( PU_INT_CQ_PBI_CTL_EN_SPEC_CILD_VPC_SW , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_SPEC_CILD_VPC_SW ); REG64_FLD( PU_INT_CQ_PBI_CTL_RESERVED_22_31 , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_22_31 ); REG64_FLD( PU_INT_CQ_PBI_CTL_RESERVED_22_31_LEN , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_22_31_LEN ); REG64_FLD( PU_INT_CQ_PBO_CTL_DIS_ECCCHK_LDO , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DIS_ECCCHK_LDO ); REG64_FLD( PU_INT_CQ_PBO_CTL_DIS_ECCCHK_WRO , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_DIS_ECCCHK_WRO ); REG64_FLD( PU_INT_CQ_PBO_CTL_DIS_ECCCHK_CLO , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_DIS_ECCCHK_CLO ); REG64_FLD( PU_INT_CQ_PBO_CTL_RESERVED_3 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_3 ); REG64_FLD( PU_INT_CQ_PBO_CTL_STRICT_ORDER , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_STRICT_ORDER ); REG64_FLD( PU_INT_CQ_PBO_CTL_FORCE_MAX_SCOPE_INTRP , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_FORCE_MAX_SCOPE_INTRP ); REG64_FLD( PU_INT_CQ_PBO_CTL_FORCE_VG_SYS_INTRP , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_FORCE_VG_SYS_INTRP ); REG64_FLD( PU_INT_CQ_PBO_CTL_DROP_PRI_INTRP , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_DROP_PRI_INTRP ); REG64_FLD( PU_INT_CQ_PBO_CTL_DROP_PRI_HPC_READ , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_DROP_PRI_HPC_READ ); REG64_FLD( PU_INT_CQ_PBO_CTL_DROP_PRI_DMA , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_DROP_PRI_DMA ); REG64_FLD( PU_INT_CQ_PBO_CTL_DROP_MASK_0_5 , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_DROP_MASK_0_5 ); REG64_FLD( PU_INT_CQ_PBO_CTL_DROP_MASK_0_5_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_DROP_MASK_0_5_LEN ); REG64_FLD( PU_INT_CQ_PBO_CTL_SLOW_CMD_RATE , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_SLOW_CMD_RATE ); REG64_FLD( PU_INT_CQ_PBO_CTL_EN_RANDOM_BACKOFF , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_RANDOM_BACKOFF ); REG64_FLD( PU_INT_CQ_PBO_CTL_EN_POLL_BACKOFF , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN_POLL_BACKOFF ); REG64_FLD( PU_INT_CQ_PBO_CTL_RESERVED_19 , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_19 ); REG64_FLD( PU_INT_CQ_PBO_CTL_FORCE_ECC_CE , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_FORCE_ECC_CE ); REG64_FLD( PU_INT_CQ_PBO_CTL_FORCE_ECC_UE , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_FORCE_ECC_UE ); REG64_FLD( PU_INT_CQ_PBO_CTL_FORCE_ECC_SEL_0_1 , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_FORCE_ECC_SEL_0_1 ); REG64_FLD( PU_INT_CQ_PBO_CTL_FORCE_ECC_SEL_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_FORCE_ECC_SEL_0_1_LEN ); REG64_FLD( PU_INT_CQ_PBO_CTL_DISABLE_INJECT , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_INJECT ); REG64_FLD( PU_INT_CQ_PBO_CTL_FORCE_CL_INJECT , 25 , SH_UNT , SH_ACS_SCOM , SH_FLD_FORCE_CL_INJECT ); REG64_FLD( PU_INT_CQ_PBO_CTL_FORCE_PR_INJECT , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_FORCE_PR_INJECT ); REG64_FLD( PU_INT_CQ_PBO_CTL_HANG_ON_ADDR_ERROR , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_HANG_ON_ADDR_ERROR ); REG64_FLD( PU_INT_CQ_PBO_CTL_HANG_ON_ACK_DEAD , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_HANG_ON_ACK_DEAD ); REG64_FLD( PU_INT_CQ_PBO_CTL_POLL_BCST_RTY_MON , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_POLL_BCST_RTY_MON ); REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_1_0_4 , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_POLL_BCAST_1_0_4 ); REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_1_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_POLL_BCAST_1_0_4_LEN ); REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_2_0_4 , 35 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_POLL_BCAST_2_0_4 ); REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_2_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_POLL_BCAST_2_0_4_LEN ); REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_3_0_4 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_POLL_BCAST_3_0_4 ); REG64_FLD( PU_INT_CQ_PBO_CTL_MAX_POLL_BCAST_3_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_POLL_BCAST_3_0_4_LEN ); REG64_FLD( PU_INT_CQ_PBO_CTL_DISABLE_NN_RN , 45 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_NN_RN ); REG64_FLD( PU_INT_CQ_PBO_CTL_DISABLE_VG_NOT_SYS , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_VG_NOT_SYS ); REG64_FLD( PU_INT_CQ_PBO_CTL_DISABLE_G , 47 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_G ); REG64_FLD( PU_INT_CQ_PBO_CTL_DISABLE_LN , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_LN ); REG64_FLD( PU_INT_CQ_PBO_CTL_SKIP_G , 49 , SH_UNT , SH_ACS_SCOM , SH_FLD_SKIP_G ); REG64_FLD( PU_INT_CQ_PBO_CTL_RESERVED_50_63 , 50 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_50_63 ); REG64_FLD( PU_INT_CQ_PBO_CTL_RESERVED_50_63_LEN , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_50_63_LEN ); REG64_FLD( PU_INT_CQ_PC_BAR_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_INT_CQ_PC_BAR_ADDR_8_38 , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_8_38 ); REG64_FLD( PU_INT_CQ_PC_BAR_ADDR_8_38_LEN , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_8_38_LEN ); REG64_FLD( PU_INT_CQ_PC_BARM_ADDR_26_38 , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_26_38 ); REG64_FLD( PU_INT_CQ_PC_BARM_ADDR_26_38_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_26_38_LEN ); REG64_FLD( PU_INT_CQ_PMC_0_COUNT_47 , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_COUNT_47 ); REG64_FLD( PU_INT_CQ_PMC_0_COUNT_47_LEN , 48 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_COUNT_47_LEN ); REG64_FLD( PU_INT_CQ_PMC_1_COUNT_0_47 , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_COUNT_0_47 ); REG64_FLD( PU_INT_CQ_PMC_1_COUNT_0_47_LEN , 48 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_COUNT_0_47_LEN ); REG64_FLD( PU_INT_CQ_PMC_2_COUNT_0_47 , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_COUNT_0_47 ); REG64_FLD( PU_INT_CQ_PMC_2_COUNT_0_47_LEN , 48 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_COUNT_0_47_LEN ); REG64_FLD( PU_INT_CQ_PMC_3_COUNT_0_47 , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_COUNT_0_47 ); REG64_FLD( PU_INT_CQ_PMC_3_COUNT_0_47_LEN , 48 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_COUNT_0_47_LEN ); REG64_FLD( PU_INT_CQ_PMC_4_COUNT_0_47 , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_COUNT_0_47 ); REG64_FLD( PU_INT_CQ_PMC_4_COUNT_0_47_LEN , 48 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_COUNT_0_47_LEN ); REG64_FLD( PU_INT_CQ_PMC_5_COUNT_0_47 , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_COUNT_0_47 ); REG64_FLD( PU_INT_CQ_PMC_5_COUNT_0_47_LEN , 48 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_COUNT_0_47_LEN ); REG64_FLD( PU_INT_CQ_PMC_6_COUNT_0_47 , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_COUNT_0_47 ); REG64_FLD( PU_INT_CQ_PMC_6_COUNT_0_47_LEN , 48 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_COUNT_0_47_LEN ); REG64_FLD( PU_INT_CQ_PMC_7_COUNT_0_47 , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_COUNT_0_47 ); REG64_FLD( PU_INT_CQ_PMC_7_COUNT_0_47_LEN , 48 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_COUNT_0_47_LEN ); REG64_FLD( PU_INT_CQ_PM_CTL_ENABLE_0_7 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_0_7 ); REG64_FLD( PU_INT_CQ_PM_CTL_ENABLE_0_7_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_0_7_LEN ); REG64_FLD( PU_INT_CQ_PM_CTL_RESET_0_7 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESET_0_7 ); REG64_FLD( PU_INT_CQ_PM_CTL_RESET_0_7_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESET_0_7_LEN ); REG64_FLD( PU_INT_CQ_PM_CTL_SOURCE_SUBUNIT_0_1 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_SOURCE_SUBUNIT_0_1 ); REG64_FLD( PU_INT_CQ_PM_CTL_SOURCE_SUBUNIT_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_SOURCE_SUBUNIT_0_1_LEN ); REG64_FLD( PU_INT_CQ_PM_CTL_GROUP_SEL_0_4 , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_GROUP_SEL_0_4 ); REG64_FLD( PU_INT_CQ_PM_CTL_GROUP_SEL_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_GROUP_SEL_0_4_LEN ); REG64_FLD( PU_INT_CQ_RST_CTL_SYNC_RESET , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_SYNC_RESET ); REG64_FLD( PU_INT_CQ_RST_CTL_QUIESCE_PB , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_QUIESCE_PB ); REG64_FLD( PU_INT_CQ_RST_CTL_MASTER_IDLE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASTER_IDLE ); REG64_FLD( PU_INT_CQ_RST_CTL_SLAVE_IDLE , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_SLAVE_IDLE ); REG64_FLD( PU_INT_CQ_RST_CTL_PB_BAR_RESET , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PB_BAR_RESET ); REG64_FLD( PU_INT_CQ_RST_CTL_RESERVED_5_7 , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_5_7 ); REG64_FLD( PU_INT_CQ_RST_CTL_RESERVED_5_7_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_5_7_LEN ); REG64_FLD( PU_INT_CQ_SWI_RSP_HIST_DONE , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HIST_DONE ); REG64_FLD( PU_INT_CQ_SWI_RSP_POLL_DONE , 1 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_POLL_DONE ); REG64_FLD( PU_INT_CQ_SWI_RSP_BCAST_DONE , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_BCAST_DONE ); REG64_FLD( PU_INT_CQ_SWI_RSP_ASSIGN_DONE , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ASSIGN_DONE ); REG64_FLD( PU_INT_CQ_SWI_RSP_BLK_UPDT_DONE , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_BLK_UPDT_DONE ); REG64_FLD( PU_INT_CQ_SWI_RSP_Z , 5 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_Z ); REG64_FLD( PU_INT_CQ_SWI_RSP_O , 6 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O ); REG64_FLD( PU_INT_CQ_SWI_RSP_M , 7 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_M ); REG64_FLD( PU_INT_CQ_SWI_RSP_CRESP_0_4 , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CRESP_0_4 ); REG64_FLD( PU_INT_CQ_SWI_RSP_CRESP_0_4_LEN , 5 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CRESP_0_4_LEN ); REG64_FLD( PU_INT_CQ_SWI_RSP_RESERVED_13 , 13 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RESERVED_13 ); REG64_FLD( PU_INT_CQ_SWI_RSP_COLLISON , 14 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_COLLISON ); REG64_FLD( PU_INT_CQ_SWI_RSP_PRECLUDE , 15 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PRECLUDE ); REG64_FLD( PU_INT_CQ_SWI_RSP_ATAG_0_15 , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ATAG_0_15 ); REG64_FLD( PU_INT_CQ_SWI_RSP_ATAG_0_15_LEN , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ATAG_0_15_LEN ); REG64_FLD( PU_INT_CQ_TAR_AUTO_INC , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_AUTO_INC ); REG64_FLD( PU_INT_CQ_TAR_TABLE_SEL_0_3 , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_TABLE_SEL_0_3 ); REG64_FLD( PU_INT_CQ_TAR_TABLE_SEL_0_3_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_TABLE_SEL_0_3_LEN ); REG64_FLD( PU_INT_CQ_TAR_ENTRY_SEL_0_5 , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENTRY_SEL_0_5 ); REG64_FLD( PU_INT_CQ_TAR_ENTRY_SEL_0_5_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENTRY_SEL_0_5_LEN ); REG64_FLD( PU_INT_CQ_TM1_BAR_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_INT_CQ_TM1_BAR_PAGE_SIZE_64K , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PAGE_SIZE_64K ); REG64_FLD( PU_INT_CQ_TM1_BAR_ADDR_8_49 , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_8_49 ); REG64_FLD( PU_INT_CQ_TM1_BAR_ADDR_8_49_LEN , 42 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_8_49_LEN ); REG64_FLD( PU_INT_CQ_TM2_BAR_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_INT_CQ_TM2_BAR_PAGE_SIZE_64K , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PAGE_SIZE_64K ); REG64_FLD( PU_INT_CQ_TM2_BAR_ADDR_8_49 , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_8_49 ); REG64_FLD( PU_INT_CQ_TM2_BAR_ADDR_8_49_LEN , 42 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_8_49_LEN ); REG64_FLD( PU_INT_CQ_VC_BAR_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_INT_CQ_VC_BAR_ADDR_8_37 , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_8_37 ); REG64_FLD( PU_INT_CQ_VC_BAR_ADDR_8_37_LEN , 30 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_8_37_LEN ); REG64_FLD( PU_INT_CQ_VC_BARM_ADDR_21_37 , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_21_37 ); REG64_FLD( PU_INT_CQ_VC_BARM_ADDR_21_37_LEN , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_21_37_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_VLD ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0 ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE0_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_VLD ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0 ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE1_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_VLD ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0 ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE10_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_VLD ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0 ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE11_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_VLD ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0 ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE12_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_VLD ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0 ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE13_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_VLD ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0 ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE14_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_VLD ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0 ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE15_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_VLD ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0 ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE2_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_VLD ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0 ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE3_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_VLD ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0 ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE4_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_VLD ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0 ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE5_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_VLD ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0 ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE6_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_VLD ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0 ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE7_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_VLD ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0 ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE8_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_VLD , 0 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_VLD ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_LVL , 1 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_LVL_LEN , 23 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_LVL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_CQ , 24 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_CQ_LEN , 12 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_CQ_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_DETAIL , 36 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_DETAIL_LEN , 20 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_DETAIL_LEN ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_RSVD0 , 56 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0 ); REG64_FLD( PU_NPU_NTL1_INT_LOG_PE9_ERR_RSVD0_LEN , 8 , SH_UNT_PU_NPU_NTL1, SH_ACS_SCOM , SH_FLD_ERR_RSVD0_LEN ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_1 ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_1_LEN ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH0_MAX , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH0_MAX ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH0_MAX_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH0_MAX_LEN ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_8_9 , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_8_9 ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_8_9_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_8_9_LEN ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH1_MAX , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH1_MAX ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH1_MAX_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH1_MAX_LEN ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_16_17 , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_16_17 ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_16_17_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_16_17_LEN ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH2_MAX , 18 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH2_MAX ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH2_MAX_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH2_MAX_LEN ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_24_25 , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24_25 ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_RESERVED_24_25_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24_25_LEN ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH3_MAX , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH3_MAX ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_CMD_CH3_MAX_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH3_MAX_LEN ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_1 ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_1_LEN ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH0_MAX , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH0_MAX ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH0_MAX_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH0_MAX_LEN ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_8_9 , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_8_9 ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_8_9_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_8_9_LEN ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH1_MAX , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH1_MAX ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH1_MAX_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH1_MAX_LEN ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_16_17 , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_16_17 ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_16_17_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_16_17_LEN ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH2_MAX , 18 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH2_MAX ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH2_MAX_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH2_MAX_LEN ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_24_25 , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24_25 ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_RESERVED_24_25_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24_25_LEN ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH3_MAX , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH3_MAX ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_DAT_CH3_MAX_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH3_MAX_LEN ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_INIT_INIT_REQUEST , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INIT_REQUEST ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_INIT_RESERVED_1_7 , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_1_7 ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_INIT_RESERVED_1_7_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_1_7_LEN ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_INIT_INIT_TIMER , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INIT_TIMER ); REG64_FLD( PU_INT_PC_AIB_RX_CRD_INIT_INIT_TIMER_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INIT_TIMER_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_CRD_INIT_REQUEST , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CRD_INIT_REQUEST ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_25 , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_25 ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_DMA_READ , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_DMA_READ ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_DMA_READ_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_DMA_READ_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_VPC_LD_RMT , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_VPC_LD_RMT ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_VPC_LD_RMT_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_VPC_LD_RMT_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_AT_MACRO , 30 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_AT_MACRO ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_AT_MACRO_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_AT_MACRO_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_32_34 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_34 ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_32_34_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_34_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_READ_POOL , 35 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_READ_POOL ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_READ_POOL_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_READ_POOL_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_40_47 , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_40_47 ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_40_47_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_40_47_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_TCTXT_WRITE , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_TCTXT_WRITE ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_TCTXT_WRITE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_TCTXT_WRITE_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_50_51 , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_50_51 ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_50_51_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_50_51_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_DMA_WRITE , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_DMA_WRITE ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_DMA_WRITE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_DMA_WRITE_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_VPC_ST_RMT , 54 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_VPC_ST_RMT ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_VPC_ST_RMT_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_VPC_ST_RMT_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_VPC_ST_RMT_VC , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_VPC_ST_RMT_VC ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RSD_VPC_ST_RMT_VC_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_VPC_ST_RMT_VC_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_RESERVED_58 , 58 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_58 ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_WRITE_POOL , 59 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRITE_POOL ); REG64_FLD( PU_INT_PC_AIB_TX_CRD_WRITE_POOL_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRITE_POOL_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_ORDER_RESERVED_12_13 , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_12_13 ); REG64_FLD( PU_INT_PC_AIB_TX_ORDER_RESERVED_12_13_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_12_13_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_ORDER_RELAXED_WR_ORDERING , 14 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RELAXED_WR_ORDERING ); REG64_FLD( PU_INT_PC_AIB_TX_ORDER_RESERVED_15 , 15 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_15 ); REG64_FLD( PU_INT_PC_AIB_TX_ORDER_REGS_ORDERING_TAG , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_REGS_ORDERING_TAG ); REG64_FLD( PU_INT_PC_AIB_TX_ORDER_REGS_ORDERING_TAG_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_REGS_ORDERING_TAG_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_DMA_ORDERING_TAG , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VPC_DMA_ORDERING_TAG ); REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_DMA_ORDERING_TAG_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VPC_DMA_ORDERING_TAG_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_LD_RSP_ORDERING_TAG , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VPC_LD_RSP_ORDERING_TAG ); REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_LD_RSP_ORDERING_TAG_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VPC_LD_RSP_ORDERING_TAG_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_LD_RMT_ORDERING_TAG , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VPC_LD_RMT_ORDERING_TAG ); REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_LD_RMT_ORDERING_TAG_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VPC_LD_RMT_ORDERING_TAG_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_ORDERING_TAG , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VPC_ST_RMT_ORDERING_TAG ); REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_ORDERING_TAG_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VPC_ST_RMT_ORDERING_TAG_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_VC_ORDERING_TAG , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VPC_ST_RMT_VC_ORDERING_TAG ); REG64_FLD( PU_INT_PC_AIB_TX_ORDER_VPC_ST_RMT_VC_ORDERING_TAG_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VPC_ST_RMT_VC_ORDERING_TAG_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_LIMIT_AT_DEM_IN_PIPE , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_LIMIT_AT_DEM_IN_PIPE ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_RESERVED_41_43 , 41 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_41_43 ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_RESERVED_41_43_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_41_43_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_REGS , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_REGS ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_REGS_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_REGS_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_TCTXT_RSP_WR , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_TCTXT_RSP_WR ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_TCTXT_RSP_WR_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_TCTXT_RSP_WR_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_BLCK_UPD , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_BLCK_UPD ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_BLCK_UPD_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_BLCK_UPD_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_RESERVED_50_51 , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_50_51 ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_RESERVED_50_51_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_50_51_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_DMA , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_VPC_DMA ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_DMA_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_VPC_DMA_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_CI_LD , 54 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_VPC_CI_LD ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_CI_LD_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_VPC_CI_LD_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_LD_RMT , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_VPC_LD_RMT ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_LD_RMT_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_VPC_LD_RMT_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_LCL_VC , 58 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_VPC_ST_LCL_VC ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_LCL_VC_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_VPC_ST_LCL_VC_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_RMT , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_VPC_ST_RMT ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_RMT_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_VPC_ST_RMT_LEN ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_RMT_VC , 62 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_VPC_ST_RMT_VC ); REG64_FLD( PU_INT_PC_AIB_TX_PRIO_ATX_FOR_VPC_ST_RMT_VC_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_FOR_VPC_ST_RMT_VC_LEN ); REG64_FLD( PU_INT_PC_AT_KILL_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_INT_PC_AT_KILL_RESERVED_24_26 , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24_26 ); REG64_FLD( PU_INT_PC_AT_KILL_RESERVED_24_26_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24_26_LEN ); REG64_FLD( PU_INT_PC_AT_KILL_BLOCKID , 27 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID ); REG64_FLD( PU_INT_PC_AT_KILL_BLOCKID_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID_LEN ); REG64_FLD( PU_INT_PC_AT_KILL_OFFSET , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET ); REG64_FLD( PU_INT_PC_AT_KILL_OFFSET_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET_LEN ); REG64_FLD( PU_INT_PC_AT_KILL_RESERVED_61_63 , 61 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_61_63 ); REG64_FLD( PU_INT_PC_AT_KILL_RESERVED_61_63_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_61_63_LEN ); REG64_FLD( PU_INT_PC_AT_KILL_MASK_RESERVED_24_26 , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24_26 ); REG64_FLD( PU_INT_PC_AT_KILL_MASK_RESERVED_24_26_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24_26_LEN ); REG64_FLD( PU_INT_PC_AT_KILL_MASK_BLOCKID , 27 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID ); REG64_FLD( PU_INT_PC_AT_KILL_MASK_BLOCKID_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID_LEN ); REG64_FLD( PU_INT_PC_AT_KILL_MASK_OFFSET , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET ); REG64_FLD( PU_INT_PC_AT_KILL_MASK_OFFSET_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET_LEN ); REG64_FLD( PU_INT_PC_AT_KILL_MASK_RESERVED_61_63 , 61 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_61_63 ); REG64_FLD( PU_INT_PC_AT_KILL_MASK_RESERVED_61_63_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_61_63_LEN ); REG64_FLD( PU_INT_PC_DBG_ECC_DIS_CRESP_CORR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_CRESP_CORR ); REG64_FLD( PU_INT_PC_DBG_ECC_DIS_ARX_DAT_CORR , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_ARX_DAT_CORR ); REG64_FLD( PU_INT_PC_DBG_ECC_DIS_ARX_DAT_CORR_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_ARX_DAT_CORR_LEN ); REG64_FLD( PU_INT_PC_DBG_ECC_DIS_ARX_TAG_CORR , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_ARX_TAG_CORR ); REG64_FLD( PU_INT_PC_DBG_ECC_DIS_MMIO_LDST_CORR , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_MMIO_LDST_CORR ); REG64_FLD( PU_INT_PC_DBG_ECC_DIS_MMIO_RSP_CORR , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_MMIO_RSP_CORR ); REG64_FLD( PU_INT_PC_DBG_ECC_DIS_VRQ_QUEUE_CORR , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_VRQ_QUEUE_CORR ); REG64_FLD( PU_INT_PC_DBG_ECC_DIS_AVX_CORR , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_AVX_CORR ); REG64_FLD( PU_INT_PC_DBG_ECC_DIS_ATX_CMD_CORR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_ATX_CMD_CORR ); REG64_FLD( PU_INT_PC_DBG_ECC_DIS_ATX_BAR_CORR , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_ATX_BAR_CORR ); REG64_FLD( PU_INT_PC_DBG_ECC_DIS_ATX_AT_CORR , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_ATX_AT_CORR ); REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_11_15 , 11 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_11_15 ); REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_11_15_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_11_15_LEN ); REG64_FLD( PU_INT_PC_DBG_ECC_FORCE_SINGLE_BIT_ERR , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FORCE_SINGLE_BIT_ERR ); REG64_FLD( PU_INT_PC_DBG_ECC_FORCE_DOUBLE_BIT_ERR , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FORCE_DOUBLE_BIT_ERR ); REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_CRESP_SRAM , 18 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ARY_SELECT_CRESP_SRAM ); REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_19 , 19 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_19 ); REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_CMD_RSP_SRAM , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ARY_SELECT_CMD_RSP_SRAM ); REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_CMD_VRQ_SRAM , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ARY_SELECT_CMD_VRQ_SRAM ); REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_CMD_SSA , 22 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ARY_SELECT_ATX_CMD_SSA ); REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_CMD_SSA_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ARY_SELECT_ATX_CMD_SSA_LEN ); REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_VPC_SSA , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ARY_SELECT_ATX_VPC_SSA ); REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_VPC_SSA_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ARY_SELECT_ATX_VPC_SSA_LEN ); REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_BAR_SRAM , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ARY_SELECT_ATX_BAR_SRAM ); REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_AT_SSA , 27 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ARY_SELECT_ATX_AT_SSA ); REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_AIB , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ARY_SELECT_ATX_AIB ); REG64_FLD( PU_INT_PC_DBG_ECC_ARY_SELECT_ATX_AIB_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ARY_SELECT_ATX_AIB_LEN ); REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_30_31 , 30 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_30_31 ); REG64_FLD( PU_INT_PC_DBG_ECC_RESERVED_30_31_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_30_31_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_RESERVED_0_15 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_15 ); REG64_FLD( PU_INT_PC_DBG_PMC_RESERVED_0_15_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_15_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R0 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R0_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R0_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R1R , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1R ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R1R_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1R_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R1W , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1W ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R1W_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1W_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R2 , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R2 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R2_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R2_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R3 , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R3 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R3_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R3_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R4R , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R4R ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R4R_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R4R_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R4W , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R4W ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R4W_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R4W_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R5 , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R5 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R5_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R5_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R6 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R6 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R6_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R6_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R7 , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R7_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R8 , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R8 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R8_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R8_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R9 , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R9 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX0_CNT_R9_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R9_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R0 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R0_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R0_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R1R , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1R ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R1R_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1R_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R1W , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1W ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R1W_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1W_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R2 , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R2 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R2_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R2_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R3 , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R3 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R3_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R3_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R4R , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R4R ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R4R_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R4R_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R4W , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R4W ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R4W_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R4W_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R5 , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R5 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R5_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R5_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R6 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R6 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R6_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R6_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R7 , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R7_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R8 , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R8 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R8_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R8_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R9 , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R9 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX1_CNT_R9_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R9_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R0 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R0_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R0_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R1R , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1R ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R1R_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1R_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R1W , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1W ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R1W_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1W_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R2 , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R2 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R2_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R2_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R3 , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R3 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R3_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R3_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R4R , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R4R ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R4R_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R4R_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R4W , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R4W ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R4W_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R4W_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R5 , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R5 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R5_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R5_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R6 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R6 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R6_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R6_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R7 , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R7_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R8 , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R8 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R8_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R8_LEN ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R9 , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R9 ); REG64_FLD( PU_INT_PC_DBG_PMC_ATX2_CNT_R9_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R9_LEN ); REG64_FLD( PU_INT_PC_DBG_TMOT_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_1 ); REG64_FLD( PU_INT_PC_DBG_TMOT_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_1_LEN ); REG64_FLD( PU_INT_PC_DBG_TMOT_ARX_TIMEOUT , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ARX_TIMEOUT ); REG64_FLD( PU_INT_PC_DBG_TMOT_ARX_TIMEOUT_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ARX_TIMEOUT_LEN ); REG64_FLD( PU_INT_PC_DBG_TMOT_RESERVED_8_9 , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_8_9 ); REG64_FLD( PU_INT_PC_DBG_TMOT_RESERVED_8_9_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_8_9_LEN ); REG64_FLD( PU_INT_PC_DBG_TMOT_MMIO_LDST_TIMEOUT , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MMIO_LDST_TIMEOUT ); REG64_FLD( PU_INT_PC_DBG_TMOT_MMIO_LDST_TIMEOUT_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MMIO_LDST_TIMEOUT_LEN ); REG64_FLD( PU_INT_PC_DBG_TRACE_RESERVED_0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0 ); REG64_FLD( PU_INT_PC_DBG_TRACE_RESERVED_1 , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_1 ); REG64_FLD( PU_INT_PC_EQD_BLOCK_MODE_MODE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MODE ); REG64_FLD( PU_INT_PC_EQD_BLOCK_MODE_MODE_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MODE_LEN ); REG64_FLD( PU_INT_PC_ERR0_CFG0_ERROR_CONFIG0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_CONFIG0 ); REG64_FLD( PU_INT_PC_ERR0_CFG0_ERROR_CONFIG0_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_CONFIG0_LEN ); REG64_FLD( PU_INT_PC_ERR0_CFG1_ERROR_CONFIG0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_CONFIG0 ); REG64_FLD( PU_INT_PC_ERR0_CFG1_ERROR_CONFIG0_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_CONFIG0_LEN ); REG64_FLD( PU_INT_PC_ERR0_FATAL_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR ); REG64_FLD( PU_INT_PC_ERR0_FATAL_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_PC_ERR0_INFO_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR ); REG64_FLD( PU_INT_PC_ERR0_INFO_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_PC_ERR0_RECOV_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR ); REG64_FLD( PU_INT_PC_ERR0_RECOV_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_PC_ERR0_WOF_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR ); REG64_FLD( PU_INT_PC_ERR0_WOF_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_PC_ERR0_WOF_DETAIL_DETAIL , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DETAIL ); REG64_FLD( PU_INT_PC_ERR0_WOF_DETAIL_DETAIL_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DETAIL_LEN ); REG64_FLD( PU_INT_PC_ERR1_CFG0_ERROR_CONFIG0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_CONFIG0 ); REG64_FLD( PU_INT_PC_ERR1_CFG0_ERROR_CONFIG0_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_CONFIG0_LEN ); REG64_FLD( PU_INT_PC_ERR1_CFG1_ERROR_CONFIG0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_CONFIG0 ); REG64_FLD( PU_INT_PC_ERR1_CFG1_ERROR_CONFIG0_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_CONFIG0_LEN ); REG64_FLD( PU_INT_PC_ERR1_FATAL_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR ); REG64_FLD( PU_INT_PC_ERR1_FATAL_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_PC_ERR1_INFO_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR ); REG64_FLD( PU_INT_PC_ERR1_INFO_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_PC_ERR1_RECOV_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR ); REG64_FLD( PU_INT_PC_ERR1_RECOV_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_PC_ERR1_WOF_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR ); REG64_FLD( PU_INT_PC_ERR1_WOF_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_PC_ERR1_WOF_DETAIL_DETAIL , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DETAIL ); REG64_FLD( PU_INT_PC_ERR1_WOF_DETAIL_DETAIL_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DETAIL_LEN ); REG64_FLD( PU_INT_PC_GLOBAL_CFG_INDIRECT_MODE , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INDIRECT_MODE ); REG64_FLD( PU_INT_PC_GLOBAL_CFG_RESERVED_33_39 , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_33_39 ); REG64_FLD( PU_INT_PC_GLOBAL_CFG_RESERVED_33_39_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_33_39_LEN ); REG64_FLD( PU_INT_PC_IVE_BLOCK_MODE_MODE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MODE ); REG64_FLD( PU_INT_PC_IVE_BLOCK_MODE_MODE_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MODE_LEN ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_LDST_PRIO_SET_LD , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_LDST_PRIO_SET_LD ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_LDST_PRIO_SET_LD_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_LDST_PRIO_SET_LD_LEN ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_LDST_PRIO_RSP_LD , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_LDST_PRIO_RSP_LD ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_LDST_PRIO_RSP_LD_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_LDST_PRIO_RSP_LD_LEN ); REG64_FLD( PU_INT_PC_MMIO_ARB_RESERVED_4_5 , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_4_5 ); REG64_FLD( PU_INT_PC_MMIO_ARB_RESERVED_4_5_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_4_5_LEN ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PARSE_PULL_RR_SEL , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_DONE_PARSE_PULL_RR_SEL ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PARSE_PULL_RR_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_DONE_PARSE_PULL_RR_SEL_LEN ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PARSE_IACK_RR_SEL , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_DONE_PARSE_IACK_RR_SEL ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PARSE_IACK_RR_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_DONE_PARSE_IACK_RR_SEL_LEN ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PULL_PRIO_HYP , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_DONE_PULL_PRIO_HYP ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PULL_PRIO_HYP_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_DONE_PULL_PRIO_HYP_LEN ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_IACK_PRIO_HYP , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_DONE_IACK_PRIO_HYP ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_IACK_PRIO_HYP_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_DONE_IACK_PRIO_HYP_LEN ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PRIO_IACK , 14 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_DONE_PRIO_IACK ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_DONE_PRIO_IACK_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_DONE_PRIO_IACK_LEN ); REG64_FLD( PU_INT_PC_MMIO_ARB_RESERVED_16 , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_16 ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_LDST_SET , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PCMD_PRIO_LDST_SET ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_LDST_SET_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PCMD_PRIO_LDST_SET_LEN ); REG64_FLD( PU_INT_PC_MMIO_ARB_RESERVED_20 , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_20 ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_LDST_RSP , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PCMD_PRIO_LDST_RSP ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_LDST_RSP_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PCMD_PRIO_LDST_RSP_LEN ); REG64_FLD( PU_INT_PC_MMIO_ARB_RESERVED_24 , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24 ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_DONE , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PCMD_PRIO_DONE ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_DONE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PCMD_PRIO_DONE_LEN ); REG64_FLD( PU_INT_PC_MMIO_ARB_RESERVED_28 , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_28 ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_RR , 29 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PCMD_PRIO_RR ); REG64_FLD( PU_INT_PC_MMIO_ARB_CFG_PCMD_PRIO_RR_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PCMD_PRIO_RR_LEN ); REG64_FLD( PU_INT_PC_PCMD_ARB_RESERVED_0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0 ); REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_LSI , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_LSI ); REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_LSI_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_LSI_LEN ); REG64_FLD( PU_INT_PC_PCMD_ARB_RESERVED_4 , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_4 ); REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_MMIO , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_MMIO ); REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_MMIO_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_MMIO_LEN ); REG64_FLD( PU_INT_PC_PCMD_ARB_RESERVED_8 , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_8 ); REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_VRQ_REQ , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_VRQ_REQ ); REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_VRQ_REQ_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_VRQ_REQ_LEN ); REG64_FLD( PU_INT_PC_PCMD_ARB_RESERVED_12 , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_12 ); REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_VRQ_RSP , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_VRQ_RSP ); REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_VRQ_RSP_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_VRQ_RSP_LEN ); REG64_FLD( PU_INT_PC_PCMD_ARB_RESERVED_16 , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_16 ); REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_RR , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_RR ); REG64_FLD( PU_INT_PC_PCMD_ARB_CFG_PRIO_RR_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_RR_LEN ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_P0_IS_IDLE , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_P0_IS_IDLE ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_P1_IS_IDLE , 1 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_P1_IS_IDLE ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_2_9 , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RESERVED_2_9 ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_2_9_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RESERVED_2_9_LEN ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_PTAG_IN_USE , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_PTAG_IN_USE ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_PTAG_IN_USE_LEN , 6 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_PTAG_IN_USE_LEN ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_16_27 , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RESERVED_16_27 ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_16_27_LEN , 12 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RESERVED_16_27_LEN ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_UNLOCK_IN_FIFO , 28 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_UNLOCK_IN_FIFO ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_UNLOCK_IN_FIFO_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_UNLOCK_IN_FIFO_LEN ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_32_33 , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RESERVED_32_33 ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_RESERVED_32_33_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RESERVED_32_33_LEN ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_OUTSTANDING_WB , 34 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_WB ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_1_MAX_OUTSTANDING_WB_LEN , 6 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_WB_LEN ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RESERVED_0_1 ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RESERVED_0_1_LEN ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_VPD_FETCH , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_VPD_FETCH ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_VPD_FETCH_LEN , 6 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_VPD_FETCH_LEN ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_8_9 , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RESERVED_8_9 ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_8_9_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RESERVED_8_9_LEN ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_LOAD , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_CI_LOAD ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_LOAD_LEN , 6 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_CI_LOAD_LEN ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_16_17 , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RESERVED_16_17 ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_16_17_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RESERVED_16_17_LEN ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_ST_RMT , 18 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_ST_RMT ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_ST_RMT_LEN , 6 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_ST_RMT_LEN ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_24_25 , 24 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RESERVED_24_25 ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_RESERVED_24_25_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RESERVED_24_25_LEN ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_ST_RMT_VC , 26 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_ST_RMT_VC ); REG64_FLD( PU_INT_PC_VPC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_ST_RMT_VC_LEN , 6 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_ST_RMT_VC_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_EN_ENABLE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE ); REG64_FLD( PU_INT_PC_VPC_CACHE_EN_ENABLE_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_VP , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VP ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_SECURE , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SECURE ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_PGOFFIRSTLS , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGOFFIRSTLS ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_PGOFFIRSTLS_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGOFFIRSTLS_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_IVE_BLOCK , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IVE_BLOCK ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_IVE_BLOCK_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IVE_BLOCK_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_IVE_INDEX , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IVE_INDEX ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA0_IVE_INDEX_LEN , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IVE_INDEX_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA2_IPB , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IPB ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA2_IPB_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IPB_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA3_MIG_REG , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MIG_REG ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA3_MIG_REG_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MIG_REG_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA3_CL , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CL ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA3_CL_LEN , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CL_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA4_VG , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VG ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA4_PGOFNEXTLS , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGOFNEXTLS ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA4_PGOFNEXTLS_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGOFNEXTLS_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA4_EQD_BLOCK , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQD_BLOCK ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA4_EQD_BLOCK_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQD_BLOCK_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA4_EQD_INDEX , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQD_INDEX ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA4_EQD_INDEX_LEN , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQD_INDEX_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BKLG0 ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG0_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BKLG0_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG1 , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BKLG1 ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG1_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BKLG1_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG2 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BKLG2 ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG2_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BKLG2_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG3 , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BKLG3 ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA6_BKLG3_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BKLG3_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG4 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BKLG4 ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG4_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BKLG4_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG5 , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BKLG5 ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG5_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BKLG5_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG6 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BKLG6 ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG6_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BKLG6_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG7 , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BKLG7 ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_DATA7_BKLG7_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BKLG7_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_CONFLICT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CONFLICT ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_1_7 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_1_7 ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_1_7_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_1_7_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_FULL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FULL ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_9_26 , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_9_26 ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_9_26_LEN , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_9_26_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_BLOCKID , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_BLOCKID ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_BLOCKID_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_BLOCKID_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_32_44 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_32_44 ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_RESERVED_32_44_LEN , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_32_44_LEN ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_OFFSET , 45 , SH_UNT , SH_ACS_SCOM , SH_FLD_OFFSET ); REG64_FLD( PU_INT_PC_VPC_CACHE_WATCH_SPEC_OFFSET_LEN , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_OFFSET_LEN ); REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_24_25 , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24_25 ); REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_24_25_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24_25_LEN ); REG64_FLD( PU_INT_PC_VPC_CONFIG_PTAG_MAX_IN_USE , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PTAG_MAX_IN_USE ); REG64_FLD( PU_INT_PC_VPC_CONFIG_PTAG_MAX_IN_USE_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PTAG_MAX_IN_USE_LEN ); REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_32 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32 ); REG64_FLD( PU_INT_PC_VPC_CONFIG_SYNC_DONE , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SYNC_DONE ); REG64_FLD( PU_INT_PC_VPC_CONFIG_SYNC_DONE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SYNC_DONE_LEN ); REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_36_39 , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_36_39 ); REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_36_39_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_36_39_LEN ); REG64_FLD( PU_INT_PC_VPC_CONFIG_LCL_FIRST_GRPSCAN_ENA , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LCL_FIRST_GRPSCAN_ENA ); REG64_FLD( PU_INT_PC_VPC_CONFIG_LCL_FIRST_GRPSCAN_RMT_ENA , 41 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LCL_FIRST_GRPSCAN_RMT_ENA ); REG64_FLD( PU_INT_PC_VPC_CONFIG_RMT_FIRST_GRPSCAN_ENA , 42 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RMT_FIRST_GRPSCAN_ENA ); REG64_FLD( PU_INT_PC_VPC_CONFIG_LSMFB_SCAN_ALL_PRIO_ENA , 43 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LSMFB_SCAN_ALL_PRIO_ENA ); REG64_FLD( PU_INT_PC_VPC_CONFIG_P0_BACK2BACK_MODE_ENA , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_P0_BACK2BACK_MODE_ENA ); REG64_FLD( PU_INT_PC_VPC_CONFIG_P0_BACK2BACK_MODE_ENA_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_P0_BACK2BACK_MODE_ENA_LEN ); REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_47_51 , 47 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_47_51 ); REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_47_51_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_47_51_LEN ); REG64_FLD( PU_INT_PC_VPC_CONFIG_BG_SCAN_RATE , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BG_SCAN_RATE ); REG64_FLD( PU_INT_PC_VPC_CONFIG_BG_SCAN_RATE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BG_SCAN_RATE_LEN ); REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_56_58 , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56_58 ); REG64_FLD( PU_INT_PC_VPC_CONFIG_RESERVED_56_58_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56_58_LEN ); REG64_FLD( PU_INT_PC_VPC_CONFIG_MAX_ENTRIES_IN_MODIFIED , 59 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MAX_ENTRIES_IN_MODIFIED ); REG64_FLD( PU_INT_PC_VPC_CONFIG_MAX_ENTRIES_IN_MODIFIED_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MAX_ENTRIES_IN_MODIFIED_LEN ); REG64_FLD( PU_INT_PC_VPC_DEBUG_RESERVED_0_29 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_29 ); REG64_FLD( PU_INT_PC_VPC_DEBUG_RESERVED_0_29_LEN , 30 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_29_LEN ); REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_LD_ECC_CORRECTION , 30 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_LD_ECC_CORRECTION ); REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_TAG_ECC_CORRECTION , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_TAG_ECC_CORRECTION ); REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_TAG_ECC_CORRECTION_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_TAG_ECC_CORRECTION_LEN ); REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_STATE_ECC_CORRECTION , 39 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_STATE_ECC_CORRECTION ); REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_STATE_ECC_CORRECTION_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_STATE_ECC_CORRECTION_LEN ); REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_PTAG_ECC_CORRECTION , 41 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_PTAG_ECC_CORRECTION ); REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_PTAG_ECC_CORRECTION_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_PTAG_ECC_CORRECTION_LEN ); REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_DATA_ECC_CORRECTION , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_DATA_ECC_CORRECTION ); REG64_FLD( PU_INT_PC_VPC_DEBUG_DIS_DATA_ECC_CORRECTION_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_DATA_ECC_CORRECTION_LEN ); REG64_FLD( PU_INT_PC_VPC_DEBUG_FORCE_SINGLE_BIT_ECC_ERR , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FORCE_SINGLE_BIT_ECC_ERR ); REG64_FLD( PU_INT_PC_VPC_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FORCE_DOUBLE_BIT_ECC_ERR ); REG64_FLD( PU_INT_PC_VPC_DEBUG_ECC_ERR_INJ_PARTITION_SEL , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_PARTITION_SEL ); REG64_FLD( PU_INT_PC_VPC_DEBUG_ECC_ERR_INJ_PARTITION_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_PARTITION_SEL_LEN ); REG64_FLD( PU_INT_PC_VPC_DEBUG_ECC_ERR_INJ_ARRAY_SEL , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_ARRAY_SEL ); REG64_FLD( PU_INT_PC_VPC_DEBUG_ECC_ERR_INJ_ARRAY_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_ARRAY_SEL_LEN ); REG64_FLD( PU_INT_PC_VPC_DEBUG_TRACE_ENABLE , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_TRACE_ENABLE ); REG64_FLD( PU_INT_PC_VPC_DEBUG_PMC_ENABLE , 57 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMC_ENABLE ); REG64_FLD( PU_INT_PC_VPC_DEBUG_RESERVED_58_59 , 58 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_58_59 ); REG64_FLD( PU_INT_PC_VPC_DEBUG_RESERVED_58_59_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_58_59_LEN ); REG64_FLD( PU_INT_PC_VPC_DEBUG_USE_WATCH_TO_READ_CTRL_ARY , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_USE_WATCH_TO_READ_CTRL_ARY ); REG64_FLD( PU_INT_PC_VPC_DEBUG_CACHE_CTRL_ARY_SELECT , 61 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CACHE_CTRL_ARY_SELECT ); REG64_FLD( PU_INT_PC_VPC_DEBUG_CACHE_CTRL_ARY_SELECT_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CACHE_CTRL_ARY_SELECT_LEN ); REG64_FLD( PU_INT_PC_VPC_ERR_CFG0_ERROR_CONFIG , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_CONFIG ); REG64_FLD( PU_INT_PC_VPC_ERR_CFG0_ERROR_CONFIG_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_CONFIG_LEN ); REG64_FLD( PU_INT_PC_VPC_ERR_CFG1_ERROR_CONFIG , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_CONFIG ); REG64_FLD( PU_INT_PC_VPC_ERR_CFG1_ERROR_CONFIG_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_CONFIG_LEN ); REG64_FLD( PU_INT_PC_VPC_FATAL_ERR_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR ); REG64_FLD( PU_INT_PC_VPC_FATAL_ERR_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_PC_VPC_INFO_ERR_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR ); REG64_FLD( PU_INT_PC_VPC_INFO_ERR_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_0_25 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_25 ); REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_0_25_LEN , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_25_LEN ); REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_STORE_RMT , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CI_STORE_RMT ); REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_STORE_RMT_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CI_STORE_RMT_LEN ); REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_32_33 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_33 ); REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_32_33_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_33_LEN ); REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_STORE_RMT_VC , 34 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CI_STORE_RMT_VC ); REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_STORE_RMT_VC_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CI_STORE_RMT_VC_LEN ); REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_40_41 , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_40_41 ); REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_40_41_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_40_41_LEN ); REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_LOAD , 42 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CI_LOAD ); REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_CI_LOAD_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CI_LOAD_LEN ); REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_48_49 , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_48_49 ); REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_48_49_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_48_49_LEN ); REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_VPD_DMA_READ , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VPD_DMA_READ ); REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_VPD_DMA_READ_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VPD_DMA_READ_LEN ); REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_56_57 , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56_57 ); REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_RESERVED_56_57_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56_57_LEN ); REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_VPD_DMA_WRITE , 58 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VPD_DMA_WRITE ); REG64_FLD( PU_INT_PC_VPC_MAX_OUTSTANDING_OUTB_CMD_VPD_DMA_WRITE_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VPD_DMA_WRITE_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PULL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VRQ_PULL ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PULL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VRQ_PULL_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PUSH_LOCAL , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VRQ_PUSH_LOCAL ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PUSH_LOCAL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VRQ_PUSH_LOCAL_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PUSH_REMOTE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VRQ_PUSH_REMOTE ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_PUSH_REMOTE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VRQ_PUSH_REMOTE_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_VC_LOAD , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_NON_SPEC_VC_LOAD ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_VC_LOAD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_NON_SPEC_VC_LOAD_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_SW_LOAD , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_NON_SPEC_SW_LOAD ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_SW_LOAD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_NON_SPEC_SW_LOAD_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_LOAD , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_NON_SPEC_LOAD ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_NON_SPEC_LOAD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_NON_SPEC_LOAD_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_LOCAL_GROUP_SCAN , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LOCAL_GROUP_SCAN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_LOCAL_GROUP_SCAN_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LOCAL_GROUP_SCAN_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_CACHE_HIT , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VRQ_CACHE_HIT ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VRQ_CACHE_HIT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VRQ_CACHE_HIT_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_LD_CACHE_HIT , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LD_CACHE_HIT ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_LD_CACHE_HIT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LD_CACHE_HIT_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_GROUP_SCAN_CACHE_HIT , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_GROUP_SCAN_CACHE_HIT ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_GROUP_SCAN_CACHE_HIT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_GROUP_SCAN_CACHE_HIT_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VICTIM_IS_LRU ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VICTIM_IS_LRU_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_FIRST_USABLE , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VICTIM_IS_FIRST_USABLE ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_FIRST_USABLE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VICTIM_IS_FIRST_USABLE_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_RETRY , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RETRY ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_RETRY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RETRY_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TOO_MANY_ENTRIES ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TOO_MANY_ENTRIES_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_RESERVED_56_63 , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56_63 ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_1_RESERVED_56_63_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56_63_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_VPD_WB , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VPD_WB ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_VPD_WB_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VPD_WB_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_VPD_FETCH , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VPD_FETCH ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_VPD_FETCH_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VPD_FETCH_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_LCL_TCTXT , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RSP_LCL_TCTXT ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_LCL_TCTXT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RSP_LCL_TCTXT_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_LCL_VC , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RSP_LCL_VC ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_LCL_VC_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RSP_LCL_VC_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_RMT , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RSP_RMT ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_RMT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RSP_RMT_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_RMT_VC , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RSP_RMT_VC ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_RMT_VC_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RSP_RMT_VC_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_SW_LD , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RSP_SW_LD ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RSP_SW_LD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RSP_SW_LD_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_1STVP , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RMT_PULL_1STVP ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_1STVP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RMT_PULL_1STVP_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_1STGRP , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RMT_PULL_1STGRP ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_1STGRP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RMT_PULL_1STGRP_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_VP , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RMT_PULL_VP ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_VP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RMT_PULL_VP_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_GRP , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RMT_PULL_GRP ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PULL_GRP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RMT_PULL_GRP_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_LCL_PRESS_RELIEF , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LCL_PRESS_RELIEF ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_LCL_PRESS_RELIEF_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LCL_PRESS_RELIEF_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_LCL_REDIST , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LCL_REDIST ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_LCL_REDIST_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LCL_REDIST_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PUSH , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RMT_PUSH ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PUSH_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RMT_PUSH_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PUSH_VC , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RMT_PUSH_VC ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_2_CNT_RMT_PUSH_VC_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RMT_PUSH_VC_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_LCL_GRPSCAN_REPLAY , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LCL_GRPSCAN_REPLAY ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_LCL_GRPSCAN_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LCL_GRPSCAN_REPLAY_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_VPD_FETCH_REPLAY , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VPD_FETCH_REPLAY ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_VPD_FETCH_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VPD_FETCH_REPLAY_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_RSP_TCTXT_REPLAY , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RSP_TCTXT_REPLAY ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_RSP_TCTXT_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RSP_TCTXT_REPLAY_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_RSP_ATX_REPLAY , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RSP_ATX_REPLAY ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_RSP_ATX_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RSP_ATX_REPLAY_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_LD_REQ_REPLAY , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LD_REQ_REPLAY ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_LD_REQ_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LD_REQ_REPLAY_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_LCL_REPLAY , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_ST_LCL_REPLAY ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_LCL_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_ST_LCL_REPLAY_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_RMT_REPLAY , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_ST_RMT_REPLAY ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_RMT_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_ST_RMT_REPLAY_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_RMT_VC_REPLAY , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_ST_RMT_VC_REPLAY ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_ST_RMT_VC_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_ST_RMT_VC_REPLAY_LEN ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_SAME_VPD_REPLAY , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_SAME_VPD_REPLAY ); REG64_FLD( PU_INT_PC_VPC_PERF_EVENT_SEL_3_CNT_SAME_VPD_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_SAME_VPD_REPLAY_LEN ); REG64_FLD( PU_INT_PC_VPC_RECOV_ERR_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR ); REG64_FLD( PU_INT_PC_VPC_RECOV_ERR_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_PC_VPC_SCRUB_MASK_BLOCKID , 27 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID ); REG64_FLD( PU_INT_PC_VPC_SCRUB_MASK_BLOCKID_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID_LEN ); REG64_FLD( PU_INT_PC_VPC_SCRUB_MASK_RESERVED_32_44 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_44 ); REG64_FLD( PU_INT_PC_VPC_SCRUB_MASK_RESERVED_32_44_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_44_LEN ); REG64_FLD( PU_INT_PC_VPC_SCRUB_MASK_OFFSET , 45 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET ); REG64_FLD( PU_INT_PC_VPC_SCRUB_MASK_OFFSET_LEN , 19 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET_LEN ); REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_WANT_CACHE_DISABLE , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WANT_CACHE_DISABLE ); REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_WANT_INVALIDATE , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WANT_INVALIDATE ); REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_BLOCKID , 27 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID ); REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_BLOCKID_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID_LEN ); REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_RESERVED_32_44 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_44 ); REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_RESERVED_32_44_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_44_LEN ); REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_OFFSET , 45 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET ); REG64_FLD( PU_INT_PC_VPC_SCRUB_TRIG_OFFSET_LEN , 19 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET_LEN ); REG64_FLD( PU_INT_PC_VPC_WOF_ERR_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR ); REG64_FLD( PU_INT_PC_VPC_WOF_ERR_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_PC_VPC_WOF_ERR_DETAIL_ERROR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ERROR ); REG64_FLD( PU_INT_PC_VPC_WOF_ERR_DETAIL_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_PC_VPD_BLOCK_MODE_MODE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MODE ); REG64_FLD( PU_INT_PC_VPD_BLOCK_MODE_MODE_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MODE_LEN ); REG64_FLD( PU_INT_PC_VRQ_CFG_CFG_CORE_PUSH_EN , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_CORE_PUSH_EN ); REG64_FLD( PU_INT_PC_VRQ_CFG_RESERVED_1_2 , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_1_2 ); REG64_FLD( PU_INT_PC_VRQ_CFG_RESERVED_1_2_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_1_2_LEN ); REG64_FLD( PU_INT_PC_VRQ_CFG_CFG_QUEUE_SIZE_PULL , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_QUEUE_SIZE_PULL ); REG64_FLD( PU_INT_PC_VRQ_CFG_CFG_QUEUE_SIZE_PULL_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_QUEUE_SIZE_PULL_LEN ); REG64_FLD( PU_INT_PC_VRQ_CFG_RESERVED_8_10 , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_8_10 ); REG64_FLD( PU_INT_PC_VRQ_CFG_RESERVED_8_10_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_8_10_LEN ); REG64_FLD( PU_INT_PC_VRQ_CFG_CFG_QUEUE_SIZE_PUSH_LCL , 11 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL ); REG64_FLD( PU_INT_PC_VRQ_CFG_CFG_QUEUE_SIZE_PUSH_LCL_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_QUEUE_SIZE_PUSH_LCL_LEN ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_QUERY_RR_SEL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PARSE_QUERY_RR_SEL ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_1 , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_1 ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_PULL_RR_SEL , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PARSE_PULL_RR_SEL ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_PULL_RR_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PARSE_PULL_RR_SEL_LEN ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_PUSH_RR_SEL , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PARSE_PUSH_RR_SEL ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PARSE_PUSH_RR_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PARSE_PUSH_RR_SEL_LEN ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_6_7 , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_6_7 ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_6_7_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_6_7_LEN ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PULL_PRIO_HYP , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PULL_PRIO_HYP ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PULL_PRIO_HYP_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PULL_PRIO_HYP_LEN ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PUSH_PRIO_HYP , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PUSH_PRIO_HYP ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PUSH_PRIO_HYP_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PUSH_PRIO_HYP_LEN ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_12_16 , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_12_16 ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_12_16_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_12_16_LEN ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_QUERY , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_QUERY ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_QUERY_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_QUERY_LEN ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_20 , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_20 ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_PUSH , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_PUSH ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_PUSH_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_PUSH_LEN ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_24 , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24 ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_PULL , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_PULL ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_PULL_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_PULL_LEN ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_RESERVED_28 , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_28 ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_RR , 29 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_RR ); REG64_FLD( PU_INT_PC_VRQ_PEND_ARB_CFG_PRIO_RR_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_RR_LEN ); REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_RESERVED_0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0 ); REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_RSVD , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_RSVD ); REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_RSVD_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_RSVD_LEN ); REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_STALL_PULL , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_STALL_PULL ); REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PULL , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_PULL ); REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PULL_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_PULL_LEN ); REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_STALL_PUSH_LCL , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_STALL_PUSH_LCL ); REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PUSH_LCL , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_PUSH_LCL ); REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PUSH_LCL_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_PUSH_LCL_LEN ); REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_STALL_PUSH_ARX , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_STALL_PUSH_ARX ); REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PUSH_ARX , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_PUSH_ARX ); REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_PUSH_ARX_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_PUSH_ARX_LEN ); REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_RESERVED_16 , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_16 ); REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_RR , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_RR ); REG64_FLD( PU_INT_PC_VRQ_VPC_ARB_CFG_PRIO_RR_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PRIO_RR_LEN ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_0_1 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_1 ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_1_LEN ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PULL_RSVD , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PULL_RSVD ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PULL_RSVD_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PULL_RSVD_LEN ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_8_9 , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_8_9 ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_8_9_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_8_9_LEN ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PULL_LMIT , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PULL_LMIT ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PULL_LMIT_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PULL_LMIT_LEN ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_16_17 , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_16_17 ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_16_17_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_16_17_LEN ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_LCL_RSVD , 18 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PUSH_LCL_RSVD ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_LCL_RSVD_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PUSH_LCL_RSVD_LEN ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_24_25 , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24_25 ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_24_25_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24_25_LEN ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_LCL_LMIT , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PUSH_LCL_LMIT ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_LCL_LMIT_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PUSH_LCL_LMIT_LEN ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_32_33 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_33 ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_32_33_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_33_LEN ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_ARX_RSVD , 34 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PUSH_ARX_RSVD ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_ARX_RSVD_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PUSH_ARX_RSVD_LEN ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_40_41 , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_40_41 ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_40_41_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_40_41_LEN ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_ARX_LMIT , 42 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PUSH_ARX_LMIT ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_PUSH_ARX_LMIT_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PUSH_ARX_LMIT_LEN ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_48_49 , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_48_49 ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_RESERVED_48_49_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_48_49_LEN ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_MAX , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_MAX ); REG64_FLD( PU_INT_PC_VRQ_VPC_CRD_CFG_MAX_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_MAX_LEN ); REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_AUTO_INCREMENT , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_AUTO_INCREMENT ); REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_RESERVED_1_3 , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_1_3 ); REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_RESERVED_1_3_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_1_3_LEN ); REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_RESERVED_12 , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_12 ); REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_SELECT , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SELECT ); REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_SELECT_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SELECT_LEN ); REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_RESERVED_24_26 , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24_26 ); REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_RESERVED_24_26_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24_26_LEN ); REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_ADDRESS , 27 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS ); REG64_FLD( PU_INT_PC_VSD_TABLE_ADDR_ADDRESS_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_00 , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_00 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_01 , 1 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_01 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_02 , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_02 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_03 , 3 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_03 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_04 , 4 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_04 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_05 , 5 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_05 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_06 , 6 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_06 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_07 , 7 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_07 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_08 , 8 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_08 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_09 , 9 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_09 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_10 , 10 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_10 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_11 , 11 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_11 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_12 , 12 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_12 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_13 , 13 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_13 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_14 , 14 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_14 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_15 , 15 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_15 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_16 , 16 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_16 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_17 , 17 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_17 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_18 , 18 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_18 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_19 , 19 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_19 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_20 , 20 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_20 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_21 , 21 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_21 ); REG64_FLD( PU_NPU_CTL_INT_REQ_INTERRUPT_22 , 22 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_INTERRUPT_22 ); REG64_FLD( PU_INT_TCTXT_CFG_CFG_BLOCK_GROUP_EN , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_BLOCK_GROUP_EN ); REG64_FLD( PU_INT_TCTXT_CFG_CFG_ACM_EN , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_ACM_EN ); REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_2_3 , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_2_3 ); REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_2_3_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_2_3_LEN ); REG64_FLD( PU_INT_TCTXT_CFG_CFG_FUSE_CORE_EN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_FUSE_CORE_EN ); REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_5 , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_5 ); REG64_FLD( PU_INT_TCTXT_CFG_CFG_SMT_MODE , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_SMT_MODE ); REG64_FLD( PU_INT_TCTXT_CFG_CFG_SMT_MODE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_SMT_MODE_LEN ); REG64_FLD( PU_INT_TCTXT_CFG_CFG_HARD_CHIPID_IN_BLOCK_EN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_HARD_CHIPID_IN_BLOCK_EN ); REG64_FLD( PU_INT_TCTXT_CFG_CFG_CHIPID_OVERRIDE , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_CHIPID_OVERRIDE ); REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_10_11 , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_10_11 ); REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_10_11_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_10_11_LEN ); REG64_FLD( PU_INT_TCTXT_CFG_CFG_CHIPID , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_CHIPID ); REG64_FLD( PU_INT_TCTXT_CFG_CFG_CHIPID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_CHIPID_LEN ); REG64_FLD( PU_INT_TCTXT_CFG_CFG_EN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_EN ); REG64_FLD( PU_INT_TCTXT_CFG_CFG_MSGSND , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_MSGSND ); REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_18_19 , 18 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_18_19 ); REG64_FLD( PU_INT_TCTXT_CFG_RESERVED_18_19_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_18_19_LEN ); REG64_FLD( PU_INT_TCTXT_CFG_CFG_PULSE_WIDTH , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PULSE_WIDTH ); REG64_FLD( PU_INT_TCTXT_CFG_CFG_PULSE_WIDTH_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PULSE_WIDTH_LEN ); REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C0_EN , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C0_EN ); REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C0_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C0_EN_LEN ); REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C1_EN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C1_EN ); REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C1_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C1_EN_LEN ); REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C2_EN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C2_EN ); REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C2_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C2_EN_LEN ); REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C3_EN , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C3_EN ); REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C3_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C3_EN_LEN ); REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C4_EN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C4_EN ); REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C4_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C4_EN_LEN ); REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C5_EN , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C5_EN ); REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C5_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C5_EN_LEN ); REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C6_EN , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C6_EN ); REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C6_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C6_EN_LEN ); REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C7_EN , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C7_EN ); REG64_FLD( PU_INT_TCTXT_EN0_CFG_THRD_C7_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C7_EN_LEN ); REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C8_EN , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C8_EN ); REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C8_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C8_EN_LEN ); REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C9_EN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C9_EN ); REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C9_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C9_EN_LEN ); REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C10_EN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C10_EN ); REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C10_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C10_EN_LEN ); REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C11_EN , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C11_EN ); REG64_FLD( PU_INT_TCTXT_EN1_CFG_THRD_C11_EN_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_THRD_C11_EN_LEN ); REG64_FLD( PU_INT_TCTXT_INDIR0_INDIR_VLD , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INDIR_VLD ); REG64_FLD( PU_INT_TCTXT_INDIR0_INDIR_THRDID , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INDIR_THRDID ); REG64_FLD( PU_INT_TCTXT_INDIR0_INDIR_THRDID_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INDIR_THRDID_LEN ); REG64_FLD( PU_INT_TCTXT_INDIR1_INDIR_VLD , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INDIR_VLD ); REG64_FLD( PU_INT_TCTXT_INDIR1_INDIR_THRDID , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INDIR_THRDID ); REG64_FLD( PU_INT_TCTXT_INDIR1_INDIR_THRDID_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INDIR_THRDID_LEN ); REG64_FLD( PU_INT_TCTXT_INDIR2_INDIR_VLD , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INDIR_VLD ); REG64_FLD( PU_INT_TCTXT_INDIR2_INDIR_THRDID , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INDIR_THRDID ); REG64_FLD( PU_INT_TCTXT_INDIR2_INDIR_THRDID_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INDIR_THRDID_LEN ); REG64_FLD( PU_INT_TCTXT_INDIR3_INDIR_VLD , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INDIR_VLD ); REG64_FLD( PU_INT_TCTXT_INDIR3_INDIR_THRDID , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INDIR_THRDID ); REG64_FLD( PU_INT_TCTXT_INDIR3_INDIR_THRDID_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INDIR_THRDID_LEN ); REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_EN , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_BLOCK_EN ); REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_VPD_EN , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_BLOCK_VPD_EN ); REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_RCMD_FILTER_EN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_BLOCK_RCMD_FILTER_EN ); REG64_FLD( PU_INT_TCTXT_TRACK_RESERVED_3_9 , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_3_9 ); REG64_FLD( PU_INT_TCTXT_TRACK_RESERVED_3_9_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_3_9_LEN ); REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_RESET_DELAY , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_BLOCK_RESET_DELAY ); REG64_FLD( PU_INT_TCTXT_TRACK_CFG_BLOCK_RESET_DELAY_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_BLOCK_RESET_DELAY_LEN ); REG64_FLD( PU_INT_VC_AIB_TIMEOUT_DELAY , 58 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DELAY ); REG64_FLD( PU_INT_VC_AIB_TIMEOUT_DELAY_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DELAY_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_PREVENT_MTP_AT_DEM_IN_PIPE , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PREVENT_MTP_AT_DEM_IN_PIPE ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_33_43 , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_33_43 ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_33_43_LEN , 11 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_33_43_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_REGS , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_PRIO_FOR_REGS ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_REGS_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_PRIO_FOR_REGS_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_IRQ , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_PRIO_FOR_IRQ ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_IRQ_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_PRIO_FOR_IRQ_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_IVC , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_PRIO_FOR_IVC ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_IVC_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_PRIO_FOR_IVC_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_50_51 , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_50_51 ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_RESERVED_50_51_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_50_51_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_SBC_EOI_RESP , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_PRIO_FOR_SBC_EOI_RESP ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_SBC_EOI_RESP_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_PRIO_FOR_SBC_EOI_RESP_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_SBC_DMA , 54 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_PRIO_FOR_SBC_DMA ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_SBC_DMA_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_PRIO_FOR_SBC_DMA_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_TRIG_FWD , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_PRIO_FOR_TRIG_FWD ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_TRIG_FWD_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_PRIO_FOR_TRIG_FWD_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_EQC_EOI_EQP , 58 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_PRIO_FOR_EQC_EOI_EQP ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_EQC_EOI_EQP_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_PRIO_FOR_EQC_EOI_EQP_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_LSS_CI_LOAD , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_PRIO_FOR_LSS_CI_LOAD ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_LSS_CI_LOAD_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_PRIO_FOR_LSS_CI_LOAD_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_EQD_DMA , 62 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_PRIO_FOR_EQD_DMA ); REG64_FLD( PU_INT_VC_AIB_TX_CMD_PRIORITY_ATX_PRIO_FOR_EQD_DMA_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ATX_PRIO_FOR_EQD_DMA_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_REGS , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_REGS ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_REGS_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_REGS_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_IRQ , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IRQ ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_IRQ_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IRQ_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_IVC , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IVC ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_IVC_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IVC_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_DMA , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SBC_DMA ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_DMA_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SBC_DMA_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_EOI , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SBC_EOI ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_1_SBC_EOI_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SBC_EOI_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RESERVED_20_21 , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_20_21 ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RESERVED_20_21_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_20_21_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_RELAXED_WR , 22 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RELAXED_WR ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_DISABLE_PTAG_IN_AIBTAG , 23 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DISABLE_PTAG_IN_AIBTAG ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_ESBE , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQC_EOI_ESBE ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_ESBE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQC_EOI_ESBE_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CISTORE , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQC_CISTORE ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CISTORE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQC_CISTORE_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_EQP , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQC_EOI_EQP ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_EOI_EQP_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQC_EOI_EQP_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CILOAD , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQC_CILOAD ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_CILOAD_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQC_CILOAD_LEN ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_DMA , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQC_DMA ); REG64_FLD( PU_INT_VC_AIB_TX_ORDERING_TAG_2_EQC_DMA_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQC_DMA_LEN ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_CRD_REQUEST , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CRD_REQUEST ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_25 , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_25 ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_DMA_READ , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_CRD_DMA_READ ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_DMA_READ_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_CRD_DMA_READ_LEN ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_AT_MACRO , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_CRD_AT_MACRO ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_AT_MACRO_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_CRD_AT_MACRO_LEN ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_EQC_DOING_CI_LOAD , 30 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_CRD_EQC_DOING_CI_LOAD ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_EQC_DOING_CI_LOAD_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_CRD_EQC_DOING_CI_LOAD_LEN ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_32_33 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_33 ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_32_33_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_33_LEN ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_READ_CRD_POOL , 34 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_READ_CRD_POOL ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_READ_CRD_POOL_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_READ_CRD_POOL_LEN ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_40_47 , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_40_47 ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_40_47_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_40_47_LEN ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_DMA_WRITE , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_CRD_DMA_WRITE ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_DMA_WRITE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_CRD_DMA_WRITE_LEN ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_EQ_POST , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_CRD_EQ_POST ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_EQ_POST_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_CRD_EQ_POST_LEN ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_TRIG_FWD_1 , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_CRD_TRIG_FWD_1 ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_TRIG_FWD_1_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_CRD_TRIG_FWD_1_LEN ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_TRIG_FWD_2 , 54 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_CRD_TRIG_FWD_2 ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RSD_CRD_TRIG_FWD_2_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RSD_CRD_TRIG_FWD_2_LEN ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_56_58 , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56_58 ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_RESERVED_56_58_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56_58_LEN ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_WRITE_CRD_POOL , 59 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRITE_CRD_POOL ); REG64_FLD( PU_INT_VC_ATX_INIT_CREDIT_COUNT_WRITE_CRD_POOL_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRITE_CRD_POOL_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R0 ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R0_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R0_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R1R , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1R ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R1R_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1R_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R1W , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1W ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R1W_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1W_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R2 , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R2 ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R2_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R2_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R3 , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R3 ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R3_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R3_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R4 , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R4 ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R4_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R4_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R5R , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R5R ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R5R_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R5R_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R5W , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R5W ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R5W_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R5W_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R6 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R6 ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R6_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R6_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7RSP , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7RSP ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7RSP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7RSP_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7INT , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7INT ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7INT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7INT_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7EQP , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7EQP ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R7EQP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7EQP_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R8 , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R8 ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R8_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R8_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R9 , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R9 ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R9_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R9_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R10R , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R10R ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R10R_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R10R_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R10W , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R10W ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_1_CNT_R10W_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R10W_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R0 ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R0_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R0_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R1R , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1R ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R1R_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1R_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R1W , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1W ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R1W_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1W_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R2 , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R2 ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R2_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R2_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R3 , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R3 ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R3_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R3_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R4 , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R4 ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R4_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R4_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R5R , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R5R ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R5R_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R5R_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R5W , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R5W ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R5W_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R5W_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R6 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R6 ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R6_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R6_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7RSP , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7RSP ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7RSP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7RSP_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7INT , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7INT ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7INT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7INT_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7EQP , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7EQP ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R7EQP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7EQP_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R8 , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R8 ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R8_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R8_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R9 , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R9 ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R9_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R9_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R10R , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R10R ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R10R_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R10R_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R10W , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R10W ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_2_CNT_R10W_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R10W_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R0 ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R0_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R0_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R1R , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1R ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R1R_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1R_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R1W , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1W ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R1W_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R1W_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R2 , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R2 ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R2_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R2_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R3 , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R3 ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R3_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R3_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R4 , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R4 ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R4_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R4_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R5R , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R5R ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R5R_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R5R_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R5W , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R5W ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R5W_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R5W_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R6 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R6 ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R6_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R6_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7RSP , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7RSP ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7RSP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7RSP_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7INT , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7INT ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7INT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7INT_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7EQP , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7EQP ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R7EQP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R7EQP_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R8 , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R8 ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R8_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R8_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R9 , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R9 ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R9_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R9_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R10R , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R10R ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R10R_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R10R_LEN ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R10W , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R10W ); REG64_FLD( PU_INT_VC_ATX_PERF_EVENT_SEL_3_CNT_R10W_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_R10W_LEN ); REG64_FLD( PU_INT_VC_AT_MACRO_KILL_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_INT_VC_AT_MACRO_KILL_VST_TYPE , 14 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VST_TYPE ); REG64_FLD( PU_INT_VC_AT_MACRO_KILL_VST_TYPE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VST_TYPE_LEN ); REG64_FLD( PU_INT_VC_AT_MACRO_KILL_BLOCKID , 27 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID ); REG64_FLD( PU_INT_VC_AT_MACRO_KILL_BLOCKID_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID_LEN ); REG64_FLD( PU_INT_VC_AT_MACRO_KILL_OFFSET , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET ); REG64_FLD( PU_INT_VC_AT_MACRO_KILL_OFFSET_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET_LEN ); REG64_FLD( PU_INT_VC_AT_MACRO_KILL_MASK_BLOCKID , 27 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID ); REG64_FLD( PU_INT_VC_AT_MACRO_KILL_MASK_BLOCKID_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID_LEN ); REG64_FLD( PU_INT_VC_AT_MACRO_KILL_MASK_OFFSET , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET ); REG64_FLD( PU_INT_VC_AT_MACRO_KILL_MASK_OFFSET_LEN , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET_LEN ); REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_P0_IS_IDLE , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_P0_IS_IDLE ); REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_P1_IS_IDLE , 1 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_P1_IS_IDLE ); REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_PTAG_IN_USE , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_PTAG_IN_USE ); REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_PTAG_IN_USE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_PTAG_IN_USE_LEN ); REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_OUTSTANDING_EOI , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_EOI ); REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_OUTSTANDING_EOI_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_EOI_LEN ); REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_UNLOCK_IN_FIFO , 24 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_UNLOCK_IN_FIFO ); REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_1_MAX_UNLOCK_IN_FIFO_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_UNLOCK_IN_FIFO_LEN ); REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQD_FETCH , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_EQD_FETCH ); REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQD_FETCH_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_EQD_FETCH_LEN ); REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQP , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_EQP ); REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQP_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_EQP_LEN ); REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING ); REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_LEN ); REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_LOAD , 24 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_CI_LOAD ); REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_LOAD_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_CI_LOAD_LEN ); REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_STORE , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_CI_STORE ); REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_CI_STORE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_CI_STORE_LEN ); REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQD_WRITE , 40 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_EQD_WRITE ); REG64_FLD( PU_INT_VC_EQC_ADDITIONAL_PERF_2_MAX_OUTSTANDING_EQD_WRITE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_EQD_WRITE_LEN ); REG64_FLD( PU_INT_VC_EQC_CACHE_EN_ENABLE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE ); REG64_FLD( PU_INT_VC_EQC_CACHE_EN_ENABLE_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_LEN ); REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA0_DATA , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA0_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA1_DATA , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA1_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA2_DATA , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA2_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA3_DATA , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_DATA3_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_CONFLICT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CONFLICT ); REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_1_7 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_1_7 ); REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_1_7_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_1_7_LEN ); REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_FULL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FULL ); REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_9_27 , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_9_27 ); REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_9_27_LEN , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_9_27_LEN ); REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_BLOCKID , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_BLOCKID ); REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_BLOCKID_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_BLOCKID_LEN ); REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_32_39 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_32_39 ); REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_RESERVED_32_39_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_32_39_LEN ); REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_OFFSET , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_OFFSET ); REG64_FLD( PU_INT_VC_EQC_CACHE_WATCH_SPEC_OFFSET_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_OFFSET_LEN ); REG64_FLD( PU_INT_VC_EQC_CONFIG_PAGE_OFFSET_CFG , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PAGE_OFFSET_CFG ); REG64_FLD( PU_INT_VC_EQC_CONFIG_PAGE_OFFSET_CFG_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PAGE_OFFSET_CFG_LEN ); REG64_FLD( PU_INT_VC_EQC_CONFIG_SYNC_DONE , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SYNC_DONE ); REG64_FLD( PU_INT_VC_EQC_CONFIG_SYNC_DONE_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SYNC_DONE_LEN ); REG64_FLD( PU_INT_VC_EQC_CONFIG_RESERVED_37_45 , 37 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_37_45 ); REG64_FLD( PU_INT_VC_EQC_CONFIG_RESERVED_37_45_LEN , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_37_45_LEN ); REG64_FLD( PU_INT_VC_EQC_CONFIG_MAX_PTAG_IN_USE , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MAX_PTAG_IN_USE ); REG64_FLD( PU_INT_VC_EQC_CONFIG_MAX_PTAG_IN_USE_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MAX_PTAG_IN_USE_LEN ); REG64_FLD( PU_INT_VC_EQC_CONFIG_BG_SCAN_RATE , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BG_SCAN_RATE ); REG64_FLD( PU_INT_VC_EQC_CONFIG_BG_SCAN_RATE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BG_SCAN_RATE_LEN ); REG64_FLD( PU_INT_VC_EQC_CONFIG_RESERVED_56_58 , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56_58 ); REG64_FLD( PU_INT_VC_EQC_CONFIG_RESERVED_56_58_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56_58_LEN ); REG64_FLD( PU_INT_VC_EQC_CONFIG_MAX_ENTRIES_IN_MODIFIED , 59 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MAX_ENTRIES_IN_MODIFIED ); REG64_FLD( PU_INT_VC_EQC_CONFIG_MAX_ENTRIES_IN_MODIFIED_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MAX_ENTRIES_IN_MODIFIED_LEN ); REG64_FLD( PU_INT_VC_EQC_DEBUG_RESERVED_0_32 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_32 ); REG64_FLD( PU_INT_VC_EQC_DEBUG_RESERVED_0_32_LEN , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_32_LEN ); REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_ARX_ECC_CORRECTION , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_ARX_ECC_CORRECTION ); REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_TAG_ECC_CORRECTION , 34 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_TAG_ECC_CORRECTION ); REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_TAG_ECC_CORRECTION_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_TAG_ECC_CORRECTION_LEN ); REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_STATE_ECC_CORRECTION , 42 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_STATE_ECC_CORRECTION ); REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_STATE_ECC_CORRECTION_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_STATE_ECC_CORRECTION_LEN ); REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_CTRLBUF_ECC_CORRECTION , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_CTRLBUF_ECC_CORRECTION ); REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_DATA_ECC_CORRECTION , 45 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_DATA_ECC_CORRECTION ); REG64_FLD( PU_INT_VC_EQC_DEBUG_DIS_DATA_ECC_CORRECTION_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_DATA_ECC_CORRECTION_LEN ); REG64_FLD( PU_INT_VC_EQC_DEBUG_FORCE_SINGLE_BIT_ECC_ERR , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FORCE_SINGLE_BIT_ECC_ERR ); REG64_FLD( PU_INT_VC_EQC_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FORCE_DOUBLE_BIT_ECC_ERR ); REG64_FLD( PU_INT_VC_EQC_DEBUG_ECC_ERR_INJ_ARRAY_SEL , 51 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_ARRAY_SEL ); REG64_FLD( PU_INT_VC_EQC_DEBUG_ECC_ERR_INJ_ARRAY_SEL_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_ARRAY_SEL_LEN ); REG64_FLD( PU_INT_VC_EQC_DEBUG_TRACE_ENABLE , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_TRACE_ENABLE ); REG64_FLD( PU_INT_VC_EQC_DEBUG_RESERVED_57_58 , 57 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_57_58 ); REG64_FLD( PU_INT_VC_EQC_DEBUG_RESERVED_57_58_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_57_58_LEN ); REG64_FLD( PU_INT_VC_EQC_DEBUG_RESERVED_59 , 59 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_59 ); REG64_FLD( PU_INT_VC_EQC_DEBUG_USE_WATCH_TO_READ_CTRL_ARY , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_USE_WATCH_TO_READ_CTRL_ARY ); REG64_FLD( PU_INT_VC_EQC_DEBUG_CACHE_CTRL_ARY_SELECT , 61 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CACHE_CTRL_ARY_SELECT ); REG64_FLD( PU_INT_VC_EQC_DEBUG_CACHE_CTRL_ARY_SELECT_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CACHE_CTRL_ARY_SELECT_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_IPI , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQ_TRIGGER_FROM_IPI ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_IPI_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQ_TRIGGER_FROM_IPI_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_HWD , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQ_TRIGGER_FROM_HWD ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_HWD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQ_TRIGGER_FROM_HWD_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_1ESC , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQ_TRIGGER_FROM_1ESC ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_1ESC_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQ_TRIGGER_FROM_1ESC_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_2ESC , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQ_TRIGGER_FROM_2ESC ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_2ESC_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQ_TRIGGER_FROM_2ESC_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_REDIS , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQ_TRIGGER_FROM_REDIS ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIGGER_FROM_REDIS_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQ_TRIGGER_FROM_REDIS_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_NON_SPEC_EOI ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_NON_SPEC_EOI_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_LOCAL_ESCALATE , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LOCAL_ESCALATE ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_LOCAL_ESCALATE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LOCAL_ESCALATE_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIG_CACHE_HIT , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQ_TRIG_CACHE_HIT ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EQ_TRIG_CACHE_HIT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQ_TRIG_CACHE_HIT_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EOI_CACHE_HIT , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EOI_CACHE_HIT ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_EOI_CACHE_HIT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EOI_CACHE_HIT_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_LOCAL_ESC_CACHE_HIT , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LOCAL_ESC_CACHE_HIT ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_LOCAL_ESC_CACHE_HIT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LOCAL_ESC_CACHE_HIT_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VICTIM_IS_LRU ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VICTIM_IS_LRU_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_FIRST_USABLE , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VICTIM_IS_FIRST_USABLE ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_FIRST_USABLE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VICTIM_IS_FIRST_USABLE_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_RETRY , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RETRY ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_RETRY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RETRY_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TOO_MANY_ENTRIES ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TOO_MANY_ENTRIES_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_RESERVED_56_63 , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56_63 ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_1_RESERVED_56_63_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56_63_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQD_FETCH , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQD_FETCH ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQD_FETCH_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQD_FETCH_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQP , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQP ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQP_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_WAKEUP , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_WAKEUP ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_WAKEUP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_WAKEUP_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LS , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LS ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LS_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LS_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_VP , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VP ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_VP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VP_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_GROUP , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_GROUP ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_GROUP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_GROUP_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_BROADCAST , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_BROADCAST ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_BROADCAST_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_BROADCAST_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQ_FWD , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQ_FWD ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_EQ_FWD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQ_FWD_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_ESCALATE , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_ESCALATE ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_ESCALATE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_ESCALATE_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LOCAL_VPC_UPD , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LOCAL_VPC_UPD ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LOCAL_VPC_UPD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LOCAL_VPC_UPD_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_REMOTE_VPC_UPD , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_REMOTE_VPC_UPD ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_REMOTE_VPC_UPD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_REMOTE_VPC_UPD_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LOCAL_SBC_UPD , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LOCAL_SBC_UPD ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_LOCAL_SBC_UPD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LOCAL_SBC_UPD_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_REMOTE_SBC_UPD , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_REMOTE_SBC_UPD ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_2_CNT_REMOTE_SBC_UPD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_REMOTE_SBC_UPD_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EQD_FETCH_REPLAY , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQD_FETCH_REPLAY ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EQD_FETCH_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQD_FETCH_REPLAY_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EQP_REPLAY , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQP_REPLAY ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EQP_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQP_REPLAY_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_REPLAY , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_REPLAY ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_REPLAY_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_CI_STORE_REPLAY , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_CI_STORE_REPLAY ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_CI_STORE_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_CI_STORE_REPLAY_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_ESC_REPLAY , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LOCAL_ESC_REPLAY ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_ESC_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LOCAL_ESC_REPLAY_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_REMOTE_CI_LOAD_REPLAY , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_REMOTE_CI_LOAD_REPLAY ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_REMOTE_CI_LOAD_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_REMOTE_CI_LOAD_REPLAY_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_VPC_REPLAY , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LOCAL_VPC_REPLAY ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_VPC_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LOCAL_VPC_REPLAY_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_SBC_REPLAY , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LOCAL_SBC_REPLAY ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_LOCAL_SBC_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_LOCAL_SBC_REPLAY_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EOI_RESP_REPLAY , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EOI_RESP_REPLAY ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_EOI_RESP_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EOI_RESP_REPLAY_LEN ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_NEW_CMD_STALLED , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_NEW_CMD_STALLED ); REG64_FLD( PU_INT_VC_EQC_PERF_EVENT_SEL_3_CNT_NEW_CMD_STALLED_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_NEW_CMD_STALLED_LEN ); REG64_FLD( PU_INT_VC_EQC_SCRUB_MASK_BLOCKID , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID ); REG64_FLD( PU_INT_VC_EQC_SCRUB_MASK_BLOCKID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID_LEN ); REG64_FLD( PU_INT_VC_EQC_SCRUB_MASK_RESERVED_32_39 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_39 ); REG64_FLD( PU_INT_VC_EQC_SCRUB_MASK_RESERVED_32_39_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_39_LEN ); REG64_FLD( PU_INT_VC_EQC_SCRUB_MASK_OFFSET , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET ); REG64_FLD( PU_INT_VC_EQC_SCRUB_MASK_OFFSET_LEN , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET_LEN ); REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_WANT_CACHE_DISABLE , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WANT_CACHE_DISABLE ); REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_WANT_INVALIDATE , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WANT_INVALIDATE ); REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_BLOCKID , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID ); REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_BLOCKID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID_LEN ); REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_RESERVED_32_39 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_39 ); REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_RESERVED_32_39_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_39_LEN ); REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_OFFSET , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET ); REG64_FLD( PU_INT_VC_EQC_SCRUB_TRIG_OFFSET_LEN , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET_LEN ); REG64_FLD( PU_INT_VC_EQD_BLOCK_MODE_MODE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MODE ); REG64_FLD( PU_INT_VC_EQD_BLOCK_MODE_MODE_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MODE_LEN ); REG64_FLD( PU_INT_VC_ERR_CFG_G0R0_ERROR_CONFIG , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_CONFIG ); REG64_FLD( PU_INT_VC_ERR_CFG_G0R0_ERROR_CONFIG_LEN , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_CONFIG_LEN ); REG64_FLD( PU_INT_VC_ERR_CFG_G0R1_ERROR_CONFIG , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_CONFIG ); REG64_FLD( PU_INT_VC_ERR_CFG_G0R1_ERROR_CONFIG_LEN , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_CONFIG_LEN ); REG64_FLD( PU_INT_VC_ERR_CFG_G1R0_ERROR_CONFIG , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_CONFIG ); REG64_FLD( PU_INT_VC_ERR_CFG_G1R0_ERROR_CONFIG_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_CONFIG_LEN ); REG64_FLD( PU_INT_VC_ERR_CFG_G1R1_ERROR_CONFIG , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_CONFIG ); REG64_FLD( PU_INT_VC_ERR_CFG_G1R1_ERROR_CONFIG_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_CONFIG_LEN ); REG64_FLD( PU_INT_VC_FATAL_ERR_G0_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR ); REG64_FLD( PU_INT_VC_FATAL_ERR_G0_ERROR_LEN , 55 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_VC_FATAL_ERR_G1_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR ); REG64_FLD( PU_INT_VC_FATAL_ERR_G1_ERROR_LEN , 43 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_VC_GLOBAL_CONFIG_INDIRECT_MODE , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_INDIRECT_MODE ); REG64_FLD( PU_INT_VC_GLOBAL_CONFIG_RESERVED_33_63 , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_33_63 ); REG64_FLD( PU_INT_VC_GLOBAL_CONFIG_RESERVED_33_63_LEN , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_33_63_LEN ); REG64_FLD( PU_INT_VC_INFO_ERR_G0_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR ); REG64_FLD( PU_INT_VC_INFO_ERR_G0_ERROR_LEN , 55 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_VC_INFO_ERR_G1_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR ); REG64_FLD( PU_INT_VC_INFO_ERR_G1_ERROR_LEN , 43 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_20 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_20 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_20_LEN , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_20_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_PREFETCH_DISTANCE , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_PREFETCH_DISTANCE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_PREFETCH_DISTANCE_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PREFETCH_DISTANCE_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_MAX_CRD_TO_CQ , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_CQ ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_MAX_CRD_TO_CQ_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_CQ_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_32_34 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_32_34 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_32_34_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_32_34_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_MAX_CRD_TO_PC , 35 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_PC ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_MAX_CRD_TO_PC_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_PC_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_40_41 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_40_41 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_40_41_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_40_41_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_PREFETCH_DISABLE , 42 , SH_UNT , SH_ACS_SCOM , SH_FLD_PREFETCH_DISABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_QUEUE_DISABLE , 43 , SH_UNT , SH_ACS_SCOM , SH_FLD_QUEUE_DISABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_IVC_INTF_DISABLE , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_IVC_INTF_DISABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_ENABLE_MEMORY_BACKING , 45 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_MEMORY_BACKING ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_MEM_SIZE , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_MEM_SIZE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_MEM_SIZE_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MEM_SIZE_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_52 , 52 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_52 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_NB_WRITE_SLOT , 53 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_WRITE_SLOT ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_NB_WRITE_SLOT_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_WRITE_SLOT_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_RESERVED_56 , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_56 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_NB_CLEAN_SLOT , 57 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_CLEAN_SLOT ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_NB_CLEAN_SLOT_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_CLEAN_SLOT_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_FULL_WRITEBACK_ENABLE , 60 , SH_UNT , SH_ACS_SCOM , SH_FLD_FULL_WRITEBACK_ENABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_QUEUE_NOT_EMPTY , 61 , SH_UNT , SH_ACS_SCOM , SH_FLD_QUEUE_NOT_EMPTY ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_CREDIT_UPDATE_PENDING , 62 , SH_UNT , SH_ACS_SCOM , SH_FLD_CREDIT_UPDATE_PENDING ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_0_FIFO_FULL , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_FULL ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_0_20 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_0_20 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_0_20_LEN , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_0_20_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_PREFETCH_DISTANCE , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_PREFETCH_DISTANCE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_PREFETCH_DISTANCE_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PREFETCH_DISTANCE_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_MAX_CRD_TO_CQ , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_CQ ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_MAX_CRD_TO_CQ_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_CQ_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_32_34 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_32_34 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_32_34_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_32_34_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_MAX_CRD_TO_PC , 35 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_PC ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_MAX_CRD_TO_PC_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_PC_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_40_41 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_40_41 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_40_41_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_40_41_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_PREFETCH_DISABLE , 42 , SH_UNT , SH_ACS_SCOM , SH_FLD_PREFETCH_DISABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_QUEUE_DISABLE , 43 , SH_UNT , SH_ACS_SCOM , SH_FLD_QUEUE_DISABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_IVC_INTF_DISABLE , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_IVC_INTF_DISABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_ENABLE_MEMORY_BACKING , 45 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_MEMORY_BACKING ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_MEM_SIZE , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_MEM_SIZE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_MEM_SIZE_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MEM_SIZE_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_52 , 52 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_52 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_NB_WRITE_SLOT , 53 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_WRITE_SLOT ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_NB_WRITE_SLOT_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_WRITE_SLOT_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_RESERVED_56 , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_56 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_NB_CLEAN_SLOT , 57 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_CLEAN_SLOT ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_NB_CLEAN_SLOT_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_CLEAN_SLOT_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_FULL_WRITEBACK_ENABLE , 60 , SH_UNT , SH_ACS_SCOM , SH_FLD_FULL_WRITEBACK_ENABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_QUEUE_NOT_EMPTY , 61 , SH_UNT , SH_ACS_SCOM , SH_FLD_QUEUE_NOT_EMPTY ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_CREDIT_UPDATE_PENDING , 62 , SH_UNT , SH_ACS_SCOM , SH_FLD_CREDIT_UPDATE_PENDING ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_1_FIFO_FULL , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_FULL ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_0_20 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_0_20 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_0_20_LEN , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_0_20_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_PREFETCH_DISTANCE , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_PREFETCH_DISTANCE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_PREFETCH_DISTANCE_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PREFETCH_DISTANCE_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_MAX_CRD_TO_CQ , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_CQ ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_MAX_CRD_TO_CQ_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_CQ_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_32_34 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_32_34 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_32_34_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_32_34_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_MAX_CRD_TO_PC , 35 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_PC ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_MAX_CRD_TO_PC_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_PC_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_40_41 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_40_41 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_40_41_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_40_41_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_PREFETCH_DISABLE , 42 , SH_UNT , SH_ACS_SCOM , SH_FLD_PREFETCH_DISABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_QUEUE_DISABLE , 43 , SH_UNT , SH_ACS_SCOM , SH_FLD_QUEUE_DISABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_IVC_INTF_DISABLE , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_IVC_INTF_DISABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_ENABLE_MEMORY_BACKING , 45 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_MEMORY_BACKING ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_MEM_SIZE , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_MEM_SIZE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_MEM_SIZE_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MEM_SIZE_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_52 , 52 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_52 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_NB_WRITE_SLOT , 53 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_WRITE_SLOT ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_NB_WRITE_SLOT_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_WRITE_SLOT_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_RESERVED_56 , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_56 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_NB_CLEAN_SLOT , 57 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_CLEAN_SLOT ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_NB_CLEAN_SLOT_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_CLEAN_SLOT_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_FULL_WRITEBACK_ENABLE , 60 , SH_UNT , SH_ACS_SCOM , SH_FLD_FULL_WRITEBACK_ENABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_QUEUE_NOT_EMPTY , 61 , SH_UNT , SH_ACS_SCOM , SH_FLD_QUEUE_NOT_EMPTY ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_CREDIT_UPDATE_PENDING , 62 , SH_UNT , SH_ACS_SCOM , SH_FLD_CREDIT_UPDATE_PENDING ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_2_FIFO_FULL , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_FULL ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_0_20 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_0_20 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_0_20_LEN , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_0_20_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_PREFETCH_DISTANCE , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_PREFETCH_DISTANCE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_PREFETCH_DISTANCE_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PREFETCH_DISTANCE_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_MAX_CRD_TO_CQ , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_CQ ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_MAX_CRD_TO_CQ_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_CQ_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_32_34 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_32_34 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_32_34_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_32_34_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_MAX_CRD_TO_PC , 35 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_PC ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_MAX_CRD_TO_PC_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_PC_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_40_41 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_40_41 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_40_41_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_40_41_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_PREFETCH_DISABLE , 42 , SH_UNT , SH_ACS_SCOM , SH_FLD_PREFETCH_DISABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_QUEUE_DISABLE , 43 , SH_UNT , SH_ACS_SCOM , SH_FLD_QUEUE_DISABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_IVC_INTF_DISABLE , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_IVC_INTF_DISABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_ENABLE_MEMORY_BACKING , 45 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_MEMORY_BACKING ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_MEM_SIZE , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_MEM_SIZE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_MEM_SIZE_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MEM_SIZE_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_52 , 52 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_52 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_NB_WRITE_SLOT , 53 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_WRITE_SLOT ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_NB_WRITE_SLOT_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_WRITE_SLOT_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_RESERVED_56 , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_56 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_NB_CLEAN_SLOT , 57 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_CLEAN_SLOT ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_NB_CLEAN_SLOT_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_CLEAN_SLOT_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_FULL_WRITEBACK_ENABLE , 60 , SH_UNT , SH_ACS_SCOM , SH_FLD_FULL_WRITEBACK_ENABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_QUEUE_NOT_EMPTY , 61 , SH_UNT , SH_ACS_SCOM , SH_FLD_QUEUE_NOT_EMPTY ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_CREDIT_UPDATE_PENDING , 62 , SH_UNT , SH_ACS_SCOM , SH_FLD_CREDIT_UPDATE_PENDING ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_3_FIFO_FULL , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_FULL ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_0_20 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_0_20 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_0_20_LEN , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_0_20_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_PREFETCH_DISTANCE , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_PREFETCH_DISTANCE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_PREFETCH_DISTANCE_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PREFETCH_DISTANCE_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_MAX_CRD_TO_CQ , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_CQ ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_MAX_CRD_TO_CQ_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_CQ_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_32_34 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_32_34 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_32_34_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_32_34_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_MAX_CRD_TO_PC , 35 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_PC ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_MAX_CRD_TO_PC_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_PC_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_40_41 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_40_41 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_40_41_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_40_41_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_PREFETCH_DISABLE , 42 , SH_UNT , SH_ACS_SCOM , SH_FLD_PREFETCH_DISABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_QUEUE_DISABLE , 43 , SH_UNT , SH_ACS_SCOM , SH_FLD_QUEUE_DISABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_IVC_INTF_DISABLE , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_IVC_INTF_DISABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_ENABLE_MEMORY_BACKING , 45 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_MEMORY_BACKING ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_MEM_SIZE , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_MEM_SIZE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_MEM_SIZE_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MEM_SIZE_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_52 , 52 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_52 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_NB_WRITE_SLOT , 53 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_WRITE_SLOT ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_NB_WRITE_SLOT_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_WRITE_SLOT_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_RESERVED_56 , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_56 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_NB_CLEAN_SLOT , 57 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_CLEAN_SLOT ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_NB_CLEAN_SLOT_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_CLEAN_SLOT_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_FULL_WRITEBACK_ENABLE , 60 , SH_UNT , SH_ACS_SCOM , SH_FLD_FULL_WRITEBACK_ENABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_QUEUE_NOT_EMPTY , 61 , SH_UNT , SH_ACS_SCOM , SH_FLD_QUEUE_NOT_EMPTY ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_CREDIT_UPDATE_PENDING , 62 , SH_UNT , SH_ACS_SCOM , SH_FLD_CREDIT_UPDATE_PENDING ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_4_FIFO_FULL , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_FULL ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_0_20 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_0_20 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_0_20_LEN , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_0_20_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_PREFETCH_DISTANCE , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_PREFETCH_DISTANCE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_PREFETCH_DISTANCE_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PREFETCH_DISTANCE_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_MAX_CRD_TO_CQ , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_CQ ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_MAX_CRD_TO_CQ_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_CQ_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_32_34 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_32_34 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_32_34_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_32_34_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_MAX_CRD_TO_PC , 35 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_PC ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_MAX_CRD_TO_PC_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAX_CRD_TO_PC_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_40_41 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_40_41 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_40_41_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_40_41_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_PREFETCH_DISABLE , 42 , SH_UNT , SH_ACS_SCOM , SH_FLD_PREFETCH_DISABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_QUEUE_DISABLE , 43 , SH_UNT , SH_ACS_SCOM , SH_FLD_QUEUE_DISABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_IVC_INTF_DISABLE , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_IVC_INTF_DISABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_ENABLE_MEMORY_BACKING , 45 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_MEMORY_BACKING ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_MEM_SIZE , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_MEM_SIZE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_MEM_SIZE_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MEM_SIZE_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_52 , 52 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_52 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_NB_WRITE_SLOT , 53 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_WRITE_SLOT ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_NB_WRITE_SLOT_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_WRITE_SLOT_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_RESERVED_56 , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_56 ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_NB_CLEAN_SLOT , 57 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_CLEAN_SLOT ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_NB_CLEAN_SLOT_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NB_CLEAN_SLOT_LEN ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_FULL_WRITEBACK_ENABLE , 60 , SH_UNT , SH_ACS_SCOM , SH_FLD_FULL_WRITEBACK_ENABLE ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_QUEUE_NOT_EMPTY , 61 , SH_UNT , SH_ACS_SCOM , SH_FLD_QUEUE_NOT_EMPTY ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_CREDIT_UPDATE_PENDING , 62 , SH_UNT , SH_ACS_SCOM , SH_FLD_CREDIT_UPDATE_PENDING ); REG64_FLD( PU_INT_VC_IRQ_CONFIG_5_FIFO_FULL , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_FULL ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_FROM_AIB , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FROM_AIB ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_FROM_AIB_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FROM_AIB_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_DROPPED , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_DROPPED ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_DROPPED_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_DROPPED_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_FWD_TO_EQC , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FWD_TO_EQC ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_TRIG_FWD_TO_EQC_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_DMA_WR , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_WR ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_DMA_WR_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_WR_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_DMA_RD , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_RD ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_DMA_RD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_RD_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_FIFO_FULL , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_FIFO_FULL ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_0_CNT_FIFO_FULL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_FIFO_FULL_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_FROM_AIB , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FROM_AIB ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_FROM_AIB_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FROM_AIB_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_DROPPED , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_DROPPED ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_DROPPED_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_DROPPED_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_FWD_TO_EQC , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FWD_TO_EQC ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_TRIG_FWD_TO_EQC_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_DMA_WR , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_WR ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_DMA_WR_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_WR_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_DMA_RD , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_RD ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_DMA_RD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_RD_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_FIFO_FULL , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_FIFO_FULL ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_1_CNT_FIFO_FULL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_FIFO_FULL_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_FROM_AIB , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FROM_AIB ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_FROM_AIB_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FROM_AIB_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_DROPPED , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_DROPPED ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_DROPPED_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_DROPPED_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_FWD_TO_EQC , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FWD_TO_EQC ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_TRIG_FWD_TO_EQC_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_DMA_WR , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_WR ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_DMA_WR_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_WR_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_DMA_RD , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_RD ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_DMA_RD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_RD_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_FIFO_FULL , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_FIFO_FULL ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_2_CNT_FIFO_FULL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_FIFO_FULL_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_FROM_AIB , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FROM_AIB ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_FROM_AIB_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FROM_AIB_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_DROPPED , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_DROPPED ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_DROPPED_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_DROPPED_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_FWD_TO_EQC , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FWD_TO_EQC ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_TRIG_FWD_TO_EQC_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_DMA_WR , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_WR ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_DMA_WR_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_WR_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_DMA_RD , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_RD ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_DMA_RD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_RD_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_FIFO_FULL , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_FIFO_FULL ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_3_CNT_FIFO_FULL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_FIFO_FULL_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_FROM_AIB , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FROM_AIB ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_FROM_AIB_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FROM_AIB_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_DROPPED , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_DROPPED ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_DROPPED_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_DROPPED_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_FWD_TO_EQC , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FWD_TO_EQC ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_TRIG_FWD_TO_EQC_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_DMA_WR , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_WR ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_DMA_WR_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_WR_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_DMA_RD , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_RD ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_DMA_RD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_RD_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_FIFO_FULL , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_FIFO_FULL ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_4_CNT_FIFO_FULL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_FIFO_FULL_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_FROM_AIB , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FROM_AIB ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_FROM_AIB_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FROM_AIB_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_DROPPED , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_DROPPED ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_DROPPED_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_DROPPED_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_FWD_TO_EQC , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FWD_TO_EQC ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_TRIG_FWD_TO_EQC_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TRIG_FWD_TO_EQC_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_DMA_WR , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_WR ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_DMA_WR_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_WR_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_DMA_RD , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_RD ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_DMA_RD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DMA_RD_LEN ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_FIFO_FULL , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_FIFO_FULL ); REG64_FLD( PU_INT_VC_IRQ_PERF_EVENT_SEL_5_CNT_FIFO_FULL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_FIFO_FULL_LEN ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_IPI_PRIORITY , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IPI_PRIORITY ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_IPI_PRIORITY_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IPI_PRIORITY_LEN ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_IPI_RSD , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IPI_RSD ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_IPI_RSD_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IPI_RSD_LEN ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_HWD_PRIORITY , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_PRIORITY ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_HWD_PRIORITY_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_PRIORITY_LEN ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_HWD_RSD , 11 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_RSD ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_HWD_RSD_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_RSD_LEN ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC1_PRIORITY , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ESC1_PRIORITY ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC1_PRIORITY_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ESC1_PRIORITY_LEN ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC1_RSD , 19 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ESC1_RSD ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC1_RSD_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ESC1_RSD_LEN ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC2_PRIORITY , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ESC2_PRIORITY ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC2_PRIORITY_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ESC2_PRIORITY_LEN ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC2_RSD , 27 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ESC2_RSD ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_ESC2_RSD_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ESC2_RSD_LEN ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_REDIS_PRIORITY , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_REDIS_PRIORITY ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_REDIS_PRIORITY_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_REDIS_PRIORITY_LEN ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_REDIS_RSD , 35 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_REDIS_RSD ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_REDIS_RSD_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_REDIS_RSD_LEN ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_RESERVED_40_42 , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_40_42 ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_RESERVED_40_42_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_40_42_LEN ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_POOL , 43 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_POOL ); REG64_FLD( PU_INT_VC_IRQ_TO_EQC_CREDITS_POOL_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_POOL_LEN ); REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_P0_IS_IDLE , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_P0_IS_IDLE ); REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_P1_IS_IDLE , 1 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_P1_IS_IDLE ); REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_PTAG_IN_USE , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_PTAG_IN_USE ); REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_PTAG_IN_USE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_PTAG_IN_USE_LEN ); REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_UNLOCK_IN_FIFO , 24 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_UNLOCK_IN_FIFO ); REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_UNLOCK_IN_FIFO_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_UNLOCK_IN_FIFO_LEN ); REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_OUTSTANDING_IVE_FETCH , 48 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_IVE_FETCH ); REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_OUTSTANDING_IVE_FETCH_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_IVE_FETCH_LEN ); REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_OUTSTANDING_SBC_LOOKUP , 56 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_SBC_LOOKUP ); REG64_FLD( PU_INT_VC_IVC_ADDITIONAL_PERF_MAX_OUTSTANDING_SBC_LOOKUP_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_SBC_LOOKUP_LEN ); REG64_FLD( PU_INT_VC_IVC_CACHE_EN_ENABLE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE ); REG64_FLD( PU_INT_VC_IVC_CACHE_EN_ENABLE_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_LEN ); REG64_FLD( PU_INT_VC_IVC_CACHE_WATCH_ADDR_SET_INDEX , 54 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SET_INDEX ); REG64_FLD( PU_INT_VC_IVC_CACHE_WATCH_ADDR_SET_INDEX_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SET_INDEX_LEN ); REG64_FLD( PU_INT_VC_IVC_CACHE_WATCH_DATA_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_INT_VC_IVC_CACHE_WATCH_DATA_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_32 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32 ); REG64_FLD( PU_INT_VC_IVC_DEBUG_MAX_PTAG_IN_USE , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MAX_PTAG_IN_USE ); REG64_FLD( PU_INT_VC_IVC_DEBUG_MAX_PTAG_IN_USE_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MAX_PTAG_IN_USE_LEN ); REG64_FLD( PU_INT_VC_IVC_DEBUG_DIS_TAG_ECC_CORRECTION , 38 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_TAG_ECC_CORRECTION ); REG64_FLD( PU_INT_VC_IVC_DEBUG_DIS_TAG_ECC_CORRECTION_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_TAG_ECC_CORRECTION_LEN ); REG64_FLD( PU_INT_VC_IVC_DEBUG_DIS_STATE_ECC_CORRECTION , 42 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_STATE_ECC_CORRECTION ); REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_43_44 , 43 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_43_44 ); REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_43_44_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_43_44_LEN ); REG64_FLD( PU_INT_VC_IVC_DEBUG_DIS_DATA_ECC_CORRECTION , 45 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_DATA_ECC_CORRECTION ); REG64_FLD( PU_INT_VC_IVC_DEBUG_DIS_DATA_ECC_CORRECTION_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_DATA_ECC_CORRECTION_LEN ); REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_47_48 , 47 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_47_48 ); REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_47_48_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_47_48_LEN ); REG64_FLD( PU_INT_VC_IVC_DEBUG_FORCE_SINGLE_BIT_ECC_ERR , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FORCE_SINGLE_BIT_ECC_ERR ); REG64_FLD( PU_INT_VC_IVC_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FORCE_DOUBLE_BIT_ECC_ERR ); REG64_FLD( PU_INT_VC_IVC_DEBUG_ECC_ERR_INJ_ARRAY_SEL , 51 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_ARRAY_SEL ); REG64_FLD( PU_INT_VC_IVC_DEBUG_ECC_ERR_INJ_ARRAY_SEL_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_ARRAY_SEL_LEN ); REG64_FLD( PU_INT_VC_IVC_DEBUG_TRACE_ENABLE , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_TRACE_ENABLE ); REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_57_58 , 57 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_57_58 ); REG64_FLD( PU_INT_VC_IVC_DEBUG_RESERVED_57_58_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_57_58_LEN ); REG64_FLD( PU_INT_VC_IVC_DEBUG_FAST_SB_LOOKUP_DISABLE , 59 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FAST_SB_LOOKUP_DISABLE ); REG64_FLD( PU_INT_VC_IVC_DEBUG_CACHE_CTRL_ARY_SELECT , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CACHE_CTRL_ARY_SELECT ); REG64_FLD( PU_INT_VC_IVC_DEBUG_CACHE_CTRL_ARY_SELECT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CACHE_CTRL_ARY_SELECT_LEN ); REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0 ); REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_0 , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_0 ); REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_0_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_0_LEN ); REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_8 , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_8 ); REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD ); REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_LEN ); REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_16 , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_16 ); REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_2 , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_2 ); REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_2_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_2_LEN ); REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_24 , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24 ); REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_3 , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_3 ); REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_3_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_3_LEN ); REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_32 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32 ); REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_4 , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_4 ); REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_4_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_4_LEN ); REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_40 , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_40 ); REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_5 , 41 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_5 ); REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_5_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_5_LEN ); REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_48 , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_48 ); REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_6 , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_6 ); REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_6_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_6_LEN ); REG64_FLD( PU_INT_VC_IVC_HASH_1_RESERVED_56 , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56 ); REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_7 , 57 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_7 ); REG64_FLD( PU_INT_VC_IVC_HASH_1_HWD_7_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_7_LEN ); REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0 ); REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_8 , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_8 ); REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_8_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_8_LEN ); REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_8 , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_8 ); REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_9 , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_9 ); REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_9_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_9_LEN ); REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_16 , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_16 ); REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_10 , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_10 ); REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_10_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_10_LEN ); REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_24 , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24 ); REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_11 , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_11 ); REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_11_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_11_LEN ); REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_32 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32 ); REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_12 , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_12 ); REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_12_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_12_LEN ); REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_40 , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_40 ); REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_13 , 41 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_13 ); REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_13_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_13_LEN ); REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_48 , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_48 ); REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_14 , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_14 ); REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_14_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_14_LEN ); REG64_FLD( PU_INT_VC_IVC_HASH_2_RESERVED_56 , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56 ); REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_15 , 57 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_15 ); REG64_FLD( PU_INT_VC_IVC_HASH_2_HWD_15_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HWD_15_LEN ); REG64_FLD( PU_INT_VC_IVC_HASH_3_RESERVED_0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0 ); REG64_FLD( PU_INT_VC_IVC_HASH_3_IPI , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IPI ); REG64_FLD( PU_INT_VC_IVC_HASH_3_IPI_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IPI_LEN ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_PRF_IVE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IPI_DOES_PRF_IVE ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_PRF_IVE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IPI_DOES_PRF_IVE_LEN ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_PRF_IVE_SBC , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IPI_DOES_PRF_IVE_SBC ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_PRF_IVE_SBC_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IPI_DOES_PRF_IVE_SBC_LEN ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_HWD_DOES_PRF_IVE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_HWD_DOES_PRF_IVE ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_HWD_DOES_PRF_IVE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_HWD_DOES_PRF_IVE_LEN ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_DEM_IVE , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IPI_DOES_DEM_IVE ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_DEM_IVE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IPI_DOES_DEM_IVE_LEN ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_DEM_IVE_SBC , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IPI_DOES_DEM_IVE_SBC ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_IPI_DOES_DEM_IVE_SBC_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IPI_DOES_DEM_IVE_SBC_LEN ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CND_HWD_DOES_DEM_IVE , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CND_HWD_DOES_DEM_IVE ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CND_HWD_DOES_DEM_IVE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CND_HWD_DOES_DEM_IVE_LEN ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_PRF_CACHE_HIT , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_PRF_CACHE_HIT ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_PRF_CACHE_HIT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_PRF_CACHE_HIT_LEN ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_DEM_CACHE_HIT , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DEM_CACHE_HIT ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_DEM_CACHE_HIT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_DEM_CACHE_HIT_LEN ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VICTIM_IS_LRU ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VICTIM_IS_LRU_LEN ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_1ST_USABLE , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VICTIM_IS_1ST_USABLE ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_1ST_USABLE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VICTIM_IS_1ST_USABLE_LEN ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_2_CNT_IVE_FETCH , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IVE_FETCH ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_2_CNT_IVE_FETCH_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IVE_FETCH_LEN ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_2_CNT_SBC_LOOKUP , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_SBC_LOOKUP ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_2_CNT_SBC_LOOKUP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_SBC_LOOKUP_LEN ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_3_CNT_IVE_FETCH_REPLAY , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IVE_FETCH_REPLAY ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_3_CNT_IVE_FETCH_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IVE_FETCH_REPLAY_LEN ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_3_CNT_SBC_LOOKUP_REPLAY , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_SBC_LOOKUP_REPLAY ); REG64_FLD( PU_INT_VC_IVC_PERF_EVENT_SEL_3_CNT_SBC_LOOKUP_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_SBC_LOOKUP_REPLAY_LEN ); REG64_FLD( PU_INT_VC_IVC_SCRUB_MASK_BLOCKID , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID ); REG64_FLD( PU_INT_VC_IVC_SCRUB_MASK_BLOCKID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID_LEN ); REG64_FLD( PU_INT_VC_IVC_SCRUB_MASK_RESERVED_32_35 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_35 ); REG64_FLD( PU_INT_VC_IVC_SCRUB_MASK_RESERVED_32_35_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_35_LEN ); REG64_FLD( PU_INT_VC_IVC_SCRUB_MASK_OFFSET , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET ); REG64_FLD( PU_INT_VC_IVC_SCRUB_MASK_OFFSET_LEN , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET_LEN ); REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_WANT_CACHE_DISABLE , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WANT_CACHE_DISABLE ); REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_BLOCKID , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID ); REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_BLOCKID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID_LEN ); REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_RESERVED_32_35 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_35 ); REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_RESERVED_32_35_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_35_LEN ); REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_OFFSET , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET ); REG64_FLD( PU_INT_VC_IVC_SCRUB_TRIG_OFFSET_LEN , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET_LEN ); REG64_FLD( PU_INT_VC_IVE_ISB_BLOCK_MODE_MODE , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MODE ); REG64_FLD( PU_INT_VC_IVE_ISB_BLOCK_MODE_MODE_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MODE_LEN ); REG64_FLD( PU_INT_VC_LBS6_DEBUG_DIS_AIB_IN_ECC_CORRECTION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_AIB_IN_ECC_CORRECTION ); REG64_FLD( PU_INT_VC_LBS6_DEBUG_DIS_IRQ_ECC_CORRECTION , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_IRQ_ECC_CORRECTION ); REG64_FLD( PU_INT_VC_LBS6_DEBUG_DIS_AT_SRAM_ECC_CORRECTION , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_AT_SRAM_ECC_CORRECTION ); REG64_FLD( PU_INT_VC_LBS6_DEBUG_DIS_BAR_SRAM_ECC_CORRECTION , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_BAR_SRAM_ECC_CORRECTION ); REG64_FLD( PU_INT_VC_LBS6_DEBUG_DIS_TAG_SRAM_ECC_CORRECTION , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_TAG_SRAM_ECC_CORRECTION ); REG64_FLD( PU_INT_VC_LBS6_DEBUG_IRQ_TRACE_ENABLE , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IRQ_TRACE_ENABLE ); REG64_FLD( PU_INT_VC_LBS6_DEBUG_FORCE_SINGLE_BIT_ECC_ERR , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FORCE_SINGLE_BIT_ECC_ERR ); REG64_FLD( PU_INT_VC_LBS6_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FORCE_DOUBLE_BIT_ECC_ERR ); REG64_FLD( PU_INT_VC_LBS6_DEBUG_RESERVED_8_9 , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_8_9 ); REG64_FLD( PU_INT_VC_LBS6_DEBUG_RESERVED_8_9_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_8_9_LEN ); REG64_FLD( PU_INT_VC_LBS6_DEBUG_ECC_ERR_INJ_SELECTION , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_SELECTION ); REG64_FLD( PU_INT_VC_LBS6_DEBUG_ECC_ERR_INJ_SELECTION_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_SELECTION_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_0_17 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_17 ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_0_17_LEN , 18 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_17_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_CI_STORE , 18 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CI_STORE ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_CI_STORE_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CI_STORE_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_24_25 , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24_25 ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_24_25_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24_25_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_REQUEST , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_REQUEST ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_REQUEST_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_REQUEST_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_32_33 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_33 ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_32_33_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_33_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQ_POST , 34 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQ_POST ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQ_POST_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQ_POST_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_40_41 , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_40_41 ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_40_41_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_40_41_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_CI_LOAD , 42 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CI_LOAD ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_CI_LOAD_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CI_LOAD_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_48_49 , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_48_49 ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_48_49_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_48_49_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQD_DMA_READ , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQD_DMA_READ ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQD_DMA_READ_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQD_DMA_READ_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_56_57 , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56_57 ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_RESERVED_56_57_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56_57_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQD_DMA_WRITE , 58 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQD_DMA_WRITE ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_EQC_OUTB_CMD_EQD_DMA_WRITE_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EQD_DMA_WRITE_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_RESERVED_0_17 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_17 ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_RESERVED_0_17_LEN , 18 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_0_17_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_DMA_READ , 18 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_READ ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_DMA_READ_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_READ_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_RESERVED_24_25 , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24_25 ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_RESERVED_24_25_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_24_25_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_DMA_WRITE , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_WRITE ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IRQ_DMA_DMA_WRITE_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_WRITE_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_RESERVED_48_50 , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_48_50 ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_RESERVED_48_50_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_48_50_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_SBC_LOOKUP , 51 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SBC_LOOKUP ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_SBC_LOOKUP_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SBC_LOOKUP_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_RESERVED_56_58 , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56_58 ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_RESERVED_56_58_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56_58_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_DMA_READ , 59 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_READ ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_IVC_CMD_DMA_READ_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_READ_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_RESERVED_48_50 , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_48_50 ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_RESERVED_48_50_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_48_50_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_DMA_READ , 51 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_READ ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_DMA_READ_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_READ_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_RESERVED_56_58 , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56_58 ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_RESERVED_56_58_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56_58_LEN ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_DMA_WRITE , 59 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_WRITE ); REG64_FLD( PU_INT_VC_MAX_OUTSTANDING_SBC_CMD_DMA_WRITE_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_WRITE_LEN ); REG64_FLD( PU_INT_VC_RECOV_ERR_G0_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR ); REG64_FLD( PU_INT_VC_RECOV_ERR_G0_ERROR_LEN , 55 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_VC_RECOV_ERR_G1_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR ); REG64_FLD( PU_INT_VC_RECOV_ERR_G1_ERROR_LEN , 43 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_P0_IS_IDLE , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_P0_IS_IDLE ); REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_P1_IS_IDLE , 1 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_P1_IS_IDLE ); REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_PTAG_IN_USE , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_PTAG_IN_USE ); REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_PTAG_IN_USE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_PTAG_IN_USE_LEN ); REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_SOFT_EOI , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_SOFT_EOI ); REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_SOFT_EOI_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_SOFT_EOI_LEN ); REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_UNLOCK_IN_FIFO , 24 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_UNLOCK_IN_FIFO ); REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_UNLOCK_IN_FIFO_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_UNLOCK_IN_FIFO_LEN ); REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_ISB_FETCH , 48 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_ISB_FETCH ); REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_ISB_FETCH_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_ISB_FETCH_LEN ); REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_ISB_WRITE , 56 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_ISB_WRITE ); REG64_FLD( PU_INT_VC_SBC_ADDITIONAL_PERF_MAX_OUTSTANDING_ISB_WRITE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MAX_OUTSTANDING_ISB_WRITE_LEN ); REG64_FLD( PU_INT_VC_SBC_CACHE_EN_ENABLE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE ); REG64_FLD( PU_INT_VC_SBC_CACHE_EN_ENABLE_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_LEN ); REG64_FLD( PU_INT_VC_SBC_CACHE_WATCH_ADDR_SET_INDEX , 54 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SET_INDEX ); REG64_FLD( PU_INT_VC_SBC_CACHE_WATCH_ADDR_SET_INDEX_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SET_INDEX_LEN ); REG64_FLD( PU_INT_VC_SBC_CACHE_WATCH_DATA_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_INT_VC_SBC_CACHE_WATCH_DATA_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_INT_VC_SBC_CONFIG_RESERVED_44_46 , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_44_46 ); REG64_FLD( PU_INT_VC_SBC_CONFIG_RESERVED_44_46_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_44_46_LEN ); REG64_FLD( PU_INT_VC_SBC_CONFIG_MAX_PTAG_IN_USE , 47 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MAX_PTAG_IN_USE ); REG64_FLD( PU_INT_VC_SBC_CONFIG_MAX_PTAG_IN_USE_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MAX_PTAG_IN_USE_LEN ); REG64_FLD( PU_INT_VC_SBC_CONFIG_BG_SCAN_RATE , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BG_SCAN_RATE ); REG64_FLD( PU_INT_VC_SBC_CONFIG_BG_SCAN_RATE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BG_SCAN_RATE_LEN ); REG64_FLD( PU_INT_VC_SBC_CONFIG_RESERVED_56_59 , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56_59 ); REG64_FLD( PU_INT_VC_SBC_CONFIG_RESERVED_56_59_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_56_59_LEN ); REG64_FLD( PU_INT_VC_SBC_CONFIG_MAX_ENTRIES_IN_MODIFIED , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MAX_ENTRIES_IN_MODIFIED ); REG64_FLD( PU_INT_VC_SBC_CONFIG_MAX_ENTRIES_IN_MODIFIED_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MAX_ENTRIES_IN_MODIFIED_LEN ); REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_32_33 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_33 ); REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_32_33_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_33_LEN ); REG64_FLD( PU_INT_VC_SBC_DEBUG_DIS_TAG_ECC_CORRECTION , 34 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_TAG_ECC_CORRECTION ); REG64_FLD( PU_INT_VC_SBC_DEBUG_DIS_TAG_ECC_CORRECTION_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_TAG_ECC_CORRECTION_LEN ); REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_38_41 , 38 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_38_41 ); REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_38_41_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_38_41_LEN ); REG64_FLD( PU_INT_VC_SBC_DEBUG_DIS_STATE_ECC_CORRECTION , 42 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_STATE_ECC_CORRECTION ); REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_43_44 , 43 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_43_44 ); REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_43_44_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_43_44_LEN ); REG64_FLD( PU_INT_VC_SBC_DEBUG_DIS_DATA_ECC_CORRECTION , 45 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_DATA_ECC_CORRECTION ); REG64_FLD( PU_INT_VC_SBC_DEBUG_DIS_DATA_ECC_CORRECTION_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DIS_DATA_ECC_CORRECTION_LEN ); REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_47_48 , 47 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_47_48 ); REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_47_48_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_47_48_LEN ); REG64_FLD( PU_INT_VC_SBC_DEBUG_FORCE_SINGLE_BIT_ECC_ERR , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FORCE_SINGLE_BIT_ECC_ERR ); REG64_FLD( PU_INT_VC_SBC_DEBUG_FORCE_DOUBLE_BIT_ECC_ERR , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FORCE_DOUBLE_BIT_ECC_ERR ); REG64_FLD( PU_INT_VC_SBC_DEBUG_ECC_ERR_INJ_ARRAY_SEL , 51 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_ARRAY_SEL ); REG64_FLD( PU_INT_VC_SBC_DEBUG_ECC_ERR_INJ_ARRAY_SEL_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_ARRAY_SEL_LEN ); REG64_FLD( PU_INT_VC_SBC_DEBUG_TRACE_ENABLE , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_TRACE_ENABLE ); REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_57_59 , 57 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_57_59 ); REG64_FLD( PU_INT_VC_SBC_DEBUG_RESERVED_57_59_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_57_59_LEN ); REG64_FLD( PU_INT_VC_SBC_DEBUG_CACHE_CTRL_ARY_SELECT , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CACHE_CTRL_ARY_SELECT ); REG64_FLD( PU_INT_VC_SBC_DEBUG_CACHE_CTRL_ARY_SELECT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CACHE_CTRL_ARY_SELECT_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_IVC_PRF , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IVC_PRF ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_IVC_PRF_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IVC_PRF_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_IVC_DEMAND , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IVC_DEMAND ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_IVC_DEMAND_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IVC_DEMAND_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_EQC_COMMAND , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQC_COMMAND ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_EQC_COMMAND_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EQC_COMMAND_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_OWNED , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_NON_SPEC_EOI_OWNED ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_OWNED_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_NON_SPEC_EOI_OWNED_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_NOTOWNED , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_NON_SPEC_EOI_NOTOWNED ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_NON_SPEC_EOI_NOTOWNED_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_NON_SPEC_EOI_NOTOWNED_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_SPEC_EOI , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_SPEC_EOI ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_SPEC_EOI_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_SPEC_EOI_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_SPEC_EOI_CACHE_HIT , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_SPEC_EOI_CACHE_HIT ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_SPEC_EOI_CACHE_HIT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_SPEC_EOI_CACHE_HIT_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_PRF_CACHE_HIT , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_PRF_CACHE_HIT ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_PRF_CACHE_HIT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_PRF_CACHE_HIT_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_OTHER_CACHE_HIT , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_OTHER_CACHE_HIT ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_OTHER_CACHE_HIT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_OTHER_CACHE_HIT_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VICTIM_IS_LRU ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_LRU_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VICTIM_IS_LRU_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_1ST_USABLE , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VICTIM_IS_1ST_USABLE ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_VICTIM_IS_1ST_USABLE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_VICTIM_IS_1ST_USABLE_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_RETRY , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RETRY ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_RETRY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_RETRY_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TOO_MANY_ENTRIES ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_1_CNT_TOO_MANY_ENTRIES_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_TOO_MANY_ENTRIES_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_FETCH , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_ISB_FETCH ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_FETCH_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_ISB_FETCH_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_IVVC_RESP , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IVVC_RESP ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_IVVC_RESP_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IVVC_RESP_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_WRITE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_ISB_WRITE ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_CNT_ISB_WRITE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_ISB_WRITE_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_RESERVED_12_15 , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_12_15 ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_2_RESERVED_12_15_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_12_15_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_ISB_FETCH_REPLAY , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_ISB_FETCH_REPLAY ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_ISB_FETCH_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_ISB_FETCH_REPLAY_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_IVC_RESP_REPLAY , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IVC_RESP_REPLAY ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_IVC_RESP_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_IVC_RESP_REPLAY_LEN ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_EOI_RESP_REPLAY , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EOI_RESP_REPLAY ); REG64_FLD( PU_INT_VC_SBC_PERF_EVENT_SEL_3_CNT_EOI_RESP_REPLAY_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CNT_EOI_RESP_REPLAY_LEN ); REG64_FLD( PU_INT_VC_SBC_SCRUB_MASK_BLOCKID , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID ); REG64_FLD( PU_INT_VC_SBC_SCRUB_MASK_BLOCKID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID_LEN ); REG64_FLD( PU_INT_VC_SBC_SCRUB_MASK_RESERVED_32_40 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_40 ); REG64_FLD( PU_INT_VC_SBC_SCRUB_MASK_RESERVED_32_40_LEN , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_40_LEN ); REG64_FLD( PU_INT_VC_SBC_SCRUB_MASK_OFFSET , 41 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET ); REG64_FLD( PU_INT_VC_SBC_SCRUB_MASK_OFFSET_LEN , 23 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET_LEN ); REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_VALID , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VALID ); REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_WANT_CACHE_DISABLE , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WANT_CACHE_DISABLE ); REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_WANT_INVALIDATE , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WANT_INVALIDATE ); REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_BLOCKID , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID ); REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_BLOCKID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID_LEN ); REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_RESERVED_32_40 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_40 ); REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_RESERVED_32_40_LEN , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_40_LEN ); REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_OFFSET , 41 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET ); REG64_FLD( PU_INT_VC_SBC_SCRUB_TRIG_OFFSET_LEN , 23 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET_LEN ); REG64_FLD( PU_INT_VC_SBC_SOFTWR_ADDR_BLOCKID , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID ); REG64_FLD( PU_INT_VC_SBC_SOFTWR_ADDR_BLOCKID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BLOCKID_LEN ); REG64_FLD( PU_INT_VC_SBC_SOFTWR_ADDR_RESERVED_32_35 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_35 ); REG64_FLD( PU_INT_VC_SBC_SOFTWR_ADDR_RESERVED_32_35_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_32_35_LEN ); REG64_FLD( PU_INT_VC_SBC_SOFTWR_ADDR_OFFSET , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET ); REG64_FLD( PU_INT_VC_SBC_SOFTWR_ADDR_OFFSET_LEN , 23 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OFFSET_LEN ); REG64_FLD( PU_INT_VC_SBC_SOFTWR_DATA_PQ_STATE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PQ_STATE ); REG64_FLD( PU_INT_VC_SBC_SOFTWR_DATA_PQ_STATE_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PQ_STATE_LEN ); REG64_FLD( PU_INT_VC_SBC_SOFTWR_MASK_MSK , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MSK ); REG64_FLD( PU_INT_VC_SBC_SOFTWR_MASK_MSK_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MSK_LEN ); REG64_FLD( PU_INT_VC_VPS_BLOCK_MODE_MODE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MODE ); REG64_FLD( PU_INT_VC_VPS_BLOCK_MODE_MODE_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MODE_LEN ); REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_AUTO_INCREMENT , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_AUTO_INCREMENT ); REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_SELECT , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SELECT ); REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_SELECT_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SELECT_LEN ); REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_RESERVED_16_26 , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_16_26 ); REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_RESERVED_16_26_LEN , 11 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_16_26_LEN ); REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_ADDRESS , 27 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS ); REG64_FLD( PU_INT_VC_VSD_TABLE_ADDR_ADDRESS_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_INT_VC_WOF_ERR_G0_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR ); REG64_FLD( PU_INT_VC_WOF_ERR_G0_ERROR_LEN , 55 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_VC_WOF_ERR_G0_DETAIL_ERROR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ERROR ); REG64_FLD( PU_INT_VC_WOF_ERR_G0_DETAIL_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_VC_WOF_ERR_G1_ERROR , 0 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR ); REG64_FLD( PU_INT_VC_WOF_ERR_G1_ERROR_LEN , 43 , SH_UNT , SH_ACS_SCOM_CLRPART, SH_FLD_ERROR_LEN ); REG64_FLD( PU_INT_VC_WOF_ERR_G1_DETAIL_ERROR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ERROR ); REG64_FLD( PU_INT_VC_WOF_ERR_G1_DETAIL_ERROR_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ERROR_LEN ); REG64_FLD( PU_NPU_SM1_IODA_ADDR_AUTO_INCREMENT , 0 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_AUTO_INCREMENT ); REG64_FLD( PU_NPU_SM1_IODA_ADDR_TABLE_SELECT , 11 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_TABLE_SELECT ); REG64_FLD( PU_NPU_SM1_IODA_ADDR_TABLE_SELECT_LEN , 5 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_TABLE_SELECT_LEN ); REG64_FLD( PU_NPU_SM1_IODA_ADDR_TABLE_ADDRESS , 54 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_TABLE_ADDRESS ); REG64_FLD( PU_NPU_SM1_IODA_ADDR_TABLE_ADDRESS_LEN , 10 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_TABLE_ADDRESS_LEN ); REG64_FLD( PU_NPU_SM1_IODA_DAT0_TABLE_DATA , 0 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_TABLE_DATA ); REG64_FLD( PU_NPU_SM1_IODA_DAT0_TABLE_DATA_LEN , 64 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_TABLE_DATA_LEN ); REG64_FLD( PU_IO_DATA_REG_PCB_TMP , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PCB_TMP ); REG64_FLD( PU_IO_DATA_REG_PCB_TMP_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PCB_TMP_LEN ); REG64_FLD( PU_IVT_OFFSET_PAYLOAD , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PAYLOAD ); REG64_FLD( PU_IVT_OFFSET_PAYLOAD_LEN , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_PAYLOAD_LEN ); REG64_FLD( PU_JTG_PIB_OJCFG_JTAG_SRC_SEL , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_JTAG_SRC_SEL ); REG64_FLD( PU_JTG_PIB_OJCFG_RUN_TCK , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RUN_TCK ); REG64_FLD( PU_JTG_PIB_OJCFG_TCK_WIDTH , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_TCK_WIDTH ); REG64_FLD( PU_JTG_PIB_OJCFG_TCK_WIDTH_LEN , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_TCK_WIDTH_LEN ); REG64_FLD( PU_JTG_PIB_OJCFG_JTAG_TRST_B , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_JTAG_TRST_B ); REG64_FLD( PU_JTG_PIB_OJCFG_DBG_HALT , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DBG_HALT ); REG64_FLD( PU_JTG_PIB_OJIC_START_JTAG_CMD , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_START_JTAG_CMD ); REG64_FLD( PU_JTG_PIB_OJIC_DO_IR , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DO_IR ); REG64_FLD( PU_JTG_PIB_OJIC_DO_DR , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DO_DR ); REG64_FLD( PU_JTG_PIB_OJIC_DO_TAP_RESET , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DO_TAP_RESET ); REG64_FLD( PU_JTG_PIB_OJIC_WR_VALID , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WR_VALID ); REG64_FLD( PU_JTG_PIB_OJIC_JTAG_INSTR , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_JTAG_INSTR ); REG64_FLD( PU_JTG_PIB_OJIC_JTAG_INSTR_LEN , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_JTAG_INSTR_LEN ); REG64_FLD( PU_JTG_PIB_OJSTAT_JTAG_INPROG , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_JTAG_INPROG ); REG64_FLD( PU_JTG_PIB_OJSTAT_SRC_SEL_EQ1_ERR , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_SRC_SEL_EQ1_ERR ); REG64_FLD( PU_JTG_PIB_OJSTAT_RUN_TCK_EQ0_ERR , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_RUN_TCK_EQ0_ERR ); REG64_FLD( PU_JTG_PIB_OJSTAT_TRST_B_EQ0_ERR , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRST_B_EQ0_ERR ); REG64_FLD( PU_JTG_PIB_OJSTAT_IR_DR_EQ0_ERR , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_IR_DR_EQ0_ERR ); REG64_FLD( PU_JTG_PIB_OJSTAT_INPROG_WR_ERR , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_INPROG_WR_ERR ); REG64_FLD( PU_JTG_PIB_OJSTAT_FSM_ERROR , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_FSM_ERROR ); REG64_FLD( PU_JTG_PIB_OJTDI_JTAG_TDI , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_JTAG_TDI ); REG64_FLD( PU_JTG_PIB_OJTDI_JTAG_TDI_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_JTAG_TDI_LEN ); REG64_FLD( PU_JTG_PIB_OJTDO_JTAG_TDO , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_JTAG_TDO ); REG64_FLD( PU_JTG_PIB_OJTDO_JTAG_TDO_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_JTAG_TDO_LEN ); REG64_FLD( PU_JTG_PIB_OJTDO_OJCFG_JTAG_SRC_SEL , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OJCFG_JTAG_SRC_SEL ); REG64_FLD( PU_JTG_PIB_OJTDO_OJCFG_RUN_TCK , 33 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OJCFG_RUN_TCK ); REG64_FLD( PU_JTG_PIB_OJTDO_OJCFG_TCK_WIDTH , 34 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OJCFG_TCK_WIDTH ); REG64_FLD( PU_JTG_PIB_OJTDO_OJCFG_TCK_WIDTH_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OJCFG_TCK_WIDTH_LEN ); REG64_FLD( PU_JTG_PIB_OJTDO_OJCFG_JTAG_TRST_B , 37 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OJCFG_JTAG_TRST_B ); REG64_FLD( PU_JTG_PIB_OJTDO_OJCFG_DBG_HALT , 38 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OJCFG_DBG_HALT ); REG64_FLD( PU_JTG_PIB_OJTDO_OJSTAT_JTAG_INPROG , 40 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OJSTAT_JTAG_INPROG ); REG64_FLD( PU_JTG_PIB_OJTDO_OJSTAT_SRC_SEL_EQ1_ERR , 41 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OJSTAT_SRC_SEL_EQ1_ERR ); REG64_FLD( PU_JTG_PIB_OJTDO_OJSTAT_RUN_TCK_EQ0_ERR , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OJSTAT_RUN_TCK_EQ0_ERR ); REG64_FLD( PU_JTG_PIB_OJTDO_OJSTAT_TRST_B_EQ0_ERR , 43 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OJSTAT_TRST_B_EQ0_ERR ); REG64_FLD( PU_JTG_PIB_OJTDO_OJSTAT_IR_DR_EQ0_ERR , 44 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OJSTAT_IR_DR_EQ0_ERR ); REG64_FLD( PU_JTG_PIB_OJTDO_OJSTAT_INPROG_WR_ERR , 45 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OJSTAT_INPROG_WR_ERR ); REG64_FLD( PU_JTG_PIB_OJTDO_OJSTAT_FSM_ERROR , 46 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OJSTAT_FSM_ERROR ); REG64_FLD( PU_JTG_PIB_OJTDO_OJIC_DO_IR , 49 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OJIC_DO_IR ); REG64_FLD( PU_JTG_PIB_OJTDO_OJIC_DO_DR , 50 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OJIC_DO_DR ); REG64_FLD( PU_JTG_PIB_OJTDO_OJIC_DO_TAP_RESET , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OJIC_DO_TAP_RESET ); REG64_FLD( PU_JTG_PIB_OJTDO_OJIC_WR_VALID , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OJIC_WR_VALID ); REG64_FLD( PU_JTG_PIB_OJTDO_OJIC_JTAG_INSTR , 60 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OJIC_JTAG_INSTR ); REG64_FLD( PU_JTG_PIB_OJTDO_OJIC_JTAG_INSTR_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OJIC_JTAG_INSTR_LEN ); REG64_FLD( PU_NPU_CTL_LCO_CONFIG_V_TARG , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_V_TARG ); REG64_FLD( PU_NPU_CTL_LCO_CONFIG_V_TARG_LEN , 12 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_V_TARG_LEN ); REG64_FLD( PU_NPU_CTL_LCO_CONFIG_E_TARG_MIN , 12 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_E_TARG_MIN ); REG64_FLD( PU_NPU_CTL_LCO_CONFIG_E_TARG_MIN_LEN , 4 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_E_TARG_MIN_LEN ); REG64_FLD( PU_NPU_CTL_LCO_CONFIG_RAND_EVENT , 16 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_RAND_EVENT ); REG64_FLD( PU_NPU_CTL_LCO_CONFIG_RAND_EVENT_LEN , 4 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_RAND_EVENT_LEN ); REG64_FLD( CAPP_LINK_DELAY_TIMER_VALUE , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_VALUE ); REG64_FLD( CAPP_LINK_DELAY_TIMER_VALUE_LEN , 29 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_VALUE_LEN ); REG64_FLD( CAPP_LINK_DELAY_TIMER_VALID , 32 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_VALID ); REG64_FLD( CAPP_LINK_DELAY_TIMER_RESP_PKT_RCV , 33 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_RESP_PKT_RCV ); REG64_FLD( CAPP_LINK_DELAY_TIMER_SECURE_ERR , 34 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SECURE_ERR ); REG64_FLD( PEC_LOCAL_FIR_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN0 ); REG64_FLD( PEC_LOCAL_FIR_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN1 ); REG64_FLD( PEC_LOCAL_FIR_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN2 ); REG64_FLD( PEC_LOCAL_FIR_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN3 ); REG64_FLD( PEC_LOCAL_FIR_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN4 ); REG64_FLD( PEC_LOCAL_FIR_IN5 , 5 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN5 ); REG64_FLD( PEC_LOCAL_FIR_IN6 , 6 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN6 ); REG64_FLD( PEC_LOCAL_FIR_IN7 , 7 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN7 ); REG64_FLD( PEC_LOCAL_FIR_IN8 , 8 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN8 ); REG64_FLD( PEC_LOCAL_FIR_IN9 , 9 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN9 ); REG64_FLD( PEC_LOCAL_FIR_IN10 , 10 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN10 ); REG64_FLD( PEC_LOCAL_FIR_IN11 , 11 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN11 ); REG64_FLD( PEC_LOCAL_FIR_IN12 , 12 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN12 ); REG64_FLD( PEC_LOCAL_FIR_IN13 , 13 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN13 ); REG64_FLD( PEC_LOCAL_FIR_IN14 , 14 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN14 ); REG64_FLD( PEC_LOCAL_FIR_IN15 , 15 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN15 ); REG64_FLD( PEC_LOCAL_FIR_IN16 , 16 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN16 ); REG64_FLD( PEC_LOCAL_FIR_IN17 , 17 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN17 ); REG64_FLD( PEC_LOCAL_FIR_IN18 , 18 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN18 ); REG64_FLD( PEC_LOCAL_FIR_IN19 , 19 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN19 ); REG64_FLD( PEC_LOCAL_FIR_IN20 , 20 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN20 ); REG64_FLD( PEC_LOCAL_FIR_IN21 , 21 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN21 ); REG64_FLD( PEC_LOCAL_FIR_IN22 , 22 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN22 ); REG64_FLD( PEC_LOCAL_FIR_IN23 , 23 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN23 ); REG64_FLD( PEC_LOCAL_FIR_IN24 , 24 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN24 ); REG64_FLD( PEC_LOCAL_FIR_IN25 , 25 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN25 ); REG64_FLD( PEC_LOCAL_FIR_IN26 , 26 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN26 ); REG64_FLD( PEC_LOCAL_FIR_IN27 , 27 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN27 ); REG64_FLD( PEC_LOCAL_FIR_IN28 , 28 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN28 ); REG64_FLD( PEC_LOCAL_FIR_IN29 , 29 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN29 ); REG64_FLD( PEC_LOCAL_FIR_IN30 , 30 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN30 ); REG64_FLD( PEC_LOCAL_FIR_IN31 , 31 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN31 ); REG64_FLD( PEC_LOCAL_FIR_IN32 , 32 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN32 ); REG64_FLD( PEC_LOCAL_FIR_IN33 , 33 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN33 ); REG64_FLD( PEC_LOCAL_FIR_IN34 , 34 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN34 ); REG64_FLD( PEC_LOCAL_FIR_IN35 , 35 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN35 ); REG64_FLD( PEC_LOCAL_FIR_IN36 , 36 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN36 ); REG64_FLD( PEC_LOCAL_FIR_IN37 , 37 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN37 ); REG64_FLD( PEC_LOCAL_FIR_IN38 , 38 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN38 ); REG64_FLD( PEC_LOCAL_FIR_IN39 , 39 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN39 ); REG64_FLD( PEC_LOCAL_FIR_IN40 , 40 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN40 ); REG64_FLD( PEC_LOCAL_FIR_IN41 , 41 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_IN41 ); REG64_FLD( PEC_LOCAL_FIR_ACTION0_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( PEC_LOCAL_FIR_ACTION0_IN_LEN , 42 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( PEC_LOCAL_FIR_ACTION1_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( PEC_LOCAL_FIR_ACTION1_IN_LEN , 42 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( PEC_LOCAL_FIR_MASK_LFIR_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_LFIR_IN ); REG64_FLD( PEC_LOCAL_FIR_MASK_LFIR_IN_LEN , 42 , SH_UNT_PEC , SH_ACS_SCOM2_OR , SH_FLD_LFIR_IN_LEN ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN0 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN1 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN2 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN3 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN4 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN5 , 5 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN5 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN6 , 6 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN6 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN7 , 7 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN7 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN8 , 8 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN8 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN9 , 9 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN9 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN10 , 10 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN10 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN11 , 11 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN11 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN12 , 12 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN12 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN13 , 13 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN13 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN14 , 14 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN14 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN15 , 15 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN15 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN16 , 16 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN16 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN17 , 17 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN17 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN18 , 18 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN18 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN19 , 19 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN19 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN20 , 20 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN20 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN21 , 21 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN21 ); REG64_FLD( PEC_LOCAL_XSTOP_ERR_IN22 , 22 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_IN22 ); REG64_FLD( PEC_LOCAL_XSTOP_MASK_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( PEC_LOCAL_XSTOP_MASK_IN_LEN , 22 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_MODE_ENABLE , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_LP_MODE_ENABLE ); REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_ONLY_MODE , 1 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_LP_ONLY_MODE ); REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_TIMER_TICK_CONFIG , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_LP_TIMER_TICK_CONFIG ); REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN , 6 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_LP_TIMER_TICK_CONFIG_LEN ); REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_MIN_CRED_THRESH , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_LP_MIN_CRED_THRESH ); REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_MIN_CRED_THRESH_LEN , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_LP_MIN_CRED_THRESH_LEN ); REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_MAX_CRED_THRESH , 20 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_LP_MAX_CRED_THRESH ); REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_MAX_CRED_THRESH_LEN , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_LP_MAX_CRED_THRESH_LEN ); REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_CNT_THRESH , 32 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_LP_CNT_THRESH ); REG64_FLD( PU_NPU2_NTL0_LOW_PWR_LP_CNT_THRESH_LEN , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_LP_CNT_THRESH_LEN ); REG64_FLD( NV_LOW_PWR_LP_MODE_ENABLE , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_LP_MODE_ENABLE ); REG64_FLD( NV_LOW_PWR_LP_ONLY_MODE , 1 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_LP_ONLY_MODE ); REG64_FLD( NV_LOW_PWR_LP_TIMER_TICK_CONFIG , 2 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_LP_TIMER_TICK_CONFIG ); REG64_FLD( NV_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN , 6 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_LP_TIMER_TICK_CONFIG_LEN ); REG64_FLD( NV_LOW_PWR_LP_MIN_CRED_THRESH , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_LP_MIN_CRED_THRESH ); REG64_FLD( NV_LOW_PWR_LP_MIN_CRED_THRESH_LEN , 12 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_LP_MIN_CRED_THRESH_LEN ); REG64_FLD( NV_LOW_PWR_LP_MAX_CRED_THRESH , 20 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_LP_MAX_CRED_THRESH ); REG64_FLD( NV_LOW_PWR_LP_MAX_CRED_THRESH_LEN , 12 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_LP_MAX_CRED_THRESH_LEN ); REG64_FLD( NV_LOW_PWR_LP_CNT_THRESH , 32 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_LP_CNT_THRESH ); REG64_FLD( NV_LOW_PWR_LP_CNT_THRESH_LEN , 12 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_LP_CNT_THRESH_LEN ); REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_MODE_ENABLE , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_LP_MODE_ENABLE ); REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_ONLY_MODE , 1 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_LP_ONLY_MODE ); REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_TIMER_TICK_CONFIG , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_LP_TIMER_TICK_CONFIG ); REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_TIMER_TICK_CONFIG_LEN , 6 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_LP_TIMER_TICK_CONFIG_LEN ); REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_MIN_CRED_THRESH , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_LP_MIN_CRED_THRESH ); REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_MIN_CRED_THRESH_LEN , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_LP_MIN_CRED_THRESH_LEN ); REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_MAX_CRED_THRESH , 20 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_LP_MAX_CRED_THRESH ); REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_MAX_CRED_THRESH_LEN , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_LP_MAX_CRED_THRESH_LEN ); REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_CNT_THRESH , 32 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_LP_CNT_THRESH ); REG64_FLD( PU_NPU2_NTL1_LOW_PWR_LP_CNT_THRESH_LEN , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_LP_CNT_THRESH_LEN ); REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES ); REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES_LEN ); REG64_FLD( PU_NPU0_SM0_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM0_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM0_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES ); REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES_LEN ); REG64_FLD( PU_NPU1_SM2_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM2_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM2_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES ); REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES_LEN ); REG64_FLD( PU_NPU2_SM3_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM3_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM3_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES ); REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES_LEN ); REG64_FLD( PU_NPU1_SM3_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM3_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM3_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES ); REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES_LEN ); REG64_FLD( PU_NPU0_SM3_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM3_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM3_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES ); REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES_LEN ); REG64_FLD( PU_NPU1_SM1_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM1_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM1_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES ); REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES_LEN ); REG64_FLD( PU_NPU2_SM2_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM2_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM2_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES ); REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES_LEN ); REG64_FLD( PU_NPU2_SM1_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM1_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM1_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES ); REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES_LEN ); REG64_FLD( PU_NPU0_SM2_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM2_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM2_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES ); REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES_LEN ); REG64_FLD( PU_NPU2_SM0_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM0_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM0_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES ); REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES_LEN ); REG64_FLD( PU_NPU0_SM1_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM1_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM1_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_XATS , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_XATS ); REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_XATS_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_XATS_LEN ); REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PWR0 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0 ); REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PWR0_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR0_LEN ); REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PWR1 , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1 ); REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PWR1_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PWR1_LEN ); REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_REQ0 , 18 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0 ); REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_REQ0_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ0_LEN ); REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PRB0 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0 ); REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PRB0_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB0_LEN ); REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_REQ1 , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1 ); REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_REQ1_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_REQ1_LEN ); REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PRB1 , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1 ); REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_PRB1_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_PRB1_LEN ); REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_MAX_MACHINES , 42 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES ); REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_MAX_MACHINES_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_MAX_MACHINES_LEN ); REG64_FLD( PU_NPU1_SM0_LOW_WATER_RESERVED1 , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM0_LOW_WATER_RESERVED1_LEN , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM0_LOW_WATER_CONFIG_ENABLE_MACHINE_ALLOC , 51 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE_MACHINE_ALLOC ); REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_BUSY_ENABLE , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_BUSY_ENABLE ); REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_WINDOW_SELECT , 1 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_WINDOW_SELECT ); REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_WINDOW_SELECT_LEN , 3 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_WINDOW_SELECT_LEN ); REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_THRESH_0 , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_THRESH_0 ); REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_THRESH_0_LEN , 10 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_THRESH_0_LEN ); REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_THRESH_1 , 14 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_THRESH_1 ); REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_THRESH_1_LEN , 10 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_THRESH_1_LEN ); REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_THRESH_2 , 24 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_THRESH_2 ); REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_THRESH_2_LEN , 10 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_THRESH_2_LEN ); REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_RESERVED1 , 34 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_CTL_LPCTH_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_BUSY_ENABLE , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_BUSY_ENABLE ); REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_WINDOW_SELECT , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_WINDOW_SELECT ); REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_WINDOW_SELECT_LEN , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_WINDOW_SELECT_LEN ); REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_THRESH_0 , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_THRESH_0 ); REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_THRESH_0_LEN , 10 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_THRESH_0_LEN ); REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_THRESH_1 , 14 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_THRESH_1 ); REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_THRESH_1_LEN , 10 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_THRESH_1_LEN ); REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_THRESH_2 , 24 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_THRESH_2 ); REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_THRESH_2_LEN , 10 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_THRESH_2_LEN ); REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_RESERVED1 , 34 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_CTL_LPCTH_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_BUSY_ENABLE , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_BUSY_ENABLE ); REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_WINDOW_SELECT , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_WINDOW_SELECT ); REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_WINDOW_SELECT_LEN , 3 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_WINDOW_SELECT_LEN ); REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_THRESH_0 , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_THRESH_0 ); REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_THRESH_0_LEN , 10 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_THRESH_0_LEN ); REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_THRESH_1 , 14 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_THRESH_1 ); REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_THRESH_1_LEN , 10 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_THRESH_1_LEN ); REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_THRESH_2 , 24 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_THRESH_2 ); REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_THRESH_2_LEN , 10 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_THRESH_2_LEN ); REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_RESERVED1 , 34 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_CTL_LPCTH_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_LPC_BASE_REG_BASE , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_BASE ); REG64_FLD( PU_LPC_BASE_REG_BASE_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_BASE_LEN ); REG64_FLD( PU_LPC_BASE_REG_DISABLE , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE ); REG64_FLD( PU_LPC_CMD_REG_RNW , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RNW ); REG64_FLD( PU_LPC_CMD_REG_SIZE , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_SIZE ); REG64_FLD( PU_LPC_CMD_REG_SIZE_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_SIZE_LEN ); REG64_FLD( PU_LPC_CMD_REG_ADR , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADR ); REG64_FLD( PU_LPC_CMD_REG_ADR_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADR_LEN ); REG64_FLD( PU_LPC_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_LPC_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_LPC_STATUS_REG_DONE , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DONE ); REG64_FLD( PU_LPC_STATUS_REG_VALID , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_VALID ); REG64_FLD( PU_LPC_STATUS_REG_ACK , 11 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ACK ); REG64_FLD( PU_MCC_FIR_REG_MCD_ARRAY_ECC_UE_ERR , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MCD_ARRAY_ECC_UE_ERR ); REG64_FLD( PU_MCC_FIR_REG_MCD_ARRAY_ECC_CE_ERR , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MCD_ARRAY_ECC_CE_ERR ); REG64_FLD( PU_MCC_FIR_REG_MCD_PB_ADDR_PARITY_ERR , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MCD_PB_ADDR_PARITY_ERR ); REG64_FLD( PU_MCC_FIR_REG_MCD_SM_OR_CASE_ERR , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MCD_SM_OR_CASE_ERR ); REG64_FLD( PU_MCC_FIR_REG_MCD_CL_PROBE_PB_HANG_ERR , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MCD_CL_PROBE_PB_HANG_ERR ); REG64_FLD( PU_MCC_FIR_REG_MCD_CRESP_ADDR_ERR , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MCD_CRESP_ADDR_ERR ); REG64_FLD( PU_MCC_FIR_REG_MCD_UNSOLICITED_CRESP_ERR , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MCD_UNSOLICITED_CRESP_ERR ); REG64_FLD( PU_MCC_FIR_REG_MCD_TTAG_PARITY_ERR , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MCD_TTAG_PARITY_ERR ); REG64_FLD( PU_MCC_FIR_REG_MCD_UPDATE_ERR , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MCD_UPDATE_ERR ); REG64_FLD( PU_MCC_FIR_REG_MCD_ACK_DEAD_CRESP_ERR , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MCD_ACK_DEAD_CRESP_ERR ); REG64_FLD( PU_MCC_FIR_REG_MCD_SCOM_ERR , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MCD_SCOM_ERR ); REG64_FLD( PU_MCC_FIR_REG_MCD_SCOM_ERR_DUP , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MCD_SCOM_ERR_DUP ); REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_ARRAY_ECC_UE_ERR , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_MCD_ARRAY_ECC_UE_ERR ); REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_ARRAY_ECC_CE_ERR , 1 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_MCD_ARRAY_ECC_CE_ERR ); REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_PB_ADDR_PARITY_ERR , 2 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_MCD_PB_ADDR_PARITY_ERR ); REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_SM_OR_CASE_ERR , 3 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_MCD_SM_OR_CASE_ERR ); REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_CL_PROBE_PB_HANG_ERR , 4 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_MCD_CL_PROBE_PB_HANG_ERR ); REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_CRESP_ADDR_ERR , 5 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_MCD_CRESP_ADDR_ERR ); REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_UNSOLICITED_CRESP_ERR , 6 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_MCD_UNSOLICITED_CRESP_ERR ); REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_TTAG_PARITY_ERR , 7 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_MCD_TTAG_PARITY_ERR ); REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_UPDATE_ERR , 8 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_MCD_UPDATE_ERR ); REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_ACK_DEAD_CRESP_ERR , 9 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_MCD_ACK_DEAD_CRESP_ERR ); REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_SCOM_ERR , 10 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_MCD_SCOM_ERR ); REG64_FLD( PU_MCD1_MCC_FIR_REG_MCD_SCOM_ERR_DUP , 11 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_MCD_SCOM_ERR_DUP ); REG64_FLD( PU_MCD_DBG_TRACE_ENABLE , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_ENABLE ); REG64_FLD( PU_MCD_DBG_TRACE_SELECT , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_SELECT ); REG64_FLD( PU_MCD_DBG_TRACE_SELECT_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_SELECT_LEN ); REG64_FLD( PU_MCD_DBG_ERR_INJ_ENABLE , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERR_INJ_ENABLE ); REG64_FLD( PU_MCD_DBG_ERR_INJ_TYPE , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERR_INJ_TYPE ); REG64_FLD( PU_MCD_DBG_ERR_INJ_ACTION , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERR_INJ_ACTION ); REG64_FLD( PU_MCD_DBG_ERR_INJ_ARRAY_SEL , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERR_INJ_ARRAY_SEL ); REG64_FLD( PU_MCD_DBG_ERR_INJ_ARRAY_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERR_INJ_ARRAY_SEL_LEN ); REG64_FLD( PU_MCD_DBG_ERR_INJ_STATUS , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERR_INJ_STATUS ); REG64_FLD( PU_MCD_DBG_PMU_ENABLE , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_PMU_ENABLE ); REG64_FLD( PU_MCD_DBG_PMU_SELECT_LOW , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_PMU_SELECT_LOW ); REG64_FLD( PU_MCD_DBG_PMU_SELECT_LOW_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_PMU_SELECT_LOW_LEN ); REG64_FLD( PU_MCD_DBG_PMU_SELECT_HIGH , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_PMU_SELECT_HIGH ); REG64_FLD( PU_MCD_DBG_PMU_SELECT_HIGH_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_PMU_SELECT_HIGH_LEN ); REG64_FLD( PU_MCD_DBG_PMU_BUS_ENABLE , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PMU_BUS_ENABLE ); REG64_FLD( PU_MCD_DBG_PMU_BUS_ENABLE_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_PMU_BUS_ENABLE_LEN ); REG64_FLD( PU_MCD1_MCD_DBG_TRACE_ENABLE , 3 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_TRACE_ENABLE ); REG64_FLD( PU_MCD1_MCD_DBG_TRACE_SELECT , 4 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_TRACE_SELECT ); REG64_FLD( PU_MCD1_MCD_DBG_TRACE_SELECT_LEN , 4 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_TRACE_SELECT_LEN ); REG64_FLD( PU_MCD1_MCD_DBG_ERR_INJ_ENABLE , 8 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_ERR_INJ_ENABLE ); REG64_FLD( PU_MCD1_MCD_DBG_ERR_INJ_TYPE , 9 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_ERR_INJ_TYPE ); REG64_FLD( PU_MCD1_MCD_DBG_ERR_INJ_ACTION , 10 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_ERR_INJ_ACTION ); REG64_FLD( PU_MCD1_MCD_DBG_ERR_INJ_ARRAY_SEL , 11 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_ERR_INJ_ARRAY_SEL ); REG64_FLD( PU_MCD1_MCD_DBG_ERR_INJ_ARRAY_SEL_LEN , 4 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_ERR_INJ_ARRAY_SEL_LEN ); REG64_FLD( PU_MCD1_MCD_DBG_ERR_INJ_STATUS , 15 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_ERR_INJ_STATUS ); REG64_FLD( PU_MCD1_MCD_DBG_PMU_ENABLE , 19 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_PMU_ENABLE ); REG64_FLD( PU_MCD1_MCD_DBG_PMU_SELECT_LOW , 20 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_PMU_SELECT_LOW ); REG64_FLD( PU_MCD1_MCD_DBG_PMU_SELECT_LOW_LEN , 3 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_PMU_SELECT_LOW_LEN ); REG64_FLD( PU_MCD1_MCD_DBG_PMU_SELECT_HIGH , 23 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_PMU_SELECT_HIGH ); REG64_FLD( PU_MCD1_MCD_DBG_PMU_SELECT_HIGH_LEN , 3 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_PMU_SELECT_HIGH_LEN ); REG64_FLD( PU_MCD1_MCD_DBG_PMU_BUS_ENABLE , 32 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_PMU_BUS_ENABLE ); REG64_FLD( PU_MCD1_MCD_DBG_PMU_BUS_ENABLE_LEN , 16 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_PMU_BUS_ENABLE_LEN ); REG64_FLD( PU_MCD_ECAP_ECC_CLEAR , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_CLEAR ); REG64_FLD( PU_MCD_ECAP_ECC_UE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_UE ); REG64_FLD( PU_MCD_ECAP_ECC_CE , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_CE ); REG64_FLD( PU_MCD_ECAP_ECC_ERROR_COUNT , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_ERROR_COUNT ); REG64_FLD( PU_MCD_ECAP_ECC_ERROR_COUNT_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_ERROR_COUNT_LEN ); REG64_FLD( PU_MCD_ECAP_ECC_ERROR_ADDR , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_ERROR_ADDR ); REG64_FLD( PU_MCD_ECAP_ECC_ERROR_ADDR_LEN , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_ERROR_ADDR_LEN ); REG64_FLD( PU_MCD_ECAP_ECC_SYNDROME , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_SYNDROME ); REG64_FLD( PU_MCD_ECAP_ECC_SYNDROME_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_SYNDROME_LEN ); REG64_FLD( PU_MCD_ECAP_SLICE0_CFG_ECC_UE_ERR , 33 , SH_UNT , SH_ACS_SCOM , SH_FLD_SLICE0_CFG_ECC_UE_ERR ); REG64_FLD( PU_MCD_ECAP_SLICE0_CFG_ECC_CE_ERR , 34 , SH_UNT , SH_ACS_SCOM , SH_FLD_SLICE0_CFG_ECC_CE_ERR ); REG64_FLD( PU_MCD_ECAP_SLICE1_CFG_ECC_UE_ERR , 35 , SH_UNT , SH_ACS_SCOM , SH_FLD_SLICE1_CFG_ECC_UE_ERR ); REG64_FLD( PU_MCD_ECAP_SLICE1_CFG_ECC_CE_ERR , 36 , SH_UNT , SH_ACS_SCOM , SH_FLD_SLICE1_CFG_ECC_CE_ERR ); REG64_FLD( PU_MCD_ECAP_SLICE2_CFG_ECC_UE_ERR , 37 , SH_UNT , SH_ACS_SCOM , SH_FLD_SLICE2_CFG_ECC_UE_ERR ); REG64_FLD( PU_MCD_ECAP_SLICE2_CFG_ECC_CE_ERR , 38 , SH_UNT , SH_ACS_SCOM , SH_FLD_SLICE2_CFG_ECC_CE_ERR ); REG64_FLD( PU_MCD_ECAP_SLICE3_CFG_ECC_UE_ERR , 39 , SH_UNT , SH_ACS_SCOM , SH_FLD_SLICE3_CFG_ECC_UE_ERR ); REG64_FLD( PU_MCD_ECAP_SLICE3_CFG_ECC_CE_ERR , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_SLICE3_CFG_ECC_CE_ERR ); REG64_FLD( PU_MCD_ECAP_PRESP_RTY_OTHER , 41 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRESP_RTY_OTHER ); REG64_FLD( PU_MCD_ECAP_REC_SM_ERROR_ERR , 42 , SH_UNT , SH_ACS_SCOM , SH_FLD_REC_SM_ERROR_ERR ); REG64_FLD( PU_MCD_ECAP_REC_PB_SM_ERROR_ERR , 43 , SH_UNT , SH_ACS_SCOM , SH_FLD_REC_PB_SM_ERROR_ERR ); REG64_FLD( PU_MCD_ECAP_ADDR_ERROR_PULSE , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDR_ERROR_PULSE ); REG64_FLD( PU_MCD_ECAP_RCMD0_ADDR_PARITY_ERROR , 45 , SH_UNT , SH_ACS_SCOM , SH_FLD_RCMD0_ADDR_PARITY_ERROR ); REG64_FLD( PU_MCD_ECAP_RCMD1_ADDR_PARITY_ERROR , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_RCMD1_ADDR_PARITY_ERROR ); REG64_FLD( PU_MCD_ECAP_RCMD2_ADDR_PARITY_ERROR , 47 , SH_UNT , SH_ACS_SCOM , SH_FLD_RCMD2_ADDR_PARITY_ERROR ); REG64_FLD( PU_MCD_ECAP_RCMD3_ADDR_PARITY_ERROR , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_RCMD3_ADDR_PARITY_ERROR ); REG64_FLD( PU_MCD_ECAP_WARB_INVALID_CASE_ERROR , 49 , SH_UNT , SH_ACS_SCOM , SH_FLD_WARB_INVALID_CASE_ERROR ); REG64_FLD( PU_MCD_ECAP_INVALID_CRESP_ERROR , 50 , SH_UNT , SH_ACS_SCOM , SH_FLD_INVALID_CRESP_ERROR ); REG64_FLD( PU_MCD_ECAP_TTAG_PARITY_ERROR , 51 , SH_UNT , SH_ACS_SCOM , SH_FLD_TTAG_PARITY_ERROR ); REG64_FLD( PU_MCD_ECAP_RDADDR_ARB_BAD_HAND , 52 , SH_UNT , SH_ACS_SCOM , SH_FLD_RDADDR_ARB_BAD_HAND ); REG64_FLD( PU_MCD_ECAP_RDWR_UPDATE_ERROR , 53 , SH_UNT , SH_ACS_SCOM , SH_FLD_RDWR_UPDATE_ERROR ); REG64_FLD( PU_MCD_ECAP_REC_UPDATE_ERROR , 54 , SH_UNT , SH_ACS_SCOM , SH_FLD_REC_UPDATE_ERROR ); REG64_FLD( PU_MCD_ECAP_REC_ACK_DEAD_ERROR , 55 , SH_UNT , SH_ACS_SCOM , SH_FLD_REC_ACK_DEAD_ERROR ); REG64_FLD( PU_MCD1_MCD_ECAP_ECC_CLEAR , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_ECC_CLEAR ); REG64_FLD( PU_MCD1_MCD_ECAP_ECC_UE , 2 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_ECC_UE ); REG64_FLD( PU_MCD1_MCD_ECAP_ECC_CE , 3 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_ECC_CE ); REG64_FLD( PU_MCD1_MCD_ECAP_ECC_ERROR_COUNT , 4 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_ECC_ERROR_COUNT ); REG64_FLD( PU_MCD1_MCD_ECAP_ECC_ERROR_COUNT_LEN , 4 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_ECC_ERROR_COUNT_LEN ); REG64_FLD( PU_MCD1_MCD_ECAP_ECC_ERROR_ADDR , 10 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_ECC_ERROR_ADDR ); REG64_FLD( PU_MCD1_MCD_ECAP_ECC_ERROR_ADDR_LEN , 14 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_ECC_ERROR_ADDR_LEN ); REG64_FLD( PU_MCD1_MCD_ECAP_ECC_SYNDROME , 24 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_ECC_SYNDROME ); REG64_FLD( PU_MCD1_MCD_ECAP_ECC_SYNDROME_LEN , 8 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_ECC_SYNDROME_LEN ); REG64_FLD( PU_MCD1_MCD_ECAP_SLICE0_CFG_ECC_UE_ERR , 33 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_SLICE0_CFG_ECC_UE_ERR ); REG64_FLD( PU_MCD1_MCD_ECAP_SLICE0_CFG_ECC_CE_ERR , 34 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_SLICE0_CFG_ECC_CE_ERR ); REG64_FLD( PU_MCD1_MCD_ECAP_SLICE1_CFG_ECC_UE_ERR , 35 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_SLICE1_CFG_ECC_UE_ERR ); REG64_FLD( PU_MCD1_MCD_ECAP_SLICE1_CFG_ECC_CE_ERR , 36 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_SLICE1_CFG_ECC_CE_ERR ); REG64_FLD( PU_MCD1_MCD_ECAP_SLICE2_CFG_ECC_UE_ERR , 37 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_SLICE2_CFG_ECC_UE_ERR ); REG64_FLD( PU_MCD1_MCD_ECAP_SLICE2_CFG_ECC_CE_ERR , 38 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_SLICE2_CFG_ECC_CE_ERR ); REG64_FLD( PU_MCD1_MCD_ECAP_SLICE3_CFG_ECC_UE_ERR , 39 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_SLICE3_CFG_ECC_UE_ERR ); REG64_FLD( PU_MCD1_MCD_ECAP_SLICE3_CFG_ECC_CE_ERR , 40 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_SLICE3_CFG_ECC_CE_ERR ); REG64_FLD( PU_MCD1_MCD_ECAP_PRESP_RTY_OTHER , 41 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_PRESP_RTY_OTHER ); REG64_FLD( PU_MCD1_MCD_ECAP_REC_SM_ERROR_ERR , 42 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_REC_SM_ERROR_ERR ); REG64_FLD( PU_MCD1_MCD_ECAP_REC_PB_SM_ERROR_ERR , 43 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_REC_PB_SM_ERROR_ERR ); REG64_FLD( PU_MCD1_MCD_ECAP_ADDR_ERROR_PULSE , 44 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_ADDR_ERROR_PULSE ); REG64_FLD( PU_MCD1_MCD_ECAP_RCMD0_ADDR_PARITY_ERROR , 45 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_RCMD0_ADDR_PARITY_ERROR ); REG64_FLD( PU_MCD1_MCD_ECAP_RCMD1_ADDR_PARITY_ERROR , 46 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_RCMD1_ADDR_PARITY_ERROR ); REG64_FLD( PU_MCD1_MCD_ECAP_RCMD2_ADDR_PARITY_ERROR , 47 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_RCMD2_ADDR_PARITY_ERROR ); REG64_FLD( PU_MCD1_MCD_ECAP_RCMD3_ADDR_PARITY_ERROR , 48 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_RCMD3_ADDR_PARITY_ERROR ); REG64_FLD( PU_MCD1_MCD_ECAP_WARB_INVALID_CASE_ERROR , 49 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_WARB_INVALID_CASE_ERROR ); REG64_FLD( PU_MCD1_MCD_ECAP_INVALID_CRESP_ERROR , 50 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_INVALID_CRESP_ERROR ); REG64_FLD( PU_MCD1_MCD_ECAP_TTAG_PARITY_ERROR , 51 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_TTAG_PARITY_ERROR ); REG64_FLD( PU_MCD1_MCD_ECAP_RDADDR_ARB_BAD_HAND , 52 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_RDADDR_ARB_BAD_HAND ); REG64_FLD( PU_MCD1_MCD_ECAP_RDWR_UPDATE_ERROR , 53 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_RDWR_UPDATE_ERROR ); REG64_FLD( PU_MCD1_MCD_ECAP_REC_UPDATE_ERROR , 54 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_REC_UPDATE_ERROR ); REG64_FLD( PU_MCD1_MCD_ECAP_REC_ACK_DEAD_ERROR , 55 , SH_UNT_PU_MCD1 , SH_ACS_SCOM , SH_FLD_REC_ACK_DEAD_ERROR ); REG64_FLD( PU_MCD_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( PU_MCD_FIR_ACTION0_REG_ACTION0_LEN , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); REG64_FLD( PU_MCD1_MCD_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( PU_MCD1_MCD_FIR_ACTION0_REG_ACTION0_LEN , 12 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); REG64_FLD( PU_MCD_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); REG64_FLD( PU_MCD_FIR_ACTION1_REG_ACTION1_LEN , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); REG64_FLD( PU_MCD1_MCD_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); REG64_FLD( PU_MCD1_MCD_FIR_ACTION1_REG_ACTION1_LEN , 12 , SH_UNT_PU_MCD1 , SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); REG64_FLD( PU_MCD_FIR_MASK_REG_ARRAY_ECC_UE , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ARRAY_ECC_UE ); REG64_FLD( PU_MCD_FIR_MASK_REG_ARRAY_ECC_CE , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ARRAY_ECC_CE ); REG64_FLD( PU_MCD_FIR_MASK_REG_PB_ADDR_PARITY , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_ADDR_PARITY ); REG64_FLD( PU_MCD_FIR_MASK_REG_SM_OR_CASE , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SM_OR_CASE ); REG64_FLD( PU_MCD_FIR_MASK_REG_CL_PROBE_PB_HANG , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CL_PROBE_PB_HANG ); REG64_FLD( PU_MCD_FIR_MASK_REG_CRESP_ADDR , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CRESP_ADDR ); REG64_FLD( PU_MCD_FIR_MASK_REG_UNSOLICITED_CRESP , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UNSOLICITED_CRESP ); REG64_FLD( PU_MCD_FIR_MASK_REG_TTAG_PARITY , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_TTAG_PARITY ); REG64_FLD( PU_MCD_FIR_MASK_REG_UPDATE_ERR , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UPDATE_ERR ); REG64_FLD( PU_MCD_FIR_MASK_REG_ACK_DEAD_CRESP , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ACK_DEAD_CRESP ); REG64_FLD( PU_MCD_FIR_MASK_REG_SCOM_ERR , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); REG64_FLD( PU_MCD_FIR_MASK_REG_SCOM_ERR_DUP , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_ARRAY_ECC_UE , 0 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_ARRAY_ECC_UE ); REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_ARRAY_ECC_CE , 1 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_ARRAY_ECC_CE ); REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_PB_ADDR_PARITY , 2 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_PB_ADDR_PARITY ); REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_SM_OR_CASE , 3 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_SM_OR_CASE ); REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_CL_PROBE_PB_HANG , 4 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_CL_PROBE_PB_HANG ); REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_CRESP_ADDR , 5 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_CRESP_ADDR ); REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_UNSOLICITED_CRESP , 6 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_UNSOLICITED_CRESP ); REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_TTAG_PARITY , 7 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_TTAG_PARITY ); REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_UPDATE_ERR , 8 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_UPDATE_ERR ); REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_ACK_DEAD_CRESP , 9 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_ACK_DEAD_CRESP ); REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_SCOM_ERR , 10 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); REG64_FLD( PU_MCD1_MCD_FIR_MASK_REG_SCOM_ERR_DUP , 11 , SH_UNT_PU_MCD1 , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); REG64_FLD( PU_MIB_XIICAC_ICACHE_TAG_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR ); REG64_FLD( PU_MIB_XIICAC_ICACHE_TAG_ADDR_LEN , 27 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_TAG_ADDR_LEN ); REG64_FLD( PU_MIB_XIICAC_ICACHE_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_ERR ); REG64_FLD( PU_MIB_XIICAC_XIMEM_MEM_IFETCH_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IFETCH_PENDING ); REG64_FLD( PU_MIB_XIICAC_ICACHE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID ); REG64_FLD( PU_MIB_XIICAC_ICACHE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ICACHE_VALID_LEN ); REG64_FLD( PU_MIB_XIMEM_MEM_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR ); REG64_FLD( PU_MIB_XIMEM_MEM_ADDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ADDR_LEN ); REG64_FLD( PU_MIB_XIMEM_MEM_R_NW , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_R_NW ); REG64_FLD( PU_MIB_XIMEM_MEM_BUSY , 33 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_BUSY ); REG64_FLD( PU_MIB_XIMEM_MEM_IMPRECISE_ERROR_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_IMPRECISE_ERROR_PENDING ); REG64_FLD( PU_MIB_XIMEM_MEM_BYTE_ENABLE , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_BYTE_ENABLE ); REG64_FLD( PU_MIB_XIMEM_MEM_BYTE_ENABLE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_BYTE_ENABLE_LEN ); REG64_FLD( PU_MIB_XIMEM_MEM_LINE_MODE , 43 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_LINE_MODE ); REG64_FLD( PU_MIB_XIMEM_MEM_ERROR , 49 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ERROR ); REG64_FLD( PU_MIB_XIMEM_MEM_ERROR_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_ERROR_LEN ); REG64_FLD( PU_MIB_XIMEM_MEM_IFETCH_PENDING , 62 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_IFETCH_PENDING ); REG64_FLD( PU_MIB_XIMEM_MEM_DATAOP_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MEM_DATAOP_PENDING ); REG64_FLD( PU_MIB_XISGB_STORE_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_STORE_ADDRESS ); REG64_FLD( PU_MIB_XISGB_STORE_ADDRESS_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_STORE_ADDRESS_LEN ); REG64_FLD( PU_MIB_XISGB_XIMEM_MEM_IMPRECISE_ERROR_PENDING , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_XIMEM_MEM_IMPRECISE_ERROR_PENDING ); REG64_FLD( PU_MIB_XISGB_SGB_BYTE_VALID , 36 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_BYTE_VALID ); REG64_FLD( PU_MIB_XISGB_SGB_BYTE_VALID_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_BYTE_VALID_LEN ); REG64_FLD( PU_MIB_XISGB_SGB_FLUSH_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SGB_FLUSH_PENDING ); REG64_FLD( PU_MIB_XISIB_PIB_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PIB_ADDR ); REG64_FLD( PU_MIB_XISIB_PIB_ADDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PIB_ADDR_LEN ); REG64_FLD( PU_MIB_XISIB_PIB_R_NW , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PIB_R_NW ); REG64_FLD( PU_MIB_XISIB_PIB_BUSY , 33 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PIB_BUSY ); REG64_FLD( PU_MIB_XISIB_PIB_IMPRECISE_ERROR_PENDING , 34 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PIB_IMPRECISE_ERROR_PENDING ); REG64_FLD( PU_MIB_XISIB_PIB_RSP_INFO , 49 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PIB_RSP_INFO ); REG64_FLD( PU_MIB_XISIB_PIB_RSP_INFO_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PIB_RSP_INFO_LEN ); REG64_FLD( PU_MIB_XISIB_PIB_IFETCH_PENDING , 62 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PIB_IFETCH_PENDING ); REG64_FLD( PU_MIB_XISIB_PIB_DATAOP_PENDING , 63 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PIB_DATAOP_PENDING ); REG64_FLD( PU_NPU_CTL_MISC_CONFIG_SYNC_WAIT , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_SYNC_WAIT ); REG64_FLD( PU_NPU_CTL_MISC_CONFIG_SYNC_WAIT_LEN , 5 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_SYNC_WAIT_LEN ); REG64_FLD( PU_NPU_CTL_MISC_CONFIG_PERF_ENABLE , 5 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_PERF_ENABLE ); REG64_FLD( PU_NPU_CTL_MISC_CONFIG_PERF_PE_MASK , 6 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_PERF_PE_MASK ); REG64_FLD( PU_NPU_CTL_MISC_CONFIG_PERF_PE_MATCH , 7 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_PERF_PE_MATCH ); REG64_FLD( PU_NPU_CTL_MISC_CONFIG_PERF_PE_MATCH_LEN , 4 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_PERF_PE_MATCH_LEN ); REG64_FLD( PU_NPU_CTL_MISC_CONFIG_RSVD , 11 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_RSVD ); REG64_FLD( PU_NPU_CTL_MISC_CONFIG_RSVD_LEN , 53 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_RSVD_LEN ); REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL0_STALL , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_NDL0_STALL ); REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL0_NOSTALL , 1 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_NDL0_NOSTALL ); REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL1_STALL , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_NDL1_STALL ); REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL1_NOSTALL , 3 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_NDL1_NOSTALL ); REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL2_STALL , 4 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_NDL2_STALL ); REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL2_NOSTALL , 5 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_NDL2_NOSTALL ); REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL3_STALL , 6 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_NDL3_STALL ); REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL3_NOSTALL , 7 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_NDL3_NOSTALL ); REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL4_STALL , 8 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_NDL4_STALL ); REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL4_NOSTALL , 9 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_NDL4_NOSTALL ); REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL5_STALL , 10 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_NDL5_STALL ); REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_NDL5_NOSTALL , 11 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_NDL5_NOSTALL ); REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_RING_ERRP , 12 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_RING_ERRP ); REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_IBAR_ERRP , 13 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_IBAR_ERRP ); REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_SCOMDAA_ERRP , 14 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_SCOMDAA_ERRP ); REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_CNTL_ERRP , 15 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_CNTL_ERRP ); REG64_FLD( PU_NPU_CTL_MISC_HOLD_IDIAL_MM_LOCAL_XSTOP , 16 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_MM_LOCAL_XSTOP ); REG64_FLD( PU_NPU_CTL_MISC_MASK_IDIAL , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU_CTL_MISC_MASK_IDIAL_LEN , 17 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_DISABLE_LN , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DMA_WR_DISABLE_LN ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_DISABLE_GROUP , 1 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DMA_WR_DISABLE_GROUP ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_DISABLE_VG_NOT_SYS , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DMA_WR_DISABLE_VG_NOT_SYS ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_DISABLE_NN_RN , 3 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DMA_WR_DISABLE_NN_RN ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_DISABLE_LN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DMA_RD_DISABLE_LN ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_DISABLE_GROUP , 5 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DMA_RD_DISABLE_GROUP ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_DISABLE_VG_NOT_SYS , 6 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DMA_RD_DISABLE_VG_NOT_SYS ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_DISABLE_NN_RN , 7 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DMA_RD_DISABLE_NN_RN ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_LCO_CRED_MASK , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_LCO_CRED_MASK ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_LCO_CRED_MASK_LEN , 3 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_LCO_CRED_MASK_LEN ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_MIN , 11 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_LCO_TARG_MIN ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_MIN_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_LCO_TARG_MIN_LEN ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_CONFIG , 15 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_LCO_TARG_CONFIG ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_LCO_TARG_CONFIG_LEN , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_LCO_TARG_CONFIG_LEN ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_UNUSED , 27 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_UNUSED_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_NX_FREEZE_MODES , 31 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NX_FREEZE_MODES ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_NX_FREEZE_MODES_LEN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NX_FREEZE_MODES_LEN ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_ADDR_BAR , 33 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_ADDR_BAR ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_SKIP_G , 34 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_SKIP_G ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_RESERVED , 35 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_RESERVED_LEN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_NXCQ_HANG_SM_ON_ARE , 37 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NXCQ_HANG_SM_ON_ARE ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_NXCQ_HANG_SM_ON_LINK_FAIL , 38 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NXCQ_HANG_SM_ON_LINK_FAIL ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_CFG_PUMP , 39 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CFG_PUMP ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_VG_RESET_TIMER_MASK , 40 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DMA_RD_VG_RESET_TIMER_MASK ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_RD_VG_RESET_TIMER_MASK_LEN , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DMA_RD_VG_RESET_TIMER_MASK_LEN ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK , 48 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DMA_WR_VG_RESET_TIMER_MASK ); REG64_FLD( PU_NMMU_MMCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK_LEN , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DMA_WR_VG_RESET_TIMER_MASK_LEN ); REG64_FLD( PEC_STACK2_MMIOBAR0_MASK_REG_PE_MMIO_MASK0 , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK0 ); REG64_FLD( PEC_STACK2_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN , 40 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK0_LEN ); REG64_FLD( PEC_STACK1_MMIOBAR0_MASK_REG_PE_MMIO_MASK0 , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK0 ); REG64_FLD( PEC_STACK1_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN , 40 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK0_LEN ); REG64_FLD( PHB_MMIOBAR0_MASK_REG_PE_MMIO_MASK0 , 0 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK0 ); REG64_FLD( PHB_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN , 40 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK0_LEN ); REG64_FLD( PEC_STACK0_MMIOBAR0_MASK_REG_PE_MMIO_MASK0 , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK0 ); REG64_FLD( PEC_STACK0_MMIOBAR0_MASK_REG_PE_MMIO_MASK0_LEN , 40 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK0_LEN ); REG64_FLD( PEC_STACK2_MMIOBAR0_REG_PE_MMIO_BAR0 , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR0 ); REG64_FLD( PEC_STACK2_MMIOBAR0_REG_PE_MMIO_BAR0_LEN , 40 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR0_LEN ); REG64_FLD( PEC_STACK1_MMIOBAR0_REG_PE_MMIO_BAR0 , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR0 ); REG64_FLD( PEC_STACK1_MMIOBAR0_REG_PE_MMIO_BAR0_LEN , 40 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR0_LEN ); REG64_FLD( PHB_MMIOBAR0_REG_PE_MMIO_BAR0 , 0 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR0 ); REG64_FLD( PHB_MMIOBAR0_REG_PE_MMIO_BAR0_LEN , 40 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR0_LEN ); REG64_FLD( PEC_STACK0_MMIOBAR0_REG_PE_MMIO_BAR0 , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR0 ); REG64_FLD( PEC_STACK0_MMIOBAR0_REG_PE_MMIO_BAR0_LEN , 40 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR0_LEN ); REG64_FLD( PEC_STACK2_MMIOBAR1_MASK_REG_PE_MMIO_MASK1 , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK1 ); REG64_FLD( PEC_STACK2_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN , 40 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK1_LEN ); REG64_FLD( PEC_STACK1_MMIOBAR1_MASK_REG_PE_MMIO_MASK1 , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK1 ); REG64_FLD( PEC_STACK1_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN , 40 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK1_LEN ); REG64_FLD( PHB_MMIOBAR1_MASK_REG_PE_MMIO_MASK1 , 0 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK1 ); REG64_FLD( PHB_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN , 40 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK1_LEN ); REG64_FLD( PEC_STACK0_MMIOBAR1_MASK_REG_PE_MMIO_MASK1 , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK1 ); REG64_FLD( PEC_STACK0_MMIOBAR1_MASK_REG_PE_MMIO_MASK1_LEN , 40 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , SH_FLD_PE_MMIO_MASK1_LEN ); REG64_FLD( PEC_STACK2_MMIOBAR1_REG_PE_MMIO_BAR1 , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR1 ); REG64_FLD( PEC_STACK2_MMIOBAR1_REG_PE_MMIO_BAR1_LEN , 40 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR1_LEN ); REG64_FLD( PEC_STACK1_MMIOBAR1_REG_PE_MMIO_BAR1 , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR1 ); REG64_FLD( PEC_STACK1_MMIOBAR1_REG_PE_MMIO_BAR1_LEN , 40 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR1_LEN ); REG64_FLD( PHB_MMIOBAR1_REG_PE_MMIO_BAR1 , 0 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR1 ); REG64_FLD( PHB_MMIOBAR1_REG_PE_MMIO_BAR1_LEN , 40 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR1_LEN ); REG64_FLD( PEC_STACK0_MMIOBAR1_REG_PE_MMIO_BAR1 , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR1 ); REG64_FLD( PEC_STACK0_MMIOBAR1_REG_PE_MMIO_BAR1_LEN , 40 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , SH_FLD_PE_MMIO_BAR1_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_BKINV_INTERLOCK_DIS , 1 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_BKINV_INTERLOCK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_EN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DYN_ST_MODE_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_HANGP_EN , 3 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DYN_ST_MODE_HANGP_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_LFSR_DIS , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_LFSR_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_LFSR_DIS , 9 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_LFSR_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_INV_AMORT_DIS , 10 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_INV_AMORT_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_DIN_ECC_CHK_DIS , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_DIN_ECC_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_XLAT_ECC_CHK_DIS , 13 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_XLAT_ECC_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_XLAT_PROT_ERR_CHK_DIS , 14 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_XLAT_PROT_ERR_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_XLAT_TIMEOUT_CHK_DIS , 15 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_XLAT_TIMEOUT_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_CO_PROT_ERR_CHK_DIS , 16 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CO_PROT_ERR_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_CO_TIMEOUT_CHK_DIS , 17 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CO_TIMEOUT_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_CKIN_PROT_ERR_CHK_DIS , 18 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CKIN_PROT_ERR_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_CKIN_TIMEOUT_CHK_DIS , 19 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CKIN_TIMEOUT_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_INV_PROT_ERR_CHK_DIS , 20 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_INV_PROT_ERR_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_INV_TIMEOUT_CHK_DIS , 21 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_INV_TIMEOUT_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_TW_PROT_ERR_CHK_DIS , 22 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_PROT_ERR_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_TW_TIMEOUT_CHK_DIS , 23 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_TIMEOUT_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_SNP_PROT_ERR_CHK_DIS , 24 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_SNP_PROT_ERR_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_SNP_TIMEOUT_CHK_DIS , 25 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_SNP_TIMEOUT_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_FBC_CMD_PROT_ERR_CHK_DIS , 26 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_CMD_PROT_ERR_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_THRESHOLD , 28 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DYN_ST_MODE_THRESHOLD ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_DYN_ST_MODE_THRESHOLD_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DYN_ST_MODE_THRESHOLD_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_HANG_PLS_MULT , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HANG_PLS_MULT ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_HANG_PLS_MULT_LEN , 16 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HANG_PLS_MULT_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_NCU_SNP_TLBIE_INC_RATE , 48 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NCU_SNP_TLBIE_INC_RATE ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_NCU_SNP_TLBIE_INC_RATE_LEN , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NCU_SNP_TLBIE_INC_RATE_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_NCU_SNP_TLBIE_DEC_RATE , 56 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NCU_SNP_TLBIE_DEC_RATE ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_MISC_NCU_SNP_TLBIE_DEC_RATE_LEN , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NCU_SNP_TLBIE_DEC_RATE_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_MBR_DIS , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_MBR_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_MBR_DIS_LEN , 16 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_MBR_DIS_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_SNGL_THD_EN , 16 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_SNGL_THD_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_CAC_ALLOC_DIS , 17 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CAC_ALLOC_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DMAP_MODE_EN , 18 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DMAP_MODE_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_ALT_SEGSZ_DIS , 19 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_ALT_SEGSZ_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DIR_PERR_CHK_DIS , 20 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DIR_PERR_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_CAC_PERR_CHK_DIS , 21 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CAC_PERR_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_LRU_PERR_CHK_DIS , 22 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_LRU_PERR_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS0_STG0_SEL , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DBG_BUS0_STG0_SEL ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS0_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DBG_BUS0_STG0_SEL_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS1_STG0_SEL , 36 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DBG_BUS1_STG0_SEL ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SLB_DBG_BUS1_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DBG_BUS1_STG0_SEL_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TWSM_DIS , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TWSM_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TWSM_DIS_LEN , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TWSM_DIS_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_CKINSM_DIS , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CKINSM_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_CKINSM_DIS_LEN , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CKINSM_DIS_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_INV_SINGLE_THREAD_EN , 20 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_INV_SINGLE_THREAD_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_CXT_CAC_DIS , 21 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_CXT_CAC_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_MPSS_DIS , 31 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_MPSS_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_CNT_THRESH , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NCU_SNP_TLBIE_CNT_THRESH ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_CNT_THRESH_LEN , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NCU_SNP_TLBIE_CNT_THRESH_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_ATT_HPT_SAO_FOLD_DIS , 40 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_ATT_HPT_SAO_FOLD_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_ATT_RDX_SAO_FOLD_DIS , 41 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_ATT_RDX_SAO_FOLD_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_ATT_RDX_NIO_FOLD_DIS , 42 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_ATT_RDX_NIO_FOLD_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_ATT_RDX_TIO_FOLD_DIS , 43 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_ATT_RDX_TIO_FOLD_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_EN , 44 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_LCO_RDX_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_P_DIS , 45 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_LCO_RDX_P_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_C_DIS , 46 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_LCO_RDX_C_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_PWC_L2_DIS , 47 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_LCO_RDX_PWC_L2_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_PWC_L3_DIS , 48 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_LCO_RDX_PWC_L3_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_PWC_L4_DIS , 49 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_LCO_RDX_PWC_L4_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_LCO_RDX_PDE_EN , 50 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_LCO_RDX_PDE_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_PWC_DIS , 52 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_RDX_PWC_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_INT_PWC_DIS , 53 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_RDX_INT_PWC_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_INT_TLB_DIS , 54 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_RDX_INT_TLB_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_PWC_SPLIT_EN , 55 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_RDX_PWC_SPLIT_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_RDX_PWC_VA_HASH , 56 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_RDX_PWC_VA_HASH ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_TW_PTE_UPD_INTR_EN , 58 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_PTE_UPD_INTR_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_NCU_SNP_TLBIE_PACING_CNT_EN , 59 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NCU_SNP_TLBIE_PACING_CNT_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_DYN_ST_FREQ_MULT , 60 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DYN_ST_FREQ_MULT ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_SM_DYN_ST_FREQ_MULT_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DYN_ST_FREQ_MULT_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_MBR_DIS , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_MBR_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_MBR_DIS_LEN , 16 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_MBR_DIS_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_SNGL_THD_EN , 16 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_SNGL_THD_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_CAC_ALLOC_DIS , 17 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CAC_ALLOC_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DMAP_MODE_EN , 18 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DMAP_MODE_EN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_MPSS_DIS , 19 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_MPSS_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_LPID_DIS , 20 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HASH_LPID_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_HASH_PID_DIS , 21 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HASH_PID_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DIR_PERR_CHK_DIS , 22 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DIR_PERR_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_CAC_PERR_CHK_DIS , 23 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CAC_PERR_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_LRU_PERR_CHK_DIS , 24 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_LRU_PERR_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_MULTIHIT_CHK_DIS , 25 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_MULTIHIT_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_EA_RANGE_CHK_DIS , 26 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_EA_RANGE_CHK_DIS ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS0_STG0_SEL , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DBG_BUS0_STG0_SEL ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS0_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DBG_BUS0_STG0_SEL_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS1_STG0_SEL , 36 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DBG_BUS1_STG0_SEL ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_DBG_BUS1_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DBG_BUS1_STG0_SEL_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_GUEST_PREF_PGSZ , 40 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_GUEST_PREF_PGSZ ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_GUEST_PREF_PGSZ_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_GUEST_PREF_PGSZ_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_HOST_PREF_PGSZ , 44 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HOST_PREF_PGSZ ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_CTL_TLB_HOST_PREF_PGSZ_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HOST_PREF_PGSZ_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG0_HRMOR , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HRMOR ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG0_HRMOR_LEN , 64 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HRMOR_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG1_PTCR , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_PTCR ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG1_PTCR_LEN , 64 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_PTCR_LEN ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG2_SEIDBAR , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_SEIDBAR ); REG64_FLD( PU_NMMU_MM_CFG_NMMU_XLAT_CTL_REG2_SEIDBAR_LEN , 64 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_SEIDBAR_LEN ); REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_1_CNT_VAL , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_WR_TIER_1_CNT_VAL ); REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_1_CNT_VAL_LEN , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_WR_TIER_1_CNT_VAL_LEN ); REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_1_DIV_VAL , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_WR_TIER_1_DIV_VAL ); REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_1_DIV_VAL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_WR_TIER_1_DIV_VAL_LEN ); REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_2_CNT_VAL , 16 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_WR_TIER_2_CNT_VAL ); REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_2_CNT_VAL_LEN , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_WR_TIER_2_CNT_VAL_LEN ); REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_2_DIV_VAL , 28 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_WR_TIER_2_DIV_VAL ); REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_WR_TIER_2_DIV_VAL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_WR_TIER_2_DIV_VAL_LEN ); REG64_FLD( PU_NMMU_MM_EPSILON_COUNTER_VALUE_DISABLE , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_DISABLE ); REG64_FLD( PU_NMMU_MM_FIR1_ACTION0_REG_ACTION0 , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( PU_NMMU_MM_FIR1_ACTION0_REG_ACTION0_LEN , 48 , SH_UNT_PU_NMMU , SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); REG64_FLD( PU_NMMU_MM_FIR1_ACTION1_REG_ACTION1 , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); REG64_FLD( PU_NMMU_MM_FIR1_ACTION1_REG_ACTION1_LEN , 48 , SH_UNT_PU_NMMU , SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); REG64_FLD( PU_NMMU_MM_FIR1_MASK_REG_MASK , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_MASK ); REG64_FLD( PU_NMMU_MM_FIR1_MASK_REG_MASK_LEN , 48 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_MASK_LEN ); REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_XLAT_ARY_ECC_CE_DET , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_FBC_XLAT_ARY_ECC_CE_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_XLAT_ARY_ECC_UE_DET , 1 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_FBC_XLAT_ARY_ECC_UE_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_XLAT_ARY_ECC_SUE_DET , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_FBC_XLAT_ARY_ECC_SUE_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_CQRD_ARY_ECC_CE_DET , 3 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_FBC_CQRD_ARY_ECC_CE_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_CQRD_ARY_ECC_UE_DET , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_FBC_CQRD_ARY_ECC_UE_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_CQRD_ARY_ECC_SUE_DET , 5 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_FBC_CQRD_ARY_ECC_SUE_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_XLAT_PROT_ERR_DET , 6 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_FBC_XLAT_PROT_ERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_XLAT_TIMEOUT_DET , 7 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_FBC_XLAT_TIMEOUT_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_SLB_DIR_PERR_DET , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_SLB_DIR_PERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_SLB_CAC_PERR_DET , 9 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_SLB_CAC_PERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_SLB_LRU_PERR_DET , 10 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_SLB_LRU_PERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_SLB_MULTIHIT_DET , 11 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_SLB_MULTIHIT_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TLB_DIR_PERR_DET , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TLB_DIR_PERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TLB_CAC_PERR_DET , 13 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TLB_CAC_PERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TLB_LRU_PERR_DET , 14 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TLB_LRU_PERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TLB_MULTIHIT_DET , 15 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TLB_MULTIHIT_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_SEG_FAULT_DET , 16 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TW_SEG_FAULT_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_PG_FAULT_NOPTE_DET , 17 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TW_PG_FAULT_NOPTE_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_PG_FAULT_BPCHK_DET , 18 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TW_PG_FAULT_BPCHK_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_PG_FAULT_VPCHK_DET , 19 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TW_PG_FAULT_VPCHK_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_PG_FAULT_SEID_DET , 20 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TW_PG_FAULT_SEID_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_ADD_ERR_CR_RD_DET , 21 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TW_ADD_ERR_CR_RD_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_PTE_UPD_FAIL_DET , 22 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TW_PTE_UPD_FAIL_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_ADD_ERR_CR_WR_DET , 23 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TW_ADD_ERR_CR_WR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_RDX_CFG_GUEST_DET , 24 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TW_RDX_CFG_GUEST_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_RDX_CFG_HOST_DET , 25 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TW_RDX_CFG_HOST_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_INVALID_WIMG_DET , 26 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TW_INVALID_WIMG_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_INV_RDX_QUAD_DET , 27 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TW_INV_RDX_QUAD_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_FOREIGN_ADDR_DET , 28 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TW_FOREIGN_ADDR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_PREFETCH_ABT_DET , 29 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TW_PREFETCH_ABT_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_CXT_CAC_PERR_DET , 30 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TW_CXT_CAC_PERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_RDX_PWC_PERR_DET , 31 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TW_RDX_PWC_PERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_SM_CTL_ERR_DET , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TW_SM_CTL_ERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_CO_SM_CTL_ERR_DET , 33 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_CO_SM_CTL_ERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_CI_SM_CTL_ERR_DET , 34 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_CI_SM_CTL_ERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_INV_SM_CTL_ERR_DET , 35 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_INV_SM_CTL_ERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_TW_TIMEOUT_ERR_DET , 36 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_TW_TIMEOUT_ERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_CO_TIMEOUT_ERR_DET , 37 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_CO_TIMEOUT_ERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_CI_TIMEOUT_ERR_DET , 38 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_CI_TIMEOUT_ERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_INV_TIMEOUT_ERR_DET , 39 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_INV_TIMEOUT_ERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_NX0_LXSTOP_ERR_DET , 40 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_NX0_LXSTOP_ERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_CP0_LXSTOP_ERR_DET , 41 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_CP0_LXSTOP_ERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_CP1_LXSTOP_ERR_DET , 42 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_CP1_LXSTOP_ERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_NPU_LXSTOP_ERR_DET , 43 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_NPU_LXSTOP_ERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_FBC_LXSTOP_ERR_DET , 44 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_FBC_LXSTOP_ERR_DET ); REG64_FLD( PU_NMMU_MM_FIR1_REG_SPARE , 45 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_SPARE ); REG64_FLD( PU_NMMU_MM_FIR1_REG_SCOM_PE_FIR , 46 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PE_FIR ); REG64_FLD( PU_NMMU_MM_FIR1_REG_SCOM_PE_DUP_FIR , 47 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PE_DUP_FIR ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_EN , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_EN ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_PRV_BUS0_STG2_SEL , 1 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_PRV_BUS0_STG2_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_PRV_BUS1_STG2_SEL , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_PRV_BUS1_STG2_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG2_SEL , 3 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_BUS0_STG2_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS1_STG2_SEL , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_BUS1_STG2_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS0_STG2_SEL , 5 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_MSC_BUS0_STG2_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS1_STG2_SEL , 6 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_MSC_BUS1_STG2_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_SLB_BUS0_STG2_SEL , 7 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_SLB_BUS0_STG2_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_SLB_BUS1_STG2_SEL , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_SLB_BUS1_STG2_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS0_STG2_SEL , 9 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_BUS0_STG2_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS1_STG2_SEL , 10 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_BUS1_STG2_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS0_STG2_SEL , 11 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_RDX_BUS0_STG2_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS1_STG2_SEL , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_RDX_BUS1_STG2_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS0_STG2_SEL , 13 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TLB_BUS0_STG2_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS1_STG2_SEL , 14 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TLB_BUS1_STG2_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG1_SEL , 15 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_BUS0_STG1_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS1_STG1_SEL , 16 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_BUS1_STG1_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS0_STG1_SEL , 17 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_MSC_BUS0_STG1_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS1_STG1_SEL , 18 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_MSC_BUS1_STG1_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_SLB_BUS0_STG1_SEL , 19 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_SLB_BUS0_STG1_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_SLB_BUS1_STG1_SEL , 20 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_SLB_BUS1_STG1_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS0_STG1_SEL , 21 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_BUS0_STG1_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS1_STG1_SEL , 22 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_BUS1_STG1_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS0_STG1_SEL , 23 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_RDX_BUS0_STG1_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS1_STG1_SEL , 24 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_RDX_BUS1_STG1_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS0_STG1_SEL , 25 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TLB_BUS0_STG1_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TLB_BUS1_STG1_SEL , 26 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TLB_BUS1_STG1_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG0_SEL , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_BUS0_STG0_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS0_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_BUS0_STG0_SEL_LEN ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS1_STG0_SEL , 36 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_BUS1_STG0_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_FBC_BUS1_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_FBC_BUS1_STG0_SEL_LEN ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS0_STG0_SEL , 40 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_MSC_BUS0_STG0_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS0_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_MSC_BUS0_STG0_SEL_LEN ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS1_STG0_SEL , 44 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_MSC_BUS1_STG0_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_MSC_BUS1_STG0_SEL_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_MSC_BUS1_STG0_SEL_LEN ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS0_STG0_SEL , 48 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_BUS0_STG0_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS0_STG0_SEL_LEN , 6 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_BUS0_STG0_SEL_LEN ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS1_STG0_SEL , 54 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_BUS1_STG0_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_TW_BUS1_STG0_SEL_LEN , 6 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_TW_BUS1_STG0_SEL_LEN ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS0_STG0_SEL , 60 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_RDX_BUS0_STG0_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS0_STG0_SEL_LEN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_RDX_BUS0_STG0_SEL_LEN ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS1_STG0_SEL , 62 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_RDX_BUS1_STG0_SEL ); REG64_FLD( PU_NMMU_MM_NMMU_DBG_MODE_RDX_BUS1_STG0_SEL_LEN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_RDX_BUS1_STG0_SEL_LEN ); REG64_FLD( PU_NMMU_MM_NMMU_ERR_INJ_INJ , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_INJ ); REG64_FLD( PU_NMMU_MM_NMMU_ERR_INJ_INJ_LEN , 64 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_INJ_LEN ); REG64_FLD( PU_NMMU_MM_NMMU_ERR_LOG_LOG , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_LOG ); REG64_FLD( PU_NMMU_MM_NMMU_ERR_LOG_LOG_LEN , 64 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_LOG_LEN ); REG64_FLD( PEC_MODE_REG_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN0 ); REG64_FLD( PEC_MODE_REG_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN1 ); REG64_FLD( PEC_MODE_REG_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN2 ); REG64_FLD( PEC_MODE_REG_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN3 ); REG64_FLD( PEC_MODE_REG_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN4 ); REG64_FLD( PEC_MODE_REG_IN5 , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN5 ); REG64_FLD( PEC_MODE_REG_IN6 , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN6 ); REG64_FLD( PEC_MODE_REG_IN7 , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN7 ); REG64_FLD( PEC_MODE_REG_IN8 , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN8 ); REG64_FLD( PEC_MODE_REG_IN9 , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN9 ); REG64_FLD( PEC_MODE_REG_IN10 , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN10 ); REG64_FLD( PEC_MODE_REG_IN11 , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN11 ); REG64_FLD( PEC_MODE_REG_IN , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( PEC_MODE_REG_IN_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( PU_MODE_REGISTER_DCOMP_ENABLE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DCOMP_ENABLE ); REG64_FLD( PU_MODE_REGISTER_ECC_ENABLE , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_ENABLE ); REG64_FLD( PU_MODE_REGISTER_PROGRAM_ENABLE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PROGRAM_ENABLE ); REG64_FLD( PU_MODE_REGISTER_ECC_CHK_DISABLE , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_CHK_DISABLE ); REG64_FLD( PU_MODE_REGISTER_UNUSED_4_15 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_4_15 ); REG64_FLD( PU_MODE_REGISTER_UNUSED_4_15_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_4_15_LEN ); REG64_FLD( PU_MODE_REGISTER_CLK_RATE_SEL , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_CLK_RATE_SEL ); REG64_FLD( PU_MODE_REGISTER_CLK_RATE_SEL_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_CLK_RATE_SEL_LEN ); REG64_FLD( PU_MODE_REGISTER_B_BIT_RATE_DIVISOR_0 , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_BIT_RATE_DIVISOR_0 ); REG64_FLD( PU_MODE_REGISTER_B_BIT_RATE_DIVISOR_0_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_BIT_RATE_DIVISOR_0_LEN ); REG64_FLD( PU_MODE_REGISTER_B_PORT_NUMBER_0 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_PORT_NUMBER_0 ); REG64_FLD( PU_MODE_REGISTER_B_PORT_NUMBER_0_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PORT_NUMBER_0_LEN ); REG64_FLD( PU_MODE_REGISTER_B_CHKSW_CMDQUEUEING_0 , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHKSW_CMDQUEUEING_0 ); REG64_FLD( PU_MODE_REGISTER_B_CHKSW_I2C_BUSY_0 , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHKSW_I2C_BUSY_0 ); REG64_FLD( PU_MODE_REGISTER_B_FGAT_0 , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_FGAT_0 ); REG64_FLD( PU_MODE_REGISTER_B_DIAG_0 , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_DIAG_0 ); REG64_FLD( PU_MODE_REGISTER_B_PACING_ALLOW_0 , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_PACING_ALLOW_0 ); REG64_FLD( PU_MODE_REGISTER_B_WRAP_0 , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_WRAP_0 ); REG64_FLD( PU_MODE_REGISTER_B_PEEK_DATA1_0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0 ); REG64_FLD( PU_MODE_REGISTER_B_PEEK_DATA1_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0_LEN ); REG64_FLD( PU_MODE_REGISTER_B_LBUS_PARITY_ERR1_0 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_0 ); REG64_FLD( PU_MODE_REGISTER_C_BIT_RATE_DIVISOR_1 , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_BIT_RATE_DIVISOR_1 ); REG64_FLD( PU_MODE_REGISTER_C_BIT_RATE_DIVISOR_1_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_BIT_RATE_DIVISOR_1_LEN ); REG64_FLD( PU_MODE_REGISTER_C_PORT_NUMBER_1 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_PORT_NUMBER_1 ); REG64_FLD( PU_MODE_REGISTER_C_PORT_NUMBER_1_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PORT_NUMBER_1_LEN ); REG64_FLD( PU_MODE_REGISTER_C_CHKSW_CMDQUEUEING_1 , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHKSW_CMDQUEUEING_1 ); REG64_FLD( PU_MODE_REGISTER_C_CHKSW_I2C_BUSY_1 , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHKSW_I2C_BUSY_1 ); REG64_FLD( PU_MODE_REGISTER_C_FGAT_1 , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_FGAT_1 ); REG64_FLD( PU_MODE_REGISTER_C_DIAG_1 , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_DIAG_1 ); REG64_FLD( PU_MODE_REGISTER_C_PACING_ALLOW_1 , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_PACING_ALLOW_1 ); REG64_FLD( PU_MODE_REGISTER_C_WRAP_1 , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_WRAP_1 ); REG64_FLD( PU_MODE_REGISTER_C_PEEK_DATA1_1 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1 ); REG64_FLD( PU_MODE_REGISTER_C_PEEK_DATA1_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1_LEN ); REG64_FLD( PU_MODE_REGISTER_C_LBUS_PARITY_ERR1_1 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_1 ); REG64_FLD( PU_MODE_REGISTER_D_BIT_RATE_DIVISOR_2 , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_BIT_RATE_DIVISOR_2 ); REG64_FLD( PU_MODE_REGISTER_D_BIT_RATE_DIVISOR_2_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_BIT_RATE_DIVISOR_2_LEN ); REG64_FLD( PU_MODE_REGISTER_D_PORT_NUMBER_2 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_PORT_NUMBER_2 ); REG64_FLD( PU_MODE_REGISTER_D_PORT_NUMBER_2_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PORT_NUMBER_2_LEN ); REG64_FLD( PU_MODE_REGISTER_D_CHKSW_CMDQUEUEING_2 , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHKSW_CMDQUEUEING_2 ); REG64_FLD( PU_MODE_REGISTER_D_CHKSW_I2C_BUSY_2 , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHKSW_I2C_BUSY_2 ); REG64_FLD( PU_MODE_REGISTER_D_FGAT_2 , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_FGAT_2 ); REG64_FLD( PU_MODE_REGISTER_D_DIAG_2 , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_DIAG_2 ); REG64_FLD( PU_MODE_REGISTER_D_PACING_ALLOW_2 , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_PACING_ALLOW_2 ); REG64_FLD( PU_MODE_REGISTER_D_WRAP_2 , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_WRAP_2 ); REG64_FLD( PU_MODE_REGISTER_D_PEEK_DATA1_2 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2 ); REG64_FLD( PU_MODE_REGISTER_D_PEEK_DATA1_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2_LEN ); REG64_FLD( PU_MODE_REGISTER_D_LBUS_PARITY_ERR1_2 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_2 ); REG64_FLD( PU_MODE_REGISTER_E_BIT_RATE_DIVISOR_3 , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_BIT_RATE_DIVISOR_3 ); REG64_FLD( PU_MODE_REGISTER_E_BIT_RATE_DIVISOR_3_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_BIT_RATE_DIVISOR_3_LEN ); REG64_FLD( PU_MODE_REGISTER_E_PORT_NUMBER_3 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_PORT_NUMBER_3 ); REG64_FLD( PU_MODE_REGISTER_E_PORT_NUMBER_3_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PORT_NUMBER_3_LEN ); REG64_FLD( PU_MODE_REGISTER_E_CHKSW_CMDQUEUEING_3 , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHKSW_CMDQUEUEING_3 ); REG64_FLD( PU_MODE_REGISTER_E_CHKSW_I2C_BUSY_3 , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHKSW_I2C_BUSY_3 ); REG64_FLD( PU_MODE_REGISTER_E_FGAT_3 , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_FGAT_3 ); REG64_FLD( PU_MODE_REGISTER_E_DIAG_3 , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_DIAG_3 ); REG64_FLD( PU_MODE_REGISTER_E_PACING_ALLOW_3 , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_PACING_ALLOW_3 ); REG64_FLD( PU_MODE_REGISTER_E_WRAP_3 , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_WRAP_3 ); REG64_FLD( PU_MODE_REGISTER_E_PEEK_DATA1_3 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3 ); REG64_FLD( PU_MODE_REGISTER_E_PEEK_DATA1_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3_LEN ); REG64_FLD( PU_MODE_REGISTER_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); REG64_FLD( PEC_MULTICAST_GROUP_1_MULTICAST1 , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MULTICAST1 ); REG64_FLD( PEC_MULTICAST_GROUP_1_MULTICAST1_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MULTICAST1_LEN ); REG64_FLD( PEC_MULTICAST_GROUP_2_MULTICAST2 , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MULTICAST2 ); REG64_FLD( PEC_MULTICAST_GROUP_2_MULTICAST2_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MULTICAST2_LEN ); REG64_FLD( PEC_MULTICAST_GROUP_3_MULTICAST3 , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MULTICAST3 ); REG64_FLD( PEC_MULTICAST_GROUP_3_MULTICAST3_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MULTICAST3_LEN ); REG64_FLD( PEC_MULTICAST_GROUP_4_MULTICAST4 , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MULTICAST4 ); REG64_FLD( PEC_MULTICAST_GROUP_4_MULTICAST4_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MULTICAST4_LEN ); REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU0_SM0_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM0_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU0_SM0_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU0_SM0_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU1_SM2_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM2_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU1_SM2_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU1_SM2_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU2_SM3_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM3_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU2_SM3_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU2_SM3_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU1_SM3_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM3_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU1_SM3_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU1_SM3_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU0_SM3_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM3_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU0_SM3_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU0_SM3_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU1_SM1_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM1_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU1_SM1_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU1_SM1_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU2_SM2_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM2_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU2_SM2_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU2_SM2_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU2_SM1_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM1_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU2_SM1_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU2_SM1_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU0_SM2_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM2_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU0_SM2_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU0_SM2_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU2_SM0_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM0_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU2_SM0_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU2_SM0_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU0_SM1_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM1_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU0_SM1_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU0_SM1_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU1_SM0_NDT0_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM0_NDT0_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU1_SM0_NDT0_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU1_SM0_NDT0_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU0_SM0_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM0_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU0_SM0_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU0_SM0_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU1_SM2_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM2_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU1_SM2_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU1_SM2_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU2_SM3_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM3_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU2_SM3_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU2_SM3_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU1_SM3_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM3_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU1_SM3_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU1_SM3_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU0_SM3_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM3_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU0_SM3_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU0_SM3_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU1_SM1_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM1_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU1_SM1_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU1_SM1_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU2_SM2_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM2_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU2_SM2_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU2_SM2_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU2_SM1_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM1_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU2_SM1_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU2_SM1_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU0_SM2_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM2_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU0_SM2_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU0_SM2_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU2_SM0_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM0_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU2_SM0_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU2_SM0_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU0_SM1_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM1_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU0_SM1_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU0_SM1_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU1_SM0_NDT1_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM0_NDT1_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU1_SM0_NDT1_BAR_CONFIG_ADDR_LEN , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU1_SM0_NDT1_BAR_RESERVED2 , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PEC_STACK0_NET_CTRL0_CHIPLET_ENABLE , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_CHIPLET_ENABLE ); REG64_FLD( PEC_STACK0_NET_CTRL0_PCB_EP_RESET , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_PCB_EP_RESET ); REG64_FLD( PEC_STACK0_NET_CTRL0_CLK_ASYNC_RESET , 2 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_CLK_ASYNC_RESET ); REG64_FLD( PEC_STACK0_NET_CTRL0_PLL_TEST_EN , 3 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_PLL_TEST_EN ); REG64_FLD( PEC_STACK0_NET_CTRL0_PLL_RESET , 4 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_PLL_RESET ); REG64_FLD( PEC_STACK0_NET_CTRL0_PLL_BYPASS , 5 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_PLL_BYPASS ); REG64_FLD( PEC_STACK0_NET_CTRL0_VITAL_SCAN , 6 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_VITAL_SCAN ); REG64_FLD( PEC_STACK0_NET_CTRL0_VITAL_SCAN_IN , 7 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_VITAL_SCAN_IN ); REG64_FLD( PEC_STACK0_NET_CTRL0_VITAL_PHASE , 8 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_VITAL_PHASE ); REG64_FLD( PEC_STACK0_NET_CTRL0_FLUSH_ALIGN_OVR , 9 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_FLUSH_ALIGN_OVR ); REG64_FLD( PEC_STACK0_NET_CTRL0_VITAL_AL , 10 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_VITAL_AL ); REG64_FLD( PEC_STACK0_NET_CTRL0_ACT_DIS , 11 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_ACT_DIS ); REG64_FLD( PEC_STACK0_NET_CTRL0_MPW1 , 12 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_MPW1 ); REG64_FLD( PEC_STACK0_NET_CTRL0_MPW2 , 13 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_MPW2 ); REG64_FLD( PEC_STACK0_NET_CTRL0_MPW3 , 14 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_MPW3 ); REG64_FLD( PEC_STACK0_NET_CTRL0_DELAY_LCLKR , 15 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_DELAY_LCLKR ); REG64_FLD( PEC_STACK0_NET_CTRL0_VITAL_THOLD , 16 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_VITAL_THOLD ); REG64_FLD( PEC_STACK0_NET_CTRL0_FLUSH_SCAN_N , 17 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_FLUSH_SCAN_N ); REG64_FLD( PEC_STACK0_NET_CTRL0_FENCE_EN , 18 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_FENCE_EN ); REG64_FLD( PEC_STACK0_NET_CTRL0_CPLT_RCTRL , 19 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_CPLT_RCTRL ); REG64_FLD( PEC_STACK0_NET_CTRL0_CPLT_DCTRL , 20 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_CPLT_DCTRL ); REG64_FLD( PEC_STACK0_NET_CTRL0_L3_EDRAM_ENABLE0 , 23 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_L3_EDRAM_ENABLE0 ); REG64_FLD( PEC_STACK0_NET_CTRL0_L3_EDRAM_ENABLE1 , 24 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_L3_EDRAM_ENABLE1 ); REG64_FLD( PEC_STACK0_NET_CTRL0_TP_FENCE_PCB , 25 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_TP_FENCE_PCB ); REG64_FLD( PEC_STACK0_NET_CTRL0_LVLTRANS_FENCE , 26 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_LVLTRANS_FENCE ); REG64_FLD( PEC_STACK0_NET_CTRL0_ARRAY_WRITE_ASSIST_EN , 27 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_ARRAY_WRITE_ASSIST_EN ); REG64_FLD( PEC_STACK0_NET_CTRL0_HTB_INTEST , 28 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_HTB_INTEST ); REG64_FLD( PEC_STACK0_NET_CTRL0_HTB_EXTEST , 29 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_HTB_EXTEST ); REG64_FLD( PEC_STACK0_NET_CTRL0_PLLFORCE_OUT_EN , 31 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_PLLFORCE_OUT_EN ); REG64_FLD( PEC_STACK0_NET_CTRL1_PLL_CLKIN_SEL , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_PLL_CLKIN_SEL ); REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_DCC_BYPASS_EN , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_CLK_DCC_BYPASS_EN ); REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_PDLY_BYPASS_EN , 2 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_CLK_PDLY_BYPASS_EN ); REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_DIV_BYPASS_EN , 3 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_CLK_DIV_BYPASS_EN ); REG64_FLD( PEC_STACK0_NET_CTRL1_REFCLK_CLKMUX0_SEL , 4 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_REFCLK_CLKMUX0_SEL ); REG64_FLD( PEC_STACK0_NET_CTRL1_REFCLK_CLKMUX1_SEL , 5 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_REFCLK_CLKMUX1_SEL ); REG64_FLD( PEC_STACK0_NET_CTRL1_PLL_BNDY_BYPASS_EN , 6 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_PLL_BNDY_BYPASS_EN ); REG64_FLD( PEC_STACK0_NET_CTRL1_DPLL_TEST_SEL , 8 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_DPLL_TEST_SEL ); REG64_FLD( PEC_STACK0_NET_CTRL1_DPLL_TEST_SEL_LEN , 8 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_DPLL_TEST_SEL_LEN ); REG64_FLD( PEC_STACK0_NET_CTRL1_SB_STRENGTH , 16 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_SB_STRENGTH ); REG64_FLD( PEC_STACK0_NET_CTRL1_SB_STRENGTH_LEN , 4 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_SB_STRENGTH_LEN ); REG64_FLD( PEC_STACK0_NET_CTRL1_ASYNC_TYPE , 20 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_ASYNC_TYPE ); REG64_FLD( PEC_STACK0_NET_CTRL1_ASYNC_OBS , 21 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_ASYNC_OBS ); REG64_FLD( PEC_STACK0_NET_CTRL1_CPM_CAL_SET , 22 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_CPM_CAL_SET ); REG64_FLD( PEC_STACK0_NET_CTRL1_SENSEADJ_RESET0 , 23 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_SENSEADJ_RESET0 ); REG64_FLD( PEC_STACK0_NET_CTRL1_SENSEADJ_RESET1 , 24 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_SENSEADJ_RESET1 ); REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_PULSE_EN , 25 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_EN ); REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_PULSE_MODE , 26 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_MODE ); REG64_FLD( PEC_STACK0_NET_CTRL1_CLK_PULSE_MODE_LEN , 2 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_WOR, SH_FLD_CLK_PULSE_MODE_LEN ); REG64_FLD( PEC_STACK2_NFIRACTION0_REG_NFIRACTION0 , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , SH_FLD_NFIRACTION0 ); REG64_FLD( PEC_STACK2_NFIRACTION0_REG_NFIRACTION0_LEN , 30 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , SH_FLD_NFIRACTION0_LEN ); REG64_FLD( PEC_STACK1_NFIRACTION0_REG_NFIRACTION0 , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , SH_FLD_NFIRACTION0 ); REG64_FLD( PEC_STACK1_NFIRACTION0_REG_NFIRACTION0_LEN , 30 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , SH_FLD_NFIRACTION0_LEN ); REG64_FLD( PHB_NFIRACTION0_REG_NFIRACTION0 , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_NFIRACTION0 ); REG64_FLD( PHB_NFIRACTION0_REG_NFIRACTION0_LEN , 30 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_NFIRACTION0_LEN ); REG64_FLD( PEC_STACK0_NFIRACTION0_REG_NFIRACTION0 , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , SH_FLD_NFIRACTION0 ); REG64_FLD( PEC_STACK0_NFIRACTION0_REG_NFIRACTION0_LEN , 30 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , SH_FLD_NFIRACTION0_LEN ); REG64_FLD( PEC_STACK2_NFIRACTION1_REG_NFIRACTION1 , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , SH_FLD_NFIRACTION1 ); REG64_FLD( PEC_STACK2_NFIRACTION1_REG_NFIRACTION1_LEN , 30 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , SH_FLD_NFIRACTION1_LEN ); REG64_FLD( PEC_STACK1_NFIRACTION1_REG_NFIRACTION1 , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , SH_FLD_NFIRACTION1 ); REG64_FLD( PEC_STACK1_NFIRACTION1_REG_NFIRACTION1_LEN , 30 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , SH_FLD_NFIRACTION1_LEN ); REG64_FLD( PHB_NFIRACTION1_REG_NFIRACTION1 , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_NFIRACTION1 ); REG64_FLD( PHB_NFIRACTION1_REG_NFIRACTION1_LEN , 30 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_NFIRACTION1_LEN ); REG64_FLD( PEC_STACK0_NFIRACTION1_REG_NFIRACTION1 , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , SH_FLD_NFIRACTION1 ); REG64_FLD( PEC_STACK0_NFIRACTION1_REG_NFIRACTION1_LEN , 30 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , SH_FLD_NFIRACTION1_LEN ); REG64_FLD( PEC_STACK2_NFIRMASK_REG_NFIRMASK , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_NFIRMASK ); REG64_FLD( PEC_STACK2_NFIRMASK_REG_NFIRMASK_LEN , 30 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_NFIRMASK_LEN ); REG64_FLD( PEC_STACK1_NFIRMASK_REG_NFIRMASK , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_NFIRMASK ); REG64_FLD( PEC_STACK1_NFIRMASK_REG_NFIRMASK_LEN , 30 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_NFIRMASK_LEN ); REG64_FLD( PHB_NFIRMASK_REG_NFIRMASK , 0 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_NFIRMASK ); REG64_FLD( PHB_NFIRMASK_REG_NFIRMASK_LEN , 30 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_NFIRMASK_LEN ); REG64_FLD( PEC_STACK0_NFIRMASK_REG_NFIRMASK , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_NFIRMASK ); REG64_FLD( PEC_STACK0_NFIRMASK_REG_NFIRMASK_LEN , 30 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_NFIRMASK_LEN ); REG64_FLD( PEC_STACK2_NFIR_REG_NFIRNFIR , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_NFIRNFIR ); REG64_FLD( PEC_STACK2_NFIR_REG_NFIRNFIR_LEN , 30 , SH_UNT_PEC_STACK2, SH_ACS_SCOM2_OR , SH_FLD_NFIRNFIR_LEN ); REG64_FLD( PEC_STACK1_NFIR_REG_NFIRNFIR , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_NFIRNFIR ); REG64_FLD( PEC_STACK1_NFIR_REG_NFIRNFIR_LEN , 30 , SH_UNT_PEC_STACK1, SH_ACS_SCOM2_OR , SH_FLD_NFIRNFIR_LEN ); REG64_FLD( PHB_NFIR_REG_NFIRNFIR , 0 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_NFIRNFIR ); REG64_FLD( PHB_NFIR_REG_NFIRNFIR_LEN , 30 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_NFIRNFIR_LEN ); REG64_FLD( PEC_STACK0_NFIR_REG_NFIRNFIR , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_NFIRNFIR ); REG64_FLD( PEC_STACK0_NFIR_REG_NFIRNFIR_LEN , 30 , SH_UNT_PEC_STACK0, SH_ACS_SCOM2_OR , SH_FLD_NFIRNFIR_LEN ); REG64_FLD( PU_NOTRUST_BAR0_UNTRUSTED , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNTRUSTED ); REG64_FLD( PU_NOTRUST_BAR0_UNTRUSTED_LEN , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNTRUSTED_LEN ); REG64_FLD( PU_NOTRUST_BAR0MASK_UNTRUSTED , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNTRUSTED ); REG64_FLD( PU_NOTRUST_BAR0MASK_UNTRUSTED_LEN , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNTRUSTED_LEN ); REG64_FLD( PU_NOTRUST_BAR1_UNTRUSTED , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNTRUSTED ); REG64_FLD( PU_NOTRUST_BAR1_UNTRUSTED_LEN , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNTRUSTED_LEN ); REG64_FLD( PU_NOTRUST_BAR1MASK_UNTRUSTED , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNTRUSTED ); REG64_FLD( PU_NOTRUST_BAR1MASK_UNTRUSTED_LEN , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNTRUSTED_LEN ); REG64_FLD( PU_NPU_SM0_NPU_ATS_DEBUG_ENABLE , 0 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_ENABLE ); REG64_FLD( PU_NPU_SM0_NPU_ATS_DEBUG_0_SELECT , 1 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_0_SELECT ); REG64_FLD( PU_NPU_SM0_NPU_ATS_DEBUG_0_SELECT_LEN , 3 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_0_SELECT_LEN ); REG64_FLD( PU_NPU_SM0_NPU_ATS_DEBUG_1_SELECT , 4 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_1_SELECT ); REG64_FLD( PU_NPU_SM0_NPU_ATS_DEBUG_1_SELECT_LEN , 3 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_1_SELECT_LEN ); REG64_FLD( PU_NPU_SM0_NPU_AT_ECC_INJECT_MODE , 0 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_INJECT_MODE ); REG64_FLD( PU_NPU_SM0_NPU_AT_ECC_INJECT_MODE_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_INJECT_MODE_LEN ); REG64_FLD( PU_NPU_SM0_NPU_AT_ECC_INJECT_TYPE , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_INJECT_TYPE ); REG64_FLD( PU_NPU_SM0_NPU_AT_ECC_INJECT_TYPE_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_INJECT_TYPE_LEN ); REG64_FLD( PU_NPU_SM0_NPU_AT_ECC_INJECT_ENABLE , 4 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_INJECT_ENABLE ); REG64_FLD( PU_NPU_SM0_NPU_AT_ECC_ARRAY_SELECT , 5 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_ARRAY_SELECT ); REG64_FLD( PU_NPU_SM0_NPU_AT_ECC_ARRAY_SELECT_LEN , 4 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_ARRAY_SELECT_LEN ); REG64_FLD( PU_NPU_SM1_NPU_AT_ESMR_IDIAL_ATS_ESR_MSK , 0 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_IDIAL_ATS_ESR_MSK ); REG64_FLD( PU_NPU_SM1_NPU_AT_ESMR_IDIAL_ATS_ESR_MSK_LEN , 20 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_IDIAL_ATS_ESR_MSK_LEN ); REG64_FLD( PU_NPU_SM1_NPU_AT_ESR_IDIAL_ATS , 0 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_IDIAL_ATS ); REG64_FLD( PU_NPU_SM1_NPU_AT_ESR_IDIAL_ATS_LEN , 20 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_IDIAL_ATS_LEN ); REG64_FLD( PU_NPU_SM1_NPU_AT_FESMR_IDIAL_ATS_FER_MSK , 0 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_IDIAL_ATS_FER_MSK ); REG64_FLD( PU_NPU_SM1_NPU_AT_FESMR_IDIAL_ATS_FER_MSK_LEN , 20 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_IDIAL_ATS_FER_MSK_LEN ); REG64_FLD( PU_NPU_SM1_NPU_AT_FESR_FIRST_ERROR_CAPTURED , 0 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_FIRST_ERROR_CAPTURED ); REG64_FLD( PU_NPU_SM1_NPU_AT_FESR_FIRST_ERROR_SPARE , 1 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_FIRST_ERROR_SPARE ); REG64_FLD( PU_NPU_SM1_NPU_AT_FESR_FIRST_ERROR_SPARE_LEN , 2 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_FIRST_ERROR_SPARE_LEN ); REG64_FLD( PU_NPU_SM1_NPU_AT_FESR_FIRST_ERROR_DECODE , 3 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_FIRST_ERROR_DECODE ); REG64_FLD( PU_NPU_SM1_NPU_AT_FESR_FIRST_ERROR_DECODE_LEN , 5 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_FIRST_ERROR_DECODE_LEN ); REG64_FLD( PU_NPU_SM1_NPU_AT_FESR_FIRST_ERROR_INFO , 8 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_FIRST_ERROR_INFO ); REG64_FLD( PU_NPU_SM1_NPU_AT_FESR_FIRST_ERROR_INFO_LEN , 56 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM_RW , SH_FLD_FIRST_ERROR_INFO_LEN ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CNT_CNT0 , 0 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO , SH_FLD_CNT0 ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CNT_CNT0_LEN , 16 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO , SH_FLD_CNT0_LEN ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CNT_CNT1 , 16 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO , SH_FLD_CNT1 ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CNT_CNT1_LEN , 16 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO , SH_FLD_CNT1_LEN ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CNT_CNT2 , 32 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO , SH_FLD_CNT2 ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CNT_CNT2_LEN , 16 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO , SH_FLD_CNT2_LEN ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CNT_CNT3 , 48 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO , SH_FLD_CNT3 ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CNT_CNT3_LEN , 16 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RO , SH_FLD_CNT3_LEN ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_ENABLE ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_RESETMODE , 1 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_RESETMODE ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_FREEZEMODE , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_FREEZEMODE ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_DISABLE_PMISC , 3 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_DISABLE_PMISC ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PMISC_MODE , 4 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_PMISC_MODE ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_CASCADE , 5 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_CASCADE ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_CASCADE_LEN , 3 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_CASCADE_LEN ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C0 , 8 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_PRESCALE_C0 ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C0_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_PRESCALE_C0_LEN ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C1 , 10 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_PRESCALE_C1 ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C1_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_PRESCALE_C1_LEN ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C2 , 12 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_PRESCALE_C2 ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C2_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_PRESCALE_C2_LEN ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C3 , 14 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_PRESCALE_C3 ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_PRESCALE_C3_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_PRESCALE_C3_LEN ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C0 , 16 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_OPERATION_C0 ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C0_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_OPERATION_C0_LEN ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C1 , 18 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_OPERATION_C1 ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C1_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_OPERATION_C1_LEN ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C2 , 20 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_OPERATION_C2 ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C2_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_OPERATION_C2_LEN ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C3 , 22 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_OPERATION_C3 ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_OPERATION_C3_LEN , 2 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_OPERATION_C3_LEN ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_EVENTS , 24 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_EVENTS ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_EVENTS_LEN , 3 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_EVENTS_LEN ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CFG_PE_MATCH0 , 27 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_CFG_PE_MATCH0 ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CFG_PE_MATCH0_LEN , 5 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_CFG_PE_MATCH0_LEN ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CFG_PE_MATCH1 , 32 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_CFG_PE_MATCH1 ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_CFG_PE_MATCH1_LEN , 5 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_CFG_PE_MATCH1_LEN ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_SPARE , 37 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_SPARE ); REG64_FLD( PU_NPU_SM0_NPU_AT_PMU_CTRL_PERF_CONFIG_SPARE_LEN , 5 , SH_UNT_PU_NPU_SM0, SH_ACS_SCOM_RW , SH_FLD_PERF_CONFIG_SPARE_LEN ); REG64_FLD( PU_NPU_SM1_NPU_Q_DMA_R_QUIESCE , 0 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_QUIESCE ); REG64_FLD( PU_NPU_SM1_NPU_Q_DMA_R_QUIESCE_AUTO_RESET , 1 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_QUIESCE_AUTO_RESET ); REG64_FLD( PU_NPU_SM1_NPU_Q_DMA_R_RESPONSE , 4 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_RESPONSE ); REG64_FLD( PU_NPU_SM1_NPU_Q_DMA_R_TCE_RESPONSE , 6 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_TCE_RESPONSE ); REG64_FLD( PU_NPU_CTL_NPU_VERSION_RSVD0 , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_RSVD0 ); REG64_FLD( PU_NPU_CTL_NPU_VERSION_RSVD0_LEN , 24 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_RSVD0_LEN ); REG64_FLD( PU_NPU_CTL_NPU_VERSION_MAJOR , 24 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MAJOR ); REG64_FLD( PU_NPU_CTL_NPU_VERSION_MAJOR_LEN , 8 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MAJOR_LEN ); REG64_FLD( PU_NPU_CTL_NPU_VERSION_RSVD1 , 32 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_RSVD1 ); REG64_FLD( PU_NPU_CTL_NPU_VERSION_RSVD1_LEN , 16 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_RSVD1_LEN ); REG64_FLD( PU_NPU_CTL_NPU_VERSION_MINOR , 48 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MINOR ); REG64_FLD( PU_NPU_CTL_NPU_VERSION_MINOR_LEN , 16 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_MINOR_LEN ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_LN , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_WR_DISABLE_LN ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_GROUP , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_WR_DISABLE_GROUP ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_VG_NOT_SYS , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_WR_DISABLE_VG_NOT_SYS ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_DISABLE_NN_RN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_WR_DISABLE_NN_RN ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_RD_DISABLE_LN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_RD_DISABLE_LN ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_RD_DISABLE_GROUP , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_RD_DISABLE_GROUP ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_RD_DISABLE_VG_NOT_SYS , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_RD_DISABLE_VG_NOT_SYS ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_RD_DISABLE_NN_RN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_RD_DISABLE_NN_RN ); REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_WR_DISABLE_LN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_UMAC_WR_DISABLE_LN ); REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_WR_DISABLE_GROUP , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_UMAC_WR_DISABLE_GROUP ); REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_WR_DISABLE_VG_NOT_SYS , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_UMAC_WR_DISABLE_VG_NOT_SYS ); REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_WR_DISABLE_NN_RN , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_UMAC_WR_DISABLE_NN_RN ); REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_RD_DISABLE_LN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_UMAC_RD_DISABLE_LN ); REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_RD_DISABLE_GROUP , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_UMAC_RD_DISABLE_GROUP ); REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_RD_DISABLE_VG_NOT_SYS , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_UMAC_RD_DISABLE_VG_NOT_SYS ); REG64_FLD( PU_NXCQ_PB_MODE_REG_UMAC_RD_DISABLE_NN_RN , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_UMAC_RD_DISABLE_NN_RN ); REG64_FLD( PU_NXCQ_PB_MODE_REG_NX_FREEZE_MODES , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_NX_FREEZE_MODES ); REG64_FLD( PU_NXCQ_PB_MODE_REG_NX_FREEZE_MODES_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_NX_FREEZE_MODES_LEN ); REG64_FLD( PU_NXCQ_PB_MODE_REG_RESERVED , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NXCQ_PB_MODE_REG_RESERVED_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_NOT_INJECT , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_WR_NOT_INJECT ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_PARTIAL_WRT_NOT_INJECT , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_PARTIAL_WRT_NOT_INJECT ); REG64_FLD( PU_NXCQ_PB_MODE_REG_RD_GO_M_QOS , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_RD_GO_M_QOS ); REG64_FLD( PU_NXCQ_PB_MODE_REG_ADDR_BAR , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDR_BAR ); REG64_FLD( PU_NXCQ_PB_MODE_REG_SKIP_G , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_SKIP_G ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DATA_ARB_LFSR_CONFIG , 25 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_ARB_LFSR_CONFIG ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DATA_ARB_LFSR_CONFIG_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_ARB_LFSR_CONFIG_LEN ); REG64_FLD( PU_NXCQ_PB_MODE_REG_HANG_SM_ON_ARE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_HANG_SM_ON_ARE ); REG64_FLD( PU_NXCQ_PB_MODE_REG_HANG_SM_ON_LINK_FAIL , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_HANG_SM_ON_LINK_FAIL ); REG64_FLD( PU_NXCQ_PB_MODE_REG_CFG_PUMP , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_PUMP ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DISABLE_FLOW_SCOPE , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_FLOW_SCOPE ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DISABLE_PMU_SNOOPING , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_PMU_SNOOPING ); REG64_FLD( PU_NXCQ_PB_MODE_REG_ENDABLE_PMU_CNT_RESET , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENDABLE_PMU_CNT_RESET ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DISABLE_WRP , 33 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_WRP ); REG64_FLD( PU_NXCQ_PB_MODE_REG_UNUSED , 34 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( PU_NXCQ_PB_MODE_REG_UNUSED_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_RD_VG_RESET_TIMER_MASK , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_RD_VG_RESET_TIMER_MASK ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_RD_VG_RESET_TIMER_MASK_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_RD_VG_RESET_TIMER_MASK_LEN ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_WR_VG_RESET_TIMER_MASK ); REG64_FLD( PU_NXCQ_PB_MODE_REG_DMA_WR_VG_RESET_TIMER_MASK_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_WR_VG_RESET_TIMER_MASK_LEN ); REG64_FLD( PU_NMMU_NX_CQ_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( PU_NMMU_NX_CQ_FIR_ACTION0_REG_ACTION0_LEN , 22 , SH_UNT_PU_NMMU , SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); REG64_FLD( PU_NX_CQ_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( PU_NX_CQ_FIR_ACTION0_REG_ACTION0_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); REG64_FLD( PU_NMMU_NX_CQ_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); REG64_FLD( PU_NMMU_NX_CQ_FIR_ACTION1_REG_ACTION1_LEN , 21 , SH_UNT_PU_NMMU , SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); REG64_FLD( PU_NX_CQ_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); REG64_FLD( PU_NX_CQ_FIR_ACTION1_REG_ACTION1_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); REG64_FLD( PU_NMMU_NX_CQ_FIR_MASK_REG_MASK , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_MASK ); REG64_FLD( PU_NMMU_NX_CQ_FIR_MASK_REG_MASK_LEN , 22 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_MASK_LEN ); REG64_FLD( PU_NX_CQ_FIR_MASK_REG_MASK , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MASK ); REG64_FLD( PU_NX_CQ_FIR_MASK_REG_MASK_LEN , 44 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MASK_LEN ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBI_PE , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_PBI_PE ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_CMD_HANG , 1 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_PBUS_CMD_HANG ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_READ_ARE , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_PBUS_READ_ARE ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_WRITE_ARE , 3 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_PBUS_WRITE_ARE ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_MISC_HW , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_PBUS_MISC_HW ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_RSVD , 5 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_RSVD ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_XLAT_ECC_UE , 6 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_PBUS_XLAT_ECC_UE ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_XLAT_ECC_SUE , 7 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_PBUS_XLAT_ECC_SUE ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_ECC_CE , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_PBUS_ECC_CE ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_ECC_UE , 9 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_PBUS_ECC_UE ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_ECC_SUE , 10 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_PBUS_ECC_SUE ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_INBD_LCO_ARRAY_ECC_CE , 11 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_INBD_LCO_ARRAY_ECC_CE ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_INBD_LCO_ARRAY_ECC_UE , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_INBD_LCO_ARRAY_ECC_UE ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_INBD_LCO_ARRAY_ECC_SUE , 13 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_INBD_LCO_ARRAY_ECC_SUE ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_INBD_ARRAY_ECC_CE , 14 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_INBD_ARRAY_ECC_CE ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_INBD_ARRAY_ECC_UE , 15 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_INBD_ARRAY_ECC_UE ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_INT_STATE_ERR , 16 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_INT_STATE_ERR ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_LOAD_LINK_ERR , 17 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_PBUS_LOAD_LINK_ERR ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_STORE_LINK_ERR , 18 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_PBUS_STORE_LINK_ERR ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_PBUS_LINK_ABORT , 19 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_PBUS_LINK_ABORT ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_SCOM_PE , 20 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PE ); REG64_FLD( PU_NMMU_NX_CQ_FIR_REG_SCOM_PE_DUP , 21 , SH_UNT_PU_NMMU , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PE_DUP ); REG64_FLD( PU_NX_CQ_FIR_REG_PBI_PE , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBI_PE ); REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_ECC_CE , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBUS_ECC_CE ); REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_ECC_UE , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBUS_ECC_UE ); REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_ECC_SUE , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBUS_ECC_SUE ); REG64_FLD( PU_NX_CQ_FIR_REG_INBD_ARRAY_ECC_CE , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INBD_ARRAY_ECC_CE ); REG64_FLD( PU_NX_CQ_FIR_REG_INBD_ARRAY_ECC_UE , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INBD_ARRAY_ECC_UE ); REG64_FLD( PU_NX_CQ_FIR_REG_PASTE_REJECT , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PASTE_REJECT ); REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_CMD_HANG , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBUS_CMD_HANG ); REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_READ_ARE , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBUS_READ_ARE ); REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_WRITE_ARE , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBUS_WRITE_ARE ); REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_MISC_HW , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBUS_MISC_HW ); REG64_FLD( PU_NX_CQ_FIR_REG_MMIO_BAR_PE , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MMIO_BAR_PE ); REG64_FLD( PU_NX_CQ_FIR_REG_UMAC_WC_INT_ADDR_UE , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UMAC_WC_INT_ADDR_UE ); REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_LOAD_LINK_ERR , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBUS_LOAD_LINK_ERR ); REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_STORE_LINK_ERR , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBUS_STORE_LINK_ERR ); REG64_FLD( PU_NX_CQ_FIR_REG_PBUS_LINK_ABORT , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBUS_LINK_ABORT ); REG64_FLD( PU_NX_CQ_FIR_REG_PBI_INTERNAL_HANG , 16 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBI_INTERNAL_HANG ); REG64_FLD( PU_NX_CQ_FIR_REG_ERAT_ARRAY_PE , 17 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ERAT_ARRAY_PE ); REG64_FLD( PU_NX_CQ_FIR_REG_ERAT_ARRAY_CE , 18 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ERAT_ARRAY_CE ); REG64_FLD( PU_NX_CQ_FIR_REG_ERAT_ARRAY_UE , 19 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ERAT_ARRAY_UE ); REG64_FLD( PU_NX_CQ_FIR_REG_ERAT_ARRAY_SUE , 20 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ERAT_ARRAY_SUE ); REG64_FLD( PU_NX_CQ_FIR_REG_ERAT_CICO_HANG , 21 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ERAT_CICO_HANG ); REG64_FLD( PU_NX_CQ_FIR_REG_ERAT_CNTRL_ERR , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ERAT_CNTRL_ERR ); REG64_FLD( PU_NX_CQ_FIR_REG_PB_XLAT_DATA_UE , 23 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_XLAT_DATA_UE ); REG64_FLD( PU_NX_CQ_FIR_REG_PB_XLAT_DATA_SUE , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_XLAT_DATA_SUE ); REG64_FLD( PU_NX_CQ_FIR_REG_UMAC_LD_LINK_ERR , 25 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UMAC_LD_LINK_ERR ); REG64_FLD( PU_NX_CQ_FIR_REG_UMAC_LINK_ABORT , 26 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UMAC_LINK_ABORT ); REG64_FLD( PU_NX_CQ_FIR_REG_UMAC_CRB_UE , 27 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UMAC_CRB_UE ); REG64_FLD( PU_NX_CQ_FIR_REG_UMAC_CRB_SUE , 28 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UMAC_CRB_SUE ); REG64_FLD( PU_NX_CQ_FIR_REG_ERAT_LOCAL_CSTOP , 29 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ERAT_LOCAL_CSTOP ); REG64_FLD( PU_NX_CQ_FIR_REG_RNG_FIRST_FAIL , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RNG_FIRST_FAIL ); REG64_FLD( PU_NX_CQ_FIR_REG_RNG_SECOND_FAIL , 33 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RNG_SECOND_FAIL ); REG64_FLD( PU_NX_CQ_FIR_REG_RNG_CNTRL_LOGIC_ERR , 34 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RNG_CNTRL_LOGIC_ERR ); REG64_FLD( PU_NX_CQ_FIR_REG_NMMU_LOCAL_XSTOP , 35 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_NMMU_LOCAL_XSTOP ); REG64_FLD( PU_NX_CQ_FIR_REG_VAS_LOCAL_XSTOP , 36 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_VAS_LOCAL_XSTOP ); REG64_FLD( PU_NX_CQ_FIR_REG_PBCQ_CNTRL_LOGIC_ERR , 37 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBCQ_CNTRL_LOGIC_ERR ); REG64_FLD( PU_NX_CQ_FIR_REG_FAILED_LINK_ON_INTERRUPT , 38 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FAILED_LINK_ON_INTERRUPT ); REG64_FLD( PU_NX_CQ_FIR_REG_SCOM_PE , 42 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PE ); REG64_FLD( PU_NX_CQ_FIR_REG_SCOM_PE_DUP , 43 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PE_DUP ); REG64_FLD( PU_NX_DEBUGMUX_CTRL_BITS , 47 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BITS ); REG64_FLD( PU_NX_DEBUGMUX_CTRL_BITS_LEN , 14 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BITS_LEN ); REG64_FLD( PU_NMMU_NX_DEBUG_SNAPSHOT_0_B0_63 , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_B0_63 ); REG64_FLD( PU_NMMU_NX_DEBUG_SNAPSHOT_0_B0_63_LEN , 64 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_B0_63_LEN ); REG64_FLD( PU_NX_DEBUG_SNAPSHOT_0_B0_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_B0_63 ); REG64_FLD( PU_NX_DEBUG_SNAPSHOT_0_B0_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_B0_63_LEN ); REG64_FLD( PU_NMMU_NX_DEBUG_SNAPSHOT_1_B64_87 , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_B64_87 ); REG64_FLD( PU_NMMU_NX_DEBUG_SNAPSHOT_1_B64_87_LEN , 24 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_B64_87_LEN ); REG64_FLD( PU_NX_DEBUG_SNAPSHOT_1_B64_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_B64_87 ); REG64_FLD( PU_NX_DEBUG_SNAPSHOT_1_B64_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_B64_87_LEN ); REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_00 , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_00 ); REG64_FLD( PU_NX_DMA_ENG_FIR_ICS_INVALID_STATE , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ICS_INVALID_STATE ); REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_02 , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_02 ); REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_03 , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_03 ); REG64_FLD( PU_NX_DMA_ENG_FIR_CH0_842_ECC_CE , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CH0_842_ECC_CE ); REG64_FLD( PU_NX_DMA_ENG_FIR_CH0_842_ECC_UE , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CH0_842_ECC_UE ); REG64_FLD( PU_NX_DMA_ENG_FIR_CH1_842_ECC_CE , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CH1_842_ECC_CE ); REG64_FLD( PU_NX_DMA_ENG_FIR_CH1_842_ECC_UE , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CH1_842_ECC_UE ); REG64_FLD( PU_NX_DMA_ENG_FIR_NONZERO_CSB_CC , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_NONZERO_CSB_CC ); REG64_FLD( PU_NX_DMA_ENG_FIR_ECC_CE , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ECC_CE ); REG64_FLD( PU_NX_DMA_ENG_FIR_OUTWR_INRD_ECC_CE , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OUTWR_INRD_ECC_CE ); REG64_FLD( PU_NX_DMA_ENG_FIR_CH5_AMF_ECC_CE , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CH5_AMF_ECC_CE ); REG64_FLD( PU_NX_DMA_ENG_FIR_CH6_AMF_ECC_CE , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CH6_AMF_ECC_CE ); REG64_FLD( PU_NX_DMA_ENG_FIR_CH7_AMF_ECC_CE , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CH7_AMF_ECC_CE ); REG64_FLD( PU_NX_DMA_ENG_FIR_OTHER_SCOM_SAT , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OTHER_SCOM_SAT ); REG64_FLD( PU_NX_DMA_ENG_FIR_INVALID_STATE_RECOV , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INVALID_STATE_RECOV ); REG64_FLD( PU_NX_DMA_ENG_FIR_INVALID_STATE_UNRECOV , 16 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INVALID_STATE_UNRECOV ); REG64_FLD( PU_NX_DMA_ENG_FIR_ECC_UE , 17 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ECC_UE ); REG64_FLD( PU_NX_DMA_ENG_FIR_OUTWR_INRD_ECC_UE , 18 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OUTWR_INRD_ECC_UE ); REG64_FLD( PU_NX_DMA_ENG_FIR_INRD_DONE_ERR , 19 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INRD_DONE_ERR ); REG64_FLD( PU_NX_DMA_ENG_FIR_CH0_INVALID_STATE , 20 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CH0_INVALID_STATE ); REG64_FLD( PU_NX_DMA_ENG_FIR_CH1_INVALID_STATE , 21 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CH1_INVALID_STATE ); REG64_FLD( PU_NX_DMA_ENG_FIR_CH2_INVALID_STATE , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CH2_INVALID_STATE ); REG64_FLD( PU_NX_DMA_ENG_FIR_CH3_INVALID_STATE , 23 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CH3_INVALID_STATE ); REG64_FLD( PU_NX_DMA_ENG_FIR_CH4_INVALID_STATE , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CH4_INVALID_STATE ); REG64_FLD( PU_NX_DMA_ENG_FIR_CH5_INVALID_STATE , 25 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CH5_INVALID_STATE ); REG64_FLD( PU_NX_DMA_ENG_FIR_CH6_INVALID_STATE , 26 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CH6_INVALID_STATE ); REG64_FLD( PU_NX_DMA_ENG_FIR_CH7_INVALID_STATE , 27 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CH7_INVALID_STATE ); REG64_FLD( PU_NX_DMA_ENG_FIR_CH5_AMF_ECC_UE , 28 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CH5_AMF_ECC_UE ); REG64_FLD( PU_NX_DMA_ENG_FIR_CH6_AMF_ECC_UE , 29 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CH6_AMF_ECC_UE ); REG64_FLD( PU_NX_DMA_ENG_FIR_CH7_AMF_ECC_UE , 30 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CH7_AMF_ECC_UE ); REG64_FLD( PU_NX_DMA_ENG_FIR_CRB_ECC_UE , 31 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CRB_ECC_UE ); REG64_FLD( PU_NX_DMA_ENG_FIR_CRB_ECC_SUE , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CRB_ECC_SUE ); REG64_FLD( PU_NX_DMA_ENG_FIR_OUTWR_INRD_ECC_SUE , 33 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OUTWR_INRD_ECC_SUE ); REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_34 , 34 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_34 ); REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_35 , 35 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_35 ); REG64_FLD( PU_NX_DMA_ENG_FIR_CH4_AMF_ECC_CE , 36 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CH4_AMF_ECC_CE ); REG64_FLD( PU_NX_DMA_ENG_FIR_CH4_AMF_ECC_UE , 37 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CH4_AMF_ECC_UE ); REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_38 , 38 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_38 ); REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_39 , 39 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_39 ); REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_40 , 40 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_40 ); REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_41 , 41 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_41 ); REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_42 , 42 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_42 ); REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_43 , 43 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_43 ); REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_44 , 44 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_44 ); REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_45 , 45 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_45 ); REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_46 , 46 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_46 ); REG64_FLD( PU_NX_DMA_ENG_FIR_RESERVED_47 , 47 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_47 ); REG64_FLD( PU_NX_DMA_ENG_FIR_SCOM_PE , 48 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PE ); REG64_FLD( PU_NX_DMA_ENG_FIR_SCOM_PE_DUP , 49 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PE_DUP ); REG64_FLD( PU_NX_DMA_ENG_FIR_ACTION0_BITS , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BITS ); REG64_FLD( PU_NX_DMA_ENG_FIR_ACTION0_BITS_LEN , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BITS_LEN ); REG64_FLD( PU_NX_DMA_ENG_FIR_ACTION1_BITS , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BITS ); REG64_FLD( PU_NX_DMA_ENG_FIR_ACTION1_BITS_LEN , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BITS_LEN ); REG64_FLD( PU_NX_DMA_ENG_FIR_MASK_BITS , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BITS ); REG64_FLD( PU_NX_DMA_ENG_FIR_MASK_BITS_LEN , 50 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BITS_LEN ); REG64_FLD( PU_NX_DMA_ENG_FIR_WOF_BITS , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_BITS ); REG64_FLD( PU_NX_DMA_ENG_FIR_WOF_BITS_LEN , 50 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_BITS_LEN ); REG64_FLD( PU_NX_ERRORINJ_CTRL_CH0EFT_ENA , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH0EFT_ENA ); REG64_FLD( PU_NX_ERRORINJ_CTRL_CH0EFT_TYPE , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH0EFT_TYPE ); REG64_FLD( PU_NX_ERRORINJ_CTRL_CH0EFT_ACTION , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH0EFT_ACTION ); REG64_FLD( PU_NX_ERRORINJ_CTRL_CH0EFT_SELECT , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH0EFT_SELECT ); REG64_FLD( PU_NX_ERRORINJ_CTRL_CH0EFT_SELECT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH0EFT_SELECT_LEN ); REG64_FLD( PU_NX_ERRORINJ_CTRL_CH1EFT_ENA , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH1EFT_ENA ); REG64_FLD( PU_NX_ERRORINJ_CTRL_CH1EFT_TYPE , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH1EFT_TYPE ); REG64_FLD( PU_NX_ERRORINJ_CTRL_CH1EFT_ACTION , 11 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH1EFT_ACTION ); REG64_FLD( PU_NX_ERRORINJ_CTRL_CH1EFT_SELECT , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH1EFT_SELECT ); REG64_FLD( PU_NX_ERRORINJ_CTRL_CH1EFT_SELECT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH1EFT_SELECT_LEN ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INWR_ENA , 23 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_INWR_ENA ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INWR_TYPE , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_INWR_TYPE ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INWR_ACTION , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_INWR_ACTION ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_OUTWR_ENA , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_OUTWR_ENA ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_OUTWR_TYPE , 27 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_OUTWR_TYPE ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_OUTWR_ACTION , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_OUTWR_ACTION ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_ENA , 29 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_INGARRAY_ENA ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_TYPE , 30 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_INGARRAY_TYPE ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_ACTION , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_INGARRAY_ACTION ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_SELECT , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_INGARRAY_SELECT ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_INGARRAY_SELECT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_INGARRAY_SELECT_LEN ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_ENA , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_EGRARRAY_ENA ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_TYPE , 37 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_EGRARRAY_TYPE ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_ACTION , 38 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_EGRARRAY_ACTION ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_SELECT , 39 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_EGRARRAY_SELECT ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_EGRARRAY_SELECT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_EGRARRAY_SELECT_LEN ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_CRBARRAY_ENA , 43 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_CRBARRAY_ENA ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_CRBARRAY_TYPE , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_CRBARRAY_TYPE ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_CRBARRAY_ACTION , 45 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_CRBARRAY_ACTION ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_CRBARRAY_SELECT , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_CRBARRAY_SELECT ); REG64_FLD( PU_NX_ERRORINJ_CTRL_CH4GZIP_ENA , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH4GZIP_ENA ); REG64_FLD( PU_NX_ERRORINJ_CTRL_CH4GZIP_TYPE , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH4GZIP_TYPE ); REG64_FLD( PU_NX_ERRORINJ_CTRL_CH4GZIP_ACTION , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH4GZIP_ACTION ); REG64_FLD( PU_NX_ERRORINJ_CTRL_CH4GZIP_SELECT , 51 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH4GZIP_SELECT ); REG64_FLD( PU_NX_ERRORINJ_CTRL_CH4GZIP_SELECT_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH4GZIP_SELECT_LEN ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_OUTWR_QW0_UEINJ_ENA , 59 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_OUTWR_QW0_UEINJ_ENA ); REG64_FLD( PU_NX_ERRORINJ_CTRL_DMA_OUTWR_QW4_UEINJ_ENA , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_OUTWR_QW4_UEINJ_ENA ); REG64_FLD( PU_NMMU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HANG_POLL_SCALE ); REG64_FLD( PU_NMMU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HANG_POLL_SCALE_LEN ); REG64_FLD( PU_NMMU_NX_MISC_CONTROL_REG_HANG_DATA_SCALE , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HANG_DATA_SCALE ); REG64_FLD( PU_NMMU_NX_MISC_CONTROL_REG_HANG_DATA_SCALE_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HANG_DATA_SCALE_LEN ); REG64_FLD( PU_NMMU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HANG_SHM_SCALE ); REG64_FLD( PU_NMMU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_HANG_SHM_SCALE_LEN ); REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_HANG_POLL_SCALE ); REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_POLL_SCALE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_HANG_POLL_SCALE_LEN ); REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_DATA_SCALE , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_HANG_DATA_SCALE ); REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_DATA_SCALE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_HANG_DATA_SCALE_LEN ); REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_HANG_SHM_SCALE ); REG64_FLD( PU_NX_MISC_CONTROL_REG_HANG_SHM_SCALE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_HANG_SHM_SCALE_LEN ); REG64_FLD( PU_NX_MISC_CONTROL_REG_ERAT_DATA_POLL_SCALE , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERAT_DATA_POLL_SCALE ); REG64_FLD( PU_NX_MISC_CONTROL_REG_ERAT_DATA_POLL_SCALE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERAT_DATA_POLL_SCALE_LEN ); REG64_FLD( PU_NX_MMIO_BAR_BAR , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAR ); REG64_FLD( PU_NX_MMIO_BAR_BAR_LEN , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAR_LEN ); REG64_FLD( PU_NX_MMIO_BAR_ENABLE , 52 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NMMU_NX_PB_DEBUG_REG_NXCQ_TRACE_CNTL , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NXCQ_TRACE_CNTL ); REG64_FLD( PU_NMMU_NX_PB_DEBUG_REG_NXCQ_TRACE_CNTL_LEN , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NXCQ_TRACE_CNTL_LEN ); REG64_FLD( PU_NX_PB_DEBUG_REG_NXCQ_TRACE_CNTL , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_NXCQ_TRACE_CNTL ); REG64_FLD( PU_NX_PB_DEBUG_REG_NXCQ_TRACE_CNTL_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_NXCQ_TRACE_CNTL_LEN ); REG64_FLD( PU_NMMU_NX_PB_ECC_REG_NXCQ_INJECT_MODE , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NXCQ_INJECT_MODE ); REG64_FLD( PU_NMMU_NX_PB_ECC_REG_NXCQ_INJECT_MODE_LEN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NXCQ_INJECT_MODE_LEN ); REG64_FLD( PU_NMMU_NX_PB_ECC_REG_NXCQ_INJECT_TYPE , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NXCQ_INJECT_TYPE ); REG64_FLD( PU_NMMU_NX_PB_ECC_REG_NXCQ_INJECT_TYPE_LEN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NXCQ_INJECT_TYPE_LEN ); REG64_FLD( PU_NMMU_NX_PB_ECC_REG_NXCQ_PBCQ_INJECT_ENABLE , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NXCQ_PBCQ_INJECT_ENABLE ); REG64_FLD( PU_NMMU_NX_PB_ECC_REG_NXCQ_PBCQ_ARRAY , 5 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NXCQ_PBCQ_ARRAY ); REG64_FLD( PU_NMMU_NX_PB_ECC_REG_NXCQ_PBCQ_ARRAY_LEN , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_NXCQ_PBCQ_ARRAY_LEN ); REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_INJECT_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_NXCQ_INJECT_MODE ); REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_INJECT_MODE_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_NXCQ_INJECT_MODE_LEN ); REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_INJECT_TYPE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_NXCQ_INJECT_TYPE ); REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_INJECT_TYPE_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_NXCQ_INJECT_TYPE_LEN ); REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_PBCQ_INJECT_ENABLE , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_NXCQ_PBCQ_INJECT_ENABLE ); REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_PBCQ_ARRAY , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_NXCQ_PBCQ_ARRAY ); REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_PBCQ_ARRAY_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_NXCQ_PBCQ_ARRAY_LEN ); REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_RNG_INJECT_ENABLE , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_NXCQ_RNG_INJECT_ENABLE ); REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_RNG_INJECT_ACTION , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_NXCQ_RNG_INJECT_ACTION ); REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_ENABLE , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_NXCQ_ERAT_ARRAY_ENABLE ); REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_TYPE , 25 , SH_UNT , SH_ACS_SCOM , SH_FLD_NXCQ_ERAT_ARRAY_TYPE ); REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_ACTION , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_NXCQ_ERAT_ARRAY_ACTION ); REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_SELECT , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_NXCQ_ERAT_ARRAY_SELECT ); REG64_FLD( PU_NX_PB_ECC_REG_NXCQ_ERAT_ARRAY_SELECT_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_NXCQ_ERAT_ARRAY_SELECT_LEN ); REG64_FLD( PU_NMMU_NX_PB_ERR_RPT_0_PBI_WRITE_IDLE , 52 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_PBI_WRITE_IDLE ); REG64_FLD( PU_NX_PB_ERR_RPT_0_PBI_WRITE_IDLE , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_PBI_WRITE_IDLE ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_ENABLE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_FREEZE , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_FREEZE ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_RESET , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESET ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_DIS_GLOB_SCOM , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_DIS_GLOB_SCOM ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL0 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRESCALAR_SEL0 ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL0_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRESCALAR_SEL0_LEN ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL1 , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRESCALAR_SEL1 ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL1_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRESCALAR_SEL1_LEN ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL2 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRESCALAR_SEL2 ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL2_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRESCALAR_SEL2_LEN ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL3 , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRESCALAR_SEL3 ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_PRESCALAR_SEL3_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRESCALAR_SEL3_LEN ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT0_PAIR_OP , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT0_PAIR_OP ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT0_PAIR_OP_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT0_PAIR_OP_LEN ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT1_PAIR_OP , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT1_PAIR_OP ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT1_PAIR_OP_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT1_PAIR_OP_LEN ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT2_PAIR_OP , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT2_PAIR_OP ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT2_PAIR_OP_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT2_PAIR_OP_LEN ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT3_PAIR_OP , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT3_PAIR_OP ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT3_PAIR_OP_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT3_PAIR_OP_LEN ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT0_MUX_SEL , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT0_MUX_SEL ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT0_MUX_SEL_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT0_MUX_SEL_LEN ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT1_MUX_SEL , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT1_MUX_SEL ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT1_MUX_SEL_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT1_MUX_SEL_LEN ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT2_MUX_SEL , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT2_MUX_SEL ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT2_MUX_SEL_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT2_MUX_SEL_LEN ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT3_MUX_SEL , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT3_MUX_SEL ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_CNT3_MUX_SEL_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT3_MUX_SEL_LEN ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_FREEZE_ON_OVERFLOW , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_FREEZE_ON_OVERFLOW ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_CASCADE , 33 , SH_UNT , SH_ACS_SCOM , SH_FLD_CASCADE ); REG64_FLD( PU_NX_PMU0_CONTROL_REG_CASCADE_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CASCADE_LEN ); REG64_FLD( PU_NX_PMU0_COUNTER_REG_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( PU_NX_PMU0_COUNTER_REG_0_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_0_LEN ); REG64_FLD( PU_NX_PMU0_COUNTER_REG_1 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_1 ); REG64_FLD( PU_NX_PMU0_COUNTER_REG_1_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_1_LEN ); REG64_FLD( PU_NX_PMU0_COUNTER_REG_2 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_2 ); REG64_FLD( PU_NX_PMU0_COUNTER_REG_2_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_2_LEN ); REG64_FLD( PU_NX_PMU0_COUNTER_REG_3 , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_3 ); REG64_FLD( PU_NX_PMU0_COUNTER_REG_3_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_3_LEN ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_ENABLE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_FREEZE , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_FREEZE ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_RESET , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESET ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_DIS_GLOB_SCOM , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_DIS_GLOB_SCOM ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL0 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRESCALAR_SEL0 ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL0_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRESCALAR_SEL0_LEN ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL1 , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRESCALAR_SEL1 ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL1_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRESCALAR_SEL1_LEN ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL2 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRESCALAR_SEL2 ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL2_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRESCALAR_SEL2_LEN ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL3 , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRESCALAR_SEL3 ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_PRESCALAR_SEL3_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRESCALAR_SEL3_LEN ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT0_PAIR_OP , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT0_PAIR_OP ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT0_PAIR_OP_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT0_PAIR_OP_LEN ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT1_PAIR_OP , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT1_PAIR_OP ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT1_PAIR_OP_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT1_PAIR_OP_LEN ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT2_PAIR_OP , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT2_PAIR_OP ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT2_PAIR_OP_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT2_PAIR_OP_LEN ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT3_PAIR_OP , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT3_PAIR_OP ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT3_PAIR_OP_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT3_PAIR_OP_LEN ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT0_MUX_SEL , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT0_MUX_SEL ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT0_MUX_SEL_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT0_MUX_SEL_LEN ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT1_MUX_SEL , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT1_MUX_SEL ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT1_MUX_SEL_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT1_MUX_SEL_LEN ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT2_MUX_SEL , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT2_MUX_SEL ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT2_MUX_SEL_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT2_MUX_SEL_LEN ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT3_MUX_SEL , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT3_MUX_SEL ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_CNT3_MUX_SEL_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CNT3_MUX_SEL_LEN ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_FREEZE_ON_OVERFLOW , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_FREEZE_ON_OVERFLOW ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_CASCADE , 33 , SH_UNT , SH_ACS_SCOM , SH_FLD_CASCADE ); REG64_FLD( PU_NX_PMU1_CONTROL_REG_CASCADE_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CASCADE_LEN ); REG64_FLD( PU_NX_PMU1_COUNTER_REG_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( PU_NX_PMU1_COUNTER_REG_0_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_0_LEN ); REG64_FLD( PU_NX_PMU1_COUNTER_REG_1 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_1 ); REG64_FLD( PU_NX_PMU1_COUNTER_REG_1_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_1_LEN ); REG64_FLD( PU_NX_PMU1_COUNTER_REG_2 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_2 ); REG64_FLD( PU_NX_PMU1_COUNTER_REG_2_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_2_LEN ); REG64_FLD( PU_NX_PMU1_COUNTER_REG_3 , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_3 ); REG64_FLD( PU_NX_PMU1_COUNTER_REG_3_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_3_LEN ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT0_ENABLE , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT0_ENABLE ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT1_ENABLE , 1 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT1_ENABLE ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT2_ENABLE , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT2_ENABLE ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT3_ENABLE , 3 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT3_ENABLE ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_PRESCALER_SEL , 4 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_PRESCALER_SEL ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_PRESCALER_SEL_LEN , 3 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_PRESCALER_SEL_LEN ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT0_POSEDGE_SEL , 7 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT0_POSEDGE_SEL ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT1_POSEDGE_SEL , 8 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT1_POSEDGE_SEL ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT2_POSEDGE_SEL , 9 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT2_POSEDGE_SEL ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT3_POSEDGE_SEL , 10 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT3_POSEDGE_SEL ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_RESET , 11 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_RESET ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT0_EVENT_SEL , 12 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT0_EVENT_SEL ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT0_EVENT_SEL_LEN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT0_EVENT_SEL_LEN ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT0_BIT_PAIR_SEL , 14 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT0_BIT_PAIR_SEL ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT0_BIT_PAIR_SEL_LEN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT0_BIT_PAIR_SEL_LEN ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT1_EVENT_SEL , 16 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT1_EVENT_SEL ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT1_EVENT_SEL_LEN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT1_EVENT_SEL_LEN ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT1_BIT_PAIR_SEL , 18 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT1_BIT_PAIR_SEL ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT1_BIT_PAIR_SEL_LEN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT1_BIT_PAIR_SEL_LEN ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT2_EVENT_SEL , 20 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT2_EVENT_SEL ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT2_EVENT_SEL_LEN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT2_EVENT_SEL_LEN ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT2_BIT_PAIR_SEL , 22 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT2_BIT_PAIR_SEL ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT2_BIT_PAIR_SEL_LEN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT2_BIT_PAIR_SEL_LEN ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT3_EVENT_SEL , 24 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT3_EVENT_SEL ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT3_EVENT_SEL_LEN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT3_EVENT_SEL_LEN ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT3_BIT_PAIR_SEL , 26 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT3_BIT_PAIR_SEL ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_CNT3_BIT_PAIR_SEL_LEN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_CNT3_BIT_PAIR_SEL_LEN ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_PORT_SEL , 28 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_PORT_SEL ); REG64_FLD( PU_NMMU_NX_PMU_CONTROL_REG_PORT_SEL_LEN , 2 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_PORT_SEL_LEN ); REG64_FLD( PU_NMMU_NX_PMU_COUNTER_REG_0 , 0 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_0 ); REG64_FLD( PU_NMMU_NX_PMU_COUNTER_REG_0_LEN , 16 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_0_LEN ); REG64_FLD( PU_NMMU_NX_PMU_COUNTER_REG_1 , 16 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_1 ); REG64_FLD( PU_NMMU_NX_PMU_COUNTER_REG_1_LEN , 16 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_1_LEN ); REG64_FLD( PU_NMMU_NX_PMU_COUNTER_REG_2 , 32 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_2 ); REG64_FLD( PU_NMMU_NX_PMU_COUNTER_REG_2_LEN , 16 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_2_LEN ); REG64_FLD( PU_NMMU_NX_PMU_COUNTER_REG_3 , 48 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_3 ); REG64_FLD( PU_NMMU_NX_PMU_COUNTER_REG_3_LEN , 16 , SH_UNT_PU_NMMU , SH_ACS_SCOM , SH_FLD_3_LEN ); REG64_FLD( PU_NX_RNG_BYPASS_RRN_DATA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RRN_DATA ); REG64_FLD( PU_NX_RNG_BYPASS_RRN_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_RRN_DATA_LEN ); REG64_FLD( PU_NX_RNG_CFG_FAIL_REG , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_FAIL_REG ); REG64_FLD( PU_NX_RNG_CFG_FAIL_REG_LEN , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_FAIL_REG_LEN ); REG64_FLD( PU_NX_RNG_CFG_RNG0_FAIL , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_RNG0_FAIL ); REG64_FLD( PU_NX_RNG_CFG_RNG1_FAIL , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_RNG1_FAIL ); REG64_FLD( PU_NX_RNG_CFG_INTERRUPT_SENT , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_INTERRUPT_SENT ); REG64_FLD( PU_NX_RNG_CFG_BIST_ENABLE , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_BIST_ENABLE ); REG64_FLD( PU_NX_RNG_CFG_BIST_COMPLETE , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_BIST_COMPLETE ); REG64_FLD( PU_NX_RNG_CFG_RNG0_BIST_FAIL , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_RNG0_BIST_FAIL ); REG64_FLD( PU_NX_RNG_CFG_RNG1_BIST_FAIL , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_RNG1_BIST_FAIL ); REG64_FLD( PU_NX_RNG_CFG_BIST_BIT_FAIL_TH , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_BIST_BIT_FAIL_TH ); REG64_FLD( PU_NX_RNG_CFG_BIST_BIT_FAIL_TH_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_BIST_BIT_FAIL_TH_LEN ); REG64_FLD( PU_NX_RNG_CFG_RNG0_INJ_CONTINOUS_ERROR , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_RNG0_INJ_CONTINOUS_ERROR ); REG64_FLD( PU_NX_RNG_CFG_RNG1_INJ_CONTINOUS_ERROR , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_RNG1_INJ_CONTINOUS_ERROR ); REG64_FLD( PU_NX_RNG_CFG_ST2_RESET_PERIOD , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_ST2_RESET_PERIOD ); REG64_FLD( PU_NX_RNG_CFG_ST2_RESET_PERIOD_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_ST2_RESET_PERIOD_LEN ); REG64_FLD( PU_NX_RNG_CFG_RRN_BYPASS_ENABLE , 38 , SH_UNT , SH_ACS_SCOM , SH_FLD_RRN_BYPASS_ENABLE ); REG64_FLD( PU_NX_RNG_CFG_MASK_TOGGLE_ENABLE , 39 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASK_TOGGLE_ENABLE ); REG64_FLD( PU_NX_RNG_CFG_SAMPTEST_ENABLE , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_SAMPTEST_ENABLE ); REG64_FLD( PU_NX_RNG_CFG_REPTEST_ENABLE , 41 , SH_UNT , SH_ACS_SCOM , SH_FLD_REPTEST_ENABLE ); REG64_FLD( PU_NX_RNG_CFG_ADAPTEST_1BIT_ENABLE , 42 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_1BIT_ENABLE ); REG64_FLD( PU_NX_RNG_CFG_ADAPTEST_ENABLE , 43 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_ENABLE ); REG64_FLD( PU_NX_RNG_CFG_COND_STARTUP_TEST_FAIL , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_COND_STARTUP_TEST_FAIL ); REG64_FLD( PU_NX_RNG_CFG_PACE_RATE , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_PACE_RATE ); REG64_FLD( PU_NX_RNG_CFG_PACE_RATE_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_PACE_RATE_LEN ); REG64_FLD( PU_NX_RNG_CFG_ENABLE , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NX_RNG_RDELAY_CQ_FILL_THRESHOLD , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_FILL_THRESHOLD ); REG64_FLD( PU_NX_RNG_RDELAY_CQ_FILL_THRESHOLD_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_FILL_THRESHOLD_LEN ); REG64_FLD( PU_NX_RNG_RDELAY_CQ_DRAIN_THRESHOLD , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_DRAIN_THRESHOLD ); REG64_FLD( PU_NX_RNG_RDELAY_CQ_DRAIN_THRESHOLD_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_DRAIN_THRESHOLD_LEN ); REG64_FLD( PU_NX_RNG_RDELAY_CQ_LFSR_RESEED_EN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_LFSR_RESEED_EN ); REG64_FLD( PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_READ_RTY_RATIO ); REG64_FLD( PU_NX_RNG_RDELAY_CQ_READ_RTY_RATIO_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_READ_RTY_RATIO_LEN ); REG64_FLD( PU_NX_RNG_RESET_RESET , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESET ); REG64_FLD( PU_NX_RNG_ST0_REPTEST_MATCH_TH , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_REPTEST_MATCH_TH ); REG64_FLD( PU_NX_RNG_ST0_REPTEST_MATCH_TH_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_REPTEST_MATCH_TH_LEN ); REG64_FLD( PU_NX_RNG_ST0_REPTEST_SOFT_FAIL_TH , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_REPTEST_SOFT_FAIL_TH ); REG64_FLD( PU_NX_RNG_ST0_REPTEST_SOFT_FAIL_TH_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_REPTEST_SOFT_FAIL_TH_LEN ); REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_SAMPLE_SIZE ); REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_SAMPLE_SIZE_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_SAMPLE_SIZE_LEN ); REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_WINDOW_SIZE , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_WINDOW_SIZE ); REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_WINDOW_SIZE_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_WINDOW_SIZE_LEN ); REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_RRN_RNG0_MATCH_TH ); REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_RRN_RNG0_MATCH_TH_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_RRN_RNG0_MATCH_TH_LEN ); REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_RRN_RNG1_MATCH_TH ); REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_RRN_RNG1_MATCH_TH_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_RRN_RNG1_MATCH_TH_LEN ); REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH , 36 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_CRN_RNG0_MATCH_TH ); REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_CRN_RNG0_MATCH_TH_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_CRN_RNG0_MATCH_TH_LEN ); REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_CRN_RNG1_MATCH_TH ); REG64_FLD( PU_NX_RNG_ST0_ADAPTEST_CRN_RNG1_MATCH_TH_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_CRN_RNG1_MATCH_TH_LEN ); REG64_FLD( PU_NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_SOFT_FAIL_TH ); REG64_FLD( PU_NX_RNG_ST1_ADAPTEST_SOFT_FAIL_TH_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_SOFT_FAIL_TH_LEN ); REG64_FLD( PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_1BIT_MATCH_TH_MIN ); REG64_FLD( PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MIN_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_1BIT_MATCH_TH_MIN_LEN ); REG64_FLD( PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_1BIT_MATCH_TH_MAX ); REG64_FLD( PU_NX_RNG_ST1_ADAPTEST_1BIT_MATCH_TH_MAX_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_1BIT_MATCH_TH_MAX_LEN ); REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0 ); REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG0_LEN ); REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1 ); REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_RRN_RNG1_LEN ); REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0 ); REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG0_LEN ); REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1 , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1 ); REG64_FLD( PU_NX_RNG_ST2_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADAPTEST_SOFT_FAIL_COUNT_CRN_RNG1_LEN ); REG64_FLD( PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG0 ); REG64_FLD( PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG0_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG0_LEN ); REG64_FLD( PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG1 , 38 , SH_UNT , SH_ACS_SCOM , SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG1 ); REG64_FLD( PU_NX_RNG_ST2_REPTEST_SOFT_FAIL_COUNT_RNG1_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_REPTEST_SOFT_FAIL_COUNT_RNG1_LEN ); REG64_FLD( PU_NX_RNG_ST3_SAMPTEST_RRN_ENABLE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_SAMPTEST_RRN_ENABLE ); REG64_FLD( PU_NX_RNG_ST3_SAMPTEST_WINDOW_SIZE , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_SAMPTEST_WINDOW_SIZE ); REG64_FLD( PU_NX_RNG_ST3_SAMPTEST_WINDOW_SIZE_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_SAMPTEST_WINDOW_SIZE_LEN ); REG64_FLD( PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_SAMPTEST_MATCH_TH_MIN ); REG64_FLD( PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MIN_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_SAMPTEST_MATCH_TH_MIN_LEN ); REG64_FLD( PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_SAMPTEST_MATCH_TH_MAX ); REG64_FLD( PU_NX_RNG_ST3_SAMPTEST_MATCH_TH_MAX_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_SAMPTEST_MATCH_TH_MAX_LEN ); REG64_FLD( PU_NX_TRIGGER_CTRL_BITS , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BITS ); REG64_FLD( PU_NX_TRIGGER_CTRL_BITS_LEN , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BITS_LEN ); REG64_FLD( PU_OCB_OCI_CCSR_CORE_CONFIG , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CORE_CONFIG ); REG64_FLD( PU_OCB_OCI_CCSR_CORE_CONFIG_LEN , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CORE_CONFIG_LEN ); REG64_FLD( PU_OCB_OCI_CCSR_RESERVED_24 , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_24 ); REG64_FLD( PU_OCB_OCI_CCSR_RESERVED_24_LEN , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_24_LEN ); REG64_FLD( PU_OCB_OCI_CCSR_CHANGE_IN_PROGRESS , 31 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CHANGE_IN_PROGRESS ); REG64_FLD( PU_OCB_OCI_O2SCMD0A_O2SCMD_A_N_RESERVED_0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2SCMD_A_N_RESERVED_0 ); REG64_FLD( PU_OCB_OCI_O2SCMD0A_O2S_CLEAR_STICKY_BITS_A_N , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_CLEAR_STICKY_BITS_A_N ); REG64_FLD( PU_OCB_OCI_O2SCMD0B_O2SCMD_A_N_RESERVED_0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2SCMD_A_N_RESERVED_0 ); REG64_FLD( PU_OCB_OCI_O2SCMD0B_O2S_CLEAR_STICKY_BITS_A_N , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_CLEAR_STICKY_BITS_A_N ); REG64_FLD( PU_OCB_OCI_O2SCMD1A_O2SCMD_A_N_RESERVED_0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2SCMD_A_N_RESERVED_0 ); REG64_FLD( PU_OCB_OCI_O2SCMD1A_O2S_CLEAR_STICKY_BITS_A_N , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_CLEAR_STICKY_BITS_A_N ); REG64_FLD( PU_OCB_OCI_O2SCMD1B_O2SCMD_A_N_RESERVED_0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2SCMD_A_N_RESERVED_0 ); REG64_FLD( PU_OCB_OCI_O2SCMD1B_O2S_CLEAR_STICKY_BITS_A_N , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_CLEAR_STICKY_BITS_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL10A_O2S_BRIDGE_ENABLE_A_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_BRIDGE_ENABLE_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL10A_O2SCTRL1_A_N_RESERVED_1 , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2SCTRL1_A_N_RESERVED_1 ); REG64_FLD( PU_OCB_OCI_O2SCTRL10A_O2S_CPOL_A_N , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_CPOL_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL10A_O2S_CPHA_A_N , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_CPHA_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL10A_O2S_CLOCK_DIVIDER_A_N , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_CLOCK_DIVIDER_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL10A_O2S_CLOCK_DIVIDER_A_N_LEN , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRL10A_O2SCTRL1_A_N_RESERVED_14_16 , 14 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 ); REG64_FLD( PU_OCB_OCI_O2SCTRL10A_O2SCTRL1_A_N_RESERVED_14_16_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRL10A_O2S_NR_OF_FRAMES_A_N , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_NR_OF_FRAMES_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL10B_O2S_BRIDGE_ENABLE_A_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_BRIDGE_ENABLE_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL10B_O2SCTRL1_A_N_RESERVED_1 , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2SCTRL1_A_N_RESERVED_1 ); REG64_FLD( PU_OCB_OCI_O2SCTRL10B_O2S_CPOL_A_N , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_CPOL_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL10B_O2S_CPHA_A_N , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_CPHA_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL10B_O2S_CLOCK_DIVIDER_A_N , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_CLOCK_DIVIDER_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL10B_O2S_CLOCK_DIVIDER_A_N_LEN , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRL10B_O2SCTRL1_A_N_RESERVED_14_16 , 14 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 ); REG64_FLD( PU_OCB_OCI_O2SCTRL10B_O2SCTRL1_A_N_RESERVED_14_16_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRL10B_O2S_NR_OF_FRAMES_A_N , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_NR_OF_FRAMES_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL11A_O2S_BRIDGE_ENABLE_A_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_BRIDGE_ENABLE_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL11A_O2SCTRL1_A_N_RESERVED_1 , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2SCTRL1_A_N_RESERVED_1 ); REG64_FLD( PU_OCB_OCI_O2SCTRL11A_O2S_CPOL_A_N , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_CPOL_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL11A_O2S_CPHA_A_N , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_CPHA_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL11A_O2S_CLOCK_DIVIDER_A_N , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_CLOCK_DIVIDER_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL11A_O2S_CLOCK_DIVIDER_A_N_LEN , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRL11A_O2SCTRL1_A_N_RESERVED_14_16 , 14 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 ); REG64_FLD( PU_OCB_OCI_O2SCTRL11A_O2SCTRL1_A_N_RESERVED_14_16_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRL11A_O2S_NR_OF_FRAMES_A_N , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_NR_OF_FRAMES_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL11B_O2S_BRIDGE_ENABLE_A_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_BRIDGE_ENABLE_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL11B_O2SCTRL1_A_N_RESERVED_1 , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2SCTRL1_A_N_RESERVED_1 ); REG64_FLD( PU_OCB_OCI_O2SCTRL11B_O2S_CPOL_A_N , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_CPOL_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL11B_O2S_CPHA_A_N , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_CPHA_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL11B_O2S_CLOCK_DIVIDER_A_N , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_CLOCK_DIVIDER_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL11B_O2S_CLOCK_DIVIDER_A_N_LEN , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_CLOCK_DIVIDER_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRL11B_O2SCTRL1_A_N_RESERVED_14_16 , 14 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16 ); REG64_FLD( PU_OCB_OCI_O2SCTRL11B_O2SCTRL1_A_N_RESERVED_14_16_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2SCTRL1_A_N_RESERVED_14_16_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRL11B_O2S_NR_OF_FRAMES_A_N , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_NR_OF_FRAMES_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL20A_O2S_INTER_FRAME_DELAY_A_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_INTER_FRAME_DELAY_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL20A_O2S_INTER_FRAME_DELAY_A_N_LEN , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRL20B_O2S_INTER_FRAME_DELAY_A_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_INTER_FRAME_DELAY_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL20B_O2S_INTER_FRAME_DELAY_A_N_LEN , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRL21A_O2S_INTER_FRAME_DELAY_A_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_INTER_FRAME_DELAY_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL21A_O2S_INTER_FRAME_DELAY_A_N_LEN , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRL21B_O2S_INTER_FRAME_DELAY_A_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_INTER_FRAME_DELAY_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRL21B_O2S_INTER_FRAME_DELAY_A_N_LEN , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_INTER_FRAME_DELAY_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLF0A_O2S_FRAME_SIZE_A_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_FRAME_SIZE_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLF0A_O2S_FRAME_SIZE_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_FRAME_SIZE_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLF0A_O2S_OUT_COUNT1_A_N , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_OUT_COUNT1_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLF0A_O2S_OUT_COUNT1_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_OUT_COUNT1_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLF0A_O2S_IN_DELAY1_A_N , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_DELAY1_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLF0A_O2S_IN_DELAY1_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_DELAY1_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLF0A_O2S_IN_COUNT1_A_N , 18 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_COUNT1_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLF0A_O2S_IN_COUNT1_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_COUNT1_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLF0B_O2S_FRAME_SIZE_A_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_FRAME_SIZE_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLF0B_O2S_FRAME_SIZE_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_FRAME_SIZE_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLF0B_O2S_OUT_COUNT1_A_N , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_OUT_COUNT1_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLF0B_O2S_OUT_COUNT1_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_OUT_COUNT1_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLF0B_O2S_IN_DELAY1_A_N , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_DELAY1_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLF0B_O2S_IN_DELAY1_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_DELAY1_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLF0B_O2S_IN_COUNT1_A_N , 18 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_COUNT1_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLF0B_O2S_IN_COUNT1_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_COUNT1_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLF1A_O2S_FRAME_SIZE_A_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_FRAME_SIZE_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLF1A_O2S_FRAME_SIZE_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_FRAME_SIZE_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLF1A_O2S_OUT_COUNT1_A_N , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_OUT_COUNT1_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLF1A_O2S_OUT_COUNT1_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_OUT_COUNT1_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLF1A_O2S_IN_DELAY1_A_N , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_DELAY1_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLF1A_O2S_IN_DELAY1_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_DELAY1_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLF1A_O2S_IN_COUNT1_A_N , 18 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_COUNT1_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLF1A_O2S_IN_COUNT1_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_COUNT1_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLF1B_O2S_FRAME_SIZE_A_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_FRAME_SIZE_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLF1B_O2S_FRAME_SIZE_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_FRAME_SIZE_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLF1B_O2S_OUT_COUNT1_A_N , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_OUT_COUNT1_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLF1B_O2S_OUT_COUNT1_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_OUT_COUNT1_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLF1B_O2S_IN_DELAY1_A_N , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_DELAY1_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLF1B_O2S_IN_DELAY1_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_DELAY1_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLF1B_O2S_IN_COUNT1_A_N , 18 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_COUNT1_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLF1B_O2S_IN_COUNT1_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_COUNT1_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLS0A_O2S_OUT_COUNT2_A_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_OUT_COUNT2_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLS0A_O2S_OUT_COUNT2_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_OUT_COUNT2_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLS0A_O2S_IN_DELAY2_A_N , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_DELAY2_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLS0A_O2S_IN_DELAY2_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_DELAY2_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLS0A_O2S_IN_COUNT2_A_N , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_COUNT2_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLS0A_O2S_IN_COUNT2_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_COUNT2_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLS0B_O2S_OUT_COUNT2_A_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_OUT_COUNT2_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLS0B_O2S_OUT_COUNT2_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_OUT_COUNT2_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLS0B_O2S_IN_DELAY2_A_N , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_DELAY2_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLS0B_O2S_IN_DELAY2_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_DELAY2_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLS0B_O2S_IN_COUNT2_A_N , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_COUNT2_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLS0B_O2S_IN_COUNT2_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_COUNT2_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLS1A_O2S_OUT_COUNT2_A_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_OUT_COUNT2_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLS1A_O2S_OUT_COUNT2_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_OUT_COUNT2_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLS1A_O2S_IN_DELAY2_A_N , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_DELAY2_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLS1A_O2S_IN_DELAY2_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_DELAY2_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLS1A_O2S_IN_COUNT2_A_N , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_COUNT2_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLS1A_O2S_IN_COUNT2_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_COUNT2_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLS1B_O2S_OUT_COUNT2_A_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_OUT_COUNT2_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLS1B_O2S_OUT_COUNT2_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_OUT_COUNT2_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLS1B_O2S_IN_DELAY2_A_N , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_DELAY2_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLS1B_O2S_IN_DELAY2_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_DELAY2_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SCTRLS1B_O2S_IN_COUNT2_A_N , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_COUNT2_A_N ); REG64_FLD( PU_OCB_OCI_O2SCTRLS1B_O2S_IN_COUNT2_A_N_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_IN_COUNT2_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SRD0A_O2S_RDATA_A_N , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2S_RDATA_A_N ); REG64_FLD( PU_OCB_OCI_O2SRD0A_O2S_RDATA_A_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2S_RDATA_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SRD0B_O2S_RDATA_A_N , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2S_RDATA_A_N ); REG64_FLD( PU_OCB_OCI_O2SRD0B_O2S_RDATA_A_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2S_RDATA_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SRD1A_O2S_RDATA_A_N , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2S_RDATA_A_N ); REG64_FLD( PU_OCB_OCI_O2SRD1A_O2S_RDATA_A_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2S_RDATA_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SRD1B_O2S_RDATA_A_N , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2S_RDATA_A_N ); REG64_FLD( PU_OCB_OCI_O2SRD1B_O2S_RDATA_A_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2S_RDATA_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SST0A_O2S_ONGOING_A_N , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2S_ONGOING_A_N ); REG64_FLD( PU_OCB_OCI_O2SST0A_O2SST_A_N_RESERVED_1_4 , 1 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2SST_A_N_RESERVED_1_4 ); REG64_FLD( PU_OCB_OCI_O2SST0A_O2SST_A_N_RESERVED_1_4_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2SST_A_N_RESERVED_1_4_LEN ); REG64_FLD( PU_OCB_OCI_O2SST0A_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N , 5 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N ); REG64_FLD( PU_OCB_OCI_O2SST0A_O2SST_A_N_RESERVED_6 , 6 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2SST_A_N_RESERVED_6 ); REG64_FLD( PU_OCB_OCI_O2SST0A_O2S_FSM_ERR_A_N , 7 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2S_FSM_ERR_A_N ); REG64_FLD( PU_OCB_OCI_O2SST0B_O2S_ONGOING_A_N , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2S_ONGOING_A_N ); REG64_FLD( PU_OCB_OCI_O2SST0B_O2SST_A_N_RESERVED_1_4 , 1 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2SST_A_N_RESERVED_1_4 ); REG64_FLD( PU_OCB_OCI_O2SST0B_O2SST_A_N_RESERVED_1_4_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2SST_A_N_RESERVED_1_4_LEN ); REG64_FLD( PU_OCB_OCI_O2SST0B_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N , 5 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N ); REG64_FLD( PU_OCB_OCI_O2SST0B_O2SST_A_N_RESERVED_6 , 6 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2SST_A_N_RESERVED_6 ); REG64_FLD( PU_OCB_OCI_O2SST0B_O2S_FSM_ERR_A_N , 7 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2S_FSM_ERR_A_N ); REG64_FLD( PU_OCB_OCI_O2SST1A_O2S_ONGOING_A_N , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2S_ONGOING_A_N ); REG64_FLD( PU_OCB_OCI_O2SST1A_O2SST_A_N_RESERVED_1_4 , 1 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2SST_A_N_RESERVED_1_4 ); REG64_FLD( PU_OCB_OCI_O2SST1A_O2SST_A_N_RESERVED_1_4_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2SST_A_N_RESERVED_1_4_LEN ); REG64_FLD( PU_OCB_OCI_O2SST1A_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N , 5 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N ); REG64_FLD( PU_OCB_OCI_O2SST1A_O2SST_A_N_RESERVED_6 , 6 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2SST_A_N_RESERVED_6 ); REG64_FLD( PU_OCB_OCI_O2SST1A_O2S_FSM_ERR_A_N , 7 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2S_FSM_ERR_A_N ); REG64_FLD( PU_OCB_OCI_O2SST1B_O2S_ONGOING_A_N , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2S_ONGOING_A_N ); REG64_FLD( PU_OCB_OCI_O2SST1B_O2SST_A_N_RESERVED_1_4 , 1 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2SST_A_N_RESERVED_1_4 ); REG64_FLD( PU_OCB_OCI_O2SST1B_O2SST_A_N_RESERVED_1_4_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2SST_A_N_RESERVED_1_4_LEN ); REG64_FLD( PU_OCB_OCI_O2SST1B_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N , 5 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR_A_N ); REG64_FLD( PU_OCB_OCI_O2SST1B_O2SST_A_N_RESERVED_6 , 6 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2SST_A_N_RESERVED_6 ); REG64_FLD( PU_OCB_OCI_O2SST1B_O2S_FSM_ERR_A_N , 7 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_O2S_FSM_ERR_A_N ); REG64_FLD( PU_OCB_OCI_O2SWD0A_O2S_WDATA_A_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_WDATA_A_N ); REG64_FLD( PU_OCB_OCI_O2SWD0A_O2S_WDATA_A_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_WDATA_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SWD0B_O2S_WDATA_A_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_WDATA_A_N ); REG64_FLD( PU_OCB_OCI_O2SWD0B_O2S_WDATA_A_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_WDATA_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SWD1A_O2S_WDATA_A_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_WDATA_A_N ); REG64_FLD( PU_OCB_OCI_O2SWD1A_O2S_WDATA_A_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_WDATA_A_N_LEN ); REG64_FLD( PU_OCB_OCI_O2SWD1B_O2S_WDATA_A_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_WDATA_A_N ); REG64_FLD( PU_OCB_OCI_O2SWD1B_O2S_WDATA_A_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_O2S_WDATA_A_N_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_ENABLE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_ENABLE ); REG64_FLD( PU_OCB_OCI_OCBLWCR0_SPARE_0 , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SPARE_0 ); REG64_FLD( PU_OCB_OCI_OCBLWCR0_SPARE_0_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SPARE_0_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_BAR , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_BAR ); REG64_FLD( PU_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_BAR_LEN , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_BAR_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_MASK , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_MASK ); REG64_FLD( PU_OCB_OCI_OCBLWCR0_LINEAR_WINDOW_MASK_LEN , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_MASK_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_ENABLE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_ENABLE ); REG64_FLD( PU_OCB_OCI_OCBLWCR1_SPARE_0 , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SPARE_0 ); REG64_FLD( PU_OCB_OCI_OCBLWCR1_SPARE_0_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SPARE_0_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_BAR , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_BAR ); REG64_FLD( PU_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_BAR_LEN , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_BAR_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_MASK , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_MASK ); REG64_FLD( PU_OCB_OCI_OCBLWCR1_LINEAR_WINDOW_MASK_LEN , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_MASK_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_ENABLE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_ENABLE ); REG64_FLD( PU_OCB_OCI_OCBLWCR2_SPARE_0 , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SPARE_0 ); REG64_FLD( PU_OCB_OCI_OCBLWCR2_SPARE_0_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SPARE_0_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_BAR , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_BAR ); REG64_FLD( PU_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_BAR_LEN , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_BAR_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_MASK , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_MASK ); REG64_FLD( PU_OCB_OCI_OCBLWCR2_LINEAR_WINDOW_MASK_LEN , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_MASK_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_ENABLE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_ENABLE ); REG64_FLD( PU_OCB_OCI_OCBLWCR3_SPARE_0 , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SPARE_0 ); REG64_FLD( PU_OCB_OCI_OCBLWCR3_SPARE_0_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SPARE_0_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_BAR , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_BAR ); REG64_FLD( PU_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_BAR_LEN , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_BAR_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_MASK , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_MASK ); REG64_FLD( PU_OCB_OCI_OCBLWCR3_LINEAR_WINDOW_MASK_LEN , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_MASK_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_REGION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_REGION ); REG64_FLD( PU_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_REGION_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_REGION_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_BASE , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_BASE ); REG64_FLD( PU_OCB_OCI_OCBLWSBR0_LINEAR_WINDOW_BASE_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_BASE_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_REGION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_REGION ); REG64_FLD( PU_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_REGION_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_REGION_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_BASE , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_BASE ); REG64_FLD( PU_OCB_OCI_OCBLWSBR1_LINEAR_WINDOW_BASE_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_BASE_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_REGION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_REGION ); REG64_FLD( PU_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_REGION_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_REGION_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_BASE , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_BASE ); REG64_FLD( PU_OCB_OCI_OCBLWSBR2_LINEAR_WINDOW_BASE_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_BASE_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_REGION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_REGION ); REG64_FLD( PU_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_REGION_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_REGION_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_BASE , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_BASE ); REG64_FLD( PU_OCB_OCI_OCBLWSBR3_LINEAR_WINDOW_BASE_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINEAR_WINDOW_BASE_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWSR0_LINEAR_WINDOW_SCRESP , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LINEAR_WINDOW_SCRESP ); REG64_FLD( PU_OCB_OCI_OCBLWSR0_LINEAR_WINDOW_SCRESP_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LINEAR_WINDOW_SCRESP_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWSR0_SPARE0 , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SPARE0 ); REG64_FLD( PU_OCB_OCI_OCBLWSR0_SPARE0_LEN , 5 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SPARE0_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWSR1_LINEAR_WINDOW_SCRESP , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LINEAR_WINDOW_SCRESP ); REG64_FLD( PU_OCB_OCI_OCBLWSR1_LINEAR_WINDOW_SCRESP_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LINEAR_WINDOW_SCRESP_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWSR1_SPARE0 , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SPARE0 ); REG64_FLD( PU_OCB_OCI_OCBLWSR1_SPARE0_LEN , 5 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SPARE0_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWSR2_LINEAR_WINDOW_SCRESP , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LINEAR_WINDOW_SCRESP ); REG64_FLD( PU_OCB_OCI_OCBLWSR2_LINEAR_WINDOW_SCRESP_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LINEAR_WINDOW_SCRESP_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWSR2_SPARE0 , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SPARE0 ); REG64_FLD( PU_OCB_OCI_OCBLWSR2_SPARE0_LEN , 5 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SPARE0_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWSR3_LINEAR_WINDOW_SCRESP , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LINEAR_WINDOW_SCRESP ); REG64_FLD( PU_OCB_OCI_OCBLWSR3_LINEAR_WINDOW_SCRESP_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LINEAR_WINDOW_SCRESP_LEN ); REG64_FLD( PU_OCB_OCI_OCBLWSR3_SPARE0 , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SPARE0 ); REG64_FLD( PU_OCB_OCI_OCBLWSR3_SPARE0_LEN , 5 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SPARE0_LEN ); REG64_FLD( PU_OCB_OCI_OCBSES0_PUSH_READ_UNDERFLOW , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PUSH_READ_UNDERFLOW ); REG64_FLD( PU_OCB_OCI_OCBSES0_PULL_WRITE_OVERFLOW , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PULL_WRITE_OVERFLOW ); REG64_FLD( PU_OCB_OCI_OCBSES1_PUSH_READ_UNDERFLOW , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PUSH_READ_UNDERFLOW ); REG64_FLD( PU_OCB_OCI_OCBSES1_PULL_WRITE_OVERFLOW , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PULL_WRITE_OVERFLOW ); REG64_FLD( PU_OCB_OCI_OCBSES2_PUSH_READ_UNDERFLOW , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PUSH_READ_UNDERFLOW ); REG64_FLD( PU_OCB_OCI_OCBSES2_PULL_WRITE_OVERFLOW , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PULL_WRITE_OVERFLOW ); REG64_FLD( PU_OCB_OCI_OCBSES3_PUSH_READ_UNDERFLOW , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PUSH_READ_UNDERFLOW ); REG64_FLD( PU_OCB_OCI_OCBSES3_PULL_WRITE_OVERFLOW , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PULL_WRITE_OVERFLOW ); REG64_FLD( PU_OCB_OCI_OCBSHBR0_PUSH_REGION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PUSH_REGION ); REG64_FLD( PU_OCB_OCI_OCBSHBR0_PUSH_REGION_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PUSH_REGION_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHBR0_PUSH_START , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PUSH_START ); REG64_FLD( PU_OCB_OCI_OCBSHBR0_PUSH_START_LEN , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PUSH_START_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHBR1_PUSH_REGION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PUSH_REGION ); REG64_FLD( PU_OCB_OCI_OCBSHBR1_PUSH_REGION_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PUSH_REGION_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHBR1_PUSH_START , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PUSH_START ); REG64_FLD( PU_OCB_OCI_OCBSHBR1_PUSH_START_LEN , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PUSH_START_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHBR2_PUSH_REGION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PUSH_REGION ); REG64_FLD( PU_OCB_OCI_OCBSHBR2_PUSH_REGION_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PUSH_REGION_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHBR2_PUSH_START , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PUSH_START ); REG64_FLD( PU_OCB_OCI_OCBSHBR2_PUSH_START_LEN , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PUSH_START_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHBR3_PUSH_REGION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PUSH_REGION ); REG64_FLD( PU_OCB_OCI_OCBSHBR3_PUSH_REGION_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PUSH_REGION_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHBR3_PUSH_START , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PUSH_START ); REG64_FLD( PU_OCB_OCI_OCBSHBR3_PUSH_START_LEN , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PUSH_START_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_FULL , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_FULL ); REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_EMPTY , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_EMPTY ); REG64_FLD( PU_OCB_OCI_OCBSHCS0_SPARE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE ); REG64_FLD( PU_OCB_OCI_OCBSHCS0_SPARE_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_INTR_ACTION_0_1 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_INTR_ACTION_0_1 ); REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_INTR_ACTION_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_INTR_ACTION_0_1_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_LENGTH , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_LENGTH ); REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_LENGTH_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_LENGTH_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_WRITE_PTR , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_WRITE_PTR ); REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_WRITE_PTR_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_WRITE_PTR_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_READ_PTR , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_READ_PTR ); REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_READ_PTR_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_READ_PTR_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHCS0_PUSH_ENABLE , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_ENABLE ); REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_FULL , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_FULL ); REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_EMPTY , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_EMPTY ); REG64_FLD( PU_OCB_OCI_OCBSHCS1_SPARE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE ); REG64_FLD( PU_OCB_OCI_OCBSHCS1_SPARE_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_INTR_ACTION_0_1 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_INTR_ACTION_0_1 ); REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_INTR_ACTION_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_INTR_ACTION_0_1_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_LENGTH , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_LENGTH ); REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_LENGTH_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_LENGTH_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_WRITE_PTR , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_WRITE_PTR ); REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_WRITE_PTR_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_WRITE_PTR_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_READ_PTR , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_READ_PTR ); REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_READ_PTR_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_READ_PTR_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHCS1_PUSH_ENABLE , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_ENABLE ); REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_FULL , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_FULL ); REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_EMPTY , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_EMPTY ); REG64_FLD( PU_OCB_OCI_OCBSHCS2_SPARE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE ); REG64_FLD( PU_OCB_OCI_OCBSHCS2_SPARE_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_INTR_ACTION_0_1 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_INTR_ACTION_0_1 ); REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_INTR_ACTION_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_INTR_ACTION_0_1_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_LENGTH , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_LENGTH ); REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_LENGTH_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_LENGTH_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_WRITE_PTR , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_WRITE_PTR ); REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_WRITE_PTR_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_WRITE_PTR_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_READ_PTR , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_READ_PTR ); REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_READ_PTR_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_READ_PTR_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHCS2_PUSH_ENABLE , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_ENABLE ); REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_FULL , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_FULL ); REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_EMPTY , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_EMPTY ); REG64_FLD( PU_OCB_OCI_OCBSHCS3_SPARE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE ); REG64_FLD( PU_OCB_OCI_OCBSHCS3_SPARE_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_INTR_ACTION_0_1 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_INTR_ACTION_0_1 ); REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_INTR_ACTION_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_INTR_ACTION_0_1_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_LENGTH , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_LENGTH ); REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_LENGTH_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_LENGTH_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_WRITE_PTR , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_WRITE_PTR ); REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_WRITE_PTR_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_WRITE_PTR_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_READ_PTR , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_READ_PTR ); REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_READ_PTR_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_READ_PTR_LEN ); REG64_FLD( PU_OCB_OCI_OCBSHCS3_PUSH_ENABLE , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_PUSH_ENABLE ); REG64_FLD( PU_OCB_OCI_OCBSLBR0_PULL_REGION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PULL_REGION ); REG64_FLD( PU_OCB_OCI_OCBSLBR0_PULL_REGION_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PULL_REGION_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLBR0_PULL_START , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PULL_START ); REG64_FLD( PU_OCB_OCI_OCBSLBR0_PULL_START_LEN , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PULL_START_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLBR1_PULL_REGION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PULL_REGION ); REG64_FLD( PU_OCB_OCI_OCBSLBR1_PULL_REGION_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PULL_REGION_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLBR1_PULL_START , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PULL_START ); REG64_FLD( PU_OCB_OCI_OCBSLBR1_PULL_START_LEN , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PULL_START_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLBR2_PULL_REGION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PULL_REGION ); REG64_FLD( PU_OCB_OCI_OCBSLBR2_PULL_REGION_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PULL_REGION_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLBR2_PULL_START , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PULL_START ); REG64_FLD( PU_OCB_OCI_OCBSLBR2_PULL_START_LEN , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PULL_START_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLBR3_PULL_REGION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PULL_REGION ); REG64_FLD( PU_OCB_OCI_OCBSLBR3_PULL_REGION_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PULL_REGION_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLBR3_PULL_START , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PULL_START ); REG64_FLD( PU_OCB_OCI_OCBSLBR3_PULL_START_LEN , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PULL_START_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_FULL , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_FULL ); REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_EMPTY , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_EMPTY ); REG64_FLD( PU_OCB_OCI_OCBSLCS0_SPARE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE ); REG64_FLD( PU_OCB_OCI_OCBSLCS0_SPARE_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_INTR_ACTION_0_1 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_INTR_ACTION_0_1 ); REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_INTR_ACTION_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_INTR_ACTION_0_1_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_LENGTH , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_LENGTH ); REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_LENGTH_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_LENGTH_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_WRITE_PTR , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_WRITE_PTR ); REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_WRITE_PTR_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_WRITE_PTR_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_READ_PTR , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_READ_PTR ); REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_READ_PTR_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_READ_PTR_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLCS0_PULL_ENABLE , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_ENABLE ); REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_FULL , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_FULL ); REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_EMPTY , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_EMPTY ); REG64_FLD( PU_OCB_OCI_OCBSLCS1_SPARE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE ); REG64_FLD( PU_OCB_OCI_OCBSLCS1_SPARE_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_INTR_ACTION_0_1 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_INTR_ACTION_0_1 ); REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_INTR_ACTION_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_INTR_ACTION_0_1_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_LENGTH , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_LENGTH ); REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_LENGTH_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_LENGTH_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_WRITE_PTR , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_WRITE_PTR ); REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_WRITE_PTR_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_WRITE_PTR_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_READ_PTR , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_READ_PTR ); REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_READ_PTR_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_READ_PTR_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLCS1_PULL_ENABLE , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_ENABLE ); REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_FULL , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_FULL ); REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_EMPTY , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_EMPTY ); REG64_FLD( PU_OCB_OCI_OCBSLCS2_SPARE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE ); REG64_FLD( PU_OCB_OCI_OCBSLCS2_SPARE_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_INTR_ACTION_0_1 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_INTR_ACTION_0_1 ); REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_INTR_ACTION_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_INTR_ACTION_0_1_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_LENGTH , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_LENGTH ); REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_LENGTH_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_LENGTH_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_WRITE_PTR , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_WRITE_PTR ); REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_WRITE_PTR_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_WRITE_PTR_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_READ_PTR , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_READ_PTR ); REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_READ_PTR_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_READ_PTR_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLCS2_PULL_ENABLE , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_ENABLE ); REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_FULL , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_FULL ); REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_EMPTY , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_EMPTY ); REG64_FLD( PU_OCB_OCI_OCBSLCS3_SPARE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE ); REG64_FLD( PU_OCB_OCI_OCBSLCS3_SPARE_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_INTR_ACTION_0_1 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_INTR_ACTION_0_1 ); REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_INTR_ACTION_0_1_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_INTR_ACTION_0_1_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_LENGTH , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_LENGTH ); REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_LENGTH_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_LENGTH_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_WRITE_PTR , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_WRITE_PTR ); REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_WRITE_PTR_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_WRITE_PTR_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_READ_PTR , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_READ_PTR ); REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_READ_PTR_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_READ_PTR_LEN ); REG64_FLD( PU_OCB_OCI_OCBSLCS3_PULL_ENABLE , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_PULL_ENABLE ); REG64_FLD( PU_OCB_OCI_OCCFLG_OCC_FLAGS , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCC_FLAGS ); REG64_FLD( PU_OCB_OCI_OCCFLG_OCC_FLAGS_LEN , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCC_FLAGS_LEN ); REG64_FLD( PU_OCB_OCI_OCCHBR_OCC_HEARTBEAT_COUNT , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCC_HEARTBEAT_COUNT ); REG64_FLD( PU_OCB_OCI_OCCHBR_OCC_HEARTBEAT_COUNT_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCC_HEARTBEAT_COUNT_LEN ); REG64_FLD( PU_OCB_OCI_OCCHBR_OCC_HEARTBEAT_EN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCC_HEARTBEAT_EN ); REG64_FLD( PU_OCB_OCI_OCCMISC_CORE_EXT_INTR , 0 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_CORE_EXT_INTR ); REG64_FLD( PU_OCB_OCI_OCCMISC_SPARE_1_3 , 1 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_SPARE_1_3 ); REG64_FLD( PU_OCB_OCI_OCCMISC_SPARE_1_3_LEN , 3 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_SPARE_1_3_LEN ); REG64_FLD( PU_OCB_OCI_OCCMISC_PVREF_ERROR_EN , 4 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PVREF_ERROR_EN ); REG64_FLD( PU_OCB_OCI_OCCMISC_PVREF_ERROR_EN_LEN , 2 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PVREF_ERROR_EN_LEN ); REG64_FLD( PU_OCB_OCI_OCCMISC_PVREF_ERROR_GROSS , 6 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PVREF_ERROR_GROSS ); REG64_FLD( PU_OCB_OCI_OCCMISC_PVREF_ERROR_FINE , 7 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PVREF_ERROR_FINE ); REG64_FLD( PU_OCB_OCI_OCCMISC_FIRMWARE_FAULT , 8 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_FIRMWARE_FAULT ); REG64_FLD( PU_OCB_OCI_OCCMISC_FIRMWARE_NOTIFY , 9 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_FIRMWARE_NOTIFY ); REG64_FLD( PU_OCB_OCI_OCCMISC_SPARE , 10 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_SPARE ); REG64_FLD( PU_OCB_OCI_OCCMISC_SPARE_LEN , 6 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_SPARE_LEN ); REG64_FLD( PU_OCB_OCI_OCCMISC_I2CM_INTR_STATUS , 16 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_I2CM_INTR_STATUS ); REG64_FLD( PU_OCB_OCI_OCCMISC_I2CM_INTR_STATUS_LEN , 3 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_I2CM_INTR_STATUS_LEN ); REG64_FLD( PU_OCB_OCI_OCCS0_OCC_SCRATCH_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCC_SCRATCH_N ); REG64_FLD( PU_OCB_OCI_OCCS0_OCC_SCRATCH_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCC_SCRATCH_N_LEN ); REG64_FLD( PU_OCB_OCI_OCCS1_OCC_SCRATCH_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCC_SCRATCH_N ); REG64_FLD( PU_OCB_OCI_OCCS1_OCC_SCRATCH_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCC_SCRATCH_N_LEN ); REG64_FLD( PU_OCB_OCI_OCCS2_OCC_SCRATCH_N , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCC_SCRATCH_N ); REG64_FLD( PU_OCB_OCI_OCCS2_OCC_SCRATCH_N_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCC_SCRATCH_N_LEN ); REG64_FLD( PU_OCB_OCI_OCICFG_M0_PRIORITY , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M0_PRIORITY ); REG64_FLD( PU_OCB_OCI_OCICFG_M0_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M0_PRIORITY_LEN ); REG64_FLD( PU_OCB_OCI_OCICFG_M1_PRIORITY , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M1_PRIORITY ); REG64_FLD( PU_OCB_OCI_OCICFG_M1_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M1_PRIORITY_LEN ); REG64_FLD( PU_OCB_OCI_OCICFG_M2_PRIORITY , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M2_PRIORITY ); REG64_FLD( PU_OCB_OCI_OCICFG_M2_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M2_PRIORITY_LEN ); REG64_FLD( PU_OCB_OCI_OCICFG_M3_PRIORITY , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M3_PRIORITY ); REG64_FLD( PU_OCB_OCI_OCICFG_M3_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M3_PRIORITY_LEN ); REG64_FLD( PU_OCB_OCI_OCICFG_M4_PRIORITY , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M4_PRIORITY ); REG64_FLD( PU_OCB_OCI_OCICFG_M4_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M4_PRIORITY_LEN ); REG64_FLD( PU_OCB_OCI_OCICFG_M5_PRIORITY , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M5_PRIORITY ); REG64_FLD( PU_OCB_OCI_OCICFG_M5_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M5_PRIORITY_LEN ); REG64_FLD( PU_OCB_OCI_OCICFG_M6_PRIORITY , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M6_PRIORITY ); REG64_FLD( PU_OCB_OCI_OCICFG_M6_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M6_PRIORITY_LEN ); REG64_FLD( PU_OCB_OCI_OCICFG_M7_PRIORITY , 14 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M7_PRIORITY ); REG64_FLD( PU_OCB_OCI_OCICFG_M7_PRIORITY_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M7_PRIORITY_LEN ); REG64_FLD( PU_OCB_OCI_OCICFG_M0_PRIORITY_SEL , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M0_PRIORITY_SEL ); REG64_FLD( PU_OCB_OCI_OCICFG_M1_PRIORITY_SEL , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M1_PRIORITY_SEL ); REG64_FLD( PU_OCB_OCI_OCICFG_M2_PRIORITY_SEL , 18 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M2_PRIORITY_SEL ); REG64_FLD( PU_OCB_OCI_OCICFG_M3_PRIORITY_SEL , 19 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M3_PRIORITY_SEL ); REG64_FLD( PU_OCB_OCI_OCICFG_OCICFG_RESERVED_20 , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCICFG_RESERVED_20 ); REG64_FLD( PU_OCB_OCI_OCICFG_M5_PRIORITY_SEL , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M5_PRIORITY_SEL ); REG64_FLD( PU_OCB_OCI_OCICFG_OCICFG_RESERVED_23 , 22 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCICFG_RESERVED_23 ); REG64_FLD( PU_OCB_OCI_OCICFG_M7_PRIORITY_SEL , 23 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_M7_PRIORITY_SEL ); REG64_FLD( PU_OCB_OCI_OCICFG_PLBARB_LOCKERR , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PLBARB_LOCKERR ); REG64_FLD( PU_OCB_OCI_OCICFG_SPARE_24_31 , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SPARE_24_31 ); REG64_FLD( PU_OCB_OCI_OCICFG_SPARE_24_31_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SPARE_24_31_LEN ); REG64_FLD( PU_OCB_OCI_OEHDR_EVENT2HALT_DELAY , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EVENT2HALT_DELAY ); REG64_FLD( PU_OCB_OCI_OEHDR_EVENT2HALT_DELAY_LEN , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EVENT2HALT_DELAY_LEN ); REG64_FLD( PU_OCB_OCI_OHTMCR_HTM_SRC_SEL , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HTM_SRC_SEL ); REG64_FLD( PU_OCB_OCI_OHTMCR_HTM_SRC_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_HTM_SRC_SEL_LEN ); REG64_FLD( PU_OCB_OCI_OHTMCR_HTM_STOP , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_HTM_STOP ); REG64_FLD( PU_OCB_OCI_OHTMCR_HTM_MARKER_SLAVE_ADRS , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_HTM_MARKER_SLAVE_ADRS ); REG64_FLD( PU_OCB_OCI_OHTMCR_HTM_MARKER_SLAVE_ADRS_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_HTM_MARKER_SLAVE_ADRS_LEN ); REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_MODE , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_EVENT2HALT_MODE ); REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_MODE_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_EVENT2HALT_MODE_LEN ); REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_EN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_EVENT2HALT_EN ); REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_EN_LEN , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_EVENT2HALT_EN_LEN ); REG64_FLD( PU_OCB_OCI_OHTMCR_HTM_GPE_SRC_SEL , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_HTM_GPE_SRC_SEL ); REG64_FLD( PU_OCB_OCI_OHTMCR_HTM_GPE_SRC_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_HTM_GPE_SRC_SEL_LEN ); REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_OCC , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_EVENT2HALT_OCC ); REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_GPE0 , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_EVENT2HALT_GPE0 ); REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_GPE1 , 25 , SH_UNT , SH_ACS_SCOM , SH_FLD_EVENT2HALT_GPE1 ); REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_GPE2 , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_EVENT2HALT_GPE2 ); REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_GPE3 , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_EVENT2HALT_GPE3 ); REG64_FLD( PU_OCB_OCI_OHTMCR_EVENT2HALT_HALT_STATE , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_EVENT2HALT_HALT_STATE ); REG64_FLD( PU_OCB_OCI_OIEPR0_INTERRUPT_EDGE_POL_N , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_EDGE_POL_N ); REG64_FLD( PU_OCB_OCI_OIEPR0_INTERRUPT_EDGE_POL_N_LEN , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_EDGE_POL_N_LEN ); REG64_FLD( PU_OCB_OCI_OIEPR1_INTERRUPT_EDGE_POL_N , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_EDGE_POL_N ); REG64_FLD( PU_OCB_OCI_OIEPR1_INTERRUPT_EDGE_POL_N_LEN , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_EDGE_POL_N_LEN ); REG64_FLD( PU_OCB_OCI_OIMR0_INTERRUPT_MASK_N , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_MASK_N ); REG64_FLD( PU_OCB_OCI_OIMR0_INTERRUPT_MASK_N_LEN , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_MASK_N_LEN ); REG64_FLD( PU_OCB_OCI_OIMR1_INTERRUPT_MASK_N , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_MASK_N ); REG64_FLD( PU_OCB_OCI_OIMR1_INTERRUPT_MASK_N_LEN , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_MASK_N_LEN ); REG64_FLD( PU_OCB_OCI_OIRR0A_INTERRUPT_ROUTE_A_N , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N ); REG64_FLD( PU_OCB_OCI_OIRR0A_INTERRUPT_ROUTE_A_N_LEN , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N_LEN ); REG64_FLD( PU_OCB_OCI_OIRR0B_INTERRUPT_ROUTE_A_N , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N ); REG64_FLD( PU_OCB_OCI_OIRR0B_INTERRUPT_ROUTE_A_N_LEN , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N_LEN ); REG64_FLD( PU_OCB_OCI_OIRR0C_INTERRUPT_ROUTE_A_N , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N ); REG64_FLD( PU_OCB_OCI_OIRR0C_INTERRUPT_ROUTE_A_N_LEN , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N_LEN ); REG64_FLD( PU_OCB_OCI_OIRR1A_INTERRUPT_ROUTE_A_N , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N ); REG64_FLD( PU_OCB_OCI_OIRR1A_INTERRUPT_ROUTE_A_N_LEN , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N_LEN ); REG64_FLD( PU_OCB_OCI_OIRR1B_INTERRUPT_ROUTE_A_N , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N ); REG64_FLD( PU_OCB_OCI_OIRR1B_INTERRUPT_ROUTE_A_N_LEN , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N_LEN ); REG64_FLD( PU_OCB_OCI_OIRR1C_INTERRUPT_ROUTE_A_N , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N ); REG64_FLD( PU_OCB_OCI_OIRR1C_INTERRUPT_ROUTE_A_N_LEN , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_ROUTE_A_N_LEN ); REG64_FLD( PU_OCB_OCI_OISR0_DEBUGGER , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DEBUGGER ); REG64_FLD( PU_OCB_OCI_OISR0_TRACE_TRIGGER , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_TRACE_TRIGGER ); REG64_FLD( PU_OCB_OCI_OISR0_OCC_ERROR , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCC_ERROR ); REG64_FLD( PU_OCB_OCI_OISR0_PBA_ERROR , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBA_ERROR ); REG64_FLD( PU_OCB_OCI_OISR0_SRT_ERROR , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SRT_ERROR ); REG64_FLD( PU_OCB_OCI_OISR0_GPE0_ERROR , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_GPE0_ERROR ); REG64_FLD( PU_OCB_OCI_OISR0_GPE1_ERROR , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_GPE1_ERROR ); REG64_FLD( PU_OCB_OCI_OISR0_GPE2_ERROR , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_GPE2_ERROR ); REG64_FLD( PU_OCB_OCI_OISR0_GPE3_ERROR , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_GPE3_ERROR ); REG64_FLD( PU_OCB_OCI_OISR0_PPC405_HALT , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PPC405_HALT ); REG64_FLD( PU_OCB_OCI_OISR0_ERROR , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ERROR ); REG64_FLD( PU_OCB_OCI_OISR0_SPARE_11 , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_11 ); REG64_FLD( PU_OCB_OCI_OISR0_CHECK_STOP_PPC405 , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CHECK_STOP_PPC405 ); REG64_FLD( PU_OCB_OCI_OISR0_CHECK_STOP_GPE0 , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CHECK_STOP_GPE0 ); REG64_FLD( PU_OCB_OCI_OISR0_CHECK_STOP_GPE1 , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CHECK_STOP_GPE1 ); REG64_FLD( PU_OCB_OCI_OISR0_CHECK_STOP_GPE2 , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CHECK_STOP_GPE2 ); REG64_FLD( PU_OCB_OCI_OISR0_CHECK_STOP_GPE3 , 16 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CHECK_STOP_GPE3 ); REG64_FLD( PU_OCB_OCI_OISR0_OCC_MALF_ALERT , 17 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCC_MALF_ALERT ); REG64_FLD( PU_OCB_OCI_OISR0_ADU_MALF_ALERT , 18 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ADU_MALF_ALERT ); REG64_FLD( PU_OCB_OCI_OISR0_EXTERNAL_TRAP , 19 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_EXTERNAL_TRAP ); REG64_FLD( PU_OCB_OCI_OISR0_IVRM_PVREF_ERROR , 20 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IVRM_PVREF_ERROR ); REG64_FLD( PU_OCB_OCI_OISR0_OCC_TIMER0 , 21 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCC_TIMER0 ); REG64_FLD( PU_OCB_OCI_OISR0_OCC_TIMER1 , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCC_TIMER1 ); REG64_FLD( PU_OCB_OCI_OISR0_AVS_SLAVE0 , 23 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AVS_SLAVE0 ); REG64_FLD( PU_OCB_OCI_OISR0_AVS_SLAVE1 , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AVS_SLAVE1 ); REG64_FLD( PU_OCB_OCI_OISR0_IPI0_HI_PRIORITY , 25 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IPI0_HI_PRIORITY ); REG64_FLD( PU_OCB_OCI_OISR0_IPI1_HI_PRIORITY , 26 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IPI1_HI_PRIORITY ); REG64_FLD( PU_OCB_OCI_OISR0_IPI2_HI_PRIORITY , 27 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IPI2_HI_PRIORITY ); REG64_FLD( PU_OCB_OCI_OISR0_IPI3_HI_PRIORITY , 28 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IPI3_HI_PRIORITY ); REG64_FLD( PU_OCB_OCI_OISR0_IPI4_HI_PRIORITY , 29 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IPI4_HI_PRIORITY ); REG64_FLD( PU_OCB_OCI_OISR0_ADCFSM_ONGOING , 30 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ADCFSM_ONGOING ); REG64_FLD( PU_OCB_OCI_OISR0_I2CM_INTER , 31 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_I2CM_INTER ); REG64_FLD( PU_OCB_OCI_OISR1_PBAX_OCC_SEND_ATTN , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBAX_OCC_SEND_ATTN ); REG64_FLD( PU_OCB_OCI_OISR1_PBAX_OCC_PUSH0 , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBAX_OCC_PUSH0 ); REG64_FLD( PU_OCB_OCI_OISR1_PBAX_OCC_PUSH1 , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBAX_OCC_PUSH1 ); REG64_FLD( PU_OCB_OCI_OISR1_PBA_BCDE_ATTN , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBA_BCDE_ATTN ); REG64_FLD( PU_OCB_OCI_OISR1_PBA_BCUE_ATTN , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBA_BCUE_ATTN ); REG64_FLD( PU_OCB_OCI_OISR1_OCC_STRM0_PULL , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCC_STRM0_PULL ); REG64_FLD( PU_OCB_OCI_OISR1_OCC_STRM0_PUSH , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCC_STRM0_PUSH ); REG64_FLD( PU_OCB_OCI_OISR1_OCC_STRM1_PULL , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCC_STRM1_PULL ); REG64_FLD( PU_OCB_OCI_OISR1_OCC_STRM1_PUSH , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCC_STRM1_PUSH ); REG64_FLD( PU_OCB_OCI_OISR1_OCC_STRM2_PULL , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCC_STRM2_PULL ); REG64_FLD( PU_OCB_OCI_OISR1_OCC_STRM2_PUSH , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCC_STRM2_PUSH ); REG64_FLD( PU_OCB_OCI_OISR1_OCC_STRM3_PULL , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCC_STRM3_PULL ); REG64_FLD( PU_OCB_OCI_OISR1_OCC_STRM3_PUSH , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCC_STRM3_PUSH ); REG64_FLD( PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE0_PENDING , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PMC_PCB_INTR_TYPE0_PENDING ); REG64_FLD( PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE1_PENDING , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PMC_PCB_INTR_TYPE1_PENDING ); REG64_FLD( PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE2_PENDING , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PMC_PCB_INTR_TYPE2_PENDING ); REG64_FLD( PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE3_PENDING , 16 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PMC_PCB_INTR_TYPE3_PENDING ); REG64_FLD( PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE4_PENDING , 17 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PMC_PCB_INTR_TYPE4_PENDING ); REG64_FLD( PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE5_PENDING , 18 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PMC_PCB_INTR_TYPE5_PENDING ); REG64_FLD( PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE6_PENDING , 19 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PMC_PCB_INTR_TYPE6_PENDING ); REG64_FLD( PU_OCB_OCI_OISR1_PMC_PCB_INTR_TYPE7_PENDING , 20 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PMC_PCB_INTR_TYPE7_PENDING ); REG64_FLD( PU_OCB_OCI_OISR1_PMC_O2S_0A_ONGOING , 21 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PMC_O2S_0A_ONGOING ); REG64_FLD( PU_OCB_OCI_OISR1_PMC_O2S_0B_ONGOING , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PMC_O2S_0B_ONGOING ); REG64_FLD( PU_OCB_OCI_OISR1_PMC_O2S_1A_ONGOING , 23 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PMC_O2S_1A_ONGOING ); REG64_FLD( PU_OCB_OCI_OISR1_PMC_O2S_1B_ONGOING , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PMC_O2S_1B_ONGOING ); REG64_FLD( PU_OCB_OCI_OISR1_PSSBRIDGE_ONGOING , 25 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PSSBRIDGE_ONGOING ); REG64_FLD( PU_OCB_OCI_OISR1_IPI0_LO_PRIORITY , 26 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IPI0_LO_PRIORITY ); REG64_FLD( PU_OCB_OCI_OISR1_IPI1_LO_PRIORITY , 27 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IPI1_LO_PRIORITY ); REG64_FLD( PU_OCB_OCI_OISR1_IPI2_LO_PRIORITY , 28 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IPI2_LO_PRIORITY ); REG64_FLD( PU_OCB_OCI_OISR1_IPI3_LO_PRIORITY , 29 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IPI3_LO_PRIORITY ); REG64_FLD( PU_OCB_OCI_OISR1_IPI4_LO_PRIORITY , 30 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IPI4_LO_PRIORITY ); REG64_FLD( PU_OCB_OCI_OISR1_SPARE_31 , 31 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_31 ); REG64_FLD( PU_OCB_OCI_OITR0_INTERRUPT_TYPE_N , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_TYPE_N ); REG64_FLD( PU_OCB_OCI_OITR0_INTERRUPT_TYPE_N_LEN , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_TYPE_N_LEN ); REG64_FLD( PU_OCB_OCI_OITR1_INTERRUPT_TYPE_N , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_TYPE_N ); REG64_FLD( PU_OCB_OCI_OITR1_INTERRUPT_TYPE_N_LEN , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_TYPE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C0_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C0_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C1_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C1_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C10_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C10_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C11_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C11_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C12_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C12_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C13_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C13_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C14_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C14_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C15_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C15_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C16_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C16_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C17_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C17_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C18_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C18_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C19_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C19_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C2_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C2_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C20_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C20_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C21_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C21_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C22_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C22_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C23_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C23_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C3_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C3_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C4_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C4_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C5_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C5_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C6_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C6_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C7_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C7_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C8_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C8_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0C9_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT0C9_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_0 , 0 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_0 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_1 , 1 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_1 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_2 , 2 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_2 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_3 , 3 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_3 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_4 , 4 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_4 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_5 , 5 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_5 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_6 , 6 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_6 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_7 , 7 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_7 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_8 , 8 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_8 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_9 , 9 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_9 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_10 , 10 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_10 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_11 , 11 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_11 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_12 , 12 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_12 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_13 , 13 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_13 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_14 , 14 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_14 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_15 , 15 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_15 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_16 , 16 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_16 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_17 , 17 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_17 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_18 , 18 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_18 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_19 , 19 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_19 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_20 , 20 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_20 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_21 , 21 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_21 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_22 , 22 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_22 ); REG64_FLD( PU_OCB_OCI_OPIT0PRA_PCB_INTR_TYPE_N_PENDING_23 , 23 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_23 ); REG64_FLD( PU_OCB_OCI_OPIT1C0_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C0_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C1_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C1_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C10_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C10_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C11_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C11_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C12_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C12_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C13_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C13_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C14_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C14_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C15_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C15_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C16_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C16_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C17_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C17_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C18_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C18_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C19_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C19_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C2_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C2_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C20_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C20_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C21_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C21_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C22_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C22_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C23_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C23_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C3_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C3_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C4_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C4_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C5_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C5_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C6_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C6_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C7_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C7_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C8_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C8_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1C9_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT1C9_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_0 , 0 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_0 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_1 , 1 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_1 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_2 , 2 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_2 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_3 , 3 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_3 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_4 , 4 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_4 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_5 , 5 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_5 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_6 , 6 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_6 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_7 , 7 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_7 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_8 , 8 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_8 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_9 , 9 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_9 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_10 , 10 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_10 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_11 , 11 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_11 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_12 , 12 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_12 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_13 , 13 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_13 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_14 , 14 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_14 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_15 , 15 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_15 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_16 , 16 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_16 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_17 , 17 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_17 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_18 , 18 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_18 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_19 , 19 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_19 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_20 , 20 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_20 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_21 , 21 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_21 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_22 , 22 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_22 ); REG64_FLD( PU_OCB_OCI_OPIT1PRA_PCB_INTR_TYPE_N_PENDING_23 , 23 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_23 ); REG64_FLD( PU_OCB_OCI_OPIT2C0_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C0_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C1_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C1_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C10_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C10_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C11_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C11_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C12_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C12_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C13_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C13_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C14_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C14_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C15_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C15_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C16_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C16_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C17_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C17_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C18_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C18_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C19_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C19_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C2_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C2_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C20_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C20_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C21_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C21_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C22_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C22_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C23_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C23_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C3_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C3_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C4_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C4_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C5_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C5_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C6_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C6_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C7_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C7_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C8_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C8_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2C9_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT2C9_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_0 , 0 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_0 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_1 , 1 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_1 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_2 , 2 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_2 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_3 , 3 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_3 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_4 , 4 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_4 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_5 , 5 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_5 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_6 , 6 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_6 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_7 , 7 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_7 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_8 , 8 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_8 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_9 , 9 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_9 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_10 , 10 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_10 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_11 , 11 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_11 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_12 , 12 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_12 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_13 , 13 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_13 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_14 , 14 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_14 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_15 , 15 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_15 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_16 , 16 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_16 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_17 , 17 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_17 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_18 , 18 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_18 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_19 , 19 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_19 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_20 , 20 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_20 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_21 , 21 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_21 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_22 , 22 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_22 ); REG64_FLD( PU_OCB_OCI_OPIT2PRA_PCB_INTR_TYPE_N_PENDING_23 , 23 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_23 ); REG64_FLD( PU_OCB_OCI_OPIT3C0_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C0_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C1_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C1_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C10_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C10_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C11_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C11_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C12_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C12_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C13_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C13_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C14_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C14_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C15_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C15_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C16_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C16_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C17_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C17_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C18_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C18_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C19_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C19_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C2_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C2_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C20_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C20_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C21_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C21_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C22_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C22_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C23_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C23_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C3_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C3_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C4_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C4_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C5_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C5_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C6_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C6_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C7_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C7_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C8_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C8_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3C9_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT3C9_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_0 , 0 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_0 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_1 , 1 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_1 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_2 , 2 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_2 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_3 , 3 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_3 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_4 , 4 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_4 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_5 , 5 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_5 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_6 , 6 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_6 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_7 , 7 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_7 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_8 , 8 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_8 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_9 , 9 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_9 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_10 , 10 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_10 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_11 , 11 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_11 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_12 , 12 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_12 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_13 , 13 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_13 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_14 , 14 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_14 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_15 , 15 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_15 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_16 , 16 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_16 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_17 , 17 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_17 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_18 , 18 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_18 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_19 , 19 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_19 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_20 , 20 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_20 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_21 , 21 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_21 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_22 , 22 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_22 ); REG64_FLD( PU_OCB_OCI_OPIT3PRA_PCB_INTR_TYPE_N_PENDING_23 , 23 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_23 ); REG64_FLD( PU_OCB_OCI_OPIT4C0_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C0_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C1_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C1_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C10_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C10_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C11_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C11_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C12_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C12_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C13_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C13_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C14_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C14_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C15_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C15_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C16_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C16_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C17_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C17_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C18_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C18_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C19_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C19_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C2_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C2_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C20_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C20_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C21_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C21_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C22_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C22_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C23_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C23_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C3_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C3_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C4_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C4_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C5_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C5_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C6_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C6_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C7_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C7_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C8_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C8_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4C9_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT4C9_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_0 , 0 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_0 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_1 , 1 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_1 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_2 , 2 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_2 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_3 , 3 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_3 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_4 , 4 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_4 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_5 , 5 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_5 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_6 , 6 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_6 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_7 , 7 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_7 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_8 , 8 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_8 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_9 , 9 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_9 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_10 , 10 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_10 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_11 , 11 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_11 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_12 , 12 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_12 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_13 , 13 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_13 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_14 , 14 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_14 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_15 , 15 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_15 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_16 , 16 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_16 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_17 , 17 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_17 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_18 , 18 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_18 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_19 , 19 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_19 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_20 , 20 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_20 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_21 , 21 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_21 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_22 , 22 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_22 ); REG64_FLD( PU_OCB_OCI_OPIT4PRA_PCB_INTR_TYPE_N_PENDING_23 , 23 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_23 ); REG64_FLD( PU_OCB_OCI_OPIT5C0_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C0_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C1_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C1_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C10_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C10_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C11_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C11_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C12_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C12_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C13_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C13_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C14_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C14_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C15_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C15_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C16_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C16_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C17_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C17_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C18_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C18_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C19_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C19_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C2_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C2_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C20_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C20_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C21_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C21_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C22_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C22_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C23_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C23_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C3_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C3_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C4_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C4_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C5_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C5_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C6_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C6_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C7_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C7_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C8_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C8_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5C9_PCB_INTR_TYPE_A_CORE_N , 20 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N ); REG64_FLD( PU_OCB_OCI_OPIT5C9_PCB_INTR_TYPE_A_CORE_N_LEN , 12 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_CORE_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_0 , 0 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_0 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_1 , 1 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_1 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_2 , 2 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_2 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_3 , 3 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_3 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_4 , 4 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_4 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_5 , 5 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_5 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_6 , 6 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_6 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_7 , 7 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_7 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_8 , 8 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_8 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_9 , 9 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_9 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_10 , 10 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_10 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_11 , 11 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_11 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_12 , 12 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_12 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_13 , 13 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_13 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_14 , 14 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_14 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_15 , 15 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_15 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_16 , 16 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_16 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_17 , 17 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_17 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_18 , 18 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_18 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_19 , 19 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_19 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_20 , 20 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_20 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_21 , 21 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_21 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_22 , 22 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_22 ); REG64_FLD( PU_OCB_OCI_OPIT5PRA_PCB_INTR_TYPE_N_PENDING_23 , 23 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_23 ); REG64_FLD( PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_0 , 0 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_0 ); REG64_FLD( PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_1 , 1 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_1 ); REG64_FLD( PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_2 , 2 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_2 ); REG64_FLD( PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_3 , 3 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_3 ); REG64_FLD( PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_4 , 4 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_4 ); REG64_FLD( PU_OCB_OCI_OPIT6PRB_PCB_INTR_TYPE_N_PENDING_5 , 5 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_5 ); REG64_FLD( PU_OCB_OCI_OPIT6Q0_PCB_INTR_TYPE_A_QUAD_N , 28 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N ); REG64_FLD( PU_OCB_OCI_OPIT6Q0_PCB_INTR_TYPE_A_QUAD_N_LEN , 4 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT6Q1_PCB_INTR_TYPE_A_QUAD_N , 28 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N ); REG64_FLD( PU_OCB_OCI_OPIT6Q1_PCB_INTR_TYPE_A_QUAD_N_LEN , 4 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT6Q2_PCB_INTR_TYPE_A_QUAD_N , 28 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N ); REG64_FLD( PU_OCB_OCI_OPIT6Q2_PCB_INTR_TYPE_A_QUAD_N_LEN , 4 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT6Q3_PCB_INTR_TYPE_A_QUAD_N , 28 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N ); REG64_FLD( PU_OCB_OCI_OPIT6Q3_PCB_INTR_TYPE_A_QUAD_N_LEN , 4 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT6Q4_PCB_INTR_TYPE_A_QUAD_N , 28 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N ); REG64_FLD( PU_OCB_OCI_OPIT6Q4_PCB_INTR_TYPE_A_QUAD_N_LEN , 4 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT6Q5_PCB_INTR_TYPE_A_QUAD_N , 28 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N ); REG64_FLD( PU_OCB_OCI_OPIT6Q5_PCB_INTR_TYPE_A_QUAD_N_LEN , 4 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_0 , 0 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_0 ); REG64_FLD( PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_1 , 1 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_1 ); REG64_FLD( PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_2 , 2 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_2 ); REG64_FLD( PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_3 , 3 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_3 ); REG64_FLD( PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_4 , 4 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_4 ); REG64_FLD( PU_OCB_OCI_OPIT7PRB_PCB_INTR_TYPE_N_PENDING_5 , 5 , SH_UNT , SH_ACS_SCOM1_CLEAR, SH_FLD_PCB_INTR_TYPE_N_PENDING_5 ); REG64_FLD( PU_OCB_OCI_OPIT7Q0_PCB_INTR_TYPE_A_QUAD_N , 28 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N ); REG64_FLD( PU_OCB_OCI_OPIT7Q0_PCB_INTR_TYPE_A_QUAD_N_LEN , 4 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT7Q1_PCB_INTR_TYPE_A_QUAD_N , 28 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N ); REG64_FLD( PU_OCB_OCI_OPIT7Q1_PCB_INTR_TYPE_A_QUAD_N_LEN , 4 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT7Q2_PCB_INTR_TYPE_A_QUAD_N , 28 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N ); REG64_FLD( PU_OCB_OCI_OPIT7Q2_PCB_INTR_TYPE_A_QUAD_N_LEN , 4 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT7Q3_PCB_INTR_TYPE_A_QUAD_N , 28 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N ); REG64_FLD( PU_OCB_OCI_OPIT7Q3_PCB_INTR_TYPE_A_QUAD_N_LEN , 4 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT7Q4_PCB_INTR_TYPE_A_QUAD_N , 28 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N ); REG64_FLD( PU_OCB_OCI_OPIT7Q4_PCB_INTR_TYPE_A_QUAD_N_LEN , 4 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN ); REG64_FLD( PU_OCB_OCI_OPIT7Q5_PCB_INTR_TYPE_A_QUAD_N , 28 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N ); REG64_FLD( PU_OCB_OCI_OPIT7Q5_PCB_INTR_TYPE_A_QUAD_N_LEN , 4 , SH_UNT , SH_ACS_SCOM1_RO , SH_FLD_PCB_INTR_TYPE_A_QUAD_N_LEN ); REG64_FLD( PU_OCB_OCI_OTBR_TIMEBASE , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_TIMEBASE ); REG64_FLD( PU_OCB_OCI_OTBR_TIMEBASE_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_TIMEBASE_LEN ); REG64_FLD( PU_OCB_OCI_OTR0_TIMEOUT_N , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_TIMEOUT_N ); REG64_FLD( PU_OCB_OCI_OTR0_CONTROL_N , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CONTROL_N ); REG64_FLD( PU_OCB_OCI_OTR0_AUTO_RELOAD_N , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_AUTO_RELOAD_N ); REG64_FLD( PU_OCB_OCI_OTR0_SPARE_N , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_N ); REG64_FLD( PU_OCB_OCI_OTR0_SPARE_N_LEN , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_N_LEN ); REG64_FLD( PU_OCB_OCI_OTR0_TIMER_N , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_TIMER_N ); REG64_FLD( PU_OCB_OCI_OTR0_TIMER_N_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_TIMER_N_LEN ); REG64_FLD( PU_OCB_OCI_OTR1_TIMEOUT_N , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_TIMEOUT_N ); REG64_FLD( PU_OCB_OCI_OTR1_CONTROL_N , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CONTROL_N ); REG64_FLD( PU_OCB_OCI_OTR1_AUTO_RELOAD_N , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_AUTO_RELOAD_N ); REG64_FLD( PU_OCB_OCI_OTR1_SPARE_N , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_N ); REG64_FLD( PU_OCB_OCI_OTR1_SPARE_N_LEN , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_N_LEN ); REG64_FLD( PU_OCB_OCI_OTR1_TIMER_N , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_TIMER_N ); REG64_FLD( PU_OCB_OCI_OTR1_TIMER_N_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_TIMER_N_LEN ); REG64_FLD( PU_OCB_OCI_QCSR_CORE_CONFIG , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CORE_CONFIG ); REG64_FLD( PU_OCB_OCI_QCSR_CORE_CONFIG_LEN , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CORE_CONFIG_LEN ); REG64_FLD( PU_OCB_OCI_QCSR_RESERVED_24_31 , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_24_31 ); REG64_FLD( PU_OCB_OCI_QCSR_RESERVED_24_31_LEN , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_24_31_LEN ); REG64_FLD( PU_OCB_OCI_QSSR_L2_STOPPED , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_L2_STOPPED ); REG64_FLD( PU_OCB_OCI_QSSR_L2_STOPPED_LEN , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_L2_STOPPED_LEN ); REG64_FLD( PU_OCB_OCI_QSSR_L3_STOPPED , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_L3_STOPPED ); REG64_FLD( PU_OCB_OCI_QSSR_L3_STOPPED_LEN , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_L3_STOPPED_LEN ); REG64_FLD( PU_OCB_OCI_QSSR_QUAD_STOPPED , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_QUAD_STOPPED ); REG64_FLD( PU_OCB_OCI_QSSR_QUAD_STOPPED_LEN , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_QUAD_STOPPED_LEN ); REG64_FLD( PU_OCB_OCI_QSSR_RESERVED_30 , 30 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_30 ); REG64_FLD( PU_OCB_OCI_QSSR_CHANGE_IN_PROGRESS , 31 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CHANGE_IN_PROGRESS ); REG64_FLD( PU_OCB_PIB_OACR_OCI_PRIORITY_MODE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_PRIORITY_MODE ); REG64_FLD( PU_OCB_PIB_OACR_OCI_PRIORITY_ORDER , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_PRIORITY_ORDER ); REG64_FLD( PU_OCB_PIB_OACR_OCI_PRIORITY_ORDER_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_PRIORITY_ORDER_LEN ); REG64_FLD( PU_OCB_PIB_OACR_OCI_HI_BUS_MODE , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_HI_BUS_MODE ); REG64_FLD( PU_OCB_PIB_OACR_OCI_READ_PIPELINE_CONTROL , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_READ_PIPELINE_CONTROL ); REG64_FLD( PU_OCB_PIB_OACR_OCI_READ_PIPELINE_CONTROL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_READ_PIPELINE_CONTROL_LEN ); REG64_FLD( PU_OCB_PIB_OACR_OCI_WRITE_PIPELINE_CONTROL , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_WRITE_PIPELINE_CONTROL ); REG64_FLD( PU_OCB_PIB_OCBAR0_OCI_REGION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_REGION ); REG64_FLD( PU_OCB_PIB_OCBAR0_OCI_REGION_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_REGION_LEN ); REG64_FLD( PU_OCB_PIB_OCBAR0_ADDRESS , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS ); REG64_FLD( PU_OCB_PIB_OCBAR0_ADDRESS_LEN , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_OCB_PIB_OCBAR1_OCI_REGION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_REGION ); REG64_FLD( PU_OCB_PIB_OCBAR1_OCI_REGION_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_REGION_LEN ); REG64_FLD( PU_OCB_PIB_OCBAR1_ADDRESS , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS ); REG64_FLD( PU_OCB_PIB_OCBAR1_ADDRESS_LEN , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_OCB_PIB_OCBAR2_OCI_REGION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_REGION ); REG64_FLD( PU_OCB_PIB_OCBAR2_OCI_REGION_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_REGION_LEN ); REG64_FLD( PU_OCB_PIB_OCBAR2_ADDRESS , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS ); REG64_FLD( PU_OCB_PIB_OCBAR2_ADDRESS_LEN , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_OCB_PIB_OCBAR3_OCI_REGION , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_REGION ); REG64_FLD( PU_OCB_PIB_OCBAR3_OCI_REGION_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_REGION_LEN ); REG64_FLD( PU_OCB_PIB_OCBAR3_ADDRESS , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS ); REG64_FLD( PU_OCB_PIB_OCBAR3_ADDRESS_LEN , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_OCB_PIB_OCBCSR0_PULL_READ_UNDERFLOW , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PULL_READ_UNDERFLOW ); REG64_FLD( PU_OCB_PIB_OCBCSR0_PUSH_WRITE_OVERFLOW , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PUSH_WRITE_OVERFLOW ); REG64_FLD( PU_OCB_PIB_OCBCSR0_PULL_READ_UNDERFLOW_EN , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PULL_READ_UNDERFLOW_EN ); REG64_FLD( PU_OCB_PIB_OCBCSR0_PUSH_WRITE_OVERFLOW_EN , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PUSH_WRITE_OVERFLOW_EN ); REG64_FLD( PU_OCB_PIB_OCBCSR0_STREAM_MODE , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_STREAM_MODE ); REG64_FLD( PU_OCB_PIB_OCBCSR0_STREAM_TYPE , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_STREAM_TYPE ); REG64_FLD( PU_OCB_PIB_OCBCSR0_SPARE0 , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE0 ); REG64_FLD( PU_OCB_PIB_OCBCSR0_SPARE0_LEN , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE0_LEN ); REG64_FLD( PU_OCB_PIB_OCBCSR0_OCI_TIMEOUT , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCI_TIMEOUT ); REG64_FLD( PU_OCB_PIB_OCBCSR0_OCI_READ_DATA_PARITY , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCI_READ_DATA_PARITY ); REG64_FLD( PU_OCB_PIB_OCBCSR0_OCI_SLAVE_ERROR , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCI_SLAVE_ERROR ); REG64_FLD( PU_OCB_PIB_OCBCSR0_ADDR_PARITY_ERR , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ADDR_PARITY_ERR ); REG64_FLD( PU_OCB_PIB_OCBCSR0_DATA_PARITY_ERR , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DATA_PARITY_ERR ); REG64_FLD( PU_OCB_PIB_OCBCSR0_SPARE1 , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE1 ); REG64_FLD( PU_OCB_PIB_OCBCSR0_FSM_ERR , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FSM_ERR ); REG64_FLD( PU_OCB_PIB_OCBCSR0_SPARE2 , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE2 ); REG64_FLD( PU_OCB_PIB_OCBCSR1_PULL_READ_UNDERFLOW , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PULL_READ_UNDERFLOW ); REG64_FLD( PU_OCB_PIB_OCBCSR1_PUSH_WRITE_OVERFLOW , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PUSH_WRITE_OVERFLOW ); REG64_FLD( PU_OCB_PIB_OCBCSR1_PULL_READ_UNDERFLOW_EN , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PULL_READ_UNDERFLOW_EN ); REG64_FLD( PU_OCB_PIB_OCBCSR1_PUSH_WRITE_OVERFLOW_EN , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PUSH_WRITE_OVERFLOW_EN ); REG64_FLD( PU_OCB_PIB_OCBCSR1_STREAM_MODE , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_STREAM_MODE ); REG64_FLD( PU_OCB_PIB_OCBCSR1_STREAM_TYPE , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_STREAM_TYPE ); REG64_FLD( PU_OCB_PIB_OCBCSR1_SPARE0 , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE0 ); REG64_FLD( PU_OCB_PIB_OCBCSR1_SPARE0_LEN , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE0_LEN ); REG64_FLD( PU_OCB_PIB_OCBCSR1_OCI_TIMEOUT , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCI_TIMEOUT ); REG64_FLD( PU_OCB_PIB_OCBCSR1_OCI_READ_DATA_PARITY , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCI_READ_DATA_PARITY ); REG64_FLD( PU_OCB_PIB_OCBCSR1_OCI_SLAVE_ERROR , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCI_SLAVE_ERROR ); REG64_FLD( PU_OCB_PIB_OCBCSR1_ADDR_PARITY_ERR , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ADDR_PARITY_ERR ); REG64_FLD( PU_OCB_PIB_OCBCSR1_DATA_PARITY_ERR , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DATA_PARITY_ERR ); REG64_FLD( PU_OCB_PIB_OCBCSR1_SPARE1 , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE1 ); REG64_FLD( PU_OCB_PIB_OCBCSR1_FSM_ERR , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FSM_ERR ); REG64_FLD( PU_OCB_PIB_OCBCSR1_SPARE2 , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE2 ); REG64_FLD( PU_OCB_PIB_OCBCSR2_PULL_READ_UNDERFLOW , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PULL_READ_UNDERFLOW ); REG64_FLD( PU_OCB_PIB_OCBCSR2_PUSH_WRITE_OVERFLOW , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PUSH_WRITE_OVERFLOW ); REG64_FLD( PU_OCB_PIB_OCBCSR2_PULL_READ_UNDERFLOW_EN , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PULL_READ_UNDERFLOW_EN ); REG64_FLD( PU_OCB_PIB_OCBCSR2_PUSH_WRITE_OVERFLOW_EN , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PUSH_WRITE_OVERFLOW_EN ); REG64_FLD( PU_OCB_PIB_OCBCSR2_STREAM_MODE , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_STREAM_MODE ); REG64_FLD( PU_OCB_PIB_OCBCSR2_STREAM_TYPE , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_STREAM_TYPE ); REG64_FLD( PU_OCB_PIB_OCBCSR2_SPARE0 , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE0 ); REG64_FLD( PU_OCB_PIB_OCBCSR2_SPARE0_LEN , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE0_LEN ); REG64_FLD( PU_OCB_PIB_OCBCSR2_OCI_TIMEOUT , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCI_TIMEOUT ); REG64_FLD( PU_OCB_PIB_OCBCSR2_OCI_READ_DATA_PARITY , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCI_READ_DATA_PARITY ); REG64_FLD( PU_OCB_PIB_OCBCSR2_OCI_SLAVE_ERROR , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCI_SLAVE_ERROR ); REG64_FLD( PU_OCB_PIB_OCBCSR2_ADDR_PARITY_ERR , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ADDR_PARITY_ERR ); REG64_FLD( PU_OCB_PIB_OCBCSR2_DATA_PARITY_ERR , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DATA_PARITY_ERR ); REG64_FLD( PU_OCB_PIB_OCBCSR2_SPARE1 , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE1 ); REG64_FLD( PU_OCB_PIB_OCBCSR2_FSM_ERR , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FSM_ERR ); REG64_FLD( PU_OCB_PIB_OCBCSR2_SPARE2 , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE2 ); REG64_FLD( PU_OCB_PIB_OCBCSR3_PULL_READ_UNDERFLOW , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PULL_READ_UNDERFLOW ); REG64_FLD( PU_OCB_PIB_OCBCSR3_PUSH_WRITE_OVERFLOW , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PUSH_WRITE_OVERFLOW ); REG64_FLD( PU_OCB_PIB_OCBCSR3_PULL_READ_UNDERFLOW_EN , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PULL_READ_UNDERFLOW_EN ); REG64_FLD( PU_OCB_PIB_OCBCSR3_PUSH_WRITE_OVERFLOW_EN , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PUSH_WRITE_OVERFLOW_EN ); REG64_FLD( PU_OCB_PIB_OCBCSR3_STREAM_MODE , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_STREAM_MODE ); REG64_FLD( PU_OCB_PIB_OCBCSR3_STREAM_TYPE , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_STREAM_TYPE ); REG64_FLD( PU_OCB_PIB_OCBCSR3_SPARE0 , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE0 ); REG64_FLD( PU_OCB_PIB_OCBCSR3_SPARE0_LEN , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE0_LEN ); REG64_FLD( PU_OCB_PIB_OCBCSR3_OCI_TIMEOUT , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCI_TIMEOUT ); REG64_FLD( PU_OCB_PIB_OCBCSR3_OCI_READ_DATA_PARITY , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCI_READ_DATA_PARITY ); REG64_FLD( PU_OCB_PIB_OCBCSR3_OCI_SLAVE_ERROR , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCI_SLAVE_ERROR ); REG64_FLD( PU_OCB_PIB_OCBCSR3_ADDR_PARITY_ERR , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ADDR_PARITY_ERR ); REG64_FLD( PU_OCB_PIB_OCBCSR3_DATA_PARITY_ERR , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DATA_PARITY_ERR ); REG64_FLD( PU_OCB_PIB_OCBCSR3_SPARE1 , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE1 ); REG64_FLD( PU_OCB_PIB_OCBCSR3_FSM_ERR , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FSM_ERR ); REG64_FLD( PU_OCB_PIB_OCBCSR3_SPARE2 , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE2 ); REG64_FLD( PU_OCB_PIB_OCBDR0_DATA , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( PU_OCB_PIB_OCBDR0_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( PU_OCB_PIB_OCBDR1_DATA , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( PU_OCB_PIB_OCBDR1_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( PU_OCB_PIB_OCBDR2_DATA , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( PU_OCB_PIB_OCBDR2_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( PU_OCB_PIB_OCBDR3_DATA , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA ); REG64_FLD( PU_OCB_PIB_OCBDR3_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DATA_LEN ); REG64_FLD( PU_OCB_PIB_OCBEAR_ERROR_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_ERROR_ADDRESS ); REG64_FLD( PU_OCB_PIB_OCBEAR_ERROR_ADDRESS_LEN , 32 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_ERROR_ADDRESS_LEN ); REG64_FLD( PU_OCB_PIB_OCBEAR_RESERVED_32_34 , 32 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_RESERVED_32_34 ); REG64_FLD( PU_OCB_PIB_OCBEAR_RESERVED_32_34_LEN , 3 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_RESERVED_32_34_LEN ); REG64_FLD( PU_OCB_PIB_OCBEAR_DIRECT_BRIDGE_SOURCE , 35 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_DIRECT_BRIDGE_SOURCE ); REG64_FLD( PU_OCB_PIB_OCBEAR_INDIRECT_BRIDGE_0_SOURCE , 36 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_INDIRECT_BRIDGE_0_SOURCE ); REG64_FLD( PU_OCB_PIB_OCBEAR_INDIRECT_BRIDGE_1_SOURCE , 37 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_INDIRECT_BRIDGE_1_SOURCE ); REG64_FLD( PU_OCB_PIB_OCBEAR_INDIRECT_BRIDGE_2_SOURCE , 38 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_INDIRECT_BRIDGE_2_SOURCE ); REG64_FLD( PU_OCB_PIB_OCBEAR_INDIRECT_BRIDGE_3_SOURCE , 39 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_INDIRECT_BRIDGE_3_SOURCE ); REG64_FLD( PU_OCB_PIB_OCBESR0_ERROR_ADDR , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_ERROR_ADDR ); REG64_FLD( PU_OCB_PIB_OCBESR0_ERROR_ADDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_ERROR_ADDR_LEN ); REG64_FLD( PU_OCB_PIB_OCBESR1_ERROR_ADDR , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_ERROR_ADDR ); REG64_FLD( PU_OCB_PIB_OCBESR1_ERROR_ADDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_ERROR_ADDR_LEN ); REG64_FLD( PU_OCB_PIB_OCBESR2_ERROR_ADDR , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_ERROR_ADDR ); REG64_FLD( PU_OCB_PIB_OCBESR2_ERROR_ADDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_ERROR_ADDR_LEN ); REG64_FLD( PU_OCB_PIB_OCBESR3_ERROR_ADDR , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_ERROR_ADDR ); REG64_FLD( PU_OCB_PIB_OCBESR3_ERROR_ADDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_ERROR_ADDR_LEN ); REG64_FLD( PU_OCB_PIB_OCDBG_MST_DIS_ABUSPAREN , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MST_DIS_ABUSPAREN ); REG64_FLD( PU_OCB_PIB_OCDBG_MST_DIS_BEPAREN , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MST_DIS_BEPAREN ); REG64_FLD( PU_OCB_PIB_OCDBG_MST_DIS_WRDBUSPAREN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MST_DIS_WRDBUSPAREN ); REG64_FLD( PU_OCB_PIB_OCDBG_MST_DIS_RDDBUSPAR , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MST_DIS_RDDBUSPAR ); REG64_FLD( PU_OCB_PIB_OCDBG_MST_SPARE , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MST_SPARE ); REG64_FLD( PU_OCB_PIB_OCDBG_SLV_DIS_SACK , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SLV_DIS_SACK ); REG64_FLD( PU_OCB_PIB_OCDBG_SLV_DIS_ABUSPAR , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SLV_DIS_ABUSPAR ); REG64_FLD( PU_OCB_PIB_OCDBG_SLV_DIS_BEPAR , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SLV_DIS_BEPAR ); REG64_FLD( PU_OCB_PIB_OCDBG_SLV_DIS_BE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SLV_DIS_BE ); REG64_FLD( PU_OCB_PIB_OCDBG_SLV_DIS_WRDBUSPAR , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SLV_DIS_WRDBUSPAR ); REG64_FLD( PU_OCB_PIB_OCDBG_SLV_DIS_RDDBUSPAREN , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SLV_DIS_RDDBUSPAREN ); REG64_FLD( PU_OCB_PIB_OCDBG_SLV_SPARE , 11 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SLV_SPARE ); REG64_FLD( PU_OCB_PIB_OCDBG_SPARE , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SPARE ); REG64_FLD( PU_OCB_PIB_OCDBG_SPARE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SPARE_LEN ); REG64_FLD( PU_OCB_PIB_OCR_CORE_RESET , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CORE_RESET ); REG64_FLD( PU_OCB_PIB_OCR_CHIP_RESET , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CHIP_RESET ); REG64_FLD( PU_OCB_PIB_OCR_SYSTEM_RESET , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SYSTEM_RESET ); REG64_FLD( PU_OCB_PIB_OCR_OCI_ARB_RESET , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCI_ARB_RESET ); REG64_FLD( PU_OCB_PIB_OCR_TRACE_DISABLE , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_TRACE_DISABLE ); REG64_FLD( PU_OCB_PIB_OCR_TRACE_EVENT , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_TRACE_EVENT ); REG64_FLD( PU_OCB_PIB_OCR_DBG_UNCONDITIONAL_EVENT , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DBG_UNCONDITIONAL_EVENT ); REG64_FLD( PU_OCB_PIB_OCR_EXT_INTERRUPT , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_EXT_INTERRUPT ); REG64_FLD( PU_OCB_PIB_OCR_CRITICAL_INTERRUPT , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CRITICAL_INTERRUPT ); REG64_FLD( PU_OCB_PIB_OCR_SLAVE_RESET_TO_405_ENABLE , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SLAVE_RESET_TO_405_ENABLE ); REG64_FLD( PU_OCB_PIB_OCR_OCR_DBG_HALT , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCR_DBG_HALT ); REG64_FLD( PU_OCB_PIB_OCR_SPARE , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE ); REG64_FLD( PU_OCB_PIB_OCR_SPARE_LEN , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_LEN ); REG64_FLD( PU_OCB_PIB_OEAR_OCI_TIMEOUT_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OCI_TIMEOUT_ADDR ); REG64_FLD( PU_OCB_PIB_OEAR_OCI_TIMEOUT_ADDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OCI_TIMEOUT_ADDR_LEN ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M0_TIMEOUT_ERROR , 0 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M0_TIMEOUT_ERROR ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M0_RW_STATUS , 1 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M0_RW_STATUS ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M0_FLCK , 2 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M0_FLCK ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M0_OEAR_LOCK , 3 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M0_OEAR_LOCK ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M1_TIMEOUT_ERROR , 4 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M1_TIMEOUT_ERROR ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M1_RW_STATUS , 5 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M1_RW_STATUS ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M1_FLCK , 6 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M1_FLCK ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M1_OEAR_LOCK , 7 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M1_OEAR_LOCK ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M2_TIMEOUT_ERROR , 8 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M2_TIMEOUT_ERROR ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M2_RW_STATUS , 9 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M2_RW_STATUS ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M2_FLCK , 10 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M2_FLCK ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M2_OEAR_LOCK , 11 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M2_OEAR_LOCK ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M3_TIMEOUT_ERROR , 12 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M3_TIMEOUT_ERROR ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M3_RW_STATUS , 13 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M3_RW_STATUS ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M3_FLCK , 14 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M3_FLCK ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M3_OEAR_LOCK , 15 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M3_OEAR_LOCK ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M4_TIMEOUT_ERROR , 16 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M4_TIMEOUT_ERROR ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M4_RW_STATUS , 17 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M4_RW_STATUS ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M4_FLCK , 18 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M4_FLCK ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M4_OEAR_LOCK , 19 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M4_OEAR_LOCK ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M5_TIMEOUT_ERROR , 20 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M5_TIMEOUT_ERROR ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M5_RW_STATUS , 21 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M5_RW_STATUS ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M5_FLCK , 22 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M5_FLCK ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M5_OEAR_LOCK , 23 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M5_OEAR_LOCK ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M6_TIMEOUT_ERROR , 24 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M6_TIMEOUT_ERROR ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M6_RW_STATUS , 25 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M6_RW_STATUS ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M6_FLCK , 26 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M6_FLCK ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M6_OEAR_LOCK , 27 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M6_OEAR_LOCK ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M7_TIMEOUT_ERROR , 28 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M7_TIMEOUT_ERROR ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M7_RW_STATUS , 29 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M7_RW_STATUS ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M7_FLCK , 30 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M7_FLCK ); REG64_FLD( PU_OCB_PIB_OESR_OCI_M7_OEAR_LOCK , 31 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_OCI_M7_OEAR_LOCK ); REG64_FLD( PU_OCB_PIB_OPPCINJ_OCI_ERR_INJ_DCU , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_ERR_INJ_DCU ); REG64_FLD( PU_OCB_PIB_OPPCINJ_OCI_ERR_INJ_ICU , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_ERR_INJ_ICU ); REG64_FLD( PU_OCB_PIB_OPPCINJ_OCI_ERR_INJ_CE_UE , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_ERR_INJ_CE_UE ); REG64_FLD( PU_OCB_PIB_OPPCINJ_OCI_ERR_INJ_SINGL_CONT , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_ERR_INJ_SINGL_CONT ); REG64_FLD( PU_OCB_PIB_OSTOEAR_OCC_SPCL_TIMEOUT_ADDR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OCC_SPCL_TIMEOUT_ADDR ); REG64_FLD( PU_OCB_PIB_OSTOEAR_OCC_SPCL_TIMEOUT_ADDR_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OCC_SPCL_TIMEOUT_ADDR_LEN ); REG64_FLD( PU_OCB_PIB_OSTOESR_ICU_TIMEOUT_ERROR , 0 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_ICU_TIMEOUT_ERROR ); REG64_FLD( PU_OCB_PIB_OSTOESR_ICU_RNW , 1 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_ICU_RNW ); REG64_FLD( PU_OCB_PIB_OSTOESR_RESERVED_2_3 , 2 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_RESERVED_2_3 ); REG64_FLD( PU_OCB_PIB_OSTOESR_RESERVED_2_3_LEN , 2 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_RESERVED_2_3_LEN ); REG64_FLD( PU_OCB_PIB_OSTOESR_DCU_TIMEOUT_ERROR , 4 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_DCU_TIMEOUT_ERROR ); REG64_FLD( PU_OCB_PIB_OSTOESR_DCU_RNW , 5 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_DCU_RNW ); REG64_FLD( PU_OCB_PIB_OSTOESR_RESERVED_6_7 , 6 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_RESERVED_6_7 ); REG64_FLD( PU_OCB_PIB_OSTOESR_RESERVED_6_7_LEN , 2 , SH_UNT , SH_ACS_SCOM_WCLEAR, SH_FLD_RESERVED_6_7_LEN ); REG64_FLD( PU_OCB_PIB_OTDCR_TRACE_BUS_EN , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_TRACE_BUS_EN ); REG64_FLD( PU_OCB_PIB_OTDCR_TRACE_MUX_SEL , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_TRACE_MUX_SEL ); REG64_FLD( PU_OCB_PIB_OTDCR_OCC_TRACE_MUX_SEL , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCC_TRACE_MUX_SEL ); REG64_FLD( PU_OCB_PIB_OTDCR_OCC_TRACE_MUX_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCC_TRACE_MUX_SEL_LEN ); REG64_FLD( PU_OCB_PIB_OTDCR_OCI_TRACE_MUX_SEL , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_TRACE_MUX_SEL ); REG64_FLD( PU_OCB_PIB_OTDCR_OCI_TRACE_MUX_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCI_TRACE_MUX_SEL_LEN ); REG64_FLD( PEC_OPCG_ALIGN_INOP , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INOP ); REG64_FLD( PEC_OPCG_ALIGN_INOP_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INOP_LEN ); REG64_FLD( PEC_OPCG_ALIGN_SNOP , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SNOP ); REG64_FLD( PEC_OPCG_ALIGN_SNOP_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SNOP_LEN ); REG64_FLD( PEC_OPCG_ALIGN_ENOP , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ENOP ); REG64_FLD( PEC_OPCG_ALIGN_ENOP_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ENOP_LEN ); REG64_FLD( PEC_OPCG_ALIGN_INOP_WAIT , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INOP_WAIT ); REG64_FLD( PEC_OPCG_ALIGN_INOP_WAIT_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INOP_WAIT_LEN ); REG64_FLD( PEC_OPCG_ALIGN_SNOP_WAIT , 20 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SNOP_WAIT ); REG64_FLD( PEC_OPCG_ALIGN_SNOP_WAIT_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SNOP_WAIT_LEN ); REG64_FLD( PEC_OPCG_ALIGN_ENOP_WAIT , 32 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ENOP_WAIT ); REG64_FLD( PEC_OPCG_ALIGN_ENOP_WAIT_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ENOP_WAIT_LEN ); REG64_FLD( PEC_OPCG_ALIGN_INOP_FORCE_SG , 40 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INOP_FORCE_SG ); REG64_FLD( PEC_OPCG_ALIGN_SNOP_FORCE_SG , 41 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SNOP_FORCE_SG ); REG64_FLD( PEC_OPCG_ALIGN_ENOP_FORCE_SG , 42 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ENOP_FORCE_SG ); REG64_FLD( PEC_OPCG_ALIGN_NO_WAIT_ON_CLK_CMD , 43 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_NO_WAIT_ON_CLK_CMD ); REG64_FLD( PEC_OPCG_ALIGN_SOURCE_SELECT , 44 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SOURCE_SELECT ); REG64_FLD( PEC_OPCG_ALIGN_SOURCE_SELECT_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SOURCE_SELECT_LEN ); REG64_FLD( PEC_OPCG_ALIGN_UNUSED46 , 46 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED46 ); REG64_FLD( PEC_OPCG_ALIGN_SCAN_RATIO , 47 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SCAN_RATIO ); REG64_FLD( PEC_OPCG_ALIGN_SCAN_RATIO_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SCAN_RATIO_LEN ); REG64_FLD( PEC_OPCG_ALIGN_WAIT_CYCLES , 52 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES ); REG64_FLD( PEC_OPCG_ALIGN_WAIT_CYCLES_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES_LEN ); REG64_FLD( PEC_OPCG_CAPT1_COUNT , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COUNT ); REG64_FLD( PEC_OPCG_CAPT1_COUNT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COUNT_LEN ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_01 , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_01 ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_01_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_01_LEN ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_02 , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_02 ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_02_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_02_LEN ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_03 , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_03 ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_03_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_03_LEN ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_04 , 19 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_04 ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_04_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_04_LEN ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_05 , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_05 ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_05_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_05_LEN ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_06 , 29 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_06 ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_06_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_06_LEN ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_07 , 34 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_07 ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_07_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_07_LEN ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_08 , 39 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_08 ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_08_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_08_LEN ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_09 , 44 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_09 ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_09_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_09_LEN ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_10 , 49 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_10 ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_10_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_10_LEN ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_11 , 54 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_11 ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_11_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_11_LEN ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_12 , 59 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_12 ); REG64_FLD( PEC_OPCG_CAPT1_SEQ_12_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_12_LEN ); REG64_FLD( PEC_OPCG_CAPT2_UNUSED , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( PEC_OPCG_CAPT2_UNUSED_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_13_01EVEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_13_01EVEN ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_13_01EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_13_01EVEN_LEN ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_14_01ODD , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_14_01ODD ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_14_01ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_14_01ODD_LEN ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_15_02EVEN , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_15_02EVEN ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_15_02EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_15_02EVEN_LEN ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_16_02ODD , 19 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_16_02ODD ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_16_02ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_16_02ODD_LEN ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_17_03EVEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_17_03EVEN ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_17_03EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_17_03EVEN_LEN ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_18_03ODD , 29 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_18_03ODD ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_18_03ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_18_03ODD_LEN ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_19_04EVEN , 34 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_19_04EVEN ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_19_04EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_19_04EVEN_LEN ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_20_04ODD , 39 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_20_04ODD ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_20_04ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_20_04ODD_LEN ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_21_05EVEN , 44 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_21_05EVEN ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_21_05EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_21_05EVEN_LEN ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_22_05ODD , 49 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_22_05ODD ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_22_05ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_22_05ODD_LEN ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_23_06EVEN , 54 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_23_06EVEN ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_23_06EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_23_06EVEN_LEN ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_24_06ODD , 59 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_24_06ODD ); REG64_FLD( PEC_OPCG_CAPT2_SEQ_24_06ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_24_06ODD_LEN ); REG64_FLD( PEC_OPCG_CAPT3_UNUSED , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( PEC_OPCG_CAPT3_UNUSED_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_07EVEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_07EVEN ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_07EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_07EVEN_LEN ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_07ODD , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_07ODD ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_07ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_07ODD_LEN ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_08EVEN , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_08EVEN ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_08EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_08EVEN_LEN ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_08ODD , 19 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_08ODD ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_08ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_08ODD_LEN ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_09EVEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_09EVEN ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_09EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_09EVEN_LEN ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_09ODD , 29 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_09ODD ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_09ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_09ODD_LEN ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_10EVEN , 34 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_10EVEN ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_10EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_10EVEN_LEN ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_10ODD , 39 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_10ODD ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_10ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_10ODD_LEN ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_11EVEN , 44 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_11EVEN ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_11EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_11EVEN_LEN ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_11ODD , 49 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_11ODD ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_11ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_11ODD_LEN ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_12EVEN , 54 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_12EVEN ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_12EVEN_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_12EVEN_LEN ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_12ODD , 59 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_12ODD ); REG64_FLD( PEC_OPCG_CAPT3_SEQ_12ODD_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SEQ_12ODD_LEN ); REG64_FLD( PEC_OPCG_REG0_RUNN_MODE , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RUNN_MODE ); REG64_FLD( PEC_OPCG_REG0_GO , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GO ); REG64_FLD( PEC_OPCG_REG0_RUN_SCAN0 , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RUN_SCAN0 ); REG64_FLD( PEC_OPCG_REG0_SCAN0_MODE , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SCAN0_MODE ); REG64_FLD( PEC_OPCG_REG0_IN_SLAVE_MODE , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN_SLAVE_MODE ); REG64_FLD( PEC_OPCG_REG0_IN_MASTER_MODE , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN_MASTER_MODE ); REG64_FLD( PEC_OPCG_REG0_KEEP_MS_MODE , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_KEEP_MS_MODE ); REG64_FLD( PEC_OPCG_REG0_TRIGGER_ON_UNIT0_SYNC_LVL , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIGGER_ON_UNIT0_SYNC_LVL ); REG64_FLD( PEC_OPCG_REG0_TRIGGER_ON_UNIT1_SYNC_LVL , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIGGER_ON_UNIT1_SYNC_LVL ); REG64_FLD( PEC_OPCG_REG0_RUN_CHIPLET_SCAN0 , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RUN_CHIPLET_SCAN0 ); REG64_FLD( PEC_OPCG_REG0_RUN_CHIPLET_SCAN0_NO_PLL , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RUN_CHIPLET_SCAN0_NO_PLL ); REG64_FLD( PEC_OPCG_REG0_RUN_ON_UPDATE_DR , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RUN_ON_UPDATE_DR ); REG64_FLD( PEC_OPCG_REG0_RUN_ON_CAPTURE_DR , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RUN_ON_CAPTURE_DR ); REG64_FLD( PEC_OPCG_REG0_STOP_RUNN_ON_XSTOP , 13 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STOP_RUNN_ON_XSTOP ); REG64_FLD( PEC_OPCG_REG0_STARTS_BIST , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STARTS_BIST ); REG64_FLD( PEC_OPCG_REG0_UNUSED1520 , 15 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED1520 ); REG64_FLD( PEC_OPCG_REG0_UNUSED1520_LEN , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED1520_LEN ); REG64_FLD( PEC_OPCG_REG0_LOOP_COUNT , 21 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_LOOP_COUNT ); REG64_FLD( PEC_OPCG_REG0_LOOP_COUNT_LEN , 43 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_LOOP_COUNT_LEN ); REG64_FLD( PEC_OPCG_REG1_SCAN_COUNT , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SCAN_COUNT ); REG64_FLD( PEC_OPCG_REG1_SCAN_COUNT_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SCAN_COUNT_LEN ); REG64_FLD( PEC_OPCG_REG1_MISR_A_VAL , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MISR_A_VAL ); REG64_FLD( PEC_OPCG_REG1_MISR_A_VAL_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MISR_A_VAL_LEN ); REG64_FLD( PEC_OPCG_REG1_MISR_B_VAL , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MISR_B_VAL ); REG64_FLD( PEC_OPCG_REG1_MISR_B_VAL_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MISR_B_VAL_LEN ); REG64_FLD( PEC_OPCG_REG1_MISR_INIT_WAIT , 36 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MISR_INIT_WAIT ); REG64_FLD( PEC_OPCG_REG1_MISR_INIT_WAIT_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MISR_INIT_WAIT_LEN ); REG64_FLD( PEC_OPCG_REG1_SUPPRESS_EVEN_CLK , 48 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SUPPRESS_EVEN_CLK ); REG64_FLD( PEC_OPCG_REG1_SCAN_CLK_USE_EVEN , 49 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SCAN_CLK_USE_EVEN ); REG64_FLD( PEC_OPCG_REG1_UNUSED2 , 50 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED2 ); REG64_FLD( PEC_OPCG_REG1_UNUSED2_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED2_LEN ); REG64_FLD( PEC_OPCG_REG1_RTIM_THOLD_FORCE , 52 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RTIM_THOLD_FORCE ); REG64_FLD( PEC_OPCG_REG1_DISABLE_ARY_CLK_DURING_FILL , 53 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DISABLE_ARY_CLK_DURING_FILL ); REG64_FLD( PEC_OPCG_REG1_SG_HIGH_DURING_FILL , 54 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SG_HIGH_DURING_FILL ); REG64_FLD( PEC_OPCG_REG1_LBIST_SKITTER_CTL , 55 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_LBIST_SKITTER_CTL ); REG64_FLD( PEC_OPCG_REG1_LBIST_SKITTER_CTL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_LBIST_SKITTER_CTL_LEN ); REG64_FLD( PEC_OPCG_REG1_MISR_MODE , 57 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MISR_MODE ); REG64_FLD( PEC_OPCG_REG1_INFINITE_MODE , 58 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INFINITE_MODE ); REG64_FLD( PEC_OPCG_REG1_NSL_FILL_COUNT , 59 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_NSL_FILL_COUNT ); REG64_FLD( PEC_OPCG_REG1_NSL_FILL_COUNT_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_NSL_FILL_COUNT_LEN ); REG64_FLD( PEC_OPCG_REG2_GO2 , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GO2 ); REG64_FLD( PEC_OPCG_REG2_PRPG_WEIGHTING , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PRPG_WEIGHTING ); REG64_FLD( PEC_OPCG_REG2_PRPG_WEIGHTING_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PRPG_WEIGHTING_LEN ); REG64_FLD( PEC_OPCG_REG2_PRPG_VALUE , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PRPG_VALUE ); REG64_FLD( PEC_OPCG_REG2_PRPG_VALUE_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PRPG_VALUE_LEN ); REG64_FLD( PEC_OPCG_REG2_PRPG_A_VAL , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PRPG_A_VAL ); REG64_FLD( PEC_OPCG_REG2_PRPG_A_VAL_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PRPG_A_VAL_LEN ); REG64_FLD( PEC_OPCG_REG2_PRPG_B_VAL , 28 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PRPG_B_VAL ); REG64_FLD( PEC_OPCG_REG2_PRPG_B_VAL_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PRPG_B_VAL_LEN ); REG64_FLD( PEC_OPCG_REG2_PRPG_MODE , 40 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PRPG_MODE ); REG64_FLD( PEC_OPCG_REG2_UNUSED41_63 , 41 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED41_63 ); REG64_FLD( PEC_OPCG_REG2_UNUSED41_63_LEN , 23 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED41_63_LEN ); REG64_FLD( PU_NPU_CTL_OPTICAL_IO_CONFIG_NDLMUX_BRK0TO2 , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_NDLMUX_BRK0TO2 ); REG64_FLD( PU_NPU_CTL_OPTICAL_IO_CONFIG_NDLMUX_BRK0TO2_LEN , 3 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_NDLMUX_BRK0TO2_LEN ); REG64_FLD( PU_PBABAR0_CMD_SCOPE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CMD_SCOPE ); REG64_FLD( PU_PBABAR0_CMD_SCOPE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CMD_SCOPE_LEN ); REG64_FLD( PU_PBABAR0_RESERVED_3 , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_3 ); REG64_FLD( PU_PBABAR0_ADDR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR ); REG64_FLD( PU_PBABAR0_ADDR_LEN , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_LEN ); REG64_FLD( PU_PBABAR0_VTARGET , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VTARGET ); REG64_FLD( PU_PBABAR0_VTARGET_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VTARGET_LEN ); REG64_FLD( PU_PBABAR1_CMD_SCOPE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CMD_SCOPE ); REG64_FLD( PU_PBABAR1_CMD_SCOPE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CMD_SCOPE_LEN ); REG64_FLD( PU_PBABAR1_RESERVED_3 , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_3 ); REG64_FLD( PU_PBABAR1_ADDR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR ); REG64_FLD( PU_PBABAR1_ADDR_LEN , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_LEN ); REG64_FLD( PU_PBABAR1_VTARGET , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VTARGET ); REG64_FLD( PU_PBABAR1_VTARGET_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VTARGET_LEN ); REG64_FLD( PU_PBABAR2_CMD_SCOPE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CMD_SCOPE ); REG64_FLD( PU_PBABAR2_CMD_SCOPE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CMD_SCOPE_LEN ); REG64_FLD( PU_PBABAR2_RESERVED_3 , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_3 ); REG64_FLD( PU_PBABAR2_ADDR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR ); REG64_FLD( PU_PBABAR2_ADDR_LEN , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_LEN ); REG64_FLD( PU_PBABAR2_VTARGET , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VTARGET ); REG64_FLD( PU_PBABAR2_VTARGET_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VTARGET_LEN ); REG64_FLD( PU_PBABAR3_CMD_SCOPE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CMD_SCOPE ); REG64_FLD( PU_PBABAR3_CMD_SCOPE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CMD_SCOPE_LEN ); REG64_FLD( PU_PBABAR3_RESERVED_3 , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_3 ); REG64_FLD( PU_PBABAR3_ADDR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR ); REG64_FLD( PU_PBABAR3_ADDR_LEN , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_LEN ); REG64_FLD( PU_PBABAR3_VTARGET , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VTARGET ); REG64_FLD( PU_PBABAR3_VTARGET_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_VTARGET_LEN ); REG64_FLD( PU_PBABARMSK0_MSK , 23 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MSK ); REG64_FLD( PU_PBABARMSK0_MSK_LEN , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MSK_LEN ); REG64_FLD( PU_PBABARMSK1_MSK , 23 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MSK ); REG64_FLD( PU_PBABARMSK1_MSK_LEN , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MSK_LEN ); REG64_FLD( PU_PBABARMSK2_MSK , 23 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MSK ); REG64_FLD( PU_PBABARMSK2_MSK_LEN , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MSK_LEN ); REG64_FLD( PU_PBABARMSK3_MSK , 23 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MSK ); REG64_FLD( PU_PBABARMSK3_MSK_LEN , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MSK_LEN ); REG64_FLD( PU_PBACFG_PBREQ_SLVFW_MAX_PRIORITY , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBREQ_SLVFW_MAX_PRIORITY ); REG64_FLD( PU_PBACFG_PBREQ_EXIT_ON_HANG , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBREQ_EXIT_ON_HANG ); REG64_FLD( PU_PBACFG_PBREQ_BCE_MAX_PRIORITY , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBREQ_BCE_MAX_PRIORITY ); REG64_FLD( PU_PBACFG_PBREQ_EXIT_ON_HANG_PBAX , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBREQ_EXIT_ON_HANG_PBAX ); REG64_FLD( PU_PBACFG_PBREQ_DATA_HANG_DIV , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBREQ_DATA_HANG_DIV ); REG64_FLD( PU_PBACFG_PBREQ_DATA_HANG_DIV_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBREQ_DATA_HANG_DIV_LEN ); REG64_FLD( PU_PBACFG_PBREQ_OPER_HANG_DIV , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBREQ_OPER_HANG_DIV ); REG64_FLD( PU_PBACFG_PBREQ_OPER_HANG_DIV_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBREQ_OPER_HANG_DIV_LEN ); REG64_FLD( PU_PBACFG_PBREQ_DROP_PRIORITY_MASK , 14 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBREQ_DROP_PRIORITY_MASK ); REG64_FLD( PU_PBACFG_PBREQ_DROP_PRIORITY_MASK_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBREQ_DROP_PRIORITY_MASK_LEN ); REG64_FLD( PU_PBACFG_PBREQ_EXIT_HANG_DIV , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBREQ_EXIT_HANG_DIV ); REG64_FLD( PU_PBACFG_PBREQ_EXIT_HANG_DIV_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBREQ_EXIT_HANG_DIV_LEN ); REG64_FLD( PU_PBACFG_CHSW_HANG_ON_ADRERROR , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHSW_HANG_ON_ADRERROR ); REG64_FLD( PU_PBACFG_CHSW_DIS_OCIABUSPAR_CHECK , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHSW_DIS_OCIABUSPAR_CHECK ); REG64_FLD( PU_PBACFG_CHSW_DIS_OCIBEPAR_CHECK , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHSW_DIS_OCIBEPAR_CHECK ); REG64_FLD( PU_PBACFG_CHSW_HANG_ON_DERROR , 27 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHSW_HANG_ON_DERROR ); REG64_FLD( PU_PBACFG_RESERVED_28 , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_28 ); REG64_FLD( PU_PBACFG_CHSW_DIS_WRITE_MATCH_REARB , 29 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHSW_DIS_WRITE_MATCH_REARB ); REG64_FLD( PU_PBACFG_CHSW_DIS_OCIDATAPAR_GEN , 30 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHSW_DIS_OCIDATAPAR_GEN ); REG64_FLD( PU_PBACFG_CHSW_DIS_OCIDATAPAR_CHECK , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHSW_DIS_OCIDATAPAR_CHECK ); REG64_FLD( PU_PBACFG_CHSW_DIS_OPER_HANG , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHSW_DIS_OPER_HANG ); REG64_FLD( PU_PBACFG_CHSW_DIS_DATA_HANG , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHSW_DIS_DATA_HANG ); REG64_FLD( PU_PBACFG_CHSW_DIS_ECC_CHECK , 34 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHSW_DIS_ECC_CHECK ); REG64_FLD( PU_PBACFG_CHSW_DIS_RETRY_BACKOFF , 35 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHSW_DIS_RETRY_BACKOFF ); REG64_FLD( PU_PBACFG_CHSW_EXIT_ON_INVALID_CRESP , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHSW_EXIT_ON_INVALID_CRESP ); REG64_FLD( PU_PBACFG_RESERVED_37 , 37 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_37 ); REG64_FLD( PU_PBACFG_CHSW_DIS_GROUP_SCOPE , 38 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHSW_DIS_GROUP_SCOPE ); REG64_FLD( PU_PBACFG_CHSW_DIS_RTAG_PARITY_CHK , 39 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHSW_DIS_RTAG_PARITY_CHK ); REG64_FLD( PU_PBACFG_CHSW_DIS_PB_PARITY_CHK , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHSW_DIS_PB_PARITY_CHK ); REG64_FLD( PU_PBACFG_CHSW_SKIP_GROUP_SCOPE , 41 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHSW_SKIP_GROUP_SCOPE ); REG64_FLD( PU_PBACFG_CHSW_USE_PR_DMA_INJ , 42 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHSW_USE_PR_DMA_INJ ); REG64_FLD( PU_PBACFG_CHSW_USE_CL_DMA_INJ , 43 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHSW_USE_CL_DMA_INJ ); REG64_FLD( PU_PBACFG_RESERVED_44_47 , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_44_47 ); REG64_FLD( PU_PBACFG_RESERVED_44_47_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RESERVED_44_47_LEN ); REG64_FLD( PU_PBAERRRPT0_CERR_PB_RDDATATO_FW , 0 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_RDDATATO_FW ); REG64_FLD( PU_PBAERRRPT0_CERR_PB_RDDATATO_FW_LEN , 6 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_RDDATATO_FW_LEN ); REG64_FLD( PU_PBAERRRPT0_CERR_PB_RDADRERR_FW , 6 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_RDADRERR_FW ); REG64_FLD( PU_PBAERRRPT0_CERR_PB_RDADRERR_FW_LEN , 6 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_RDADRERR_FW_LEN ); REG64_FLD( PU_PBAERRRPT0_CERR_PB_WRADRERR_FW , 12 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_WRADRERR_FW ); REG64_FLD( PU_PBAERRRPT0_CERR_PB_WRADRERR_FW_LEN , 4 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_WRADRERR_FW_LEN ); REG64_FLD( PU_PBAERRRPT0_CERR_PB_ACKDEAD_FW_RD , 16 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_ACKDEAD_FW_RD ); REG64_FLD( PU_PBAERRRPT0_CERR_PB_ACKDEAD_FW_RD_LEN , 6 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_ACKDEAD_FW_RD_LEN ); REG64_FLD( PU_PBAERRRPT0_CERR_PB_ACKDEAD_FW_WR , 22 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_ACKDEAD_FW_WR ); REG64_FLD( PU_PBAERRRPT0_CERR_PB_ACKDEAD_FW_WR_LEN , 2 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_ACKDEAD_FW_WR_LEN ); REG64_FLD( PU_PBAERRRPT0_CERR_PB_UNEXPCRESP , 24 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_UNEXPCRESP ); REG64_FLD( PU_PBAERRRPT0_CERR_PB_UNEXPCRESP_LEN , 11 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_UNEXPCRESP_LEN ); REG64_FLD( PU_PBAERRRPT0_CERR_PB_UNEXPDATA , 35 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_UNEXPDATA ); REG64_FLD( PU_PBAERRRPT0_CERR_PB_UNEXPDATA_LEN , 6 , SH_UNT , SH_ACS_SCOM_WCLRPART, SH_FLD_CERR_PB_UNEXPDATA_LEN ); REG64_FLD( PU_PBAERRRPT1_CERR_PB_BADCRESP , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_PB_BADCRESP ); REG64_FLD( PU_PBAERRRPT1_CERR_PB_BADCRESP_LEN , 12 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_PB_BADCRESP_LEN ); REG64_FLD( PU_PBAERRRPT1_CERR_PB_OPERTO , 12 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_PB_OPERTO ); REG64_FLD( PU_PBAERRRPT1_CERR_PB_OPERTO_LEN , 12 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_PB_OPERTO_LEN ); REG64_FLD( PU_PBAERRRPT1_RESERVED_24_29 , 24 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RESERVED_24_29 ); REG64_FLD( PU_PBAERRRPT1_RESERVED_24_29_LEN , 6 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RESERVED_24_29_LEN ); REG64_FLD( PU_PBAERRRPT1_CERR_BCDE_SETUP_ERR , 30 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_BCDE_SETUP_ERR ); REG64_FLD( PU_PBAERRRPT1_CERR_BCDE_SETUP_ERR_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_BCDE_SETUP_ERR_LEN ); REG64_FLD( PU_PBAERRRPT1_CERR_BCUE_SETUP_ERR , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_BCUE_SETUP_ERR ); REG64_FLD( PU_PBAERRRPT1_CERR_BCUE_SETUP_ERR_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_BCUE_SETUP_ERR_LEN ); REG64_FLD( PU_PBAERRRPT1_CERR_BCUE_OCI_DATAERR , 34 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_BCUE_OCI_DATAERR ); REG64_FLD( PU_PBAERRRPT1_CERR_BCUE_OCI_DATAERR_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_BCUE_OCI_DATAERR_LEN ); REG64_FLD( PU_PBAERRRPT2_CERR_SLV_INTERNAL_ERR , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_SLV_INTERNAL_ERR ); REG64_FLD( PU_PBAERRRPT2_CERR_SLV_INTERNAL_ERR_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_SLV_INTERNAL_ERR_LEN ); REG64_FLD( PU_PBAERRRPT2_CERR_BCDE_INTERNAL_ERR , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_BCDE_INTERNAL_ERR ); REG64_FLD( PU_PBAERRRPT2_CERR_BCDE_INTERNAL_ERR_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_BCDE_INTERNAL_ERR_LEN ); REG64_FLD( PU_PBAERRRPT2_CERR_BCUE_INTERNAL_ERR , 12 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_BCUE_INTERNAL_ERR ); REG64_FLD( PU_PBAERRRPT2_CERR_BCUE_INTERNAL_ERR_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_BCUE_INTERNAL_ERR_LEN ); REG64_FLD( PU_PBAERRRPT2_CERR_BAR_PARITY_ERR , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_BAR_PARITY_ERR ); REG64_FLD( PU_PBAERRRPT2_CERR_SCOMTB_ERR , 17 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_SCOMTB_ERR ); REG64_FLD( PU_PBAERRRPT2_CERR_SPARE , 18 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_SPARE ); REG64_FLD( PU_PBAERRRPT2_CERR_SPARE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_SPARE_LEN ); REG64_FLD( PU_PBAERRRPT2_CERR_PBDOUT_PARITY_ERR , 20 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_PBDOUT_PARITY_ERR ); REG64_FLD( PU_PBAERRRPT2_CERR_PB_PARITY_ERR , 21 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_PB_PARITY_ERR ); REG64_FLD( PU_PBAERRRPT2_CERR_PB_PARITY_ERR_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_PB_PARITY_ERR_LEN ); REG64_FLD( PU_PBAERRRPT2_CERR_AXFLOW_ERR , 24 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_AXFLOW_ERR ); REG64_FLD( PU_PBAERRRPT2_CERR_AXFLOW_ERR_LEN , 5 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_AXFLOW_ERR_LEN ); REG64_FLD( PU_PBAERRRPT2_CERR_AXPUSH_WRERR , 29 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_AXPUSH_WRERR ); REG64_FLD( PU_PBAERRRPT2_CERR_AXPUSH_WRERR_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CERR_AXPUSH_WRERR_LEN ); REG64_FLD( PU_PBAFIR_OCI_APAR_ERR , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCI_APAR_ERR ); REG64_FLD( PU_PBAFIR_PB_RDADRERR_FW , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_RDADRERR_FW ); REG64_FLD( PU_PBAFIR_PB_RDDATATO_FW , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_RDDATATO_FW ); REG64_FLD( PU_PBAFIR_PB_SUE_FW , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_SUE_FW ); REG64_FLD( PU_PBAFIR_PB_UE_FW , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_UE_FW ); REG64_FLD( PU_PBAFIR_PB_CE_FW , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_CE_FW ); REG64_FLD( PU_PBAFIR_OCI_SLAVE_INIT , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCI_SLAVE_INIT ); REG64_FLD( PU_PBAFIR_OCI_WRPAR_ERR , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCI_WRPAR_ERR ); REG64_FLD( PU_PBAFIR_RESERVED_8 , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_8 ); REG64_FLD( PU_PBAFIR_PB_UNEXPCRESP , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_UNEXPCRESP ); REG64_FLD( PU_PBAFIR_PB_UNEXPDATA , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_UNEXPDATA ); REG64_FLD( PU_PBAFIR_PB_PARITY_ERR , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_PARITY_ERR ); REG64_FLD( PU_PBAFIR_PB_WRADRERR_FW , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_WRADRERR_FW ); REG64_FLD( PU_PBAFIR_PB_BADCRESP , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_BADCRESP ); REG64_FLD( PU_PBAFIR_PB_ACKDEAD_FW_RD , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_ACKDEAD_FW_RD ); REG64_FLD( PU_PBAFIR_PB_OPERTO , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_OPERTO ); REG64_FLD( PU_PBAFIR_BCUE_SETUP_ERR , 16 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCUE_SETUP_ERR ); REG64_FLD( PU_PBAFIR_BCUE_PB_ACK_DEAD , 17 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCUE_PB_ACK_DEAD ); REG64_FLD( PU_PBAFIR_BCUE_PB_ADRERR , 18 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCUE_PB_ADRERR ); REG64_FLD( PU_PBAFIR_BCUE_OCI_DATERR , 19 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCUE_OCI_DATERR ); REG64_FLD( PU_PBAFIR_BCDE_SETUP_ERR , 20 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCDE_SETUP_ERR ); REG64_FLD( PU_PBAFIR_BCDE_PB_ACK_DEAD , 21 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCDE_PB_ACK_DEAD ); REG64_FLD( PU_PBAFIR_BCDE_PB_ADRERR , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCDE_PB_ADRERR ); REG64_FLD( PU_PBAFIR_BCDE_RDDATATO_ERR , 23 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCDE_RDDATATO_ERR ); REG64_FLD( PU_PBAFIR_BCDE_SUE_ERR , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCDE_SUE_ERR ); REG64_FLD( PU_PBAFIR_BCDE_UE_ERR , 25 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCDE_UE_ERR ); REG64_FLD( PU_PBAFIR_BCDE_CE , 26 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCDE_CE ); REG64_FLD( PU_PBAFIR_BCDE_OCI_DATERR , 27 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCDE_OCI_DATERR ); REG64_FLD( PU_PBAFIR_INTERNAL_ERR , 28 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_ERR ); REG64_FLD( PU_PBAFIR_ILLEGAL_CACHE_OP , 29 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ILLEGAL_CACHE_OP ); REG64_FLD( PU_PBAFIR_OCI_BAD_REG_ADDR , 30 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCI_BAD_REG_ADDR ); REG64_FLD( PU_PBAFIR_AXPUSH_WRERR , 31 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AXPUSH_WRERR ); REG64_FLD( PU_PBAFIR_AXRCV_DLO_ERR , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AXRCV_DLO_ERR ); REG64_FLD( PU_PBAFIR_AXRCV_DLO_TO , 33 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AXRCV_DLO_TO ); REG64_FLD( PU_PBAFIR_AXRCV_RSVDATA_TO , 34 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AXRCV_RSVDATA_TO ); REG64_FLD( PU_PBAFIR_AXFLOW_ERR , 35 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AXFLOW_ERR ); REG64_FLD( PU_PBAFIR_AXSND_DHI_RTYTO , 36 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AXSND_DHI_RTYTO ); REG64_FLD( PU_PBAFIR_AXSND_DLO_RTYTO , 37 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AXSND_DLO_RTYTO ); REG64_FLD( PU_PBAFIR_AXSND_RSVTO , 38 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AXSND_RSVTO ); REG64_FLD( PU_PBAFIR_AXSND_RSVERR , 39 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AXSND_RSVERR ); REG64_FLD( PU_PBAFIR_PB_ACKDEAD_FW_WR , 40 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_ACKDEAD_FW_WR ); REG64_FLD( PU_PBAFIR_RESERVED_41 , 41 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_41 ); REG64_FLD( PU_PBAFIR_RESERVED_42 , 42 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_42 ); REG64_FLD( PU_PBAFIR_RESERVED_43 , 43 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_43 ); REG64_FLD( PU_PBAFIR_FIR_PARITY_ERR2 , 44 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR2 ); REG64_FLD( PU_PBAFIR_FIR_PARITY_ERR , 45 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR ); REG64_FLD( PU_PBAFIRACT0_FIR_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION0 ); REG64_FLD( PU_PBAFIRACT0_FIR_ACTION0_LEN , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION0_LEN ); REG64_FLD( PU_PBAFIRACT1_FIR_ACTION1 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION1 ); REG64_FLD( PU_PBAFIRACT1_FIR_ACTION1_LEN , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION1_LEN ); REG64_FLD( PU_PBAFIRMASK_OCI_APAR_ERR_MASK , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCI_APAR_ERR_MASK ); REG64_FLD( PU_PBAFIRMASK_PB_RDADRERR_FW_MASK , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_RDADRERR_FW_MASK ); REG64_FLD( PU_PBAFIRMASK_PB_RDDATATO_FW_MASK , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_RDDATATO_FW_MASK ); REG64_FLD( PU_PBAFIRMASK_PB_SUE_FW_MASK , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_SUE_FW_MASK ); REG64_FLD( PU_PBAFIRMASK_PB_UE_FW_MASK , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_UE_FW_MASK ); REG64_FLD( PU_PBAFIRMASK_PB_CE_FW_MASK , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_CE_FW_MASK ); REG64_FLD( PU_PBAFIRMASK_OCI_SLAVE_INIT_MASK , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCI_SLAVE_INIT_MASK ); REG64_FLD( PU_PBAFIRMASK_OCI_WRPAR_ERR_MASK , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCI_WRPAR_ERR_MASK ); REG64_FLD( PU_PBAFIRMASK_RESERVED_8 , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_8 ); REG64_FLD( PU_PBAFIRMASK_PB_UNEXPCRESP_MASK , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_UNEXPCRESP_MASK ); REG64_FLD( PU_PBAFIRMASK_PB_UNEXPDATA_MASK , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_UNEXPDATA_MASK ); REG64_FLD( PU_PBAFIRMASK_PB_PARITY_ERR_MASK , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_PARITY_ERR_MASK ); REG64_FLD( PU_PBAFIRMASK_PB_WRADRERR_FW_MASK , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_WRADRERR_FW_MASK ); REG64_FLD( PU_PBAFIRMASK_PB_BADCRESP_MASK , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_BADCRESP_MASK ); REG64_FLD( PU_PBAFIRMASK_PB_ACKDEAD_FW_RD_MASK , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_ACKDEAD_FW_RD_MASK ); REG64_FLD( PU_PBAFIRMASK_PB_OPERTO_MASK , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_OPERTO_MASK ); REG64_FLD( PU_PBAFIRMASK_BCUE_SETUP_ERR_MASK , 16 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCUE_SETUP_ERR_MASK ); REG64_FLD( PU_PBAFIRMASK_BCUE_PB_ACK_DEAD_MASK , 17 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCUE_PB_ACK_DEAD_MASK ); REG64_FLD( PU_PBAFIRMASK_BCUE_PB_ADRERR_MASK , 18 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCUE_PB_ADRERR_MASK ); REG64_FLD( PU_PBAFIRMASK_BCUE_OCI_DATERR_MASK , 19 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCUE_OCI_DATERR_MASK ); REG64_FLD( PU_PBAFIRMASK_BCDE_SETUP_ERR_MASK , 20 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCDE_SETUP_ERR_MASK ); REG64_FLD( PU_PBAFIRMASK_BCDE_PB_ACK_DEAD_MASK , 21 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCDE_PB_ACK_DEAD_MASK ); REG64_FLD( PU_PBAFIRMASK_BCDE_PB_ADRERR_MASK , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCDE_PB_ADRERR_MASK ); REG64_FLD( PU_PBAFIRMASK_BCDE_RDDATATO_ERR_MASK , 23 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCDE_RDDATATO_ERR_MASK ); REG64_FLD( PU_PBAFIRMASK_BCDE_SUE_ERR_MASK , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCDE_SUE_ERR_MASK ); REG64_FLD( PU_PBAFIRMASK_BCDE_UE_ERR_MASK , 25 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCDE_UE_ERR_MASK ); REG64_FLD( PU_PBAFIRMASK_BCDE_CE_MASK , 26 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCDE_CE_MASK ); REG64_FLD( PU_PBAFIRMASK_BCDE_OCI_DATERR_MASK , 27 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCDE_OCI_DATERR_MASK ); REG64_FLD( PU_PBAFIRMASK_INTERNAL_ERR_MASK , 28 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_ERR_MASK ); REG64_FLD( PU_PBAFIRMASK_ILLEGAL_CACHE_OP_MASK , 29 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ILLEGAL_CACHE_OP_MASK ); REG64_FLD( PU_PBAFIRMASK_OCI_BAD_REG_ADDR_MASK , 30 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OCI_BAD_REG_ADDR_MASK ); REG64_FLD( PU_PBAFIRMASK_AXPUSH_WRERR_MASK , 31 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AXPUSH_WRERR_MASK ); REG64_FLD( PU_PBAFIRMASK_AXRCV_DLO_ERR_MASK , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AXRCV_DLO_ERR_MASK ); REG64_FLD( PU_PBAFIRMASK_AXRCV_DLO_TO_MASK , 33 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AXRCV_DLO_TO_MASK ); REG64_FLD( PU_PBAFIRMASK_AXRCV_RSVDATA_TO_MASK , 34 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AXRCV_RSVDATA_TO_MASK ); REG64_FLD( PU_PBAFIRMASK_AXFLOW_ERR_MASK , 35 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AXFLOW_ERR_MASK ); REG64_FLD( PU_PBAFIRMASK_AXSND_DHI_RTYTO_MASK , 36 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AXSND_DHI_RTYTO_MASK ); REG64_FLD( PU_PBAFIRMASK_AXSND_DLO_RTYTO_MASK , 37 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AXSND_DLO_RTYTO_MASK ); REG64_FLD( PU_PBAFIRMASK_AXSND_RSVTO_MASK , 38 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AXSND_RSVTO_MASK ); REG64_FLD( PU_PBAFIRMASK_AXSND_RSVERR_MASK , 39 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_AXSND_RSVERR_MASK ); REG64_FLD( PU_PBAFIRMASK_PB_ACKDEAD_FW_WR_MASK , 40 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_ACKDEAD_FW_WR_MASK ); REG64_FLD( PU_PBAFIRMASK_RESERVED_41_43 , 41 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_41_43 ); REG64_FLD( PU_PBAFIRMASK_RESERVED_41_43_LEN , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED_41_43_LEN ); REG64_FLD( PU_PBAFIRMASK_FIR_PARITY_ERR2_MASK , 44 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR2_MASK ); REG64_FLD( PU_PBAFIRMASK_FIR_PARITY_ERR_MASK , 45 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR_MASK ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_DATASTART_MODE , 16 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_OSMB_DATASTART_MODE ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_DATASTART_MODE_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_OSMB_DATASTART_MODE_LEN ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_TX_RESP_HWM , 20 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_TX_RESP_HWM ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_TX_RESP_HWM_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_TX_RESP_HWM_LEN ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_TX_RESP_LWM , 24 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_TX_RESP_LWM ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_TX_RESP_LWM_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_TX_RESP_LWM_LEN ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_EARLYEMPTY_MODE , 28 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_OSMB_EARLYEMPTY_MODE ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_EARLYEMPTY_MODE_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_OSMB_EARLYEMPTY_MODE_LEN ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_PCIE_CLK_TRACE_EN , 30 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PCIE_CLK_TRACE_EN ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_SELECT_ETU_TRACE , 31 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_SELECT_ETU_TRACE ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_PCI_CLK_TRACE_SEL , 32 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PCI_CLK_TRACE_SEL ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_PCI_CLK_TRACE_SEL_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PCI_CLK_TRACE_SEL_LEN ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_ISMB_ERROR_INJECT , 36 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_ISMB_ERROR_INJECT ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_ISMB_ERROR_INJECT_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_ISMB_ERROR_INJECT_LEN ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT , 40 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_OSMB_HOL_BLK_CNT ); REG64_FLD( PEC_PBAIBHWCFG_REG_PE_OSMB_HOL_BLK_CNT_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_OSMB_HOL_BLK_CNT_LEN ); REG64_FLD( PU_PBAMODE_RESERVED_0_3 , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_3 ); REG64_FLD( PU_PBAMODE_RESERVED_0_3_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_0_3_LEN ); REG64_FLD( PU_PBAMODE_DIS_REARB , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_REARB ); REG64_FLD( PU_PBAMODE_DIS_MSTID_MATCH_PREF_INV , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_MSTID_MATCH_PREF_INV ); REG64_FLD( PU_PBAMODE_DIS_SLAVE_RDPIPE , 6 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_SLAVE_RDPIPE ); REG64_FLD( PU_PBAMODE_DIS_SLAVE_WRPIPE , 7 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_SLAVE_WRPIPE ); REG64_FLD( PU_PBAMODE_EN_MARKER_ACK , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_EN_MARKER_ACK ); REG64_FLD( PU_PBAMODE_RESERVED_9 , 9 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_9 ); REG64_FLD( PU_PBAMODE_EN_SECOND_WRBUF , 10 , SH_UNT , SH_ACS_PIB , SH_FLD_EN_SECOND_WRBUF ); REG64_FLD( PU_PBAMODE_DIS_REREQUEST_TO , 11 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_REREQUEST_TO ); REG64_FLD( PU_PBAMODE_INJECT_TYPE , 12 , SH_UNT , SH_ACS_PIB , SH_FLD_INJECT_TYPE ); REG64_FLD( PU_PBAMODE_INJECT_TYPE_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_INJECT_TYPE_LEN ); REG64_FLD( PU_PBAMODE_INJECT_MODE , 14 , SH_UNT , SH_ACS_PIB , SH_FLD_INJECT_MODE ); REG64_FLD( PU_PBAMODE_INJECT_MODE_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_INJECT_MODE_LEN ); REG64_FLD( PU_PBAMODE_PBA_REGION , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_PBA_REGION ); REG64_FLD( PU_PBAMODE_PBA_REGION_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_PBA_REGION_LEN ); REG64_FLD( PU_PBAMODE_OCI_MARKER_SPACE , 18 , SH_UNT , SH_ACS_PIB , SH_FLD_OCI_MARKER_SPACE ); REG64_FLD( PU_PBAMODE_OCI_MARKER_SPACE_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_OCI_MARKER_SPACE_LEN ); REG64_FLD( PU_PBAMODE_BCDE_OCITRANS , 21 , SH_UNT , SH_ACS_PIB , SH_FLD_BCDE_OCITRANS ); REG64_FLD( PU_PBAMODE_BCDE_OCITRANS_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_BCDE_OCITRANS_LEN ); REG64_FLD( PU_PBAMODE_BCUE_OCITRANS , 23 , SH_UNT , SH_ACS_PIB , SH_FLD_BCUE_OCITRANS ); REG64_FLD( PU_PBAMODE_BCUE_OCITRANS_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_BCUE_OCITRANS_LEN ); REG64_FLD( PU_PBAMODE_DIS_MASTER_RD_PIPE , 25 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_MASTER_RD_PIPE ); REG64_FLD( PU_PBAMODE_DIS_MASTER_WR_PIPE , 26 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_MASTER_WR_PIPE ); REG64_FLD( PU_PBAMODE_EN_SLV_FAIRNESS , 27 , SH_UNT , SH_ACS_PIB , SH_FLD_EN_SLV_FAIRNESS ); REG64_FLD( PU_PBAMODE_EN_EVENT_COUNT , 28 , SH_UNT , SH_ACS_PIB , SH_FLD_EN_EVENT_COUNT ); REG64_FLD( PU_PBAMODE_PB_NOCI_EVENT_SEL , 29 , SH_UNT , SH_ACS_PIB , SH_FLD_PB_NOCI_EVENT_SEL ); REG64_FLD( PU_PBAMODE_SLV_EVENT_MUX , 30 , SH_UNT , SH_ACS_PIB , SH_FLD_SLV_EVENT_MUX ); REG64_FLD( PU_PBAMODE_SLV_EVENT_MUX_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_SLV_EVENT_MUX_LEN ); REG64_FLD( PU_PBAMODE_ENABLE_DEBUG_BUS , 32 , SH_UNT , SH_ACS_PIB , SH_FLD_ENABLE_DEBUG_BUS ); REG64_FLD( PU_PBAMODE_DEBUG_PB_NOT_OCI , 33 , SH_UNT , SH_ACS_PIB , SH_FLD_DEBUG_PB_NOT_OCI ); REG64_FLD( PU_PBAMODE_DEBUG_OCI_MODE , 34 , SH_UNT , SH_ACS_PIB , SH_FLD_DEBUG_OCI_MODE ); REG64_FLD( PU_PBAMODE_DEBUG_OCI_MODE_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_DEBUG_OCI_MODE_LEN ); REG64_FLD( PU_PBAMODE_RESERVED_39 , 39 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_39 ); REG64_FLD( PU_PBAMODE_OCISLV_FAIRNESS_MASK , 40 , SH_UNT , SH_ACS_PIB , SH_FLD_OCISLV_FAIRNESS_MASK ); REG64_FLD( PU_PBAMODE_OCISLV_FAIRNESS_MASK_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_OCISLV_FAIRNESS_MASK_LEN ); REG64_FLD( PU_PBAMODE_OCISLV_REREQ_HANG_DIV , 45 , SH_UNT , SH_ACS_PIB , SH_FLD_OCISLV_REREQ_HANG_DIV ); REG64_FLD( PU_PBAMODE_OCISLV_REREQ_HANG_DIV_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_OCISLV_REREQ_HANG_DIV_LEN ); REG64_FLD( PU_PBAMODE_DIS_CHGRATE_COUNT , 50 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_CHGRATE_COUNT ); REG64_FLD( PU_PBAMODE_PBREQ_EVENT_MUX , 51 , SH_UNT , SH_ACS_PIB , SH_FLD_PBREQ_EVENT_MUX ); REG64_FLD( PU_PBAMODE_PBREQ_EVENT_MUX_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_PBREQ_EVENT_MUX_LEN ); REG64_FLD( PU_PBAMODE_RESERVED_53_63 , 53 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_53_63 ); REG64_FLD( PU_PBAMODE_RESERVED_53_63_LEN , 11 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_53_63_LEN ); REG64_FLD( PU_PBAOCCACT_OCC_ACTION_SET , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCC_ACTION_SET ); REG64_FLD( PU_PBAOCCACT_OCC_ACTION_SET_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_OCC_ACTION_SET_LEN ); REG64_FLD( PU_PBAPBOCR0_EVENT , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT ); REG64_FLD( PU_PBAPBOCR0_EVENT_LEN , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT_LEN ); REG64_FLD( PU_PBAPBOCR0_ACCUM , 44 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM ); REG64_FLD( PU_PBAPBOCR0_ACCUM_LEN , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM_LEN ); REG64_FLD( PU_PBAPBOCR1_EVENT , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT ); REG64_FLD( PU_PBAPBOCR1_EVENT_LEN , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT_LEN ); REG64_FLD( PU_PBAPBOCR1_ACCUM , 44 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM ); REG64_FLD( PU_PBAPBOCR1_ACCUM_LEN , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM_LEN ); REG64_FLD( PU_PBAPBOCR2_EVENT , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT ); REG64_FLD( PU_PBAPBOCR2_EVENT_LEN , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT_LEN ); REG64_FLD( PU_PBAPBOCR2_ACCUM , 44 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM ); REG64_FLD( PU_PBAPBOCR2_ACCUM_LEN , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM_LEN ); REG64_FLD( PU_PBAPBOCR3_EVENT , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT ); REG64_FLD( PU_PBAPBOCR3_EVENT_LEN , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT_LEN ); REG64_FLD( PU_PBAPBOCR3_ACCUM , 44 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM ); REG64_FLD( PU_PBAPBOCR3_ACCUM_LEN , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM_LEN ); REG64_FLD( PU_PBAPBOCR4_EVENT , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT ); REG64_FLD( PU_PBAPBOCR4_EVENT_LEN , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT_LEN ); REG64_FLD( PU_PBAPBOCR4_ACCUM , 44 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM ); REG64_FLD( PU_PBAPBOCR4_ACCUM_LEN , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM_LEN ); REG64_FLD( PU_PBAPBOCR5_EVENT , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT ); REG64_FLD( PU_PBAPBOCR5_EVENT_LEN , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_EVENT_LEN ); REG64_FLD( PU_PBAPBOCR5_ACCUM , 44 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM ); REG64_FLD( PU_PBAPBOCR5_ACCUM_LEN , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_ACCUM_LEN ); REG64_FLD( PU_PBARBUFVAL0_RD_SLVNUM , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RD_SLVNUM ); REG64_FLD( PU_PBARBUFVAL0_RD_SLVNUM_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RD_SLVNUM_LEN ); REG64_FLD( PU_PBARBUFVAL0_CUR_RD_ADDR , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CUR_RD_ADDR ); REG64_FLD( PU_PBARBUFVAL0_CUR_RD_ADDR_LEN , 23 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CUR_RD_ADDR_LEN ); REG64_FLD( PU_PBARBUFVAL0_PREFETCH , 28 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PREFETCH ); REG64_FLD( PU_PBARBUFVAL0_ABORT , 31 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ABORT ); REG64_FLD( PU_PBARBUFVAL0_BUFFER_STATUS , 33 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_BUFFER_STATUS ); REG64_FLD( PU_PBARBUFVAL0_BUFFER_STATUS_LEN , 7 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_BUFFER_STATUS_LEN ); REG64_FLD( PU_PBARBUFVAL0_MASTERID , 41 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MASTERID ); REG64_FLD( PU_PBARBUFVAL0_MASTERID_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MASTERID_LEN ); REG64_FLD( PU_PBARBUFVAL1_RD_SLVNUM , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RD_SLVNUM ); REG64_FLD( PU_PBARBUFVAL1_RD_SLVNUM_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RD_SLVNUM_LEN ); REG64_FLD( PU_PBARBUFVAL1_CUR_RD_ADDR , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CUR_RD_ADDR ); REG64_FLD( PU_PBARBUFVAL1_CUR_RD_ADDR_LEN , 23 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CUR_RD_ADDR_LEN ); REG64_FLD( PU_PBARBUFVAL1_PREFETCH , 28 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PREFETCH ); REG64_FLD( PU_PBARBUFVAL1_ABORT , 31 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ABORT ); REG64_FLD( PU_PBARBUFVAL1_BUFFER_STATUS , 33 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_BUFFER_STATUS ); REG64_FLD( PU_PBARBUFVAL1_BUFFER_STATUS_LEN , 7 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_BUFFER_STATUS_LEN ); REG64_FLD( PU_PBARBUFVAL1_MASTERID , 41 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MASTERID ); REG64_FLD( PU_PBARBUFVAL1_MASTERID_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MASTERID_LEN ); REG64_FLD( PU_PBARBUFVAL2_RD_SLVNUM , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RD_SLVNUM ); REG64_FLD( PU_PBARBUFVAL2_RD_SLVNUM_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RD_SLVNUM_LEN ); REG64_FLD( PU_PBARBUFVAL2_CUR_RD_ADDR , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CUR_RD_ADDR ); REG64_FLD( PU_PBARBUFVAL2_CUR_RD_ADDR_LEN , 23 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CUR_RD_ADDR_LEN ); REG64_FLD( PU_PBARBUFVAL2_PREFETCH , 28 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PREFETCH ); REG64_FLD( PU_PBARBUFVAL2_ABORT , 31 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ABORT ); REG64_FLD( PU_PBARBUFVAL2_BUFFER_STATUS , 33 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_BUFFER_STATUS ); REG64_FLD( PU_PBARBUFVAL2_BUFFER_STATUS_LEN , 7 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_BUFFER_STATUS_LEN ); REG64_FLD( PU_PBARBUFVAL2_MASTERID , 41 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MASTERID ); REG64_FLD( PU_PBARBUFVAL2_MASTERID_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MASTERID_LEN ); REG64_FLD( PU_PBARBUFVAL3_RD_SLVNUM , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RD_SLVNUM ); REG64_FLD( PU_PBARBUFVAL3_RD_SLVNUM_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RD_SLVNUM_LEN ); REG64_FLD( PU_PBARBUFVAL3_CUR_RD_ADDR , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CUR_RD_ADDR ); REG64_FLD( PU_PBARBUFVAL3_CUR_RD_ADDR_LEN , 23 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CUR_RD_ADDR_LEN ); REG64_FLD( PU_PBARBUFVAL3_PREFETCH , 28 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PREFETCH ); REG64_FLD( PU_PBARBUFVAL3_ABORT , 31 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ABORT ); REG64_FLD( PU_PBARBUFVAL3_BUFFER_STATUS , 33 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_BUFFER_STATUS ); REG64_FLD( PU_PBARBUFVAL3_BUFFER_STATUS_LEN , 7 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_BUFFER_STATUS_LEN ); REG64_FLD( PU_PBARBUFVAL3_MASTERID , 41 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MASTERID ); REG64_FLD( PU_PBARBUFVAL3_MASTERID_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MASTERID_LEN ); REG64_FLD( PU_PBARBUFVAL4_RD_SLVNUM , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RD_SLVNUM ); REG64_FLD( PU_PBARBUFVAL4_RD_SLVNUM_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RD_SLVNUM_LEN ); REG64_FLD( PU_PBARBUFVAL4_CUR_RD_ADDR , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CUR_RD_ADDR ); REG64_FLD( PU_PBARBUFVAL4_CUR_RD_ADDR_LEN , 23 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CUR_RD_ADDR_LEN ); REG64_FLD( PU_PBARBUFVAL4_PREFETCH , 28 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PREFETCH ); REG64_FLD( PU_PBARBUFVAL4_ABORT , 31 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ABORT ); REG64_FLD( PU_PBARBUFVAL4_BUFFER_STATUS , 33 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_BUFFER_STATUS ); REG64_FLD( PU_PBARBUFVAL4_BUFFER_STATUS_LEN , 7 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_BUFFER_STATUS_LEN ); REG64_FLD( PU_PBARBUFVAL4_MASTERID , 41 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MASTERID ); REG64_FLD( PU_PBARBUFVAL4_MASTERID_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MASTERID_LEN ); REG64_FLD( PU_PBARBUFVAL5_RD_SLVNUM , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RD_SLVNUM ); REG64_FLD( PU_PBARBUFVAL5_RD_SLVNUM_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RD_SLVNUM_LEN ); REG64_FLD( PU_PBARBUFVAL5_CUR_RD_ADDR , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CUR_RD_ADDR ); REG64_FLD( PU_PBARBUFVAL5_CUR_RD_ADDR_LEN , 23 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CUR_RD_ADDR_LEN ); REG64_FLD( PU_PBARBUFVAL5_PREFETCH , 28 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PREFETCH ); REG64_FLD( PU_PBARBUFVAL5_ABORT , 31 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ABORT ); REG64_FLD( PU_PBARBUFVAL5_BUFFER_STATUS , 33 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_BUFFER_STATUS ); REG64_FLD( PU_PBARBUFVAL5_BUFFER_STATUS_LEN , 7 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_BUFFER_STATUS_LEN ); REG64_FLD( PU_PBARBUFVAL5_MASTERID , 41 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MASTERID ); REG64_FLD( PU_PBARBUFVAL5_MASTERID_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MASTERID_LEN ); REG64_FLD( PU_PBASLVCTL0_ENABLE , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_ENABLE ); REG64_FLD( PU_PBASLVCTL0_MID_MATCH_VALUE , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_MATCH_VALUE ); REG64_FLD( PU_PBASLVCTL0_MID_MATCH_VALUE_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_MATCH_VALUE_LEN ); REG64_FLD( PU_PBASLVCTL0_RESERVED_4 , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_4 ); REG64_FLD( PU_PBASLVCTL0_MID_CARE_MASK , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_CARE_MASK ); REG64_FLD( PU_PBASLVCTL0_MID_CARE_MASK_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_CARE_MASK_LEN ); REG64_FLD( PU_PBASLVCTL0_WRITE_TTYPE , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TTYPE ); REG64_FLD( PU_PBASLVCTL0_WRITE_TTYPE_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TTYPE_LEN ); REG64_FLD( PU_PBASLVCTL0_RESERVED_11_14 , 11 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_11_14 ); REG64_FLD( PU_PBASLVCTL0_RESERVED_11_14_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_11_14_LEN ); REG64_FLD( PU_PBASLVCTL0_READ_TTYPE , 15 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_TTYPE ); REG64_FLD( PU_PBASLVCTL0_READ_PREFETCH_CTL , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_PREFETCH_CTL ); REG64_FLD( PU_PBASLVCTL0_READ_PREFETCH_CTL_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_PREFETCH_CTL_LEN ); REG64_FLD( PU_PBASLVCTL0_BUF_INVALIDATE_CTL , 18 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_INVALIDATE_CTL ); REG64_FLD( PU_PBASLVCTL0_BUF_ALLOC_W , 19 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_W ); REG64_FLD( PU_PBASLVCTL0_BUF_ALLOC_A , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_A ); REG64_FLD( PU_PBASLVCTL0_BUF_ALLOC_B , 21 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_B ); REG64_FLD( PU_PBASLVCTL0_BUF_ALLOC_C , 22 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_C ); REG64_FLD( PU_PBASLVCTL0_RESERVED_23 , 23 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_23 ); REG64_FLD( PU_PBASLVCTL0_DIS_WRITE_GATHER , 24 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_WRITE_GATHER ); REG64_FLD( PU_PBASLVCTL0_WR_GATHER_TIMEOUT , 25 , SH_UNT , SH_ACS_PIB , SH_FLD_WR_GATHER_TIMEOUT ); REG64_FLD( PU_PBASLVCTL0_WR_GATHER_TIMEOUT_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_WR_GATHER_TIMEOUT_LEN ); REG64_FLD( PU_PBASLVCTL0_WRITE_TSIZE , 28 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TSIZE ); REG64_FLD( PU_PBASLVCTL0_WRITE_TSIZE_LEN , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TSIZE_LEN ); REG64_FLD( PU_PBASLVCTL0_EXTADDR , 36 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR ); REG64_FLD( PU_PBASLVCTL0_EXTADDR_LEN , 14 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR_LEN ); REG64_FLD( PU_PBASLVCTL0_RESERVED_50 , 50 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_50 ); REG64_FLD( PU_PBASLVCTL1_ENABLE , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_ENABLE ); REG64_FLD( PU_PBASLVCTL1_MID_MATCH_VALUE , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_MATCH_VALUE ); REG64_FLD( PU_PBASLVCTL1_MID_MATCH_VALUE_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_MATCH_VALUE_LEN ); REG64_FLD( PU_PBASLVCTL1_RESERVED_4 , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_4 ); REG64_FLD( PU_PBASLVCTL1_MID_CARE_MASK , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_CARE_MASK ); REG64_FLD( PU_PBASLVCTL1_MID_CARE_MASK_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_CARE_MASK_LEN ); REG64_FLD( PU_PBASLVCTL1_WRITE_TTYPE , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TTYPE ); REG64_FLD( PU_PBASLVCTL1_WRITE_TTYPE_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TTYPE_LEN ); REG64_FLD( PU_PBASLVCTL1_RESERVED_11_14 , 11 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_11_14 ); REG64_FLD( PU_PBASLVCTL1_RESERVED_11_14_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_11_14_LEN ); REG64_FLD( PU_PBASLVCTL1_READ_TTYPE , 15 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_TTYPE ); REG64_FLD( PU_PBASLVCTL1_READ_PREFETCH_CTL , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_PREFETCH_CTL ); REG64_FLD( PU_PBASLVCTL1_READ_PREFETCH_CTL_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_PREFETCH_CTL_LEN ); REG64_FLD( PU_PBASLVCTL1_BUF_INVALIDATE_CTL , 18 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_INVALIDATE_CTL ); REG64_FLD( PU_PBASLVCTL1_BUF_ALLOC_W , 19 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_W ); REG64_FLD( PU_PBASLVCTL1_BUF_ALLOC_A , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_A ); REG64_FLD( PU_PBASLVCTL1_BUF_ALLOC_B , 21 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_B ); REG64_FLD( PU_PBASLVCTL1_BUF_ALLOC_C , 22 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_C ); REG64_FLD( PU_PBASLVCTL1_RESERVED_23 , 23 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_23 ); REG64_FLD( PU_PBASLVCTL1_DIS_WRITE_GATHER , 24 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_WRITE_GATHER ); REG64_FLD( PU_PBASLVCTL1_WR_GATHER_TIMEOUT , 25 , SH_UNT , SH_ACS_PIB , SH_FLD_WR_GATHER_TIMEOUT ); REG64_FLD( PU_PBASLVCTL1_WR_GATHER_TIMEOUT_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_WR_GATHER_TIMEOUT_LEN ); REG64_FLD( PU_PBASLVCTL1_WRITE_TSIZE , 28 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TSIZE ); REG64_FLD( PU_PBASLVCTL1_WRITE_TSIZE_LEN , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TSIZE_LEN ); REG64_FLD( PU_PBASLVCTL1_EXTADDR , 36 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR ); REG64_FLD( PU_PBASLVCTL1_EXTADDR_LEN , 14 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR_LEN ); REG64_FLD( PU_PBASLVCTL1_RESERVED_50 , 50 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_50 ); REG64_FLD( PU_PBASLVCTL2_ENABLE , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_ENABLE ); REG64_FLD( PU_PBASLVCTL2_MID_MATCH_VALUE , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_MATCH_VALUE ); REG64_FLD( PU_PBASLVCTL2_MID_MATCH_VALUE_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_MATCH_VALUE_LEN ); REG64_FLD( PU_PBASLVCTL2_RESERVED_4 , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_4 ); REG64_FLD( PU_PBASLVCTL2_MID_CARE_MASK , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_CARE_MASK ); REG64_FLD( PU_PBASLVCTL2_MID_CARE_MASK_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_CARE_MASK_LEN ); REG64_FLD( PU_PBASLVCTL2_WRITE_TTYPE , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TTYPE ); REG64_FLD( PU_PBASLVCTL2_WRITE_TTYPE_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TTYPE_LEN ); REG64_FLD( PU_PBASLVCTL2_RESERVED_11_14 , 11 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_11_14 ); REG64_FLD( PU_PBASLVCTL2_RESERVED_11_14_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_11_14_LEN ); REG64_FLD( PU_PBASLVCTL2_READ_TTYPE , 15 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_TTYPE ); REG64_FLD( PU_PBASLVCTL2_READ_PREFETCH_CTL , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_PREFETCH_CTL ); REG64_FLD( PU_PBASLVCTL2_READ_PREFETCH_CTL_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_PREFETCH_CTL_LEN ); REG64_FLD( PU_PBASLVCTL2_BUF_INVALIDATE_CTL , 18 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_INVALIDATE_CTL ); REG64_FLD( PU_PBASLVCTL2_BUF_ALLOC_W , 19 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_W ); REG64_FLD( PU_PBASLVCTL2_BUF_ALLOC_A , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_A ); REG64_FLD( PU_PBASLVCTL2_BUF_ALLOC_B , 21 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_B ); REG64_FLD( PU_PBASLVCTL2_BUF_ALLOC_C , 22 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_C ); REG64_FLD( PU_PBASLVCTL2_RESERVED_23 , 23 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_23 ); REG64_FLD( PU_PBASLVCTL2_DIS_WRITE_GATHER , 24 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_WRITE_GATHER ); REG64_FLD( PU_PBASLVCTL2_WR_GATHER_TIMEOUT , 25 , SH_UNT , SH_ACS_PIB , SH_FLD_WR_GATHER_TIMEOUT ); REG64_FLD( PU_PBASLVCTL2_WR_GATHER_TIMEOUT_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_WR_GATHER_TIMEOUT_LEN ); REG64_FLD( PU_PBASLVCTL2_WRITE_TSIZE , 28 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TSIZE ); REG64_FLD( PU_PBASLVCTL2_WRITE_TSIZE_LEN , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TSIZE_LEN ); REG64_FLD( PU_PBASLVCTL2_EXTADDR , 36 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR ); REG64_FLD( PU_PBASLVCTL2_EXTADDR_LEN , 14 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR_LEN ); REG64_FLD( PU_PBASLVCTL2_RESERVED_50 , 50 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_50 ); REG64_FLD( PU_PBASLVCTL3_ENABLE , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_ENABLE ); REG64_FLD( PU_PBASLVCTL3_MID_MATCH_VALUE , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_MATCH_VALUE ); REG64_FLD( PU_PBASLVCTL3_MID_MATCH_VALUE_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_MATCH_VALUE_LEN ); REG64_FLD( PU_PBASLVCTL3_RESERVED_4 , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_4 ); REG64_FLD( PU_PBASLVCTL3_MID_CARE_MASK , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_CARE_MASK ); REG64_FLD( PU_PBASLVCTL3_MID_CARE_MASK_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_MID_CARE_MASK_LEN ); REG64_FLD( PU_PBASLVCTL3_WRITE_TTYPE , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TTYPE ); REG64_FLD( PU_PBASLVCTL3_WRITE_TTYPE_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TTYPE_LEN ); REG64_FLD( PU_PBASLVCTL3_RESERVED_11_14 , 11 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_11_14 ); REG64_FLD( PU_PBASLVCTL3_RESERVED_11_14_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_11_14_LEN ); REG64_FLD( PU_PBASLVCTL3_READ_TTYPE , 15 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_TTYPE ); REG64_FLD( PU_PBASLVCTL3_READ_PREFETCH_CTL , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_PREFETCH_CTL ); REG64_FLD( PU_PBASLVCTL3_READ_PREFETCH_CTL_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_READ_PREFETCH_CTL_LEN ); REG64_FLD( PU_PBASLVCTL3_BUF_INVALIDATE_CTL , 18 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_INVALIDATE_CTL ); REG64_FLD( PU_PBASLVCTL3_BUF_ALLOC_W , 19 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_W ); REG64_FLD( PU_PBASLVCTL3_BUF_ALLOC_A , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_A ); REG64_FLD( PU_PBASLVCTL3_BUF_ALLOC_B , 21 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_B ); REG64_FLD( PU_PBASLVCTL3_BUF_ALLOC_C , 22 , SH_UNT , SH_ACS_PIB , SH_FLD_BUF_ALLOC_C ); REG64_FLD( PU_PBASLVCTL3_RESERVED_23 , 23 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_23 ); REG64_FLD( PU_PBASLVCTL3_DIS_WRITE_GATHER , 24 , SH_UNT , SH_ACS_PIB , SH_FLD_DIS_WRITE_GATHER ); REG64_FLD( PU_PBASLVCTL3_WR_GATHER_TIMEOUT , 25 , SH_UNT , SH_ACS_PIB , SH_FLD_WR_GATHER_TIMEOUT ); REG64_FLD( PU_PBASLVCTL3_WR_GATHER_TIMEOUT_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_WR_GATHER_TIMEOUT_LEN ); REG64_FLD( PU_PBASLVCTL3_WRITE_TSIZE , 28 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TSIZE ); REG64_FLD( PU_PBASLVCTL3_WRITE_TSIZE_LEN , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_WRITE_TSIZE_LEN ); REG64_FLD( PU_PBASLVCTL3_EXTADDR , 36 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR ); REG64_FLD( PU_PBASLVCTL3_EXTADDR_LEN , 14 , SH_UNT , SH_ACS_PIB , SH_FLD_EXTADDR_LEN ); REG64_FLD( PU_PBASLVCTL3_RESERVED_50 , 50 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_50 ); REG64_FLD( PU_PBASLVRST_SET , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_SET ); REG64_FLD( PU_PBASLVRST_SET_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_SET_LEN ); REG64_FLD( PU_PBASLVRST_IN_PROG , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_IN_PROG ); REG64_FLD( PU_PBASLVRST_IN_PROG_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_IN_PROG_LEN ); REG64_FLD( PU_PBASLVRST_BUSY_STATUS , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_BUSY_STATUS ); REG64_FLD( PU_PBASLVRST_BUSY_STATUS_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_BUSY_STATUS_LEN ); REG64_FLD( PU_PBASLVRST_SCOPE_ATTN_BAR , 12 , SH_UNT , SH_ACS_PIB , SH_FLD_SCOPE_ATTN_BAR ); REG64_FLD( PU_PBASLVRST_SCOPE_ATTN_BAR_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_SCOPE_ATTN_BAR_LEN ); REG64_FLD( PU_PBAWBUFVAL0_WR_SLVNUM , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WR_SLVNUM ); REG64_FLD( PU_PBAWBUFVAL0_WR_SLVNUM_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WR_SLVNUM_LEN ); REG64_FLD( PU_PBAWBUFVAL0_START_WR_ADDR , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_START_WR_ADDR ); REG64_FLD( PU_PBAWBUFVAL0_START_WR_ADDR_LEN , 30 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_START_WR_ADDR_LEN ); REG64_FLD( PU_PBAWBUFVAL0_WR_BUFFER_STATUS , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WR_BUFFER_STATUS ); REG64_FLD( PU_PBAWBUFVAL0_WR_BUFFER_STATUS_LEN , 5 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WR_BUFFER_STATUS_LEN ); REG64_FLD( PU_PBAWBUFVAL0_WR_BYTE_COUNT , 41 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WR_BYTE_COUNT ); REG64_FLD( PU_PBAWBUFVAL0_WR_BYTE_COUNT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WR_BYTE_COUNT_LEN ); REG64_FLD( PU_PBAWBUFVAL1_WR_SLVNUM , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WR_SLVNUM ); REG64_FLD( PU_PBAWBUFVAL1_WR_SLVNUM_LEN , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WR_SLVNUM_LEN ); REG64_FLD( PU_PBAWBUFVAL1_START_WR_ADDR , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_START_WR_ADDR ); REG64_FLD( PU_PBAWBUFVAL1_START_WR_ADDR_LEN , 30 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_START_WR_ADDR_LEN ); REG64_FLD( PU_PBAWBUFVAL1_WR_BUFFER_STATUS , 35 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WR_BUFFER_STATUS ); REG64_FLD( PU_PBAWBUFVAL1_WR_BUFFER_STATUS_LEN , 5 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WR_BUFFER_STATUS_LEN ); REG64_FLD( PU_PBAWBUFVAL1_WR_BYTE_COUNT , 41 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WR_BYTE_COUNT ); REG64_FLD( PU_PBAWBUFVAL1_WR_BYTE_COUNT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WR_BYTE_COUNT_LEN ); REG64_FLD( PU_PBAXCFG_PBAX_EN , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_PBAX_EN ); REG64_FLD( PU_PBAXCFG_RESERVATION_EN , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVATION_EN ); REG64_FLD( PU_PBAXCFG_SND_RESET , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_RESET ); REG64_FLD( PU_PBAXCFG_RCV_RESET , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_RESET ); REG64_FLD( PU_PBAXCFG_RCV_GROUPID , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_GROUPID ); REG64_FLD( PU_PBAXCFG_RCV_GROUPID_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_GROUPID_LEN ); REG64_FLD( PU_PBAXCFG_RCV_CHIPID , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_CHIPID ); REG64_FLD( PU_PBAXCFG_RCV_CHIPID_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_CHIPID_LEN ); REG64_FLD( PU_PBAXCFG_RESERVED_11 , 11 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_11 ); REG64_FLD( PU_PBAXCFG_RCV_BRDCST_GROUP , 12 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_BRDCST_GROUP ); REG64_FLD( PU_PBAXCFG_RCV_BRDCST_GROUP_LEN , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_BRDCST_GROUP_LEN ); REG64_FLD( PU_PBAXCFG_RCV_DATATO_DIV , 20 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_DATATO_DIV ); REG64_FLD( PU_PBAXCFG_RCV_DATATO_DIV_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_DATATO_DIV_LEN ); REG64_FLD( PU_PBAXCFG_RESERVED_25_26 , 25 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_25_26 ); REG64_FLD( PU_PBAXCFG_RESERVED_25_26_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_25_26_LEN ); REG64_FLD( PU_PBAXCFG_SND_RETRY_COUNT_OVERCOM , 27 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_RETRY_COUNT_OVERCOM ); REG64_FLD( PU_PBAXCFG_SND_RETRY_THRESH , 28 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_RETRY_THRESH ); REG64_FLD( PU_PBAXCFG_SND_RETRY_THRESH_LEN , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_RETRY_THRESH_LEN ); REG64_FLD( PU_PBAXCFG_SND_RSVTO_DIV , 36 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_RSVTO_DIV ); REG64_FLD( PU_PBAXCFG_SND_RSVTO_DIV_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_RSVTO_DIV_LEN ); REG64_FLD( PU_PBAXRCVSTAT_RCV_IN_PROGRESS , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_IN_PROGRESS ); REG64_FLD( PU_PBAXRCVSTAT_RCV_ERROR , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_ERROR ); REG64_FLD( PU_PBAXRCVSTAT_RCV_WRITE_IN_PROGRESS , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_WRITE_IN_PROGRESS ); REG64_FLD( PU_PBAXRCVSTAT_RCV_RESERVATION_SET , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_RESERVATION_SET ); REG64_FLD( PU_PBAXRCVSTAT_RCV_CAPTURE , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_CAPTURE ); REG64_FLD( PU_PBAXRCVSTAT_RCV_CAPTURE_LEN , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_RCV_CAPTURE_LEN ); REG64_FLD( PU_PBAXSHBR0_PUSH_START , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_START ); REG64_FLD( PU_PBAXSHBR0_PUSH_START_LEN , 29 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_START_LEN ); REG64_FLD( PU_PBAXSHBR1_PUSH_START , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_START ); REG64_FLD( PU_PBAXSHBR1_PUSH_START_LEN , 29 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_START_LEN ); REG64_FLD( PU_PBAXSHCS0_PUSH_FULL , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_FULL ); REG64_FLD( PU_PBAXSHCS0_PUSH_EMPTY , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_EMPTY ); REG64_FLD( PU_PBAXSHCS0_RESERVED_2_3 , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_2_3 ); REG64_FLD( PU_PBAXSHCS0_RESERVED_2_3_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_2_3_LEN ); REG64_FLD( PU_PBAXSHCS0_PUSH_INTR_ACTION_0_1 , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_INTR_ACTION_0_1 ); REG64_FLD( PU_PBAXSHCS0_PUSH_INTR_ACTION_0_1_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_INTR_ACTION_0_1_LEN ); REG64_FLD( PU_PBAXSHCS0_PUSH_LENGTH , 6 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_LENGTH ); REG64_FLD( PU_PBAXSHCS0_PUSH_LENGTH_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_LENGTH_LEN ); REG64_FLD( PU_PBAXSHCS0_PUSH_WRITE_PTR , 13 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_WRITE_PTR ); REG64_FLD( PU_PBAXSHCS0_PUSH_WRITE_PTR_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_WRITE_PTR_LEN ); REG64_FLD( PU_PBAXSHCS0_PUSH_READ_PTR , 21 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_READ_PTR ); REG64_FLD( PU_PBAXSHCS0_PUSH_READ_PTR_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_READ_PTR_LEN ); REG64_FLD( PU_PBAXSHCS0_PUSH_ENABLE , 31 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_ENABLE ); REG64_FLD( PU_PBAXSHCS1_PUSH_FULL , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_FULL ); REG64_FLD( PU_PBAXSHCS1_PUSH_EMPTY , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_EMPTY ); REG64_FLD( PU_PBAXSHCS1_RESERVED_2_3 , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_2_3 ); REG64_FLD( PU_PBAXSHCS1_RESERVED_2_3_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_2_3_LEN ); REG64_FLD( PU_PBAXSHCS1_PUSH_INTR_ACTION_0_1 , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_INTR_ACTION_0_1 ); REG64_FLD( PU_PBAXSHCS1_PUSH_INTR_ACTION_0_1_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_INTR_ACTION_0_1_LEN ); REG64_FLD( PU_PBAXSHCS1_PUSH_LENGTH , 6 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_LENGTH ); REG64_FLD( PU_PBAXSHCS1_PUSH_LENGTH_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_LENGTH_LEN ); REG64_FLD( PU_PBAXSHCS1_PUSH_WRITE_PTR , 13 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_WRITE_PTR ); REG64_FLD( PU_PBAXSHCS1_PUSH_WRITE_PTR_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_WRITE_PTR_LEN ); REG64_FLD( PU_PBAXSHCS1_PUSH_READ_PTR , 21 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_READ_PTR ); REG64_FLD( PU_PBAXSHCS1_PUSH_READ_PTR_LEN , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_READ_PTR_LEN ); REG64_FLD( PU_PBAXSHCS1_PUSH_ENABLE , 31 , SH_UNT , SH_ACS_PIB , SH_FLD_PUSH_ENABLE ); REG64_FLD( PU_PBAXSNDSTAT_SND_IN_PROGRESS , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_IN_PROGRESS ); REG64_FLD( PU_PBAXSNDSTAT_SND_ERROR , 1 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_ERROR ); REG64_FLD( PU_PBAXSNDSTAT_SND_PHASE_STATUS , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_PHASE_STATUS ); REG64_FLD( PU_PBAXSNDSTAT_SND_PHASE_STATUS_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_PHASE_STATUS_LEN ); REG64_FLD( PU_PBAXSNDSTAT_SND_CNT_STATUS , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_CNT_STATUS ); REG64_FLD( PU_PBAXSNDSTAT_SND_CNT_STATUS_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_CNT_STATUS_LEN ); REG64_FLD( PU_PBAXSNDSTAT_SND_RETRY_COUNT , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_RETRY_COUNT ); REG64_FLD( PU_PBAXSNDSTAT_SND_RETRY_COUNT_LEN , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_RETRY_COUNT_LEN ); REG64_FLD( PU_PBAXSNDTX_SND_SCOPE , 0 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_SCOPE ); REG64_FLD( PU_PBAXSNDTX_SND_SCOPE_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_SCOPE_LEN ); REG64_FLD( PU_PBAXSNDTX_SND_QID , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_QID ); REG64_FLD( PU_PBAXSNDTX_SND_TYPE , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_TYPE ); REG64_FLD( PU_PBAXSNDTX_SND_RESERVATION , 5 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_RESERVATION ); REG64_FLD( PU_PBAXSNDTX_RESERVED_6_7 , 6 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_6_7 ); REG64_FLD( PU_PBAXSNDTX_RESERVED_6_7_LEN , 2 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_6_7_LEN ); REG64_FLD( PU_PBAXSNDTX_SND_GROUPID , 8 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_GROUPID ); REG64_FLD( PU_PBAXSNDTX_SND_GROUPID_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_GROUPID_LEN ); REG64_FLD( PU_PBAXSNDTX_SND_CHIPID , 12 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_CHIPID ); REG64_FLD( PU_PBAXSNDTX_SND_CHIPID_LEN , 3 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_CHIPID_LEN ); REG64_FLD( PU_PBAXSNDTX_RESERVED_15 , 15 , SH_UNT , SH_ACS_PIB , SH_FLD_RESERVED_15 ); REG64_FLD( PU_PBAXSNDTX_VG_TARGE , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_VG_TARGE ); REG64_FLD( PU_PBAXSNDTX_VG_TARGE_LEN , 16 , SH_UNT , SH_ACS_PIB , SH_FLD_VG_TARGE_LEN ); REG64_FLD( PU_PBAXSNDTX_SND_STOP , 59 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_STOP ); REG64_FLD( PU_PBAXSNDTX_SND_CNT , 60 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_CNT ); REG64_FLD( PU_PBAXSNDTX_SND_CNT_LEN , 4 , SH_UNT , SH_ACS_PIB , SH_FLD_SND_CNT_LEN ); REG64_FLD( PEC_PBCQEINJ_REG_PE_ECC_INJECT_TYPE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_ECC_INJECT_TYPE ); REG64_FLD( PEC_PBCQEINJ_REG_PE_ECC_INJECT_TYPE_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_ECC_INJECT_TYPE_LEN ); REG64_FLD( PEC_PBCQEINJ_REG_PE_CQ_ECC_INJECT_ENABLE , 2 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_CQ_ECC_INJECT_ENABLE ); REG64_FLD( PEC_PBCQEINJ_REG_PE_CQ_SRAM_ARRAY , 3 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_CQ_SRAM_ARRAY ); REG64_FLD( PEC_PBCQEINJ_REG_PE_CQ_SRAM_ARRAY_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_CQ_SRAM_ARRAY_LEN ); REG64_FLD( PEC_PBCQEINJ_REG_PE_CQ_PAR_INJECT_ENABLE , 7 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_CQ_PAR_INJECT_ENABLE ); REG64_FLD( PEC_PBCQEINJ_REG_PE_CQ_REGISTER_ARRAY , 8 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_CQ_REGISTER_ARRAY ); REG64_FLD( PEC_PBCQEINJ_REG_PE_CQ_REGISTER_ARRAY_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_CQ_REGISTER_ARRAY_LEN ); REG64_FLD( PEC_PBCQEINJ_REG_PE_CONSTANT_EINJ , 11 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_CONSTANT_EINJ ); REG64_FLD( PEC_PBCQHWCFG_REG_HANG_POLL_SCALE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_HANG_POLL_SCALE ); REG64_FLD( PEC_PBCQHWCFG_REG_HANG_POLL_SCALE_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_HANG_POLL_SCALE_LEN ); REG64_FLD( PEC_PBCQHWCFG_REG_HANG_DATA_SCALE , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_HANG_DATA_SCALE ); REG64_FLD( PEC_PBCQHWCFG_REG_HANG_DATA_SCALE_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_HANG_DATA_SCALE_LEN ); REG64_FLD( PEC_PBCQHWCFG_REG_HANG_PE_SCALE , 8 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_HANG_PE_SCALE ); REG64_FLD( PEC_PBCQHWCFG_REG_HANG_PE_SCALE_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_HANG_PE_SCALE_LEN ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_BLOCK_CQPB_PB_INIT , 12 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_BLOCK_CQPB_PB_INIT ); REG64_FLD( PEC_PBCQHWCFG_REG_DISABLE_RCMD_CLKGATE , 13 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_DISABLE_RCMD_CLKGATE ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_HANG_SM_ON_ARE , 14 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_HANG_SM_ON_ARE ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_PCI_CLK_CHECK , 15 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_PCI_CLK_CHECK ); REG64_FLD( PEC_PBCQHWCFG_REG_LFSR_ARB_MODE , 16 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_LFSR_ARB_MODE ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_ENABLE_DMAR_IOPACING , 17 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_ENABLE_DMAR_IOPACING ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_ENABLE_DMAW_IOPACING , 18 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_ENABLE_DMAW_IOPACING ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_ADR_BAR_MODE , 19 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_ADR_BAR_MODE ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_STQ_ALLOCATION , 20 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_STQ_ALLOCATION ); REG64_FLD( PEC_PBCQHWCFG_REG_DISABLE_LPC_CMDS , 21 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_DISABLE_LPC_CMDS ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_OOO_MODE , 22 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_OOO_MODE ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_OSMB_EARLY_START , 23 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_OSMB_EARLY_START ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_OSMB_EARLY_START_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_OSMB_EARLY_START_LEN ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_QFIFO_HOLD_MODE , 27 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_QFIFO_HOLD_MODE ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_QFIFO_HOLD_MODE_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_QFIFO_HOLD_MODE_LEN ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_WR_STRICT_ORDER_MODE , 32 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_WR_STRICT_ORDER_MODE ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_CHANNEL_STREAMING_EN , 33 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_CHANNEL_STREAMING_EN ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_WR_CACHE_INJECT_MODE , 34 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_WR_CACHE_INJECT_MODE ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_WR_CACHE_INJECT_MODE_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_WR_CACHE_INJECT_MODE_LEN ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_ENABLE_NEW_FLOW_CACHE_INJECT , 36 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_ENABLE_NEW_FLOW_CACHE_INJECT ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_INJ_ON_RESEND , 37 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_INJ_ON_RESEND ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_FORCE_DISABLED_CTAG_TO_FOLLOW_FLOW , 38 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_FORCE_DISABLED_CTAG_TO_FOLLOW_FLOW ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_ENABLE_ENH_FLOW , 39 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_ENABLE_ENH_FLOW ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_WR_VG , 41 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_WR_VG ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_WR_SCOPE_GROUP , 42 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_WR_SCOPE_GROUP ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_INTWR_VG , 43 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_INTWR_VG ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_INTWR_SCOPE_GROUP , 44 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_INTWR_SCOPE_GROUP ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_INTWR_SCOPE_NODE , 45 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_INTWR_SCOPE_NODE ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_RD_WRITE_ORDERING , 48 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_RD_WRITE_ORDERING ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_RD_WRITE_ORDERING_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_RD_WRITE_ORDERING_LEN ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_RD_SCOPE_NODAL , 50 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_RD_SCOPE_NODAL ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_RD_SCOPE_GROUP , 51 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_RD_SCOPE_GROUP ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_RD_SCOPE_RNNN , 52 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_RD_SCOPE_RNNN ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_ENABLE_RD_SKIP_GROUP , 53 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_ENABLE_RD_SKIP_GROUP ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_RD_VG , 54 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_RD_VG ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_SCOPE_NODAL , 55 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_TCE_SCOPE_NODAL ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_SCOPE_GROUP , 56 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_TCE_SCOPE_GROUP ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_SCOPE_RNNN , 57 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_TCE_SCOPE_RNNN ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_ENABLE_TCE_SKIP_GROUP , 58 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_ENABLE_TCE_SKIP_GROUP ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_VG , 59 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_TCE_VG ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_TCE_ARBITRATION , 60 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_TCE_ARBITRATION ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_CQ_TCE_ARBITRATION , 61 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_CQ_TCE_ARBITRATION ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_DISABLE_MC_PREFETCH , 62 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_DISABLE_MC_PREFETCH ); REG64_FLD( PEC_PBCQHWCFG_REG_PE_IGNORE_SFSTAT , 63 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_IGNORE_SFSTAT ); REG64_FLD( PEC_STACK2_PBCQMODE_REG_PE_PEER2PEER_MODDE , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , SH_FLD_PE_PEER2PEER_MODDE ); REG64_FLD( PEC_STACK2_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE , 1 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , SH_FLD_PE_ENHANCED_PEER2PEER_MODDE ); REG64_FLD( PEC_STACK1_PBCQMODE_REG_PE_PEER2PEER_MODDE , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , SH_FLD_PE_PEER2PEER_MODDE ); REG64_FLD( PEC_STACK1_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE , 1 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , SH_FLD_PE_ENHANCED_PEER2PEER_MODDE ); REG64_FLD( PHB_PBCQMODE_REG_PE_PEER2PEER_MODDE , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_PE_PEER2PEER_MODDE ); REG64_FLD( PHB_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE , 1 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_PE_ENHANCED_PEER2PEER_MODDE ); REG64_FLD( PEC_STACK0_PBCQMODE_REG_PE_PEER2PEER_MODDE , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , SH_FLD_PE_PEER2PEER_MODDE ); REG64_FLD( PEC_STACK0_PBCQMODE_REG_PE_ENHANCED_PEER2PEER_MODDE , 1 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , SH_FLD_PE_ENHANCED_PEER2PEER_MODDE ); REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_VALID , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MB_VALID ); REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_WR_NOT_RD , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_MB_WR_NOT_RD ); REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_BAD_ADDR , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MB_BAD_ADDR ); REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_LINK_DOWN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_MB_LINK_DOWN ); REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_CORRUPT , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MB_CORRUPT ); REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_SENT , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MB_SENT ); REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_BAD_WRITE , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MB_BAD_WRITE ); REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_RESET , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_MB_RESET ); REG64_FLD( PU_PBE_MAILBOX_CTL_REG_ID , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_ID ); REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_LINK_ID , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_MB_LINK_ID ); REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_LINK_ID_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_MB_LINK_ID_LEN ); REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_SPARE , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_MB_SPARE ); REG64_FLD( PU_PBE_MAILBOX_CTL_REG_MB_SPARE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MB_SPARE_LEN ); REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_VALID , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_MB_VALID ); REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_WR_NOT_RD , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_MB_WR_NOT_RD ); REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_BAD_ADDR , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_MB_BAD_ADDR ); REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_LINK_DOWN , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_MB_LINK_DOWN ); REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_CORRUPT , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_MB_CORRUPT ); REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_SENT , 5 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_MB_SENT ); REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_BAD_WRITE , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_MB_BAD_WRITE ); REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_RESET , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_MB_RESET ); REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_ID , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_ID ); REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_LINK_ID , 9 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_MB_LINK_ID ); REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_LINK_ID_LEN , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_MB_LINK_ID_LEN ); REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_SPARE , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_MB_SPARE ); REG64_FLD( PU_IOE_PBO_MAILBOX_CTL_REG_MB_SPARE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_MB_SPARE_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_EN , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_RESET_MODE , 1 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_RESET_MODE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_COUNTER_MODE , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_COUNTER_MODE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_GLOBAL_PMISC_DIS , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_GLOBAL_PMISC_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_GLOBAL_PMISC_MODE , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_GLOBAL_PMISC_MODE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_EXTERNAL_FREEZE , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_EXTERNAL_FREEZE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_0_1_OP , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_0_1_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_0_1_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_0_1_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_2_3_OP , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_2_3_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_2_3_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_2_3_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_4_5_OP , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_4_5_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_4_5_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_4_5_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_6_7_OP , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_6_7_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_6_7_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_6_7_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_8_9_OP , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_8_9_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_8_9_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_8_9_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_10_11_OP , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_10_11_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_10_11_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_10_11_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_12_13_OP , 18 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_12_13_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_12_13_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_12_13_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_14_15_OP , 20 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_14_15_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_14_15_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_14_15_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_16_17_OP , 22 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_16_17_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_16_17_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_16_17_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_18_19_OP , 24 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_18_19_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_18_19_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_18_19_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_20_21_OP , 26 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_20_21_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_20_21_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_20_21_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_22_23_OP , 28 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_22_23_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_22_23_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_22_23_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_24_25_OP , 30 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_24_25_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_24_25_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_24_25_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_26_27_OP , 32 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_26_27_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_26_27_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_26_27_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_28_29_OP , 34 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_28_29_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_28_29_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_28_29_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_30_31_OP , 36 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_30_31_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_30_31_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_30_31_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU0 , 38 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CASCADE_PMU0 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU0_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CASCADE_PMU0_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU1 , 41 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CASCADE_PMU1 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU1_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CASCADE_PMU1_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU2 , 44 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CASCADE_PMU2 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU2_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CASCADE_PMU2_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU3 , 47 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CASCADE_PMU3 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_CASCADE_PMU3_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CASCADE_PMU3_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MASK , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC2_MCS0_MASK , 51 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_MC2_MCS0_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC2_MCS1_MASK , 52 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_MC2_MCS1_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC3_MCS0_MASK , 53 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_MC3_MCS0_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MC3_MCS1_MASK , 54 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_MC3_MCS1_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_MCD_MASK , 56 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_MCD_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_PE0_MASK , 57 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PE0_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_PE1_MASK , 58 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PE1_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_PE2_MASK , 59 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PE2_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPME_CFG_VAS_MASK , 60 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_VAS_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_EN , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_RESET_MODE , 1 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_RESET_MODE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_COUNTER_MODE , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_COUNTER_MODE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_GLOBAL_PMISC_DIS , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_GLOBAL_PMISC_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_GLOBAL_PMISC_MODE , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_GLOBAL_PMISC_MODE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_EXTERNAL_FREEZE , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_EXTERNAL_FREEZE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_0_1_OP , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_0_1_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_0_1_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_0_1_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_2_3_OP , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_2_3_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_2_3_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_2_3_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_4_5_OP , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_4_5_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_4_5_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_4_5_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_6_7_OP , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_6_7_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_6_7_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_6_7_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_8_9_OP , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_8_9_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_8_9_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_8_9_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_10_11_OP , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_10_11_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_10_11_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_10_11_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_12_13_OP , 18 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_12_13_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_12_13_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_12_13_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_14_15_OP , 20 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_14_15_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_14_15_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_14_15_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_16_17_OP , 22 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_16_17_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_16_17_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_16_17_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_18_19_OP , 24 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_18_19_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_18_19_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_18_19_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_20_21_OP , 26 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_20_21_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_20_21_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_20_21_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_22_23_OP , 28 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_22_23_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_22_23_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_22_23_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_24_25_OP , 30 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_24_25_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_24_25_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_24_25_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_26_27_OP , 32 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_26_27_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_26_27_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_26_27_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_28_29_OP , 34 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_28_29_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_28_29_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_28_29_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_30_31_OP , 36 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_30_31_OP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_30_31_OP_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_30_31_OP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU0 , 38 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CASCADE_PMU0 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU0_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CASCADE_PMU0_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU1 , 41 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CASCADE_PMU1 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU1_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CASCADE_PMU1_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU2 , 44 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CASCADE_PMU2 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU2_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CASCADE_PMU2_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU3 , 47 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CASCADE_PMU3 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_CASCADE_PMU3_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CASCADE_PMU3_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MASK , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MC0_MCS0_MASK , 51 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_MC0_MCS0_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MC0_MCS1_MASK , 52 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_MC0_MCS1_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MC1_MCS0_MASK , 53 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_MC1_MCS0_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_MC1_MCS1_MASK , 54 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_MC1_MCS1_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_INT_MASK , 56 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_INT_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_PE0_MASK , 57 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PE0_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_PE1_MASK , 58 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PE1_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_CNPMW_CFG_PE2_MASK , 59 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PE2_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TTYPE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE_LEN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TTYPE_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE_MASK , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TTYPE_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTYPE_MASK_LEN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TTYPE_MASK_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TSIZE , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TSIZE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TSIZE_LEN , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TSIZE_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TSIZE_MASK , 22 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TSIZE_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TSIZE_MASK_LEN , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TSIZE_MASK_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTAG , 30 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TTAG ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTAG_LEN , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TTAG_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTAG_MASK , 40 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TTAG_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_TTAG_MASK_LEN , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TTAG_MASK_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CRESP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP_LEN , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CRESP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP_MASK , 55 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CRESP_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP_MASK_LEN , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CRESP_MASK_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_CRESP_POLARITY , 60 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CRESP_POLARITY ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_SCOPE , 61 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SCOPE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPA_CFG_SCOPE_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SCOPE_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTYPE , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TTYPE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTYPE_LEN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TTYPE_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTYPE_MASK , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TTYPE_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTYPE_MASK_LEN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TTYPE_MASK_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TSIZE , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TSIZE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TSIZE_LEN , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TSIZE_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TSIZE_MASK , 22 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TSIZE_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TSIZE_MASK_LEN , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TSIZE_MASK_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTAG , 30 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TTAG ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTAG_LEN , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TTAG_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTAG_MASK , 40 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TTAG_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_TTAG_MASK_LEN , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TTAG_MASK_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CRESP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP_LEN , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CRESP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP_MASK , 55 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CRESP_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP_MASK_LEN , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CRESP_MASK_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_CRESP_POLARITY , 60 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CRESP_POLARITY ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_SCOPE , 61 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SCOPE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPB_CFG_SCOPE_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SCOPE_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_SCOPE_MASK , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_COMPA_SCOPE_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_SCOPE_MASK_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_COMPA_SCOPE_MASK_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_PRESP , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_COMPA_PRESP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_PRESP_LEN , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_COMPA_PRESP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_PRESP_MASK , 17 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_COMPA_PRESP_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPA_PRESP_MASK_LEN , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_COMPA_PRESP_MASK_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_SCOPE_MASK , 32 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_COMPB_SCOPE_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_SCOPE_MASK_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_COMPB_SCOPE_MASK_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_PRESP , 35 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_COMPB_PRESP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_PRESP_LEN , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_COMPB_PRESP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_PRESP_MASK , 49 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_COMPB_PRESP_MASK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_COMPX_CFG_COMPB_PRESP_MASK_LEN , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_COMPB_PRESP_MASK_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL0 , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PMU_SEL0 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL0_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PMU_SEL0_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL1 , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PMU_SEL1 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL1_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PMU_SEL1_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL2 , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PMU_SEL2 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL2_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PMU_SEL2_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL3 , 9 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PMU_SEL3 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL3_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PMU_SEL3_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL4 , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PMU_SEL4 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL4_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PMU_SEL4_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL5 , 15 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PMU_SEL5 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL5_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PMU_SEL5_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL6 , 18 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PMU_SEL6 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL6_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PMU_SEL6_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL7 , 21 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PMU_SEL7 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_SEL7_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PMU_SEL7_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPME_BITWISE_ENABLE , 24 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_BITWISE_ENABLE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPME_BITWISE_ENABLE_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_BITWISE_ENABLE_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPMW_BITWISE_ENABLE , 40 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_BITWISE_ENABLE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_CNPMW_BITWISE_ENABLE_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_BITWISE_ENABLE_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_EVENT_SEL_CFG_PMU_PORT , 56 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PMU_PORT ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_ACTION0_REG_ACTION0_LEN , 18 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_ACTION1_REG_ACTION1_LEN , 18 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_PROTOCOL_ERROR , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_PROTOCOL_ERROR ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_OVERFLOW_ERROR , 1 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_OVERFLOW_ERROR ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_HW_PARITY_ERROR , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_HW_PARITY_ERROR ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_3 , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_3 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_COHERENCY_ERROR , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_COHERENCY_ERROR ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_CRESP_ADDR_ERROR , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_CRESP_ADDR_ERROR ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_CRESP_ERROR , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_CRESP_ERROR ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_HANG_RECOVERY_LIMIT_ERROR , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_HANG_RECOVERY_LIMIT_ERROR ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_DATA_ROUTE_ERROR , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_DATA_ROUTE_ERROR ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_HANG_RECOVERY_GTE_LEVEL1 , 9 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_HANG_RECOVERY_GTE_LEVEL1 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_FORCE_MP_IPL , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_FORCE_MP_IPL ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_11 , 11 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_11 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_12 , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_12 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_13 , 13 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_13 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_14 , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_14 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SPARE_15 , 15 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_15 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SCOM_ERR , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_MASK_REG_SCOM_ERR_DUP , 17 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_PROTOCOL_ERROR , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_PROTOCOL_ERROR ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_OVERFLOW_ERROR , 1 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_OVERFLOW_ERROR ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_HW_PARITY_ERROR , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_HW_PARITY_ERROR ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_3 , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_3 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_COHERENCY_ERROR , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_COHERENCY_ERROR ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_CRESP_ADDR_ERROR , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_CRESP_ADDR_ERROR ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_CRESP_ERROR , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_CRESP_ERROR ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_HANG_RECOVERY_LIMIT_ERROR , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_HANG_RECOVERY_LIMIT_ERROR ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_DATA_ROUTE_ERROR , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_DATA_ROUTE_ERROR ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_HANG_RECOVERY_GTE_LEVEL1 , 9 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_HANG_RECOVERY_GTE_LEVEL1 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_FORCE_MP_IPL , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_FORCE_MP_IPL ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_11 , 11 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_11 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_12 , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_12 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_13 , 13 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_13 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_14 , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_14 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SPARE_15 , 15 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_15 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SCOM_ERR , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_FIR_REG_SCOM_ERR_DUP , 17 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL0 , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL0 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL0_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL0_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL1 , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL1 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL1_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL1_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL2 , 16 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL2 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL2_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL2_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL3 , 24 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL3 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL3_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL3_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL4 , 32 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL4 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL4_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL4_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL5 , 40 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL5 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL5_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL5_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL6 , 48 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL6 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL6_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL6_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL7 , 56 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL7 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP0_CFG_LVL7_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL7_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL0 , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL0 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL0_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL0_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL1 , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL1 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL1_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL1_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL2 , 16 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL2 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL2_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL2_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL3 , 24 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL3 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL3_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL3_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL4 , 32 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL4 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL4_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL4_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL5 , 40 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL5 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL5_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL5_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL6 , 48 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL6 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL6_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL6_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL7 , 56 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL7 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_GP_CMD_RATE_DP1_CFG_LVL7_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_LVL7_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X0_EN , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X1_EN , 1 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X1_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X2_EN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X2_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X3_EN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X3_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X4_EN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X4_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X5_EN , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X5_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X6_EN , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X6_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX0_ADDR_DIS , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX0_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX1_ADDR_DIS , 9 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX1_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX2_ADDR_DIS , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX2_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX3_ADDR_DIS , 11 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX3_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX4_ADDR_DIS , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX4_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX5_ADDR_DIS , 13 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX5_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_NX6_ADDR_DIS , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX6_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X0_CHIPID , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_CHIPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X0_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_CHIPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X1_CHIPID , 19 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X1_CHIPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X1_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X1_CHIPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X2_CHIPID , 22 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X2_CHIPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X2_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X2_CHIPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X3_CHIPID , 25 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X3_CHIPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X3_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X3_CHIPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X4_CHIPID , 28 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X4_CHIPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X4_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X4_CHIPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X5_CHIPID , 31 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X5_CHIPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X5_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X5_CHIPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X6_CHIPID , 34 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X6_CHIPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_LINK_X6_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X6_CHIPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_AGGREGATE , 37 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_AGGREGATE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_FP_DISABLED , 48 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_FP_DISABLED ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_INDIRECT_EN , 49 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_INDIRECT_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_GATHER_ENABLE , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_GATHER_ENABLE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_CMD_RATE , 56 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_CMD_RATE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_CURR_CFG_X_CMD_RATE_LEN , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_CMD_RATE_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X0_EN , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X1_EN , 1 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X1_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X2_EN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X2_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X3_EN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X3_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X4_EN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X4_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X5_EN , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X5_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X6_EN , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X6_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX0_ADDR_DIS , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX0_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX1_ADDR_DIS , 9 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX1_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX2_ADDR_DIS , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX2_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX3_ADDR_DIS , 11 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX3_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX4_ADDR_DIS , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX4_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX5_ADDR_DIS , 13 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX5_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_NX6_ADDR_DIS , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX6_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_CHIPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_CHIPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID , 19 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X1_CHIPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X1_CHIPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID , 22 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X2_CHIPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X2_CHIPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID , 25 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X3_CHIPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X3_CHIPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID , 28 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X4_CHIPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X4_CHIPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID , 31 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X5_CHIPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X5_CHIPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID , 34 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X6_CHIPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X6_CHIPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_AGGREGATE , 37 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_AGGREGATE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_FP_DISABLED , 48 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_FP_DISABLED ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_INDIRECT_EN , 49 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_INDIRECT_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_GATHER_ENABLE , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_GATHER_ENABLE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_CMD_RATE , 56 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_CMD_RATE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HPX_MODE_NEXT_CFG_X_CMD_RATE_LEN , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_CMD_RATE_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_MASTER_CHIP , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_MASTER_CHIP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_TM_MASTER , 1 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TM_MASTER ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_CHG_RATE_GP_MASTER , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CHG_RATE_GP_MASTER ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_CHG_RATE_SP_MASTER , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CHG_RATE_SP_MASTER ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A0_EN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A0_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A1_EN , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A1_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A2_EN , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A2_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A3_EN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A3_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_NA0_ADDR_DIS , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NA0_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_NA1_ADDR_DIS , 9 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NA1_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_NA2_ADDR_DIS , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NA2_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_NA3_ADDR_DIS , 11 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NA3_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A0_GROUPID , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A0_GROUPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A0_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A0_GROUPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A1_GROUPID , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A1_GROUPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A1_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A1_GROUPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A2_GROUPID , 20 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A2_GROUPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A2_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A2_GROUPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A3_GROUPID , 24 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A3_GROUPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_LINK_A3_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A3_GROUPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_AGGREGATE , 28 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_AGGREGATE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_HOP , 29 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_HOP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_SMP_OPTICS , 30 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SMP_OPTICS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_CAPI , 31 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CAPI ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT0 , 32 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT0 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT0_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT1 , 34 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT1 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT1_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT2 , 36 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT2 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT2_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT3 , 38 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT3 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_OPT3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT3_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID , 40 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_GATHER_ENABLE , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_GATHER_ENABLE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_PHYP_IS_GROUP , 52 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PHYP_IS_GROUP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_ADDR_BAR , 53 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_ADDR_BAR ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_PUMP , 54 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PUMP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_DCACHE_CAPP , 55 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_DCACHE_CAPP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_CMD_RATE , 56 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_CMD_RATE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_CURR_CFG_A_CMD_RATE_LEN , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_CMD_RATE_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_MASTER_CHIP , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_MASTER_CHIP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_TM_MASTER , 1 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_TM_MASTER ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_CHG_RATE_GP_MASTER , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CHG_RATE_GP_MASTER ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_CHG_RATE_SP_MASTER , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CHG_RATE_SP_MASTER ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A0_EN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A0_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A1_EN , 5 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A1_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A2_EN , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A2_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A3_EN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A3_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_NA0_ADDR_DIS , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NA0_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_NA1_ADDR_DIS , 9 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NA1_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_NA2_ADDR_DIS , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NA2_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_NA3_ADDR_DIS , 11 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NA3_ADDR_DIS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A0_GROUPID , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A0_GROUPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A0_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A0_GROUPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A1_GROUPID , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A1_GROUPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A1_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A1_GROUPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A2_GROUPID , 20 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A2_GROUPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A2_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A2_GROUPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A3_GROUPID , 24 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A3_GROUPID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_LINK_A3_GROUPID_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A3_GROUPID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_AGGREGATE , 28 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_AGGREGATE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_HOP , 29 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_HOP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_SMP_OPTICS , 30 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SMP_OPTICS ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_CAPI , 31 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CAPI ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT0 , 32 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT0 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT0_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT1 , 34 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT1 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT1_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT2 , 36 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT2 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT2_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT3 , 38 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT3 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_OPT3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT3_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID , 40 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_GATHER_ENABLE , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_GATHER_ENABLE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_PHYP_IS_GROUP , 52 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PHYP_IS_GROUP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_ADDR_BAR , 53 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_ADDR_BAR ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_PUMP , 54 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PUMP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_DCACHE_CAPP , 55 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_DCACHE_CAPP ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_CMD_RATE , 56 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_CMD_RATE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_HP_MODE_NEXT_CFG_A_CMD_RATE_LEN , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_CMD_RATE_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_DD1_MODE , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_APM_DD1_MODE ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_SEL , 1 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_APM_SEL ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_SEL_LEN , 2 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_APM_SEL_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_PMU_FREEZE_MODE , 4 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_PMU_FREEZE_MODE ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_HI_COMP , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_APM_LM_HI_COMP ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_HI_COMP_LEN , 4 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_APM_LM_HI_COMP_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_LO_COMP , 12 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_APM_LM_LO_COMP ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_LMPM_COUNTER_CFG_APM_LM_LO_COMP_LEN , 4 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_APM_LM_LO_COMP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_CHIP_IS_SYSTEM , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CHIP_IS_SYSTEM ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_HNG_CHK_DISABLE , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_HNG_CHK_DISABLE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_DBG_CLR_MAX_HANG_STAGE , 9 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_DBG_CLR_MAX_HANG_STAGE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SW_AB_WAIT , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SW_AB_WAIT ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SW_AB_WAIT_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SW_AB_WAIT_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SP_HW_MARK , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SP_HW_MARK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SP_HW_MARK_LEN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SP_HW_MARK_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_GP_HW_MARK , 23 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_GP_HW_MARK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_GP_HW_MARK_LEN , 7 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_GP_HW_MARK_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_LCL_HW_MARK , 30 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LCL_HW_MARK ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_LCL_HW_MARK_LEN , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_LCL_HW_MARK_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_REQ_GATHER_ENABLE , 57 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_REQ_GATHER_ENABLE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SWITCH_CD_PULSE , 58 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SWITCH_CD_PULSE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_SWITCH_OPTION_AB , 59 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SWITCH_OPTION_AB ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_MODE_CFG_RESET_ERROR_CAPTURE , 63 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_RESET_ERROR_CAPTURE ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_ENABLE , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_APM_ENABLE ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_SAMPLE_SEL , 1 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_APM_SAMPLE_SEL ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_SAMPLE_SEL_LEN , 2 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_APM_SAMPLE_SEL_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_PMUCNT_EN , 3 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_PMUCNT_EN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_PMUCNT_SEL , 4 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_PMUCNT_SEL ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_PMUCNT_SEL_LEN , 2 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_PMUCNT_SEL_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_HI_COMP , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_APM_NM_HI_COMP ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_HI_COMP_LEN , 4 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_APM_NM_HI_COMP_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_LO_COMP , 12 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_APM_NM_LO_COMP ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_NMPM_COUNTER_CFG_APM_NM_LO_COMP_LEN , 4 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_APM_NM_LO_COMP_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C0 , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP0_C0 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP0_C0_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C1 , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP0_C1 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP0_C1_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C2 , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP0_C2 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP0_C2_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C3 , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP0_C3 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP0_C3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP0_C3_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C0 , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP1_C0 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP1_C0_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C1 , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP1_C1 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP1_C1_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C2 , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP1_C2 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP1_C2_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C3 , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP1_C3 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP1_C3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP1_C3_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C0 , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP2_C0 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP2_C0_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C1 , 18 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP2_C1 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP2_C1_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C2 , 20 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP2_C2 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP2_C2_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C3 , 22 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP2_C3 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP2_C3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP2_C3_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C0 , 24 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP3_C0 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP3_C0_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C1 , 26 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP3_C1 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP3_C1_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C2 , 28 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP3_C2 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP3_C2_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C3 , 30 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP3_C3 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPME_GRP3_C3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPME_GRP3_C3_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C0 , 33 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP0_C0 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C1 , 34 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP0_C1 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP0_C1_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C2 , 36 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP0_C2 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP0_C2_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C3 , 38 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP0_C3 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP0_C3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP0_C3_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C0 , 40 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP1_C0 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP1_C0_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C1 , 42 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP1_C1 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP1_C1_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C2 , 44 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP1_C2 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP1_C2_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C3 , 46 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP1_C3 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP1_C3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP1_C3_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C0 , 48 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP2_C0 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP2_C0_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C1 , 50 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP2_C1 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP2_C1_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C2 , 52 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP2_C2 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP2_C2_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C3 , 54 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP2_C3 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP2_C3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP2_C3_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C0 , 56 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP3_C0 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP3_C0_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C1 , 58 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP3_C1 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP3_C1_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C2 , 60 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP3_C2 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP3_C2_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C3 , 62 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP3_C3 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_PMU_PRESCALER_CFG_CNPMW_GRP3_C3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_CNPMW_GRP3_C3_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL0 , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL0 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL0_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL0_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL1 , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL1 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL1_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL1_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL2 , 16 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL2 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL2_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL2_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL3 , 24 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL3 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL3_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL3_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL4 , 32 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL4 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL4_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL4_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL5 , 40 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL5 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL5_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL5_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL6 , 48 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL6 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL6_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL6_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL7 , 56 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL7 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP0_CFG_RNS_LVL7_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL7_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL0 , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL0 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL0_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL0_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL1 , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL1 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL1_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL1_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL2 , 16 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL2 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL2_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL2_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL3 , 24 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL3 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL3_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL3_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL4 , 32 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL4 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL4_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL4_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL5 , 40 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL5 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL5_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL5_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL6 , 48 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL6 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL6_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL6_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL7 , 56 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL7 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_RGP_CMD_RATE_DP1_CFG_RNS_LVL7_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_RNS_LVL7_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SLOW , 1 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SLOW ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SHIFT_COUNT , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SHIFT_COUNT ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SHIFT_COUNT_LEN , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SHIFT_COUNT_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SELECT , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELECT ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SELECT_LEN , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELECT_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SHIFT_DATA , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SHIFT_DATA ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_SCONFIG_LOAD_CFG_SHIFT_DATA_LEN , 52 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SHIFT_DATA_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL0 , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL0 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL0_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL0_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL1 , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL1 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL1_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL1_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL2 , 16 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL2 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL2_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL2_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL3 , 24 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL3 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL3_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL3_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL4 , 32 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL4 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL4_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL4_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL5 , 40 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL5 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL5_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL5_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL6 , 48 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL6 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL6_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL6_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL7 , 56 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL7 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP0_CFG_VG_LVL7_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL7_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL0 , 0 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL0 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL0_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL0_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL1 , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL1 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL1_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL1_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL2 , 16 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL2 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL2_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL2_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL3 , 24 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL3 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL3_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL3_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL4 , 32 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL4 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL4_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL4_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL5 , 40 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL5 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL5_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL5_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL6 , 48 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL6 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL6_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL6_LEN ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL7 , 56 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL7 ); REG64_FLD( PU_PB_CENT_SM1_PB_CENT_SP_CMD_RATE_DP1_CFG_VG_LVL7_LEN , 8 , SH_UNT_PU_PB_CENT_SM1, SH_ACS_SCOM , SH_FLD_CFG_VG_LVL7_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN0 , 0 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELSN0 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELSN0_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN1 , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELSN1 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELSN1_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN2 , 4 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELSN2 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELSN2_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN3 , 6 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELSN3 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELSN3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELSN3_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR0 , 8 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELCR0 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR0_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELCR0_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR1 , 10 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELCR1 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR1_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELCR1_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR2 , 12 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELCR2 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR2_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELCR2_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR3 , 14 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELCR3 ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELCR3_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELCR3_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIEN_DBG_0_SEL , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PBIEN_DBG_0_SEL ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIEN_DBG_0_SEL_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PBIEN_DBG_0_SEL_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIEN_DBG_1_SEL , 18 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PBIEN_DBG_1_SEL ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIEN_DBG_1_SEL_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PBIEN_DBG_1_SEL_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIES_DBG_0_SEL , 20 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PBIES_DBG_0_SEL ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIES_DBG_0_SEL_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PBIES_DBG_0_SEL_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIES_DBG_1_SEL , 22 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PBIES_DBG_1_SEL ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIES_DBG_1_SEL_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PBIES_DBG_1_SEL_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_DBG_0_SEL , 24 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PBIOT_DBG_0_SEL ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_DBG_0_SEL_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PBIOT_DBG_0_SEL_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_DBG_1_SEL , 26 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PBIOT_DBG_1_SEL ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_DBG_1_SEL_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PBIOT_DBG_1_SEL_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PBIOT_SEL , 28 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PBIOT_SEL ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELRT , 29 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELRT ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_SELRT_LEN , 3 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELRT_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_EN , 32 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PERFTRACE_EN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_TRIG , 33 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PERFTRACE_TRIG ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_COUNTER_SEL , 34 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PERFTRACE_COUNTER_SEL ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_COUNTER_SEL_LEN , 2 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PERFTRACE_COUNTER_SEL_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_COUNTER_MATCH , 36 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PERFTRACE_COUNTER_MATCH ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_COUNTER_MATCH_LEN , 16 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PERFTRACE_COUNTER_MATCH_LEN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_ENABLE_PERFTRACE_PRESCALE , 52 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_ENABLE_PERFTRACE_PRESCALE ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_ENABLE_PERFTRACE_FIXED_WIN , 53 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_ENABLE_PERFTRACE_FIXED_WIN ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_GRP1_SEL , 54 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PERFTRACE_GRP1_SEL ); REG64_FLD( PU_PB_CENT_SM0_PB_CENT_TRACE_CFG_PERFTRACE_GRP2_SEL , 55 , SH_UNT_PU_PB_CENT_SM0, SH_ACS_SCOM , SH_FLD_CFG_PERFTRACE_GRP2_SEL ); REG64_FLD( PU_PB_EAST_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( PU_PB_EAST_FIR_ACTION0_REG_ACTION0_LEN , 34 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); REG64_FLD( PU_PB_EAST_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); REG64_FLD( PU_PB_EAST_FIR_ACTION1_REG_ACTION1_LEN , 34 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ04_PBH_HW1_ERROR , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBIEQ04_PBH_HW1_ERROR ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ04_PBH_HW2_ERROR , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBIEQ04_PBH_HW2_ERROR ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ04_PBH_PROTOCOL_ERROR , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBIEQ04_PBH_PROTOCOL_ERROR ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ04_PBH_OVERFLOW_ERROR , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBIEQ04_PBH_OVERFLOW_ERROR ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ05_PBH_HW1_ERROR , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBIEQ05_PBH_HW1_ERROR ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ05_PBH_HW2_ERROR , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBIEQ05_PBH_HW2_ERROR ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ05_PBH_PROTOCOL_ERROR , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBIEQ05_PBH_PROTOCOL_ERROR ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PBIEQ05_PBH_OVERFLOW_ERROR , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBIEQ05_PBH_OVERFLOW_ERROR ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_8 , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_8 ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_9 , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_9 ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_10 , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_10 ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_11 , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_11 ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_12 , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_12 ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_13 , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_13 ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_14 , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_14 ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_15 , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_15 ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_OVERFLOW_CHECKSTOP , 16 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OVERFLOW_CHECKSTOP ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_PROTOCOL_CHECKSTOP , 17 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PROTOCOL_CHECKSTOP ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_ROUTE_CHECKSTOP , 18 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ROUTE_CHECKSTOP ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_19 , 19 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_19 ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_20 , 20 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_20 ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_21 , 21 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_21 ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_22 , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_22 ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_23 , 23 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_23 ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_24 , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_24 ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_25 , 25 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_25 ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_26 , 26 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_26 ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_27 , 27 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_27 ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_28 , 28 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_28 ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_29 , 29 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_29 ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_30 , 30 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_30 ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SPARE_31 , 31 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_31 ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SCOM_ERR , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); REG64_FLD( PU_PB_EAST_FIR_MASK_REG_SCOM_ERR_DUP , 33 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ04_PBH_HW1_ERROR , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBIEQ04_PBH_HW1_ERROR ); REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ04_PBH_HW2_ERROR , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBIEQ04_PBH_HW2_ERROR ); REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ04_PBH_PROTOCOL_ERROR , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBIEQ04_PBH_PROTOCOL_ERROR ); REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ04_PBH_OVERFLOW_ERROR , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBIEQ04_PBH_OVERFLOW_ERROR ); REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ05_PBH_HW1_ERROR , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBIEQ05_PBH_HW1_ERROR ); REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ05_PBH_HW2_ERROR , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBIEQ05_PBH_HW2_ERROR ); REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ05_PBH_PROTOCOL_ERROR , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBIEQ05_PBH_PROTOCOL_ERROR ); REG64_FLD( PU_PB_EAST_FIR_REG_PBIEQ05_PBH_OVERFLOW_ERROR , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PBIEQ05_PBH_OVERFLOW_ERROR ); REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_8 , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_8 ); REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_9 , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_9 ); REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_10 , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_10 ); REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_11 , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_11 ); REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_12 , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_12 ); REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_13 , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_13 ); REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_14 , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_14 ); REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_15 , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_15 ); REG64_FLD( PU_PB_EAST_FIR_REG_OVERFLOW_CHECKSTOP , 16 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OVERFLOW_CHECKSTOP ); REG64_FLD( PU_PB_EAST_FIR_REG_PROTOCOL_CHECKSTOP , 17 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PROTOCOL_CHECKSTOP ); REG64_FLD( PU_PB_EAST_FIR_REG_ROUTE_CHECKSTOP , 18 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ROUTE_CHECKSTOP ); REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_19 , 19 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_19 ); REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_20 , 20 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_20 ); REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_21 , 21 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_21 ); REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_22 , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_22 ); REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_23 , 23 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_23 ); REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_24 , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_24 ); REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_25 , 25 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_25 ); REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_26 , 26 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_26 ); REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_27 , 27 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_27 ); REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_28 , 28 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_28 ); REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_29 , 29 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_29 ); REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_30 , 30 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_30 ); REG64_FLD( PU_PB_EAST_FIR_REG_SPARE_31 , 31 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_31 ); REG64_FLD( PU_PB_EAST_FIR_REG_SCOM_ERR , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); REG64_FLD( PU_PB_EAST_FIR_REG_SCOM_ERR_DUP , 33 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X0_EN , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_EN ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X1_EN , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X1_EN ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X2_EN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X2_EN ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X3_EN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X3_EN ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X4_EN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X4_EN ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X5_EN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X5_EN ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X6_EN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X6_EN ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX0_ADDR_DIS , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NX0_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX1_ADDR_DIS , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NX1_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX2_ADDR_DIS , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NX2_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX3_ADDR_DIS , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NX3_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX4_ADDR_DIS , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NX4_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX5_ADDR_DIS , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NX5_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_NX6_ADDR_DIS , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NX6_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X0_CHIPID , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_CHIPID ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X0_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_CHIPID_LEN ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X1_CHIPID , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X1_CHIPID ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X1_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X1_CHIPID_LEN ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X2_CHIPID , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X2_CHIPID ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X2_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X2_CHIPID_LEN ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X3_CHIPID , 25 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X3_CHIPID ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X3_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X3_CHIPID_LEN ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X4_CHIPID , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X4_CHIPID ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X4_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X4_CHIPID_LEN ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X5_CHIPID , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X5_CHIPID ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X5_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X5_CHIPID_LEN ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X6_CHIPID , 34 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X6_CHIPID ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_LINK_X6_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X6_CHIPID_LEN ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_X_AGGREGATE , 37 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_X_AGGREGATE ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_X_FP_DISABLED , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_X_FP_DISABLED ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_X_INDIRECT_EN , 49 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_X_INDIRECT_EN ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_X_GATHER_ENABLE , 50 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_X_GATHER_ENABLE ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_X_CMD_RATE , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_X_CMD_RATE ); REG64_FLD( PU_PB_EAST_HPX_MODE_CURR_CFG_X_CMD_RATE_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_X_CMD_RATE_LEN ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X0_EN , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_EN ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X1_EN , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X1_EN ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X2_EN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X2_EN ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X3_EN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X3_EN ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X4_EN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X4_EN ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X5_EN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X5_EN ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X6_EN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X6_EN ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX0_ADDR_DIS , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NX0_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX1_ADDR_DIS , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NX1_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX2_ADDR_DIS , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NX2_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX3_ADDR_DIS , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NX3_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX4_ADDR_DIS , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NX4_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX5_ADDR_DIS , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NX5_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_NX6_ADDR_DIS , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NX6_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_CHIPID ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_CHIPID_LEN ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X1_CHIPID ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X1_CHIPID_LEN ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X2_CHIPID ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X2_CHIPID_LEN ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID , 25 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X3_CHIPID ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X3_CHIPID_LEN ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X4_CHIPID ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X4_CHIPID_LEN ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X5_CHIPID ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X5_CHIPID_LEN ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID , 34 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X6_CHIPID ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_X6_CHIPID_LEN ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_X_AGGREGATE , 37 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_X_AGGREGATE ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_X_FP_DISABLED , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_X_FP_DISABLED ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_X_INDIRECT_EN , 49 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_X_INDIRECT_EN ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_X_GATHER_ENABLE , 50 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_X_GATHER_ENABLE ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_X_CMD_RATE , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_X_CMD_RATE ); REG64_FLD( PU_PB_EAST_HPX_MODE_NEXT_CFG_X_CMD_RATE_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_X_CMD_RATE_LEN ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_MASTER_CHIP , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_MASTER_CHIP ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_TM_MASTER , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_TM_MASTER ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_CHG_RATE_GP_MASTER , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_CHG_RATE_GP_MASTER ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_CHG_RATE_SP_MASTER , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_CHG_RATE_SP_MASTER ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A0_EN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A0_EN ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A1_EN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A1_EN ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A2_EN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A2_EN ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A3_EN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A3_EN ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_NA0_ADDR_DIS , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NA0_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_NA1_ADDR_DIS , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NA1_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_NA2_ADDR_DIS , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NA2_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_NA3_ADDR_DIS , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NA3_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A0_GROUPID , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A0_GROUPID ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A0_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A0_GROUPID_LEN ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A1_GROUPID , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A1_GROUPID ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A1_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A1_GROUPID_LEN ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A2_GROUPID , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A2_GROUPID ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A2_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A2_GROUPID_LEN ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A3_GROUPID , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A3_GROUPID ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_LINK_A3_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A3_GROUPID_LEN ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_A_AGGREGATE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_A_AGGREGATE ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_HOP , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_HOP ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_SMP_OPTICS , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_SMP_OPTICS ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_CAPI , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_CAPI ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_OPT0 ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT0_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_OPT0_LEN ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT1 , 34 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_OPT1 ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT1_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_OPT1_LEN ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT2 , 36 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_OPT2 ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT2_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_OPT2_LEN ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT3 , 38 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_OPT3 ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_OPT3_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_OPT3_LEN ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_A_GATHER_ENABLE , 50 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_A_GATHER_ENABLE ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_PHYP_IS_GROUP , 52 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_PHYP_IS_GROUP ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_ADDR_BAR , 53 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_ADDR_BAR ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_PUMP , 54 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_PUMP ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_DCACHE_CAPP , 55 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_DCACHE_CAPP ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_A_CMD_RATE , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_A_CMD_RATE ); REG64_FLD( PU_PB_EAST_HP_MODE_CURR_CFG_A_CMD_RATE_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_A_CMD_RATE_LEN ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_MASTER_CHIP , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_MASTER_CHIP ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_TM_MASTER , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_TM_MASTER ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_CHG_RATE_GP_MASTER , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_CHG_RATE_GP_MASTER ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_CHG_RATE_SP_MASTER , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_CHG_RATE_SP_MASTER ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A0_EN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A0_EN ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A1_EN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A1_EN ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A2_EN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A2_EN ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A3_EN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A3_EN ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_NA0_ADDR_DIS , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NA0_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_NA1_ADDR_DIS , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NA1_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_NA2_ADDR_DIS , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NA2_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_NA3_ADDR_DIS , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_NA3_ADDR_DIS ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A0_GROUPID , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A0_GROUPID ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A0_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A0_GROUPID_LEN ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A1_GROUPID , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A1_GROUPID ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A1_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A1_GROUPID_LEN ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A2_GROUPID , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A2_GROUPID ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A2_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A2_GROUPID_LEN ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A3_GROUPID , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A3_GROUPID ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_LINK_A3_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LINK_A3_GROUPID_LEN ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_A_AGGREGATE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_A_AGGREGATE ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_HOP , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_HOP ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_SMP_OPTICS , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_SMP_OPTICS ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_CAPI , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_CAPI ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_OPT0 ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT0_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_OPT0_LEN ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT1 , 34 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_OPT1 ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT1_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_OPT1_LEN ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT2 , 36 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_OPT2 ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT2_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_OPT2_LEN ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT3 , 38 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_OPT3 ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_OPT3_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_OPT3_LEN ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_A_GATHER_ENABLE , 50 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_A_GATHER_ENABLE ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_PHYP_IS_GROUP , 52 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_PHYP_IS_GROUP ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_ADDR_BAR , 53 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_ADDR_BAR ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_PUMP , 54 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_PUMP ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_DCACHE_CAPP , 55 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_DCACHE_CAPP ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_A_CMD_RATE , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_A_CMD_RATE ); REG64_FLD( PU_PB_EAST_HP_MODE_NEXT_CFG_A_CMD_RATE_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_A_CMD_RATE_LEN ); REG64_FLD( PU_PB_EAST_MODE_CFG_CHIP_IS_SYSTEM , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_CHIP_IS_SYSTEM ); REG64_FLD( PU_PB_EAST_MODE_CFG_HNG_CHK_DISABLE , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_HNG_CHK_DISABLE ); REG64_FLD( PU_PB_EAST_MODE_DBG_CLR_MAX_HANG_STAGE , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_DBG_CLR_MAX_HANG_STAGE ); REG64_FLD( PU_PB_EAST_MODE_CFG_SW_AB_WAIT , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_SW_AB_WAIT ); REG64_FLD( PU_PB_EAST_MODE_CFG_SW_AB_WAIT_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_SW_AB_WAIT_LEN ); REG64_FLD( PU_PB_EAST_MODE_CFG_SP_HW_MARK , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_SP_HW_MARK ); REG64_FLD( PU_PB_EAST_MODE_CFG_SP_HW_MARK_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_SP_HW_MARK_LEN ); REG64_FLD( PU_PB_EAST_MODE_CFG_GP_HW_MARK , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_GP_HW_MARK ); REG64_FLD( PU_PB_EAST_MODE_CFG_GP_HW_MARK_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_GP_HW_MARK_LEN ); REG64_FLD( PU_PB_EAST_MODE_CFG_LCL_HW_MARK , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LCL_HW_MARK ); REG64_FLD( PU_PB_EAST_MODE_CFG_LCL_HW_MARK_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_LCL_HW_MARK_LEN ); REG64_FLD( PU_PB_EAST_MODE_CFG_REQ_GATHER_ENABLE , 57 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_REQ_GATHER_ENABLE ); REG64_FLD( PU_PB_EAST_MODE_CFG_SWITCH_CD_PULSE , 58 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_SWITCH_CD_PULSE ); REG64_FLD( PU_PB_EAST_MODE_CFG_SWITCH_OPTION_AB , 59 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_SWITCH_OPTION_AB ); REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG ); REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SLOW , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_SLOW ); REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_COUNT , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_SHIFT_COUNT ); REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_COUNT_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_SHIFT_COUNT_LEN ); REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SELECT , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_SELECT ); REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SELECT_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_SELECT_LEN ); REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_DATA , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_SHIFT_DATA ); REG64_FLD( PU_PB_EAST_SCONFIG_LOAD_CFG_SHIFT_DATA_LEN , 52 , SH_UNT , SH_ACS_SCOM , SH_FLD_CFG_SHIFT_DATA_LEN ); REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK0_DOB_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK0_DOB_LIMIT_LEN ); REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_VC0_LIMIT , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK0_DOB_VC0_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_VC0_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK0_DOB_VC0_LIMIT_LEN ); REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_VC1_LIMIT , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK0_DOB_VC1_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK0_DOB_VC1_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK0_DOB_VC1_LIMIT_LEN ); REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK01_DIB_VC_LIMIT , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK01_DIB_VC_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK01_DIB_VC_LIMIT_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK01_DIB_VC_LIMIT_LEN ); REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_LIMIT , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK1_DOB_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK1_DOB_LIMIT_LEN ); REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_VC0_LIMIT , 41 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK1_DOB_VC0_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_VC0_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK1_DOB_VC0_LIMIT_LEN ); REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_VC1_LIMIT , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK1_DOB_VC1_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_01_CFG_REG_LINK1_DOB_VC1_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK1_DOB_VC1_LIMIT_LEN ); REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_LIMIT , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK2_DOB_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK2_DOB_LIMIT_LEN ); REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_VC0_LIMIT , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK2_DOB_VC0_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_VC0_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK2_DOB_VC0_LIMIT_LEN ); REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_VC1_LIMIT , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK2_DOB_VC1_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK2_DOB_VC1_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK2_DOB_VC1_LIMIT_LEN ); REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK23_DIB_VC_LIMIT , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK23_DIB_VC_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK23_DIB_VC_LIMIT_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK23_DIB_VC_LIMIT_LEN ); REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_LIMIT , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK3_DOB_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK3_DOB_LIMIT_LEN ); REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_VC0_LIMIT , 41 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK3_DOB_VC0_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_VC0_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK3_DOB_VC0_LIMIT_LEN ); REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_VC1_LIMIT , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK3_DOB_VC1_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_23_CFG_REG_LINK3_DOB_VC1_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK3_DOB_VC1_LIMIT_LEN ); REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_LIMIT , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK4_DOB_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK4_DOB_LIMIT_LEN ); REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_VC0_LIMIT , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK4_DOB_VC0_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_VC0_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK4_DOB_VC0_LIMIT_LEN ); REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_VC1_LIMIT , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK4_DOB_VC1_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK4_DOB_VC1_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK4_DOB_VC1_LIMIT_LEN ); REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK45_DIB_VC_LIMIT , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK45_DIB_VC_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK45_DIB_VC_LIMIT_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK45_DIB_VC_LIMIT_LEN ); REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_LIMIT , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK5_DOB_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK5_DOB_LIMIT_LEN ); REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC0_LIMIT , 41 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK5_DOB_VC0_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC0_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK5_DOB_VC0_LIMIT_LEN ); REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK5_DOB_VC1_LIMIT ); REG64_FLD( PU_PB_ELINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK5_DOB_VC1_LIMIT_LEN ); REG64_FLD( PU_PB_ELINK_PMU0_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); REG64_FLD( PU_PB_ELINK_PMU0_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); REG64_FLD( PU_PB_ELINK_PMU0_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); REG64_FLD( PU_PB_ELINK_PMU0_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); REG64_FLD( PU_PB_ELINK_PMU0_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); REG64_FLD( PU_PB_ELINK_PMU0_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); REG64_FLD( PU_PB_ELINK_PMU0_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); REG64_FLD( PU_PB_ELINK_PMU0_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); REG64_FLD( PU_PB_ELINK_PMU1_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); REG64_FLD( PU_PB_ELINK_PMU1_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); REG64_FLD( PU_PB_ELINK_PMU1_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); REG64_FLD( PU_PB_ELINK_PMU1_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); REG64_FLD( PU_PB_ELINK_PMU1_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); REG64_FLD( PU_PB_ELINK_PMU1_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); REG64_FLD( PU_PB_ELINK_PMU1_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); REG64_FLD( PU_PB_ELINK_PMU1_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); REG64_FLD( PU_PB_ELINK_PMU2_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); REG64_FLD( PU_PB_ELINK_PMU2_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); REG64_FLD( PU_PB_ELINK_PMU2_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); REG64_FLD( PU_PB_ELINK_PMU2_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); REG64_FLD( PU_PB_ELINK_PMU2_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); REG64_FLD( PU_PB_ELINK_PMU2_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); REG64_FLD( PU_PB_ELINK_PMU2_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); REG64_FLD( PU_PB_ELINK_PMU2_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); REG64_FLD( PU_PB_ELINK_PMU3_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); REG64_FLD( PU_PB_ELINK_PMU3_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); REG64_FLD( PU_PB_ELINK_PMU3_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); REG64_FLD( PU_PB_ELINK_PMU3_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); REG64_FLD( PU_PB_ELINK_PMU3_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); REG64_FLD( PU_PB_ELINK_PMU3_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); REG64_FLD( PU_PB_ELINK_PMU3_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); REG64_FLD( PU_PB_ELINK_PMU3_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); REG64_FLD( PU_PB_ELINK_PMU4_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); REG64_FLD( PU_PB_ELINK_PMU4_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); REG64_FLD( PU_PB_ELINK_PMU4_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); REG64_FLD( PU_PB_ELINK_PMU4_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); REG64_FLD( PU_PB_ELINK_PMU4_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); REG64_FLD( PU_PB_ELINK_PMU4_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); REG64_FLD( PU_PB_ELINK_PMU4_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); REG64_FLD( PU_PB_ELINK_PMU4_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); REG64_FLD( PU_PB_ELINK_PMU5_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); REG64_FLD( PU_PB_ELINK_PMU5_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); REG64_FLD( PU_PB_ELINK_PMU5_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); REG64_FLD( PU_PB_ELINK_PMU5_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); REG64_FLD( PU_PB_ELINK_PMU5_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); REG64_FLD( PU_PB_ELINK_PMU5_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); REG64_FLD( PU_PB_ELINK_PMU5_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); REG64_FLD( PU_PB_ELINK_PMU5_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); REG64_FLD( PU_PB_ELINK_PMU6_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); REG64_FLD( PU_PB_ELINK_PMU6_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); REG64_FLD( PU_PB_ELINK_PMU6_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); REG64_FLD( PU_PB_ELINK_PMU6_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); REG64_FLD( PU_PB_ELINK_PMU6_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); REG64_FLD( PU_PB_ELINK_PMU6_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); REG64_FLD( PU_PB_ELINK_PMU6_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); REG64_FLD( PU_PB_ELINK_PMU6_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); REG64_FLD( PU_PB_ELINK_PMU7_COUNTER0 , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); REG64_FLD( PU_PB_ELINK_PMU7_COUNTER0_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); REG64_FLD( PU_PB_ELINK_PMU7_COUNTER1 , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); REG64_FLD( PU_PB_ELINK_PMU7_COUNTER1_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); REG64_FLD( PU_PB_ELINK_PMU7_COUNTER2 , 32 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); REG64_FLD( PU_PB_ELINK_PMU7_COUNTER2_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); REG64_FLD( PU_PB_ELINK_PMU7_COUNTER3 , 48 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); REG64_FLD( PU_PB_ELINK_PMU7_COUNTER3_LEN , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0_ENABLE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU0_ENABLE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU1_ENABLE , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU1_ENABLE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2_ENABLE , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU2_ENABLE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU3_ENABLE , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU3_ENABLE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU4_ENABLE , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU4_ENABLE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU5_ENABLE , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU5_ENABLE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU6_ENABLE , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU6_ENABLE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU7_ENABLE , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU7_ENABLE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMULET_FREEZE_MODE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMULET_FREEZE_MODE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_COMMON_FREEZE_MODE , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_COMMON_FREEZE_MODE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMULET_RESET_MODE , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMULET_RESET_MODE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_EVENT0_SEL , 11 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EVENT0_SEL ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_EVENT1_SEL , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EVENT1_SEL ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_EVENT1_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EVENT1_SEL_LEN ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_EVENT2_SEL , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EVENT2_SEL ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_EVENT2_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EVENT2_SEL_LEN ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_EVENT3_SEL , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EVENT3_SEL ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_EVENT3_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EVENT3_SEL_LEN ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0_SIZE , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU0_SIZE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0_SIZE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU0_SIZE_LEN ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU1_SIZE , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU1_SIZE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU1_SIZE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU1_SIZE_LEN ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2_SIZE , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU2_SIZE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2_SIZE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU2_SIZE_LEN ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU3_SIZE , 30 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU3_SIZE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU3_SIZE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU3_SIZE_LEN ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU01_LINK_SELECT , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU01_LINK_SELECT ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU23_LINK_SELECT , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU23_LINK_SELECT ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU45_LINK_SELECT , 34 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU45_LINK_SELECT ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU67_LINK_SELECT , 35 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU67_LINK_SELECT ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT0_MODE , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU0145_EVENT0_MODE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT0_MODE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU0145_EVENT0_MODE_LEN ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT1_MODE , 38 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU0145_EVENT1_MODE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT1_MODE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU0145_EVENT1_MODE_LEN ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT2_MODE , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU0145_EVENT2_MODE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT2_MODE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU0145_EVENT2_MODE_LEN ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT3_MODE , 42 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU0145_EVENT3_MODE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU0145_EVENT3_MODE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU0145_EVENT3_MODE_LEN ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT0_MODE , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU2367_EVENT0_MODE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT0_MODE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU2367_EVENT0_MODE_LEN ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT1_MODE , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU2367_EVENT1_MODE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT1_MODE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU2367_EVENT1_MODE_LEN ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT2_MODE , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU2367_EVENT2_MODE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT2_MODE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU2367_EVENT2_MODE_LEN ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT3_MODE , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU2367_EVENT3_MODE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_PMU2367_EVENT3_MODE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PMU2367_EVENT3_MODE_LEN ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_ENABLE_GLOBAL_RUN , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_GLOBAL_RUN ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_GLOBAL_RUN_MODE , 53 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GLOBAL_RUN_MODE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_SPARE , 54 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SPARE ); REG64_FLD( PU_PB_ELINK_PMU_CTL_REG_SPARE_LEN , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SPARE_LEN ); REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_SET , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_SET ); REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_SET_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_SET_LEN ); REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_STAT , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_STAT ); REG64_FLD( PU_PB_ELINK_RT_DELAY_CTL_REG_STAT_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_STAT_LEN ); REG64_FLD( PU_PB_FP01_CFG_FP0_CREDIT_PRIORITY_4_NOT_8 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP0_CREDIT_PRIORITY_4_NOT_8 ); REG64_FLD( PU_PB_FP01_CFG_FP0_DISABLE_GATHERING , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP0_DISABLE_GATHERING ); REG64_FLD( PU_PB_FP01_CFG_FP0_DISABLE_CMD_COMPRESSION , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP0_DISABLE_CMD_COMPRESSION ); REG64_FLD( PU_PB_FP01_CFG_FP0_DISABLE_PRSP_COMPRESSION , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP0_DISABLE_PRSP_COMPRESSION ); REG64_FLD( PU_PB_FP01_CFG_FP0_LL_CREDIT_LO_LIMIT , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP0_LL_CREDIT_LO_LIMIT ); REG64_FLD( PU_PB_FP01_CFG_FP0_LL_CREDIT_LO_LIMIT_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP0_LL_CREDIT_LO_LIMIT_LEN ); REG64_FLD( PU_PB_FP01_CFG_FP0_LL_CREDIT_HI_LIMIT , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP0_LL_CREDIT_HI_LIMIT ); REG64_FLD( PU_PB_FP01_CFG_FP0_LL_CREDIT_HI_LIMIT_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP0_LL_CREDIT_HI_LIMIT_LEN ); REG64_FLD( PU_PB_FP01_CFG_FP0_FMR_DISABLE , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP0_FMR_DISABLE ); REG64_FLD( PU_PB_FP01_CFG_FP0_FMR_SPARE , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP0_FMR_SPARE ); REG64_FLD( PU_PB_FP01_CFG_CMD_EXP_TIME , 22 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CMD_EXP_TIME ); REG64_FLD( PU_PB_FP01_CFG_CMD_EXP_TIME_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CMD_EXP_TIME_LEN ); REG64_FLD( PU_PB_FP01_CFG_FP0_RUN_AFTER_FRAME_ERROR , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP0_RUN_AFTER_FRAME_ERROR ); REG64_FLD( PU_PB_FP01_CFG_FP0_PRS_DISABLE , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP0_PRS_DISABLE ); REG64_FLD( PU_PB_FP01_CFG_FP0_PRS_SPARE , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP0_PRS_SPARE ); REG64_FLD( PU_PB_FP01_CFG_FP0_PRS_SPARE_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP0_PRS_SPARE_LEN ); REG64_FLD( PU_PB_FP01_CFG_FP1_CREDIT_PRIORITY_4_NOT_8 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP1_CREDIT_PRIORITY_4_NOT_8 ); REG64_FLD( PU_PB_FP01_CFG_FP1_DISABLE_GATHERING , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP1_DISABLE_GATHERING ); REG64_FLD( PU_PB_FP01_CFG_FP1_DISABLE_CMD_COMPRESSION , 34 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP1_DISABLE_CMD_COMPRESSION ); REG64_FLD( PU_PB_FP01_CFG_FP1_DISABLE_PRSP_COMPRESSION , 35 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP1_DISABLE_PRSP_COMPRESSION ); REG64_FLD( PU_PB_FP01_CFG_FP1_LL_CREDIT_LO_LIMIT , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP1_LL_CREDIT_LO_LIMIT ); REG64_FLD( PU_PB_FP01_CFG_FP1_LL_CREDIT_LO_LIMIT_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP1_LL_CREDIT_LO_LIMIT_LEN ); REG64_FLD( PU_PB_FP01_CFG_FP1_LL_CREDIT_HI_LIMIT , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP1_LL_CREDIT_HI_LIMIT ); REG64_FLD( PU_PB_FP01_CFG_FP1_LL_CREDIT_HI_LIMIT_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP1_LL_CREDIT_HI_LIMIT_LEN ); REG64_FLD( PU_PB_FP01_CFG_FP1_FMR_DISABLE , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP1_FMR_DISABLE ); REG64_FLD( PU_PB_FP01_CFG_FP1_FMR_SPARE , 53 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP1_FMR_SPARE ); REG64_FLD( PU_PB_FP01_CFG_FP1_FMR_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP1_FMR_SPARE_LEN ); REG64_FLD( PU_PB_FP01_CFG_FP1_RUN_AFTER_FRAME_ERROR , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP1_RUN_AFTER_FRAME_ERROR ); REG64_FLD( PU_PB_FP01_CFG_FP1_PRS_DISABLE , 57 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP1_PRS_DISABLE ); REG64_FLD( PU_PB_FP01_CFG_FP1_PRS_SPARE , 58 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP1_PRS_SPARE ); REG64_FLD( PU_PB_FP01_CFG_FP1_PRS_SPARE_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP1_PRS_SPARE_LEN ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_CREDIT_PRIORITY_4_NOT_8 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP0_CREDIT_PRIORITY_4_NOT_8 ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_DISABLE_GATHERING , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP0_DISABLE_GATHERING ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_DISABLE_CMD_COMPRESSION , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP0_DISABLE_CMD_COMPRESSION ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_DISABLE_PRSP_COMPRESSION , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP0_DISABLE_PRSP_COMPRESSION ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_LL_CREDIT_LO_LIMIT , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP0_LL_CREDIT_LO_LIMIT ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_LL_CREDIT_LO_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP0_LL_CREDIT_LO_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_LL_CREDIT_HI_LIMIT , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP0_LL_CREDIT_HI_LIMIT ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_LL_CREDIT_HI_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP0_LL_CREDIT_HI_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_FMR_DISABLE , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP0_FMR_DISABLE ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_FMR_SPARE , 21 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP0_FMR_SPARE ); REG64_FLD( PU_IOE_PB_FP01_CFG_CMD_EXP_TIME , 22 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_CMD_EXP_TIME ); REG64_FLD( PU_IOE_PB_FP01_CFG_CMD_EXP_TIME_LEN , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_CMD_EXP_TIME_LEN ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_RUN_AFTER_FRAME_ERROR , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP0_RUN_AFTER_FRAME_ERROR ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_PRS_DISABLE , 25 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP0_PRS_DISABLE ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_PRS_SPARE , 26 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP0_PRS_SPARE ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP0_PRS_SPARE_LEN , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP0_PRS_SPARE_LEN ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_CREDIT_PRIORITY_4_NOT_8 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP1_CREDIT_PRIORITY_4_NOT_8 ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_DISABLE_GATHERING , 33 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP1_DISABLE_GATHERING ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_DISABLE_CMD_COMPRESSION , 34 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP1_DISABLE_CMD_COMPRESSION ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_DISABLE_PRSP_COMPRESSION , 35 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP1_DISABLE_PRSP_COMPRESSION ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_LL_CREDIT_LO_LIMIT , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP1_LL_CREDIT_LO_LIMIT ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_LL_CREDIT_LO_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP1_LL_CREDIT_LO_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_LL_CREDIT_HI_LIMIT , 44 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP1_LL_CREDIT_HI_LIMIT ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_LL_CREDIT_HI_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP1_LL_CREDIT_HI_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_FMR_DISABLE , 52 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP1_FMR_DISABLE ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_FMR_SPARE , 53 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP1_FMR_SPARE ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_FMR_SPARE_LEN , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP1_FMR_SPARE_LEN ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_RUN_AFTER_FRAME_ERROR , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP1_RUN_AFTER_FRAME_ERROR ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_PRS_DISABLE , 57 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP1_PRS_DISABLE ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_PRS_SPARE , 58 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP1_PRS_SPARE ); REG64_FLD( PU_IOE_PB_FP01_CFG_FP1_PRS_SPARE_LEN , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP1_PRS_SPARE_LEN ); REG64_FLD( PU_PB_FP23_CFG_FP2_CREDIT_PRIORITY_4_NOT_8 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP2_CREDIT_PRIORITY_4_NOT_8 ); REG64_FLD( PU_PB_FP23_CFG_FP2_DISABLE_GATHERING , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP2_DISABLE_GATHERING ); REG64_FLD( PU_PB_FP23_CFG_FP2_DISABLE_CMD_COMPRESSION , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP2_DISABLE_CMD_COMPRESSION ); REG64_FLD( PU_PB_FP23_CFG_FP2_DISABLE_PRSP_COMPRESSION , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP2_DISABLE_PRSP_COMPRESSION ); REG64_FLD( PU_PB_FP23_CFG_FP2_LL_CREDIT_LO_LIMIT , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP2_LL_CREDIT_LO_LIMIT ); REG64_FLD( PU_PB_FP23_CFG_FP2_LL_CREDIT_LO_LIMIT_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP2_LL_CREDIT_LO_LIMIT_LEN ); REG64_FLD( PU_PB_FP23_CFG_FP2_LL_CREDIT_HI_LIMIT , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP2_LL_CREDIT_HI_LIMIT ); REG64_FLD( PU_PB_FP23_CFG_FP2_LL_CREDIT_HI_LIMIT_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP2_LL_CREDIT_HI_LIMIT_LEN ); REG64_FLD( PU_PB_FP23_CFG_FP2_FMR_DISABLE , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP2_FMR_DISABLE ); REG64_FLD( PU_PB_FP23_CFG_FP2_FMR_SPARE , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP2_FMR_SPARE ); REG64_FLD( PU_PB_FP23_CFG_CMD_EXP_TIME , 22 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CMD_EXP_TIME ); REG64_FLD( PU_PB_FP23_CFG_CMD_EXP_TIME_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CMD_EXP_TIME_LEN ); REG64_FLD( PU_PB_FP23_CFG_FP2_RUN_AFTER_FRAME_ERROR , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP2_RUN_AFTER_FRAME_ERROR ); REG64_FLD( PU_PB_FP23_CFG_FP2_PRS_DISABLE , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP2_PRS_DISABLE ); REG64_FLD( PU_PB_FP23_CFG_FP2_PRS_SPARE , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP2_PRS_SPARE ); REG64_FLD( PU_PB_FP23_CFG_FP2_PRS_SPARE_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP2_PRS_SPARE_LEN ); REG64_FLD( PU_PB_FP23_CFG_FP3_CREDIT_PRIORITY_4_NOT_8 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP3_CREDIT_PRIORITY_4_NOT_8 ); REG64_FLD( PU_PB_FP23_CFG_FP3_DISABLE_GATHERING , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP3_DISABLE_GATHERING ); REG64_FLD( PU_PB_FP23_CFG_FP3_DISABLE_CMD_COMPRESSION , 34 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP3_DISABLE_CMD_COMPRESSION ); REG64_FLD( PU_PB_FP23_CFG_FP3_DISABLE_PRSP_COMPRESSION , 35 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP3_DISABLE_PRSP_COMPRESSION ); REG64_FLD( PU_PB_FP23_CFG_FP3_LL_CREDIT_LO_LIMIT , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP3_LL_CREDIT_LO_LIMIT ); REG64_FLD( PU_PB_FP23_CFG_FP3_LL_CREDIT_LO_LIMIT_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP3_LL_CREDIT_LO_LIMIT_LEN ); REG64_FLD( PU_PB_FP23_CFG_FP3_LL_CREDIT_HI_LIMIT , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP3_LL_CREDIT_HI_LIMIT ); REG64_FLD( PU_PB_FP23_CFG_FP3_LL_CREDIT_HI_LIMIT_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP3_LL_CREDIT_HI_LIMIT_LEN ); REG64_FLD( PU_PB_FP23_CFG_FP3_FMR_DISABLE , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP3_FMR_DISABLE ); REG64_FLD( PU_PB_FP23_CFG_FP3_FMR_SPARE , 53 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP3_FMR_SPARE ); REG64_FLD( PU_PB_FP23_CFG_FP3_FMR_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP3_FMR_SPARE_LEN ); REG64_FLD( PU_PB_FP23_CFG_FP3_RUN_AFTER_FRAME_ERROR , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP3_RUN_AFTER_FRAME_ERROR ); REG64_FLD( PU_PB_FP23_CFG_FP3_PRS_DISABLE , 57 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP3_PRS_DISABLE ); REG64_FLD( PU_PB_FP23_CFG_FP3_PRS_SPARE , 58 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP3_PRS_SPARE ); REG64_FLD( PU_PB_FP23_CFG_FP3_PRS_SPARE_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP3_PRS_SPARE_LEN ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_CREDIT_PRIORITY_4_NOT_8 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP2_CREDIT_PRIORITY_4_NOT_8 ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_DISABLE_GATHERING , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP2_DISABLE_GATHERING ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_DISABLE_CMD_COMPRESSION , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP2_DISABLE_CMD_COMPRESSION ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_DISABLE_PRSP_COMPRESSION , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP2_DISABLE_PRSP_COMPRESSION ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_LL_CREDIT_LO_LIMIT , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP2_LL_CREDIT_LO_LIMIT ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_LL_CREDIT_LO_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP2_LL_CREDIT_LO_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_LL_CREDIT_HI_LIMIT , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP2_LL_CREDIT_HI_LIMIT ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_LL_CREDIT_HI_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP2_LL_CREDIT_HI_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_FMR_DISABLE , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP2_FMR_DISABLE ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_FMR_SPARE , 21 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP2_FMR_SPARE ); REG64_FLD( PU_IOE_PB_FP23_CFG_CMD_EXP_TIME , 22 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_CMD_EXP_TIME ); REG64_FLD( PU_IOE_PB_FP23_CFG_CMD_EXP_TIME_LEN , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_CMD_EXP_TIME_LEN ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_RUN_AFTER_FRAME_ERROR , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP2_RUN_AFTER_FRAME_ERROR ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_PRS_DISABLE , 25 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP2_PRS_DISABLE ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_PRS_SPARE , 26 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP2_PRS_SPARE ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP2_PRS_SPARE_LEN , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP2_PRS_SPARE_LEN ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_CREDIT_PRIORITY_4_NOT_8 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP3_CREDIT_PRIORITY_4_NOT_8 ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_DISABLE_GATHERING , 33 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP3_DISABLE_GATHERING ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_DISABLE_CMD_COMPRESSION , 34 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP3_DISABLE_CMD_COMPRESSION ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_DISABLE_PRSP_COMPRESSION , 35 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP3_DISABLE_PRSP_COMPRESSION ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_LL_CREDIT_LO_LIMIT , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP3_LL_CREDIT_LO_LIMIT ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_LL_CREDIT_LO_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP3_LL_CREDIT_LO_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_LL_CREDIT_HI_LIMIT , 44 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP3_LL_CREDIT_HI_LIMIT ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_LL_CREDIT_HI_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP3_LL_CREDIT_HI_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_FMR_DISABLE , 52 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP3_FMR_DISABLE ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_FMR_SPARE , 53 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP3_FMR_SPARE ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_FMR_SPARE_LEN , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP3_FMR_SPARE_LEN ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_RUN_AFTER_FRAME_ERROR , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP3_RUN_AFTER_FRAME_ERROR ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_PRS_DISABLE , 57 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP3_PRS_DISABLE ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_PRS_SPARE , 58 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP3_PRS_SPARE ); REG64_FLD( PU_IOE_PB_FP23_CFG_FP3_PRS_SPARE_LEN , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP3_PRS_SPARE_LEN ); REG64_FLD( PU_PB_FP45_CFG_FP4_CREDIT_PRIORITY_4_NOT_8 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP4_CREDIT_PRIORITY_4_NOT_8 ); REG64_FLD( PU_PB_FP45_CFG_FP4_DISABLE_GATHERING , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP4_DISABLE_GATHERING ); REG64_FLD( PU_PB_FP45_CFG_FP4_DISABLE_CMD_COMPRESSION , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP4_DISABLE_CMD_COMPRESSION ); REG64_FLD( PU_PB_FP45_CFG_FP4_DISABLE_PRSP_COMPRESSION , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP4_DISABLE_PRSP_COMPRESSION ); REG64_FLD( PU_PB_FP45_CFG_FP4_LL_CREDIT_LO_LIMIT , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP4_LL_CREDIT_LO_LIMIT ); REG64_FLD( PU_PB_FP45_CFG_FP4_LL_CREDIT_LO_LIMIT_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP4_LL_CREDIT_LO_LIMIT_LEN ); REG64_FLD( PU_PB_FP45_CFG_FP4_LL_CREDIT_HI_LIMIT , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP4_LL_CREDIT_HI_LIMIT ); REG64_FLD( PU_PB_FP45_CFG_FP4_LL_CREDIT_HI_LIMIT_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP4_LL_CREDIT_HI_LIMIT_LEN ); REG64_FLD( PU_PB_FP45_CFG_FP4_FMR_DISABLE , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP4_FMR_DISABLE ); REG64_FLD( PU_PB_FP45_CFG_FP4_FMR_SPARE , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP4_FMR_SPARE ); REG64_FLD( PU_PB_FP45_CFG_CMD_EXP_TIME , 22 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CMD_EXP_TIME ); REG64_FLD( PU_PB_FP45_CFG_CMD_EXP_TIME_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CMD_EXP_TIME_LEN ); REG64_FLD( PU_PB_FP45_CFG_FP4_RUN_AFTER_FRAME_ERROR , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP4_RUN_AFTER_FRAME_ERROR ); REG64_FLD( PU_PB_FP45_CFG_FP4_PRS_DISABLE , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP4_PRS_DISABLE ); REG64_FLD( PU_PB_FP45_CFG_FP4_PRS_SPARE , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP4_PRS_SPARE ); REG64_FLD( PU_PB_FP45_CFG_FP4_PRS_SPARE_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP4_PRS_SPARE_LEN ); REG64_FLD( PU_PB_FP45_CFG_FP5_CREDIT_PRIORITY_4_NOT_8 , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP5_CREDIT_PRIORITY_4_NOT_8 ); REG64_FLD( PU_PB_FP45_CFG_FP5_DISABLE_GATHERING , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP5_DISABLE_GATHERING ); REG64_FLD( PU_PB_FP45_CFG_FP5_DISABLE_CMD_COMPRESSION , 34 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP5_DISABLE_CMD_COMPRESSION ); REG64_FLD( PU_PB_FP45_CFG_FP5_DISABLE_PRSP_COMPRESSION , 35 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP5_DISABLE_PRSP_COMPRESSION ); REG64_FLD( PU_PB_FP45_CFG_FP5_LL_CREDIT_LO_LIMIT , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP5_LL_CREDIT_LO_LIMIT ); REG64_FLD( PU_PB_FP45_CFG_FP5_LL_CREDIT_LO_LIMIT_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP5_LL_CREDIT_LO_LIMIT_LEN ); REG64_FLD( PU_PB_FP45_CFG_FP5_LL_CREDIT_HI_LIMIT , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP5_LL_CREDIT_HI_LIMIT ); REG64_FLD( PU_PB_FP45_CFG_FP5_LL_CREDIT_HI_LIMIT_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP5_LL_CREDIT_HI_LIMIT_LEN ); REG64_FLD( PU_PB_FP45_CFG_FP5_FMR_DISABLE , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP5_FMR_DISABLE ); REG64_FLD( PU_PB_FP45_CFG_FP5_FMR_SPARE , 53 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP5_FMR_SPARE ); REG64_FLD( PU_PB_FP45_CFG_FP5_FMR_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP5_FMR_SPARE_LEN ); REG64_FLD( PU_PB_FP45_CFG_FP5_RUN_AFTER_FRAME_ERROR , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP5_RUN_AFTER_FRAME_ERROR ); REG64_FLD( PU_PB_FP45_CFG_FP5_PRS_DISABLE , 57 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP5_PRS_DISABLE ); REG64_FLD( PU_PB_FP45_CFG_FP5_PRS_SPARE , 58 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP5_PRS_SPARE ); REG64_FLD( PU_PB_FP45_CFG_FP5_PRS_SPARE_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FP5_PRS_SPARE_LEN ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_CREDIT_PRIORITY_4_NOT_8 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP4_CREDIT_PRIORITY_4_NOT_8 ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_DISABLE_GATHERING , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP4_DISABLE_GATHERING ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_DISABLE_CMD_COMPRESSION , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP4_DISABLE_CMD_COMPRESSION ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_DISABLE_PRSP_COMPRESSION , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP4_DISABLE_PRSP_COMPRESSION ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_LL_CREDIT_LO_LIMIT , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP4_LL_CREDIT_LO_LIMIT ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_LL_CREDIT_LO_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP4_LL_CREDIT_LO_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_LL_CREDIT_HI_LIMIT , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP4_LL_CREDIT_HI_LIMIT ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_LL_CREDIT_HI_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP4_LL_CREDIT_HI_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_FMR_DISABLE , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP4_FMR_DISABLE ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_FMR_SPARE , 21 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP4_FMR_SPARE ); REG64_FLD( PU_IOE_PB_FP45_CFG_CMD_EXP_TIME , 22 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_CMD_EXP_TIME ); REG64_FLD( PU_IOE_PB_FP45_CFG_CMD_EXP_TIME_LEN , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_CMD_EXP_TIME_LEN ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_RUN_AFTER_FRAME_ERROR , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP4_RUN_AFTER_FRAME_ERROR ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_PRS_DISABLE , 25 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP4_PRS_DISABLE ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_PRS_SPARE , 26 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP4_PRS_SPARE ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP4_PRS_SPARE_LEN , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP4_PRS_SPARE_LEN ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_CREDIT_PRIORITY_4_NOT_8 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP5_CREDIT_PRIORITY_4_NOT_8 ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_DISABLE_GATHERING , 33 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP5_DISABLE_GATHERING ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_DISABLE_CMD_COMPRESSION , 34 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP5_DISABLE_CMD_COMPRESSION ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_DISABLE_PRSP_COMPRESSION , 35 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP5_DISABLE_PRSP_COMPRESSION ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_LL_CREDIT_LO_LIMIT , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP5_LL_CREDIT_LO_LIMIT ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_LL_CREDIT_LO_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP5_LL_CREDIT_LO_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_LL_CREDIT_HI_LIMIT , 44 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP5_LL_CREDIT_HI_LIMIT ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_LL_CREDIT_HI_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP5_LL_CREDIT_HI_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_FMR_DISABLE , 52 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP5_FMR_DISABLE ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_FMR_SPARE , 53 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP5_FMR_SPARE ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_FMR_SPARE_LEN , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP5_FMR_SPARE_LEN ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_RUN_AFTER_FRAME_ERROR , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP5_RUN_AFTER_FRAME_ERROR ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_PRS_DISABLE , 57 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP5_PRS_DISABLE ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_PRS_SPARE , 58 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP5_PRS_SPARE ); REG64_FLD( PU_IOE_PB_FP45_CFG_FP5_PRS_SPARE_LEN , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP5_PRS_SPARE_LEN ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_CREDIT_PRIORITY_4_NOT_8 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP6_CREDIT_PRIORITY_4_NOT_8 ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_DISABLE_GATHERING , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP6_DISABLE_GATHERING ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_DISABLE_CMD_COMPRESSION , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP6_DISABLE_CMD_COMPRESSION ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_DISABLE_PRSP_COMPRESSION , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP6_DISABLE_PRSP_COMPRESSION ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_LL_CREDIT_LO_LIMIT , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP6_LL_CREDIT_LO_LIMIT ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_LL_CREDIT_LO_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP6_LL_CREDIT_LO_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_LL_CREDIT_HI_LIMIT , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP6_LL_CREDIT_HI_LIMIT ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_LL_CREDIT_HI_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP6_LL_CREDIT_HI_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_FMR_DISABLE , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP6_FMR_DISABLE ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_FMR_SPARE , 21 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP6_FMR_SPARE ); REG64_FLD( PU_IOE_PB_FP67_CFG_CMD_EXP_TIME , 22 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_CMD_EXP_TIME ); REG64_FLD( PU_IOE_PB_FP67_CFG_CMD_EXP_TIME_LEN , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_CMD_EXP_TIME_LEN ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_RUN_AFTER_FRAME_ERROR , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP6_RUN_AFTER_FRAME_ERROR ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_PRS_DISABLE , 25 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP6_PRS_DISABLE ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_PRS_SPARE , 26 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP6_PRS_SPARE ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP6_PRS_SPARE_LEN , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP6_PRS_SPARE_LEN ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_CREDIT_PRIORITY_4_NOT_8 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP7_CREDIT_PRIORITY_4_NOT_8 ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_DISABLE_GATHERING , 33 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP7_DISABLE_GATHERING ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_DISABLE_CMD_COMPRESSION , 34 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP7_DISABLE_CMD_COMPRESSION ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_DISABLE_PRSP_COMPRESSION , 35 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP7_DISABLE_PRSP_COMPRESSION ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_LL_CREDIT_LO_LIMIT , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP7_LL_CREDIT_LO_LIMIT ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_LL_CREDIT_LO_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP7_LL_CREDIT_LO_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_LL_CREDIT_HI_LIMIT , 44 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP7_LL_CREDIT_HI_LIMIT ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_LL_CREDIT_HI_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP7_LL_CREDIT_HI_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_FMR_DISABLE , 52 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP7_FMR_DISABLE ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_FMR_SPARE , 53 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP7_FMR_SPARE ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_FMR_SPARE_LEN , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP7_FMR_SPARE_LEN ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_RUN_AFTER_FRAME_ERROR , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP7_RUN_AFTER_FRAME_ERROR ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_PRS_DISABLE , 57 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP7_PRS_DISABLE ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_PRS_SPARE , 58 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP7_PRS_SPARE ); REG64_FLD( PU_IOE_PB_FP67_CFG_FP7_PRS_SPARE_LEN , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_FP7_PRS_SPARE_LEN ); REG64_FLD( PU_PB_IOE_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( PU_PB_IOE_FIR_ACTION0_REG_ACTION0_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); REG64_FLD( PU_PB_IOE_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); REG64_FLD( PU_PB_IOE_FIR_ACTION1_REG_ACTION1_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FMR00_TRAINED , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FMR00_TRAINED ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FMR01_TRAINED , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FMR01_TRAINED ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FMR02_TRAINED , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FMR02_TRAINED ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FMR03_TRAINED , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FMR03_TRAINED ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FMR04_TRAINED , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FMR04_TRAINED ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FMR05_TRAINED , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FMR05_TRAINED ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV6 , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RSV6 ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV7 , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RSV7 ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB01_UE , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB01_UE ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB01_CE , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB01_CE ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB01_SUE , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB01_SUE ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB23_UE , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB23_UE ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB23_CE , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB23_CE ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB23_SUE , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB23_SUE ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB45_UE , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB45_UE ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB45_CE , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB45_CE ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB45_SUE , 16 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB45_SUE ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV17 , 17 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RSV17 ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV18 , 18 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RSV18 ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV19 , 19 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RSV19 ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FRAMER00_ATTN , 20 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FRAMER00_ATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FRAMER01_ATTN , 21 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FRAMER01_ATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FRAMER02_ATTN , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FRAMER02_ATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FRAMER03_ATTN , 23 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FRAMER03_ATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FRAMER04_ATTN , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FRAMER04_ATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_FRAMER05_ATTN , 25 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FRAMER05_ATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV26 , 26 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RSV26 ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV27 , 27 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RSV27 ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_PARSER00_ATTN , 28 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARSER00_ATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_PARSER01_ATTN , 29 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARSER01_ATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_PARSER02_ATTN , 30 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARSER02_ATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_PARSER03_ATTN , 31 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARSER03_ATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_PARSER04_ATTN , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARSER04_ATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_PARSER05_ATTN , 33 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARSER05_ATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV34 , 34 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RSV34 ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_RSV35 , 35 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RSV35 ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB00_SPATTN , 36 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB00_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB01_SPATTN , 37 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB01_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB10_SPATTN , 38 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB10_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB11_SPATTN , 39 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB11_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB20_SPATTN , 40 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB20_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB21_SPATTN , 41 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB21_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB30_SPATTN , 42 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB30_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB31_SPATTN , 43 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB31_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB40_SPATTN , 44 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB40_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB41_SPATTN , 45 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB41_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB50_SPATTN , 46 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB50_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_MB51_SPATTN , 47 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB51_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB01_ERR , 52 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB01_ERR ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB23_ERR , 53 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB23_ERR ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DOB45_ERR , 54 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB45_ERR ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DIB01_ERR , 56 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DIB01_ERR ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DIB23_ERR , 57 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DIB23_ERR ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_DIB45_ERR , 58 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DIB45_ERR ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_SCOM_ERR_DUP , 62 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); REG64_FLD( PU_PB_IOE_FIR_MASK_REG_SCOM_ERR , 63 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); REG64_FLD( PU_PB_IOE_FIR_REG_FMR00_TRAINED , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FMR00_TRAINED ); REG64_FLD( PU_PB_IOE_FIR_REG_FMR01_TRAINED , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FMR01_TRAINED ); REG64_FLD( PU_PB_IOE_FIR_REG_FMR02_TRAINED , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FMR02_TRAINED ); REG64_FLD( PU_PB_IOE_FIR_REG_FMR03_TRAINED , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FMR03_TRAINED ); REG64_FLD( PU_PB_IOE_FIR_REG_FMR04_TRAINED , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FMR04_TRAINED ); REG64_FLD( PU_PB_IOE_FIR_REG_FMR05_TRAINED , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FMR05_TRAINED ); REG64_FLD( PU_PB_IOE_FIR_REG_RSV6 , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RSV6 ); REG64_FLD( PU_PB_IOE_FIR_REG_RSV7 , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RSV7 ); REG64_FLD( PU_PB_IOE_FIR_REG_DOB01_UE , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB01_UE ); REG64_FLD( PU_PB_IOE_FIR_REG_DOB01_CE , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB01_CE ); REG64_FLD( PU_PB_IOE_FIR_REG_DOB01_SUE , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB01_SUE ); REG64_FLD( PU_PB_IOE_FIR_REG_DOB23_UE , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB23_UE ); REG64_FLD( PU_PB_IOE_FIR_REG_DOB23_CE , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB23_CE ); REG64_FLD( PU_PB_IOE_FIR_REG_DOB23_SUE , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB23_SUE ); REG64_FLD( PU_PB_IOE_FIR_REG_DOB45_UE , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB45_UE ); REG64_FLD( PU_PB_IOE_FIR_REG_DOB45_CE , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB45_CE ); REG64_FLD( PU_PB_IOE_FIR_REG_DOB45_SUE , 16 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB45_SUE ); REG64_FLD( PU_PB_IOE_FIR_REG_RSV17 , 17 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RSV17 ); REG64_FLD( PU_PB_IOE_FIR_REG_RSV18 , 18 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RSV18 ); REG64_FLD( PU_PB_IOE_FIR_REG_RSV19 , 19 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RSV19 ); REG64_FLD( PU_PB_IOE_FIR_REG_FRAMER00_ATTN , 20 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FRAMER00_ATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_FRAMER01_ATTN , 21 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FRAMER01_ATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_FRAMER02_ATTN , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FRAMER02_ATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_FRAMER03_ATTN , 23 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FRAMER03_ATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_FRAMER04_ATTN , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FRAMER04_ATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_FRAMER05_ATTN , 25 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FRAMER05_ATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_RSV26 , 26 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RSV26 ); REG64_FLD( PU_PB_IOE_FIR_REG_RSV27 , 27 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RSV27 ); REG64_FLD( PU_PB_IOE_FIR_REG_PARSER00_ATTN , 28 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARSER00_ATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_PARSER01_ATTN , 29 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARSER01_ATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_PARSER02_ATTN , 30 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARSER02_ATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_PARSER03_ATTN , 31 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARSER03_ATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_PARSER04_ATTN , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARSER04_ATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_PARSER05_ATTN , 33 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARSER05_ATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_RSV34 , 34 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RSV34 ); REG64_FLD( PU_PB_IOE_FIR_REG_RSV35 , 35 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RSV35 ); REG64_FLD( PU_PB_IOE_FIR_REG_MB00_SPATTN , 36 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB00_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_MB01_SPATTN , 37 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB01_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_MB10_SPATTN , 38 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB10_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_MB11_SPATTN , 39 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB11_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_MB20_SPATTN , 40 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB20_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_MB21_SPATTN , 41 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB21_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_MB30_SPATTN , 42 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB30_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_MB31_SPATTN , 43 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB31_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_MB40_SPATTN , 44 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB40_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_MB41_SPATTN , 45 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB41_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_MB50_SPATTN , 46 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB50_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_MB51_SPATTN , 47 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MB51_SPATTN ); REG64_FLD( PU_PB_IOE_FIR_REG_DOB01_ERR , 52 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB01_ERR ); REG64_FLD( PU_PB_IOE_FIR_REG_DOB23_ERR , 53 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB23_ERR ); REG64_FLD( PU_PB_IOE_FIR_REG_DOB45_ERR , 54 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DOB45_ERR ); REG64_FLD( PU_PB_IOE_FIR_REG_DIB01_ERR , 56 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DIB01_ERR ); REG64_FLD( PU_PB_IOE_FIR_REG_DIB23_ERR , 57 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DIB23_ERR ); REG64_FLD( PU_PB_IOE_FIR_REG_DIB45_ERR , 58 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DIB45_ERR ); REG64_FLD( PU_PB_IOE_FIR_REG_SCOM_ERR_DUP , 62 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); REG64_FLD( PU_PB_IOE_FIR_REG_SCOM_ERR , 63 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); REG64_FLD( PU_IOE_PB_IOO_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( PU_IOE_PB_IOO_FIR_ACTION0_REG_ACTION0_LEN , 64 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); REG64_FLD( PU_IOE_PB_IOO_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); REG64_FLD( PU_IOE_PB_IOO_FIR_ACTION1_REG_ACTION1_LEN , 64 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FMR00_TRAINED , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FMR00_TRAINED ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FMR01_TRAINED , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FMR01_TRAINED ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FMR02_TRAINED , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FMR02_TRAINED ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FMR03_TRAINED , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FMR03_TRAINED ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FMR04_TRAINED , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FMR04_TRAINED ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FMR05_TRAINED , 5 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FMR05_TRAINED ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FMR06_TRAINED , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FMR06_TRAINED ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FMR07_TRAINED , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FMR07_TRAINED ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB01_UE , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB01_UE ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB01_CE , 9 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB01_CE ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB01_SUE , 10 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB01_SUE ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB23_UE , 11 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB23_UE ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB23_CE , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB23_CE ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB23_SUE , 13 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB23_SUE ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB45_UE , 14 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB45_UE ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB45_CE , 15 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB45_CE ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB45_SUE , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB45_SUE ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB67_UE , 17 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB67_UE ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB67_CE , 18 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB67_CE ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB67_SUE , 19 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB67_SUE ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER00_ATTN , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FRAMER00_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER01_ATTN , 21 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FRAMER01_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER02_ATTN , 22 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FRAMER02_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER03_ATTN , 23 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FRAMER03_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER04_ATTN , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FRAMER04_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER05_ATTN , 25 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FRAMER05_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER06_ATTN , 26 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FRAMER06_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_FRAMER07_ATTN , 27 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FRAMER07_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_PARSER00_ATTN , 28 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_PARSER00_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_PARSER01_ATTN , 29 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_PARSER01_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_PARSER02_ATTN , 30 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_PARSER02_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_PARSER03_ATTN , 31 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_PARSER03_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_PARSER04_ATTN , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_PARSER04_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_PARSER05_ATTN , 33 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_PARSER05_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_PARSER06_ATTN , 34 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_PARSER06_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_PARSER07_ATTN , 35 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_PARSER07_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB00_SPATTN , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB00_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB01_SPATTN , 37 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB01_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB10_SPATTN , 38 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB10_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB11_SPATTN , 39 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB11_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB20_SPATTN , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB20_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB21_SPATTN , 41 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB21_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB30_SPATTN , 42 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB30_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB31_SPATTN , 43 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB31_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB40_SPATTN , 44 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB40_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB41_SPATTN , 45 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB41_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB50_SPATTN , 46 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB50_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB51_SPATTN , 47 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB51_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB60_SPATTN , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB60_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB61_SPATTN , 49 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB61_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB70_SPATTN , 50 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB70_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_MB71_SPATTN , 51 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB71_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB01_ERR , 52 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB01_ERR ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB23_ERR , 53 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB23_ERR ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB45_ERR , 54 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB45_ERR ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DOB67_ERR , 55 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB67_ERR ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DIB01_ERR , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DIB01_ERR ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DIB23_ERR , 57 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DIB23_ERR ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DIB45_ERR , 58 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DIB45_ERR ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_DIB67_ERR , 59 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DIB67_ERR ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_SCOM_ERR_DUP , 62 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); REG64_FLD( PU_IOE_PB_IOO_FIR_MASK_REG_SCOM_ERR , 63 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FMR00_TRAINED , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FMR00_TRAINED ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FMR01_TRAINED , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FMR01_TRAINED ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FMR02_TRAINED , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FMR02_TRAINED ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FMR03_TRAINED , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FMR03_TRAINED ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FMR04_TRAINED , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FMR04_TRAINED ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FMR05_TRAINED , 5 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FMR05_TRAINED ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FMR06_TRAINED , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FMR06_TRAINED ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FMR07_TRAINED , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FMR07_TRAINED ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB01_UE , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB01_UE ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB01_CE , 9 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB01_CE ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB01_SUE , 10 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB01_SUE ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB23_UE , 11 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB23_UE ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB23_CE , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB23_CE ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB23_SUE , 13 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB23_SUE ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB45_UE , 14 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB45_UE ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB45_CE , 15 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB45_CE ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB45_SUE , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB45_SUE ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB67_UE , 17 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB67_UE ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB67_CE , 18 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB67_CE ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB67_SUE , 19 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB67_SUE ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FRAMER00_ATTN , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FRAMER00_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FRAMER01_ATTN , 21 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FRAMER01_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FRAMER02_ATTN , 22 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FRAMER02_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FRAMER03_ATTN , 23 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FRAMER03_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FRAMER04_ATTN , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FRAMER04_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FRAMER05_ATTN , 25 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FRAMER05_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FRAMER06_ATTN , 26 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FRAMER06_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_FRAMER07_ATTN , 27 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_FRAMER07_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_PARSER00_ATTN , 28 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_PARSER00_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_PARSER01_ATTN , 29 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_PARSER01_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_PARSER02_ATTN , 30 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_PARSER02_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_PARSER03_ATTN , 31 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_PARSER03_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_PARSER04_ATTN , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_PARSER04_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_PARSER05_ATTN , 33 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_PARSER05_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_PARSER06_ATTN , 34 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_PARSER06_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_PARSER07_ATTN , 35 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_PARSER07_ATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB00_SPATTN , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB00_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB01_SPATTN , 37 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB01_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB10_SPATTN , 38 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB10_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB11_SPATTN , 39 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB11_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB20_SPATTN , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB20_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB21_SPATTN , 41 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB21_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB30_SPATTN , 42 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB30_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB31_SPATTN , 43 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB31_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB40_SPATTN , 44 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB40_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB41_SPATTN , 45 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB41_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB50_SPATTN , 46 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB50_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB51_SPATTN , 47 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB51_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB60_SPATTN , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB60_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB61_SPATTN , 49 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB61_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB70_SPATTN , 50 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB70_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_MB71_SPATTN , 51 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_MB71_SPATTN ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB01_ERR , 52 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB01_ERR ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB23_ERR , 53 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB23_ERR ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB45_ERR , 54 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB45_ERR ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DOB67_ERR , 55 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DOB67_ERR ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DIB01_ERR , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DIB01_ERR ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DIB23_ERR , 57 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DIB23_ERR ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DIB45_ERR , 58 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DIB45_ERR ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_DIB67_ERR , 59 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_DIB67_ERR ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_SCOM_ERR_DUP , 62 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); REG64_FLD( PU_IOE_PB_IOO_FIR_REG_SCOM_ERR , 63 , SH_UNT_PU_IOE , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); REG64_FLD( PU_PB_MISC_CFG_IOE01_IS_LOGICAL_PAIR , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_IOE01_IS_LOGICAL_PAIR ); REG64_FLD( PU_PB_MISC_CFG_IOE23_IS_LOGICAL_PAIR , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_IOE23_IS_LOGICAL_PAIR ); REG64_FLD( PU_PB_MISC_CFG_IOE45_IS_LOGICAL_PAIR , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_IOE45_IS_LOGICAL_PAIR ); REG64_FLD( PU_PB_MISC_CFG_SPARE3 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE3 ); REG64_FLD( PU_PB_MISC_CFG_SCOM_LINK01_RESET_KEEPER , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_SCOM_LINK01_RESET_KEEPER ); REG64_FLD( PU_PB_MISC_CFG_SCOM_LINK23_RESET_KEEPER , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_SCOM_LINK23_RESET_KEEPER ); REG64_FLD( PU_PB_MISC_CFG_SCOM_LINK45_RESET_KEEPER , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_SCOM_LINK45_RESET_KEEPER ); REG64_FLD( PU_PB_MISC_CFG_SPARE7 , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE7 ); REG64_FLD( PU_PB_MISC_CFG_SPARE8 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE8 ); REG64_FLD( PU_PB_MISC_CFG_SPARE9 , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE9 ); REG64_FLD( PU_PB_MISC_CFG_SPARE10 , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE10 ); REG64_FLD( PU_PB_MISC_CFG_SPARE11 , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE11 ); REG64_FLD( PU_PB_MISC_CFG_LINK_AVP_MODE , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_LINK_AVP_MODE ); REG64_FLD( PU_PB_MISC_CFG_SPARE13 , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE13 ); REG64_FLD( PU_PB_MISC_CFG_SPARE14 , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE14 ); REG64_FLD( PU_PB_MISC_CFG_SPARE15 , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE15 ); REG64_FLD( PU_IOE_PB_MISC_CFG_IOO01_IS_LOGICAL_PAIR , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_IOO01_IS_LOGICAL_PAIR ); REG64_FLD( PU_IOE_PB_MISC_CFG_IOO23_IS_LOGICAL_PAIR , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_IOO23_IS_LOGICAL_PAIR ); REG64_FLD( PU_IOE_PB_MISC_CFG_IOO45_IS_LOGICAL_PAIR , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_IOO45_IS_LOGICAL_PAIR ); REG64_FLD( PU_IOE_PB_MISC_CFG_IOO67_IS_LOGICAL_PAIR , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_IOO67_IS_LOGICAL_PAIR ); REG64_FLD( PU_IOE_PB_MISC_CFG_SCOM_LINK01_RESET_KEEPER , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_SCOM_LINK01_RESET_KEEPER ); REG64_FLD( PU_IOE_PB_MISC_CFG_SCOM_LINK23_RESET_KEEPER , 5 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_SCOM_LINK23_RESET_KEEPER ); REG64_FLD( PU_IOE_PB_MISC_CFG_SCOM_LINK45_RESET_KEEPER , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_SCOM_LINK45_RESET_KEEPER ); REG64_FLD( PU_IOE_PB_MISC_CFG_SCOM_LINK67_RESET_KEEPER , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_SCOM_LINK67_RESET_KEEPER ); REG64_FLD( PU_IOE_PB_MISC_CFG_LINKS01_TOD_ENABLE , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_LINKS01_TOD_ENABLE ); REG64_FLD( PU_IOE_PB_MISC_CFG_LINKS23_TOD_ENABLE , 9 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_LINKS23_TOD_ENABLE ); REG64_FLD( PU_IOE_PB_MISC_CFG_LINKS45_TOD_ENABLE , 10 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_LINKS45_TOD_ENABLE ); REG64_FLD( PU_IOE_PB_MISC_CFG_LINKS67_TOD_ENABLE , 11 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_LINKS67_TOD_ENABLE ); REG64_FLD( PU_IOE_PB_MISC_CFG_LINK_AVP_MODE , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_LINK_AVP_MODE ); REG64_FLD( PU_IOE_PB_MISC_CFG_SEL_03_NPU_NOT , 13 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_SEL_03_NPU_NOT ); REG64_FLD( PU_IOE_PB_MISC_CFG_SEL_04_NPU_NOT , 14 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_SEL_04_NPU_NOT ); REG64_FLD( PU_IOE_PB_MISC_CFG_SEL_05_NPU_NOT , 15 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_SEL_05_NPU_NOT ); REG64_FLD( PU_IOE_PB_MISC_CFG_SPARE , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_SPARE ); REG64_FLD( PU_IOE_PB_MISC_CFG_SPARE_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK01_CAPP_MODE , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK01_CAPP_MODE ); REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK01_HRB_INIT_STATE , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK01_HRB_INIT_STATE ); REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_SPARE , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK0_SPARE ); REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_SPARE_LEN , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK0_SPARE_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_VC0_LIMIT , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK0_DOB_VC0_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_VC0_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK0_DOB_VC0_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_VC1_LIMIT , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK0_DOB_VC1_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK0_DOB_VC1_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK0_DOB_VC1_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK01_DIB_VC_LIMIT , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK01_DIB_VC_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK01_DIB_VC_LIMIT_LEN , 5 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK01_DIB_VC_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_DIB01_SPARE , 29 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_DIB01_SPARE ); REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_DIB01_SPARE_LEN , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_DIB01_SPARE_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_SPARE , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK1_SPARE ); REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_SPARE_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK1_SPARE_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_VC0_LIMIT , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK1_DOB_VC0_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_VC0_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK1_DOB_VC0_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_VC1_LIMIT , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK1_DOB_VC1_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_01_CFG_REG_LINK1_DOB_VC1_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK1_DOB_VC1_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_LIMIT , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK2_DOB_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_LIMIT_LEN , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK2_DOB_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_VC0_LIMIT , 9 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK2_DOB_VC0_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_VC0_LIMIT_LEN , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK2_DOB_VC0_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_VC1_LIMIT , 17 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK2_DOB_VC1_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK2_DOB_VC1_LIMIT_LEN , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK2_DOB_VC1_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK23_DIB_VC_LIMIT , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK23_DIB_VC_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK23_DIB_VC_LIMIT_LEN , 5 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK23_DIB_VC_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_LIMIT , 33 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK3_DOB_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_LIMIT_LEN , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK3_DOB_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_VC0_LIMIT , 41 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK3_DOB_VC0_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_VC0_LIMIT_LEN , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK3_DOB_VC0_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_VC1_LIMIT , 49 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK3_DOB_VC1_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_23_CFG_REG_LINK3_DOB_VC1_LIMIT_LEN , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK3_DOB_VC1_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_LIMIT , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK4_DOB_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_LIMIT_LEN , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK4_DOB_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_VC0_LIMIT , 9 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK4_DOB_VC0_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_VC0_LIMIT_LEN , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK4_DOB_VC0_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_VC1_LIMIT , 17 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK4_DOB_VC1_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK4_DOB_VC1_LIMIT_LEN , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK4_DOB_VC1_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK45_DIB_VC_LIMIT , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK45_DIB_VC_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK45_DIB_VC_LIMIT_LEN , 5 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK45_DIB_VC_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_LIMIT , 33 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK5_DOB_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_LIMIT_LEN , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK5_DOB_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_VC0_LIMIT , 41 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK5_DOB_VC0_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_VC0_LIMIT_LEN , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK5_DOB_VC0_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT , 49 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK5_DOB_VC1_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_45_CFG_REG_LINK5_DOB_VC1_LIMIT_LEN , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK5_DOB_VC1_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK67_CAPP_MODE , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK67_CAPP_MODE ); REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK67_HRB_INIT_STATE , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK67_HRB_INIT_STATE ); REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_SPARE , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK6_SPARE ); REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_SPARE_LEN , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK6_SPARE_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_VC0_LIMIT , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK6_DOB_VC0_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_VC0_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK6_DOB_VC0_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_VC1_LIMIT , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK6_DOB_VC1_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK6_DOB_VC1_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK6_DOB_VC1_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK67_DIB_VC_LIMIT , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK67_DIB_VC_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK67_DIB_VC_LIMIT_LEN , 5 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK67_DIB_VC_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_DIB67_SPARE , 29 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_DIB67_SPARE ); REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_DIB67_SPARE_LEN , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_DIB67_SPARE_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_SPARE , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK7_SPARE ); REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_SPARE_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK7_SPARE_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC0_LIMIT , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK7_DOB_VC0_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC0_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK7_DOB_VC0_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC1_LIMIT , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK7_DOB_VC1_LIMIT ); REG64_FLD( PU_IOE_PB_OLINK_DATA_67_CFG_REG_LINK7_DOB_VC1_LIMIT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK7_DOB_VC1_LIMIT_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); REG64_FLD( PU_IOE_PB_OLINK_PMU0_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); REG64_FLD( PU_IOE_PB_OLINK_PMU1_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); REG64_FLD( PU_IOE_PB_OLINK_PMU2_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); REG64_FLD( PU_IOE_PB_OLINK_PMU3_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); REG64_FLD( PU_IOE_PB_OLINK_PMU4_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); REG64_FLD( PU_IOE_PB_OLINK_PMU5_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); REG64_FLD( PU_IOE_PB_OLINK_PMU6_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER0 , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0 ); REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER0_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER0_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER1 , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1 ); REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER1_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER1_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER2 , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2 ); REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER2_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER2_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER3 , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3 ); REG64_FLD( PU_IOE_PB_OLINK_PMU7_COUNTER3_LEN , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_WCLRREG, SH_FLD_COUNTER3_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0_ENABLE , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU0_ENABLE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU1_ENABLE , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU1_ENABLE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2_ENABLE , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU2_ENABLE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU3_ENABLE , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU3_ENABLE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU4_ENABLE , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU4_ENABLE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU5_ENABLE , 5 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU5_ENABLE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU6_ENABLE , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU6_ENABLE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU7_ENABLE , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU7_ENABLE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMULET_FREEZE_MODE , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMULET_FREEZE_MODE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_COMMON_FREEZE_MODE , 9 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_COMMON_FREEZE_MODE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMULET_RESET_MODE , 10 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMULET_RESET_MODE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT0_SEL , 11 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_EVENT0_SEL ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT1_SEL , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_EVENT1_SEL ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT1_SEL_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_EVENT1_SEL_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT2_SEL , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_EVENT2_SEL ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT2_SEL_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_EVENT2_SEL_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT3_SEL , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_EVENT3_SEL ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_EVENT3_SEL_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_EVENT3_SEL_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0_SIZE , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU0_SIZE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0_SIZE_LEN , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU0_SIZE_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU1_SIZE , 26 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU1_SIZE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU1_SIZE_LEN , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU1_SIZE_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2_SIZE , 28 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU2_SIZE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2_SIZE_LEN , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU2_SIZE_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU3_SIZE , 30 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU3_SIZE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU3_SIZE_LEN , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU3_SIZE_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU01_LINK_SELECT , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU01_LINK_SELECT ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU23_LINK_SELECT , 33 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU23_LINK_SELECT ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU45_LINK_SELECT , 34 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU45_LINK_SELECT ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU67_LINK_SELECT , 35 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU67_LINK_SELECT ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT0_MODE , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU0145_EVENT0_MODE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT0_MODE_LEN , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU0145_EVENT0_MODE_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT1_MODE , 38 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU0145_EVENT1_MODE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT1_MODE_LEN , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU0145_EVENT1_MODE_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT2_MODE , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU0145_EVENT2_MODE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT2_MODE_LEN , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU0145_EVENT2_MODE_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT3_MODE , 42 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU0145_EVENT3_MODE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU0145_EVENT3_MODE_LEN , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU0145_EVENT3_MODE_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT0_MODE , 44 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU2367_EVENT0_MODE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT0_MODE_LEN , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU2367_EVENT0_MODE_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT1_MODE , 46 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU2367_EVENT1_MODE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT1_MODE_LEN , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU2367_EVENT1_MODE_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT2_MODE , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU2367_EVENT2_MODE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT2_MODE_LEN , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU2367_EVENT2_MODE_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT3_MODE , 50 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU2367_EVENT3_MODE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_PMU2367_EVENT3_MODE_LEN , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PMU2367_EVENT3_MODE_LEN ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_ENABLE_GLOBAL_RUN , 52 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_ENABLE_GLOBAL_RUN ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_GLOBAL_RUN_MODE , 53 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_GLOBAL_RUN_MODE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_SPARE , 54 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_SPARE ); REG64_FLD( PU_IOE_PB_OLINK_PMU_CTL_REG_SPARE_LEN , 10 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_SPARE_LEN ); REG64_FLD( PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_SET , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_SET ); REG64_FLD( PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_SET_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_SET_LEN ); REG64_FLD( PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_STAT , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_STAT ); REG64_FLD( PU_IOE_PB_OLINK_RT_DELAY_CTL_REG_STAT_LEN , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM , SH_FLD_STAT_LEN ); REG64_FLD( PU_PB_PERFTRACE_CFG_REG_HI_ENABLE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HI_ENABLE ); REG64_FLD( PU_PB_PERFTRACE_CFG_REG_HI_FIXED_WINDOW_MODE , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HI_FIXED_WINDOW_MODE ); REG64_FLD( PU_PB_PERFTRACE_CFG_REG_HI_PRESCALE_MODE , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HI_PRESCALE_MODE ); REG64_FLD( PU_PB_PERFTRACE_CFG_REG_PTSPARE6 , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PTSPARE6 ); REG64_FLD( PU_PB_PERFTRACE_CFG_REG_LO_ENABLE , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LO_ENABLE ); REG64_FLD( PU_PB_PERFTRACE_CFG_REG_LO_FIXED_WINDOW_MODE , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LO_FIXED_WINDOW_MODE ); REG64_FLD( PU_PB_PERFTRACE_CFG_REG_LO_PRESCALE_MODE , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LO_PRESCALE_MODE ); REG64_FLD( PU_PB_PERFTRACE_CFG_REG_PTSPARE7 , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PTSPARE7 ); REG64_FLD( PU_PB_PERFTRACE_CFG_REG_HI_SELECT , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HI_SELECT ); REG64_FLD( PU_PB_PERFTRACE_CFG_REG_HI_SELECT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HI_SELECT_LEN ); REG64_FLD( PU_PB_PERFTRACE_CFG_REG_LO_SELECT , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LO_SELECT ); REG64_FLD( PU_PB_PERFTRACE_CFG_REG_LO_SELECT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LO_SELECT_LEN ); REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_HI_ENABLE , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_HI_ENABLE ); REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_HI_FIXED_WINDOW_MODE , 1 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_HI_FIXED_WINDOW_MODE ); REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_HI_PRESCALE_MODE , 2 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_HI_PRESCALE_MODE ); REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_PTSPARE6 , 3 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PTSPARE6 ); REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_LO_ENABLE , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LO_ENABLE ); REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_LO_FIXED_WINDOW_MODE , 5 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LO_FIXED_WINDOW_MODE ); REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_LO_PRESCALE_MODE , 6 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LO_PRESCALE_MODE ); REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_PTSPARE7 , 7 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_PTSPARE7 ); REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_HI_SELECT , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_HI_SELECT ); REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_HI_SELECT_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_HI_SELECT_LEN ); REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_LO_SELECT , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LO_SELECT ); REG64_FLD( PU_IOE_PB_PERFTRACE_CFG_REG_LO_SELECT_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LO_SELECT_LEN ); REG64_FLD( PU_PB_PPE_LFIR_INTERNAL_ERROR , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERNAL_ERROR ); REG64_FLD( PU_PB_PPE_LFIR_EXTERNAL_ERROR , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_EXTERNAL_ERROR ); REG64_FLD( PU_PB_PPE_LFIR_PROGRESS_ERROR , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PROGRESS_ERROR ); REG64_FLD( PU_PB_PPE_LFIR_BREAKPOINT_ERROR , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BREAKPOINT_ERROR ); REG64_FLD( PU_PB_PPE_LFIR_WATCHDOG , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WATCHDOG ); REG64_FLD( PU_PB_PPE_LFIR_HALTED , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_HALTED ); REG64_FLD( PU_PB_PPE_LFIR_DEBUG_TRIGGER , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DEBUG_TRIGGER ); REG64_FLD( PU_PB_PPE_LFIR_SRAM_UE , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SRAM_UE ); REG64_FLD( PU_PB_PPE_LFIR_SRAM_CE , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SRAM_CE ); REG64_FLD( PU_PB_PPE_LFIR_SRAM_SCRUB_ERR , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SRAM_SCRUB_ERR ); REG64_FLD( PU_PB_PPE_LFIR_BCE_ERROR , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_BCE_ERROR ); REG64_FLD( PU_PB_PPE_LFIR_SPARE11 , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE11 ); REG64_FLD( PU_PB_PPE_LFIR_FIR_PARITY_ERR_DUP , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR_DUP ); REG64_FLD( PU_PB_PPE_LFIR_FIR_PARITY_ERR , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FIR_PARITY_ERR ); REG64_FLD( PU_PB_PPE_LFIRACT0_FIR_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION0 ); REG64_FLD( PU_PB_PPE_LFIRACT0_FIR_ACTION0_LEN , 14 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION0_LEN ); REG64_FLD( PU_PB_PPE_LFIRACT1_FIR_ACTION1 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION1 ); REG64_FLD( PU_PB_PPE_LFIRACT1_FIR_ACTION1_LEN , 14 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_FIR_ACTION1_LEN ); REG64_FLD( PU_PB_PPE_LFIRMASK_FIR_MASK , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FIR_MASK ); REG64_FLD( PU_PB_PPE_LFIRMASK_FIR_MASK_LEN , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FIR_MASK_LEN ); REG64_FLD( PU_PB_PSAVE_CFG_ENABLE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_PB_PSAVE_CFG_X0_ACT , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_X0_ACT ); REG64_FLD( PU_PB_PSAVE_CFG_X1_ACT , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_X1_ACT ); REG64_FLD( PU_PB_PSAVE_CFG_X2_ACT , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_X2_ACT ); REG64_FLD( PU_PB_PSAVE_CFG_PS_SPARE1 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PS_SPARE1 ); REG64_FLD( PU_PB_PSAVE_CFG_WSIZE , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_WSIZE ); REG64_FLD( PU_PB_PSAVE_CFG_WSIZE_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_WSIZE_LEN ); REG64_FLD( PU_PB_PSAVE_CFG_LUC , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_LUC ); REG64_FLD( PU_PB_PSAVE_CFG_LUC_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_LUC_LEN ); REG64_FLD( PU_PB_PSAVE_CFG_HUC , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_HUC ); REG64_FLD( PU_PB_PSAVE_CFG_HUC_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_HUC_LEN ); REG64_FLD( PU_PB_PSAVE_CFG_LUT , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_LUT ); REG64_FLD( PU_PB_PSAVE_CFG_LUT_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_LUT_LEN ); REG64_FLD( PU_PB_PSAVE_CFG_HUT , 35 , SH_UNT , SH_ACS_SCOM , SH_FLD_HUT ); REG64_FLD( PU_PB_PSAVE_CFG_HUT_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_HUT_LEN ); REG64_FLD( PU_PB_PSAVE_MON_CFG_X0_LO , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_X0_LO ); REG64_FLD( PU_PB_PSAVE_MON_CFG_X0_LO_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_X0_LO_LEN ); REG64_FLD( PU_PB_PSAVE_MON_CFG_X0_HI , 11 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_X0_HI ); REG64_FLD( PU_PB_PSAVE_MON_CFG_X0_HI_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_X0_HI_LEN ); REG64_FLD( PU_PB_PSAVE_MON_CFG_X1_LO , 19 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_X1_LO ); REG64_FLD( PU_PB_PSAVE_MON_CFG_X1_LO_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_X1_LO_LEN ); REG64_FLD( PU_PB_PSAVE_MON_CFG_X1_HI , 27 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_X1_HI ); REG64_FLD( PU_PB_PSAVE_MON_CFG_X1_HI_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_X1_HI_LEN ); REG64_FLD( PU_PB_PSAVE_MON_CFG_X2_LO , 35 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_X2_LO ); REG64_FLD( PU_PB_PSAVE_MON_CFG_X2_LO_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_X2_LO_LEN ); REG64_FLD( PU_PB_PSAVE_MON_CFG_X2_HI , 43 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_X2_HI ); REG64_FLD( PU_PB_PSAVE_MON_CFG_X2_HI_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_X2_HI_LEN ); REG64_FLD( PU_PB_TRACE_CFG_LINK00_HI , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK00_HI ); REG64_FLD( PU_PB_TRACE_CFG_LINK00_HI_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK00_HI_LEN ); REG64_FLD( PU_PB_TRACE_CFG_LINK00_LO , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK00_LO ); REG64_FLD( PU_PB_TRACE_CFG_LINK00_LO_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK00_LO_LEN ); REG64_FLD( PU_PB_TRACE_CFG_LINK01_HI , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK01_HI ); REG64_FLD( PU_PB_TRACE_CFG_LINK01_HI_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK01_HI_LEN ); REG64_FLD( PU_PB_TRACE_CFG_LINK01_LO , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK01_LO ); REG64_FLD( PU_PB_TRACE_CFG_LINK01_LO_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK01_LO_LEN ); REG64_FLD( PU_PB_TRACE_CFG_LINK02_HI , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK02_HI ); REG64_FLD( PU_PB_TRACE_CFG_LINK02_HI_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK02_HI_LEN ); REG64_FLD( PU_PB_TRACE_CFG_LINK02_LO , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK02_LO ); REG64_FLD( PU_PB_TRACE_CFG_LINK02_LO_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK02_LO_LEN ); REG64_FLD( PU_PB_TRACE_CFG_LINK03_HI , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK03_HI ); REG64_FLD( PU_PB_TRACE_CFG_LINK03_HI_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK03_HI_LEN ); REG64_FLD( PU_PB_TRACE_CFG_LINK03_LO , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK03_LO ); REG64_FLD( PU_PB_TRACE_CFG_LINK03_LO_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK03_LO_LEN ); REG64_FLD( PU_PB_TRACE_CFG_LINK04_HI , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK04_HI ); REG64_FLD( PU_PB_TRACE_CFG_LINK04_HI_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK04_HI_LEN ); REG64_FLD( PU_PB_TRACE_CFG_LINK04_LO , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK04_LO ); REG64_FLD( PU_PB_TRACE_CFG_LINK04_LO_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK04_LO_LEN ); REG64_FLD( PU_PB_TRACE_CFG_LINK05_HI , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK05_HI ); REG64_FLD( PU_PB_TRACE_CFG_LINK05_HI_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK05_HI_LEN ); REG64_FLD( PU_PB_TRACE_CFG_LINK05_LO , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK05_LO ); REG64_FLD( PU_PB_TRACE_CFG_LINK05_LO_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LINK05_LO_LEN ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK00_HI , 0 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK00_HI ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK00_HI_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK00_HI_LEN ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK00_LO , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK00_LO ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK00_LO_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK00_LO_LEN ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK01_HI , 8 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK01_HI ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK01_HI_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK01_HI_LEN ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK01_LO , 12 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK01_LO ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK01_LO_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK01_LO_LEN ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK02_HI , 16 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK02_HI ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK02_HI_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK02_HI_LEN ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK02_LO , 20 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK02_LO ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK02_LO_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK02_LO_LEN ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK03_HI , 24 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK03_HI ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK03_HI_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK03_HI_LEN ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK03_LO , 28 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK03_LO ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK03_LO_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK03_LO_LEN ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK04_HI , 32 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK04_HI ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK04_HI_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK04_HI_LEN ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK04_LO , 36 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK04_LO ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK04_LO_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK04_LO_LEN ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK05_HI , 40 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK05_HI ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK05_HI_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK05_HI_LEN ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK05_LO , 44 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK05_LO ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK05_LO_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK05_LO_LEN ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK06_HI , 48 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK06_HI ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK06_HI_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK06_HI_LEN ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK06_LO , 52 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK06_LO ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK06_LO_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK06_LO_LEN ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK07_HI , 56 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK07_HI ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK07_HI_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK07_HI_LEN ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK07_LO , 60 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK07_LO ); REG64_FLD( PU_IOE_PB_TRACE_CFG_LINK07_LO_LEN , 4 , SH_UNT_PU_IOE , SH_ACS_SCOM_RW , SH_FLD_LINK07_LO_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_ACTION0_REG_ACTION0_LEN , 34 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_ACTION1_REG_ACTION1_LEN , 34 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_HW1_ERROR , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ00_PBH_HW1_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_HW2_ERROR , 1 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ00_PBH_HW2_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_PROTOCOL_ERROR , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ00_PBH_PROTOCOL_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ00_PBH_OVERFLOW_ERROR , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ00_PBH_OVERFLOW_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_HW1_ERROR , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ01_PBH_HW1_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_HW2_ERROR , 5 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ01_PBH_HW2_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_PROTOCOL_ERROR , 6 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ01_PBH_PROTOCOL_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ01_PBH_OVERFLOW_ERROR , 7 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ01_PBH_OVERFLOW_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_HW1_ERROR , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ02_PBH_HW1_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_HW2_ERROR , 9 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ02_PBH_HW2_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_PROTOCOL_ERROR , 10 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ02_PBH_PROTOCOL_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ02_PBH_OVERFLOW_ERROR , 11 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ02_PBH_OVERFLOW_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_HW1_ERROR , 12 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ03_PBH_HW1_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_HW2_ERROR , 13 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ03_PBH_HW2_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_PROTOCOL_ERROR , 14 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ03_PBH_PROTOCOL_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_PBIEQ03_PBH_OVERFLOW_ERROR , 15 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ03_PBH_OVERFLOW_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_16 , 16 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_16 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_17 , 17 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_17 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_18 , 18 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_18 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_19 , 19 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_19 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_20 , 20 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_20 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_21 , 21 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_21 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_22 , 22 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_22 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_23 , 23 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_23 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_24 , 24 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_24 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_25 , 25 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_25 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_26 , 26 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_26 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_27 , 27 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_27 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_28 , 28 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_28 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_29 , 29 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_29 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_30 , 30 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_30 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SPARE_31 , 31 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_31 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SCOM_ERR , 32 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_MASK_REG_SCOM_ERR_DUP , 33 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_HW1_ERROR , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ00_PBH_HW1_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_HW2_ERROR , 1 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ00_PBH_HW2_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_PROTOCOL_ERROR , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ00_PBH_PROTOCOL_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ00_PBH_OVERFLOW_ERROR , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ00_PBH_OVERFLOW_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_HW1_ERROR , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ01_PBH_HW1_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_HW2_ERROR , 5 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ01_PBH_HW2_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_PROTOCOL_ERROR , 6 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ01_PBH_PROTOCOL_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ01_PBH_OVERFLOW_ERROR , 7 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ01_PBH_OVERFLOW_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_HW1_ERROR , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ02_PBH_HW1_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_HW2_ERROR , 9 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ02_PBH_HW2_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_PROTOCOL_ERROR , 10 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ02_PBH_PROTOCOL_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ02_PBH_OVERFLOW_ERROR , 11 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ02_PBH_OVERFLOW_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_HW1_ERROR , 12 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ03_PBH_HW1_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_HW2_ERROR , 13 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ03_PBH_HW2_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_PROTOCOL_ERROR , 14 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ03_PBH_PROTOCOL_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_PBIEQ03_PBH_OVERFLOW_ERROR , 15 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_PBIEQ03_PBH_OVERFLOW_ERROR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_16 , 16 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_16 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_17 , 17 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_17 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_18 , 18 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_18 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_19 , 19 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_19 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_20 , 20 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_20 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_21 , 21 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_21 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_22 , 22 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_22 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_23 , 23 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_23 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_24 , 24 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_24 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_25 , 25 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_25 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_26 , 26 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_26 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_27 , 27 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_27 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_28 , 28 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_28 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_29 , 29 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_29 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_30 , 30 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_30 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SPARE_31 , 31 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SPARE_31 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SCOM_ERR , 32 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_FIR_REG_SCOM_ERR_DUP , 33 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERR_DUP ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X0_EN , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X1_EN , 1 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X1_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X2_EN , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X2_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X3_EN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X3_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X4_EN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X4_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X5_EN , 5 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X5_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X6_EN , 6 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X6_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX0_ADDR_DIS , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX0_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX1_ADDR_DIS , 9 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX1_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX2_ADDR_DIS , 10 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX2_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX3_ADDR_DIS , 11 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX3_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX4_ADDR_DIS , 12 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX4_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX5_ADDR_DIS , 13 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX5_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_NX6_ADDR_DIS , 14 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX6_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X0_CHIPID , 16 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_CHIPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X0_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_CHIPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X1_CHIPID , 19 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X1_CHIPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X1_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X1_CHIPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X2_CHIPID , 22 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X2_CHIPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X2_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X2_CHIPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X3_CHIPID , 25 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X3_CHIPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X3_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X3_CHIPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X4_CHIPID , 28 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X4_CHIPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X4_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X4_CHIPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X5_CHIPID , 31 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X5_CHIPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X5_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X5_CHIPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X6_CHIPID , 34 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X6_CHIPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_LINK_X6_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X6_CHIPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_AGGREGATE , 37 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_AGGREGATE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_FP_DISABLED , 48 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_FP_DISABLED ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_INDIRECT_EN , 49 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_INDIRECT_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_GATHER_ENABLE , 50 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_GATHER_ENABLE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_CMD_RATE , 56 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_CMD_RATE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_CURR_CFG_X_CMD_RATE_LEN , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_CMD_RATE_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X0_EN , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X1_EN , 1 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X1_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X2_EN , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X2_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X3_EN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X3_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X4_EN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X4_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X5_EN , 5 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X5_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X6_EN , 6 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X6_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX0_ADDR_DIS , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX0_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX1_ADDR_DIS , 9 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX1_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX2_ADDR_DIS , 10 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX2_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX3_ADDR_DIS , 11 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX3_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX4_ADDR_DIS , 12 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX4_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX5_ADDR_DIS , 13 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX5_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_NX6_ADDR_DIS , 14 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NX6_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID , 16 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_CHIPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X0_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X0_CHIPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID , 19 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X1_CHIPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X1_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X1_CHIPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID , 22 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X2_CHIPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X2_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X2_CHIPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID , 25 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X3_CHIPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X3_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X3_CHIPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID , 28 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X4_CHIPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X4_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X4_CHIPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID , 31 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X5_CHIPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X5_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X5_CHIPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID , 34 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X6_CHIPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_LINK_X6_CHIPID_LEN , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_X6_CHIPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_AGGREGATE , 37 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_AGGREGATE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_FP_DISABLED , 48 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_FP_DISABLED ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_INDIRECT_EN , 49 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_INDIRECT_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_GATHER_ENABLE , 50 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_GATHER_ENABLE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_CMD_RATE , 56 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_CMD_RATE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HPX_MODE_NEXT_CFG_X_CMD_RATE_LEN , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_X_CMD_RATE_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_MASTER_CHIP , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_MASTER_CHIP ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_TM_MASTER , 1 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_TM_MASTER ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_CHG_RATE_GP_MASTER , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_CHG_RATE_GP_MASTER ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_CHG_RATE_SP_MASTER , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_CHG_RATE_SP_MASTER ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A0_EN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A0_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A1_EN , 5 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A1_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A2_EN , 6 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A2_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A3_EN , 7 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A3_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_NA0_ADDR_DIS , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NA0_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_NA1_ADDR_DIS , 9 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NA1_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_NA2_ADDR_DIS , 10 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NA2_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_NA3_ADDR_DIS , 11 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NA3_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A0_GROUPID , 12 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A0_GROUPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A0_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A0_GROUPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A1_GROUPID , 16 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A1_GROUPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A1_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A1_GROUPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A2_GROUPID , 20 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A2_GROUPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A2_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A2_GROUPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A3_GROUPID , 24 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A3_GROUPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_LINK_A3_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A3_GROUPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_AGGREGATE , 28 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_AGGREGATE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_HOP , 29 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_HOP ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_SMP_OPTICS , 30 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_SMP_OPTICS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_CAPI , 31 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_CAPI ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT0 , 32 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT0 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT0_LEN , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT0_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT1 , 34 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT1 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT1_LEN , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT1_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT2 , 36 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT2 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT2_LEN , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT2_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT3 , 38 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT3 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_OPT3_LEN , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT3_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID , 40 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_GATHER_ENABLE , 50 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_GATHER_ENABLE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_PHYP_IS_GROUP , 52 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_PHYP_IS_GROUP ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_ADDR_BAR , 53 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_ADDR_BAR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_PUMP , 54 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_PUMP ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_DCACHE_CAPP , 55 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_DCACHE_CAPP ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_CMD_RATE , 56 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_CMD_RATE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_CURR_CFG_A_CMD_RATE_LEN , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_CMD_RATE_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_MASTER_CHIP , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_MASTER_CHIP ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_TM_MASTER , 1 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_TM_MASTER ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_CHG_RATE_GP_MASTER , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_CHG_RATE_GP_MASTER ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_CHG_RATE_SP_MASTER , 3 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_CHG_RATE_SP_MASTER ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A0_EN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A0_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A1_EN , 5 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A1_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A2_EN , 6 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A2_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A3_EN , 7 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A3_EN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_NA0_ADDR_DIS , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NA0_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_NA1_ADDR_DIS , 9 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NA1_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_NA2_ADDR_DIS , 10 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NA2_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_NA3_ADDR_DIS , 11 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_NA3_ADDR_DIS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A0_GROUPID , 12 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A0_GROUPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A0_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A0_GROUPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A1_GROUPID , 16 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A1_GROUPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A1_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A1_GROUPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A2_GROUPID , 20 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A2_GROUPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A2_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A2_GROUPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A3_GROUPID , 24 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A3_GROUPID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_LINK_A3_GROUPID_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LINK_A3_GROUPID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_AGGREGATE , 28 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_AGGREGATE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_HOP , 29 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_HOP ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_SMP_OPTICS , 30 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_SMP_OPTICS ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_CAPI , 31 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_CAPI ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT0 , 32 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT0 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT0_LEN , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT0_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT1 , 34 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT1 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT1_LEN , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT1_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT2 , 36 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT2 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT2_LEN , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT2_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT3 , 38 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT3 ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_OPT3_LEN , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_OPT3_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID , 40 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_XLATE_ADDR_TO_ID_LEN , 7 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_XLATE_ADDR_TO_ID_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_GATHER_ENABLE , 50 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_GATHER_ENABLE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_PHYP_IS_GROUP , 52 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_PHYP_IS_GROUP ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_ADDR_BAR , 53 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_ADDR_BAR ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_PUMP , 54 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_PUMP ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_DCACHE_CAPP , 55 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_DCACHE_CAPP ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_CMD_RATE , 56 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_CMD_RATE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_HP_MODE_NEXT_CFG_A_CMD_RATE_LEN , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_A_CMD_RATE_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_CHIP_IS_SYSTEM , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_CHIP_IS_SYSTEM ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_HNG_CHK_DISABLE , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_HNG_CHK_DISABLE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_DBG_CLR_MAX_HANG_STAGE , 9 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_DBG_CLR_MAX_HANG_STAGE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SW_AB_WAIT , 12 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_SW_AB_WAIT ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SW_AB_WAIT_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_SW_AB_WAIT_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SP_HW_MARK , 16 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_SP_HW_MARK ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SP_HW_MARK_LEN , 7 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_SP_HW_MARK_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_GP_HW_MARK , 23 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_GP_HW_MARK ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_GP_HW_MARK_LEN , 7 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_GP_HW_MARK_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_LCL_HW_MARK , 30 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LCL_HW_MARK ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_LCL_HW_MARK_LEN , 6 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_LCL_HW_MARK_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_CPU_RATIO_OVERRIDE , 36 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_CPU_RATIO_OVERRIDE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_CPU_RATIO_OVERRIDE_LEN , 6 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_CPU_RATIO_OVERRIDE_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_REQ_GATHER_ENABLE , 57 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_REQ_GATHER_ENABLE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SWITCH_CD_PULSE , 58 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_SWITCH_CD_PULSE ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_MODE_CFG_SWITCH_OPTION_AB , 59 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_SWITCH_OPTION_AB ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG , 0 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SLOW , 1 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_SLOW ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_COUNT , 2 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_SHIFT_COUNT ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_COUNT_LEN , 6 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_SHIFT_COUNT_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SELECT , 8 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELECT ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SELECT_LEN , 4 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_SELECT_LEN ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_DATA , 12 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_SHIFT_DATA ); REG64_FLD( PU_PB_WEST_SM0_PB_WEST_SCONFIG_LOAD_CFG_SHIFT_DATA_LEN , 52 , SH_UNT_PU_PB_WEST_SM0, SH_ACS_SCOM , SH_FLD_CFG_SHIFT_DATA_LEN ); REG64_FLD( PEC_PCS_M1_CONTROL_REG_CONTROL , 48 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CONTROL ); REG64_FLD( PEC_PCS_M1_CONTROL_REG_CONTROL_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CONTROL_LEN ); REG64_FLD( PEC_PCS_M2_CONTROL_REG_CONTROL , 48 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CONTROL ); REG64_FLD( PEC_PCS_M2_CONTROL_REG_CONTROL_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CONTROL_LEN ); REG64_FLD( PEC_PCS_M3_CONTROL_REG_CONTROL , 48 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CONTROL ); REG64_FLD( PEC_PCS_M3_CONTROL_REG_CONTROL_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CONTROL_LEN ); REG64_FLD( PEC_PCS_M4_CONTROL_REG_CONTROL , 48 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CONTROL ); REG64_FLD( PEC_PCS_M4_CONTROL_REG_CONTROL_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CONTROL_LEN ); REG64_FLD( PEC_PCS_SYS_CONTROL_REG_CONTROL , 48 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CONTROL ); REG64_FLD( PEC_PCS_SYS_CONTROL_REG_CONTROL_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CONTROL_LEN ); REG64_FLD( PEC_PECAPP_CNTL_REG_PE_CAPP_EN , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_CAPP_EN ); REG64_FLD( PEC_PECAPP_CNTL_REG_PE_CAPP_P8_MODE , 1 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_CAPP_P8_MODE ); REG64_FLD( PEC_PECAPP_CNTL_REG_PE_CAPP_NUM_MSG_ENG , 12 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_CAPP_NUM_MSG_ENG ); REG64_FLD( PEC_PECAPP_CNTL_REG_PE_CAPP_NUM_MSG_ENG_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_CAPP_NUM_MSG_ENG_LEN ); REG64_FLD( PEC_PECAPP_CNTL_REG_PE_CAPP_APC_ENG , 16 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_CAPP_APC_ENG ); REG64_FLD( PEC_PECAPP_CNTL_REG_PE_CAPP_APC_ENG_LEN , 48 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_CAPP_APC_ENG_LEN ); REG64_FLD( PEC_PECAPP_SEC_BAR_PE_CAPP , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PE_CAPP ); REG64_FLD( PEC_PECAPP_SEC_BAR_PE_CAPP_LEN , 26 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PE_CAPP_LEN ); REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_LATSTART ); REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_LATSTART_LEN ); REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_LATCANCEL ); REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_LATCANCEL_LEN ); REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_EVENT0 ); REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_EVENT0_LEN ); REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_EVENT1 ); REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_EVENT1_LEN ); REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_EVENT2 ); REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_EVENT2_LEN ); REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_EVENT3 ); REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_LATFINISH ); REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_LATFINISH_LEN ); REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU1_SM2_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_LATSTART ); REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_LATSTART_LEN ); REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_LATCANCEL ); REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_LATCANCEL_LEN ); REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_EVENT0 ); REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_EVENT0_LEN ); REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_EVENT1 ); REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_EVENT1_LEN ); REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_EVENT2 ); REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_EVENT2_LEN ); REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_EVENT3 ); REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_LATFINISH ); REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_LATFINISH_LEN ); REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU1_SM3_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_RESETMODE , 1 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESETMODE ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_FREEZEMODE , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_FREEZEMODE ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_DISABLE_PMISC , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_DISABLE_PMISC ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PMISC_MODE , 4 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_PMISC_MODE ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_CASCADE , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_CASCADE ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_CASCADE_LEN , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_CASCADE_LEN ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C0 , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_PRESCALE_C0 ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C0_LEN , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_PRESCALE_C0_LEN ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C1 , 10 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_PRESCALE_C1 ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C1_LEN , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_PRESCALE_C1_LEN ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C2 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_PRESCALE_C2 ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C2_LEN , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_PRESCALE_C2_LEN ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C3 , 14 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_PRESCALE_C3 ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_PRESCALE_C3_LEN , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_PRESCALE_C3_LEN ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_EVENT0 ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_EVENT0_LEN ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_EVENT1 ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_EVENT1_LEN ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_EVENT2 ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_EVENT2_LEN ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_EVENT3 ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_LATENCY , 48 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_LATENCY ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_LATENCY_LEN , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_LATENCY_LEN ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_RESERVED , 51 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU2_NTL1_PERF_CONFIG_RESERVED_LEN , 13 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_LATSTART ); REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_LATSTART_LEN ); REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_LATCANCEL ); REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_LATCANCEL_LEN ); REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_EVENT0 ); REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_EVENT0_LEN ); REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_EVENT1 ); REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_EVENT1_LEN ); REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_EVENT2 ); REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_EVENT2_LEN ); REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_EVENT3 ); REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_LATFINISH ); REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_LATFINISH_LEN ); REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU1_SM1_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_LATSTART ); REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_LATSTART_LEN ); REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_LATCANCEL ); REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_LATCANCEL_LEN ); REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_EVENT0 ); REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_EVENT0_LEN ); REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_EVENT1 ); REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_EVENT1_LEN ); REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_EVENT2 ); REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_EVENT2_LEN ); REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_EVENT3 ); REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_LATFINISH ); REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_LATFINISH_LEN ); REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU0_SM2_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_RESETMODE , 1 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESETMODE ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_FREEZEMODE , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_FREEZEMODE ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_DISABLE_PMISC , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_DISABLE_PMISC ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PMISC_MODE , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PMISC_MODE ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_CASCADE , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CASCADE ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_CASCADE_LEN , 3 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CASCADE_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C0 , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C0 ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C0_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C0_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C1 , 10 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C1 ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C1_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C1_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C2 , 12 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C2 ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C2_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C2_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C3 , 14 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C3 ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_PRESCALE_C3_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C3_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_EVENT0 ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_EVENT0_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_EVENT1 ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_EVENT1_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_EVENT2 ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_EVENT2_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_EVENT3 ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATSTART , 48 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_LATSTART ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATSTART_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_LATSTART_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATCANCEL , 53 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_LATCANCEL ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATCANCEL_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_LATCANCEL_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATFINISH , 58 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_LATFINISH ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_LATFINISH_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_LATFINISH_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_CONFIG_RESERVED , 63 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_LATSTART ); REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_LATSTART_LEN ); REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_LATCANCEL ); REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_LATCANCEL_LEN ); REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_EVENT0 ); REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_EVENT0_LEN ); REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_EVENT1 ); REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_EVENT1_LEN ); REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_EVENT2 ); REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_EVENT2_LEN ); REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_EVENT3 ); REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_LATFINISH ); REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_LATFINISH_LEN ); REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU0_SM1_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_LATSTART ); REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_LATSTART_LEN ); REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_LATCANCEL ); REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_LATCANCEL_LEN ); REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_EVENT0 ); REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_EVENT0_LEN ); REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_EVENT1 ); REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_EVENT1_LEN ); REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_EVENT2 ); REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_EVENT2_LEN ); REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_EVENT3 ); REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_LATFINISH ); REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_LATFINISH_LEN ); REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU0_SM0_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_RESETMODE , 1 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESETMODE ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_FREEZEMODE , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_FREEZEMODE ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_DISABLE_PMISC , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_DISABLE_PMISC ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PMISC_MODE , 4 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_PMISC_MODE ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_CASCADE , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_CASCADE ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_CASCADE_LEN , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_CASCADE_LEN ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C0 , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_PRESCALE_C0 ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C0_LEN , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_PRESCALE_C0_LEN ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C1 , 10 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_PRESCALE_C1 ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C1_LEN , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_PRESCALE_C1_LEN ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C2 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_PRESCALE_C2 ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C2_LEN , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_PRESCALE_C2_LEN ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C3 , 14 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_PRESCALE_C3 ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_PRESCALE_C3_LEN , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_PRESCALE_C3_LEN ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_EVENT0 ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_EVENT0_LEN ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_EVENT1 ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_EVENT1_LEN ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_EVENT2 ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_EVENT2_LEN ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_EVENT3 ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_LATENCY , 48 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_LATENCY ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_LATENCY_LEN , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_LATENCY_LEN ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_RESERVED , 51 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU2_NTL0_PERF_CONFIG_RESERVED_LEN , 13 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_LATSTART ); REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_LATSTART_LEN ); REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_LATCANCEL ); REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_LATCANCEL_LEN ); REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_EVENT0 ); REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_EVENT0_LEN ); REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_EVENT1 ); REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_EVENT1_LEN ); REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_EVENT2 ); REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_EVENT2_LEN ); REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_EVENT3 ); REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_LATFINISH ); REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_LATFINISH_LEN ); REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU2_SM3_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_LATSTART ); REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_LATSTART_LEN ); REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_LATCANCEL ); REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_LATCANCEL_LEN ); REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_EVENT0 ); REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_EVENT0_LEN ); REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_EVENT1 ); REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_EVENT1_LEN ); REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_EVENT2 ); REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_EVENT2_LEN ); REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_EVENT3 ); REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_LATFINISH ); REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_LATFINISH_LEN ); REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU0_SM3_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_LATSTART ); REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_LATSTART_LEN ); REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_LATCANCEL ); REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_LATCANCEL_LEN ); REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_EVENT0 ); REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_EVENT0_LEN ); REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_EVENT1 ); REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_EVENT1_LEN ); REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_EVENT2 ); REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_EVENT2_LEN ); REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_EVENT3 ); REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_LATFINISH ); REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_LATFINISH_LEN ); REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU2_SM2_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_RESETMODE , 1 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESETMODE ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_FREEZEMODE , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_FREEZEMODE ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_DISABLE_PMISC , 3 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_DISABLE_PMISC ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_PMISC_MODE , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PMISC_MODE ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_CASCADE , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CASCADE ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_CASCADE_LEN , 3 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CASCADE_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_PRESCALE_C0 , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C0 ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_PRESCALE_C0_LEN , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C0_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_PRESCALE_C1 , 10 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C1 ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_PRESCALE_C1_LEN , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C1_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_PRESCALE_C2 , 12 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C2 ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_PRESCALE_C2_LEN , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C2_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_PRESCALE_C3 , 14 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C3 ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_PRESCALE_C3_LEN , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C3_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_EVENT0 ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_EVENT0_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_EVENT1 ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_EVENT1_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_EVENT2 ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_EVENT2_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_EVENT3 ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_LATSTART , 48 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_LATSTART ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_LATSTART_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_LATSTART_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_LATCANCEL , 53 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_LATCANCEL ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_LATCANCEL_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_LATCANCEL_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_LATFINISH , 58 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_LATFINISH ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_LATFINISH_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_LATFINISH_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_CONFIG_RESERVED , 63 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_LATSTART ); REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_LATSTART_LEN ); REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_LATCANCEL ); REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_LATCANCEL_LEN ); REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_EVENT0 ); REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_EVENT0_LEN ); REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_EVENT1 ); REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_EVENT1_LEN ); REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_EVENT2 ); REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_EVENT2_LEN ); REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_EVENT3 ); REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_LATFINISH ); REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_LATFINISH_LEN ); REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU2_SM1_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_LATSTART ); REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_LATSTART_LEN ); REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_LATCANCEL ); REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_LATCANCEL_LEN ); REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_EVENT0 ); REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_EVENT0_LEN ); REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_EVENT1 ); REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_EVENT1_LEN ); REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_EVENT2 ); REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_EVENT2_LEN ); REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_EVENT3 ); REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_LATFINISH ); REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_LATFINISH_LEN ); REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU2_SM0_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_RESETMODE , 1 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESETMODE ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_FREEZEMODE , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_FREEZEMODE ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_DISABLE_PMISC , 3 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_DISABLE_PMISC ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_PMISC_MODE , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PMISC_MODE ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_CASCADE , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CASCADE ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_CASCADE_LEN , 3 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CASCADE_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_PRESCALE_C0 , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C0 ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_PRESCALE_C0_LEN , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C0_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_PRESCALE_C1 , 10 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C1 ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_PRESCALE_C1_LEN , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C1_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_PRESCALE_C2 , 12 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C2 ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_PRESCALE_C2_LEN , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C2_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_PRESCALE_C3 , 14 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C3 ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_PRESCALE_C3_LEN , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PRESCALE_C3_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_EVENT0 ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_EVENT0_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_EVENT1 ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_EVENT1_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_EVENT2 ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_EVENT2_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_EVENT3 ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_LATSTART , 48 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_LATSTART ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_LATSTART_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_LATSTART_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_LATCANCEL , 53 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_LATCANCEL ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_LATCANCEL_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_LATCANCEL_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_LATFINISH , 58 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_LATFINISH ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_LATFINISH_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_LATFINISH_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_CONFIG_RESERVED , 63 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( NV_PERF_CONFIG_ENABLE , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( NV_PERF_CONFIG_RESETMODE , 1 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESETMODE ); REG64_FLD( NV_PERF_CONFIG_FREEZEMODE , 2 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_FREEZEMODE ); REG64_FLD( NV_PERF_CONFIG_DISABLE_PMISC , 3 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_DISABLE_PMISC ); REG64_FLD( NV_PERF_CONFIG_PMISC_MODE , 4 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_PMISC_MODE ); REG64_FLD( NV_PERF_CONFIG_CASCADE , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_CASCADE ); REG64_FLD( NV_PERF_CONFIG_CASCADE_LEN , 3 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_CASCADE_LEN ); REG64_FLD( NV_PERF_CONFIG_PRESCALE_C0 , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_PRESCALE_C0 ); REG64_FLD( NV_PERF_CONFIG_PRESCALE_C0_LEN , 2 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_PRESCALE_C0_LEN ); REG64_FLD( NV_PERF_CONFIG_PRESCALE_C1 , 10 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_PRESCALE_C1 ); REG64_FLD( NV_PERF_CONFIG_PRESCALE_C1_LEN , 2 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_PRESCALE_C1_LEN ); REG64_FLD( NV_PERF_CONFIG_PRESCALE_C2 , 12 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_PRESCALE_C2 ); REG64_FLD( NV_PERF_CONFIG_PRESCALE_C2_LEN , 2 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_PRESCALE_C2_LEN ); REG64_FLD( NV_PERF_CONFIG_PRESCALE_C3 , 14 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_PRESCALE_C3 ); REG64_FLD( NV_PERF_CONFIG_PRESCALE_C3_LEN , 2 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_PRESCALE_C3_LEN ); REG64_FLD( NV_PERF_CONFIG_EVENT0 , 16 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_EVENT0 ); REG64_FLD( NV_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_EVENT0_LEN ); REG64_FLD( NV_PERF_CONFIG_EVENT1 , 24 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_EVENT1 ); REG64_FLD( NV_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_EVENT1_LEN ); REG64_FLD( NV_PERF_CONFIG_EVENT2 , 32 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_EVENT2 ); REG64_FLD( NV_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_EVENT2_LEN ); REG64_FLD( NV_PERF_CONFIG_EVENT3 , 40 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_EVENT3 ); REG64_FLD( NV_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); REG64_FLD( NV_PERF_CONFIG_LATENCY , 48 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_LATENCY ); REG64_FLD( NV_PERF_CONFIG_LATENCY_LEN , 3 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_LATENCY_LEN ); REG64_FLD( NV_PERF_CONFIG_RESERVED , 51 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( NV_PERF_CONFIG_RESERVED_LEN , 13 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_LATSTART , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_LATSTART ); REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_LATSTART_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_LATSTART_LEN ); REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_LATCANCEL , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_LATCANCEL ); REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_LATCANCEL_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_LATCANCEL_LEN ); REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT0 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_EVENT0 ); REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT0_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_EVENT0_LEN ); REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT1 , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_EVENT1 ); REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT1_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_EVENT1_LEN ); REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT2 , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_EVENT2 ); REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT2_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_EVENT2_LEN ); REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT3 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_EVENT3 ); REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_EVENT3_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_EVENT3_LEN ); REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_LATFINISH , 48 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_LATFINISH ); REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_LATFINISH_LEN , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_LATFINISH_LEN ); REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_RESERVED2 , 56 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_RESERVED2_LEN , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU1_SM0_PERF_CONFIG_ACT , 63 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_ACT ); REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT0 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT0 ); REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT0_LEN , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT0_LEN ); REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT1 , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT1 ); REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT1_LEN , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT1_LEN ); REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT2 , 32 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT2 ); REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT2_LEN , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT2_LEN ); REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT3 , 48 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT3 ); REG64_FLD( PU_NPU2_NTL0_PERF_COUNT_IDIAL_COUNT3_LEN , 16 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT3_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_COUNT_IDIAL_COUNT0 , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT0 ); REG64_FLD( PU_NPU1_CTL_PERF_COUNT_IDIAL_COUNT0_LEN , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT0_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_COUNT_IDIAL_COUNT1 , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT1 ); REG64_FLD( PU_NPU1_CTL_PERF_COUNT_IDIAL_COUNT1_LEN , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT1_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_COUNT_IDIAL_COUNT2 , 32 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT2 ); REG64_FLD( PU_NPU1_CTL_PERF_COUNT_IDIAL_COUNT2_LEN , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT2_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_COUNT_IDIAL_COUNT3 , 48 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT3 ); REG64_FLD( PU_NPU1_CTL_PERF_COUNT_IDIAL_COUNT3_LEN , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT3_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_COUNT_IDIAL_COUNT0 , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT0 ); REG64_FLD( PU_NPU0_CTL_PERF_COUNT_IDIAL_COUNT0_LEN , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT0_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_COUNT_IDIAL_COUNT1 , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT1 ); REG64_FLD( PU_NPU0_CTL_PERF_COUNT_IDIAL_COUNT1_LEN , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT1_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_COUNT_IDIAL_COUNT2 , 32 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT2 ); REG64_FLD( PU_NPU0_CTL_PERF_COUNT_IDIAL_COUNT2_LEN , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT2_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_COUNT_IDIAL_COUNT3 , 48 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT3 ); REG64_FLD( PU_NPU0_CTL_PERF_COUNT_IDIAL_COUNT3_LEN , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT3_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_COUNT_IDIAL_COUNT0 , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT0 ); REG64_FLD( PU_NPU2_CTL_PERF_COUNT_IDIAL_COUNT0_LEN , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT0_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_COUNT_IDIAL_COUNT1 , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT1 ); REG64_FLD( PU_NPU2_CTL_PERF_COUNT_IDIAL_COUNT1_LEN , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT1_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_COUNT_IDIAL_COUNT2 , 32 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT2 ); REG64_FLD( PU_NPU2_CTL_PERF_COUNT_IDIAL_COUNT2_LEN , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT2_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_COUNT_IDIAL_COUNT3 , 48 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT3 ); REG64_FLD( PU_NPU2_CTL_PERF_COUNT_IDIAL_COUNT3_LEN , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT3_LEN ); REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT0 , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_IDIAL_COUNT0 ); REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT0_LEN , 16 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_IDIAL_COUNT0_LEN ); REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT1 , 16 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_IDIAL_COUNT1 ); REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT1_LEN , 16 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_IDIAL_COUNT1_LEN ); REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT2 , 32 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_IDIAL_COUNT2 ); REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT2_LEN , 16 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_IDIAL_COUNT2_LEN ); REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT3 , 48 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_IDIAL_COUNT3 ); REG64_FLD( NV_PERF_COUNT_IDIAL_COUNT3_LEN , 16 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_IDIAL_COUNT3_LEN ); REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT0 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT0 ); REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT0_LEN , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT0_LEN ); REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT1 , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT1 ); REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT1_LEN , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT1_LEN ); REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT2 , 32 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT2 ); REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT2_LEN , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT2_LEN ); REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT3 , 48 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT3 ); REG64_FLD( PU_NPU2_NTL1_PERF_COUNT_IDIAL_COUNT3_LEN , 16 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_IDIAL_COUNT3_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_NMCMD , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_NMCMD ); REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_NMCMD_LEN , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_NMCMD_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_NMEXCMD , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_NMEXCMD ); REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_NMEXCMD_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_NMEXCMD_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_BE , 11 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_BE ); REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_CS , 12 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CS ); REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_CS_LEN , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CS_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_AECS , 18 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_AECS ); REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_AECS_LEN , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_AECS_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_PE , 34 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_CTL_PERF_MASK_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_NMCMD , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_NMCMD ); REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_NMCMD_LEN , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_NMCMD_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_NMEXCMD , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_NMEXCMD ); REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_NMEXCMD_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_NMEXCMD_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_BE , 11 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_BE ); REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_CS , 12 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CS ); REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_CS_LEN , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CS_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_AECS , 18 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_AECS ); REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_AECS_LEN , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_AECS_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_PE , 34 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_CTL_PERF_MASK_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_NMCMD , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_NMCMD ); REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_NMCMD_LEN , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_NMCMD_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_NMEXCMD , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_NMEXCMD ); REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_NMEXCMD_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_NMEXCMD_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_BE , 11 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_BE ); REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_CS , 12 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CS ); REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_CS_LEN , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CS_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_AECS , 18 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_AECS ); REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_AECS_LEN , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_AECS_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_PE , 34 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_CTL_PERF_MASK_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_NMCMD , 0 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_NMCMD ); REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_NMCMD_LEN , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_NMCMD_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_NMEXCMD , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_NMEXCMD ); REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_NMEXCMD_LEN , 5 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_NMEXCMD_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_BE , 11 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_BE ); REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_CS , 12 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CS ); REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_CS_LEN , 6 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_CS_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_AECS , 18 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_AECS ); REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_AECS_LEN , 16 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_AECS_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_PE , 34 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_CTL_PERF_MATCH_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_NMCMD , 0 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_NMCMD ); REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_NMCMD_LEN , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_NMCMD_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_NMEXCMD , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_NMEXCMD ); REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_NMEXCMD_LEN , 5 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_NMEXCMD_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_BE , 11 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_BE ); REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_CS , 12 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CS ); REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_CS_LEN , 6 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_CS_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_AECS , 18 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_AECS ); REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_AECS_LEN , 16 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_AECS_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_PE , 34 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_CTL_PERF_MATCH_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_NMCMD , 0 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_NMCMD ); REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_NMCMD_LEN , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_NMCMD_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_NMEXCMD , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_NMEXCMD ); REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_NMEXCMD_LEN , 5 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_NMEXCMD_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_BE , 11 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_BE ); REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_CS , 12 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CS ); REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_CS_LEN , 6 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_CS_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_AECS , 18 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_AECS ); REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_AECS_LEN , 16 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_AECS_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_PE , 34 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PE ); REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_PE_LEN , 4 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_PE_LEN ); REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_RESERVED1 , 38 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_CTL_PERF_MATCH_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE0_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE0_DMA_STOPPED_STATE_LEN , 37 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE_LEN ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE1_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE1_DMA_STOPPED_STATE_LEN , 37 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE_LEN ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE10_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE10_DMA_STOPPED_STATE_LEN , 37 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE_LEN ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE11_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE11_DMA_STOPPED_STATE_LEN , 37 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE_LEN ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE12_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE12_DMA_STOPPED_STATE_LEN , 37 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE_LEN ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE13_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE13_DMA_STOPPED_STATE_LEN , 37 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE_LEN ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE14_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE14_DMA_STOPPED_STATE_LEN , 37 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE_LEN ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE15_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE15_DMA_STOPPED_STATE_LEN , 37 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE_LEN ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE2_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE2_DMA_STOPPED_STATE_LEN , 37 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE_LEN ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE3_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE3_DMA_STOPPED_STATE_LEN , 37 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE_LEN ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE4_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE4_DMA_STOPPED_STATE_LEN , 37 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE_LEN ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE5_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE5_DMA_STOPPED_STATE_LEN , 37 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE_LEN ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE6_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE6_DMA_STOPPED_STATE_LEN , 37 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE_LEN ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE7_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE7_DMA_STOPPED_STATE_LEN , 37 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE_LEN ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE8_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE8_DMA_STOPPED_STATE_LEN , 37 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE_LEN ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE9_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_ADDR_PE9_DMA_STOPPED_STATE_LEN , 37 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE_LEN ); REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE0_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE1_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE10_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE11_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE12_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE13_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE14_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE15_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE2_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE3_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE4_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE5_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE6_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE7_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE8_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PU_NPU_NTL0_PESTB_DATA_PE9_DMA_STOPPED_STATE , 0 , SH_UNT_PU_NPU_NTL0, SH_ACS_SCOM , SH_FLD_DMA_STOPPED_STATE ); REG64_FLD( PEC_STACK2_PE_DFREEZE_REG_DFREEZE , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , SH_FLD_DFREEZE ); REG64_FLD( PEC_STACK2_PE_DFREEZE_REG_DFREEZE_LEN , 28 , SH_UNT_PEC_STACK2, SH_ACS_SCOM_RW , SH_FLD_DFREEZE_LEN ); REG64_FLD( PEC_STACK1_PE_DFREEZE_REG_DFREEZE , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , SH_FLD_DFREEZE ); REG64_FLD( PEC_STACK1_PE_DFREEZE_REG_DFREEZE_LEN , 28 , SH_UNT_PEC_STACK1, SH_ACS_SCOM_RW , SH_FLD_DFREEZE_LEN ); REG64_FLD( PHB_PE_DFREEZE_REG_DFREEZE , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_DFREEZE ); REG64_FLD( PHB_PE_DFREEZE_REG_DFREEZE_LEN , 28 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_DFREEZE_LEN ); REG64_FLD( PEC_STACK0_PE_DFREEZE_REG_DFREEZE , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , SH_FLD_DFREEZE ); REG64_FLD( PEC_STACK0_PE_DFREEZE_REG_DFREEZE_LEN , 28 , SH_UNT_PEC_STACK0, SH_ACS_SCOM_RW , SH_FLD_DFREEZE_LEN ); REG64_FLD( PU_PBAIB_STACK5_PFIRACTION0_REG_PFIRACTION0 , 0 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RW , SH_FLD_PFIRACTION0 ); REG64_FLD( PU_PBAIB_STACK5_PFIRACTION0_REG_PFIRACTION0_LEN , 7 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RW , SH_FLD_PFIRACTION0_LEN ); REG64_FLD( PHB_PFIRACTION0_REG_PFIRACTION0 , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_PFIRACTION0 ); REG64_FLD( PHB_PFIRACTION0_REG_PFIRACTION0_LEN , 7 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_PFIRACTION0_LEN ); REG64_FLD( PU_PBAIB_STACK2_PFIRACTION0_REG_PFIRACTION0 , 0 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RW , SH_FLD_PFIRACTION0 ); REG64_FLD( PU_PBAIB_STACK2_PFIRACTION0_REG_PFIRACTION0_LEN , 7 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RW , SH_FLD_PFIRACTION0_LEN ); REG64_FLD( PU_PBAIB_STACK1_PFIRACTION0_REG_PFIRACTION0 , 0 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RW , SH_FLD_PFIRACTION0 ); REG64_FLD( PU_PBAIB_STACK1_PFIRACTION0_REG_PFIRACTION0_LEN , 7 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RW , SH_FLD_PFIRACTION0_LEN ); REG64_FLD( PU_PBAIB_STACK5_PFIRACTION1_REG_PFIRACTION1 , 0 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RW , SH_FLD_PFIRACTION1 ); REG64_FLD( PU_PBAIB_STACK5_PFIRACTION1_REG_PFIRACTION1_LEN , 7 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RW , SH_FLD_PFIRACTION1_LEN ); REG64_FLD( PHB_PFIRACTION1_REG_PFIRACTION1 , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_PFIRACTION1 ); REG64_FLD( PHB_PFIRACTION1_REG_PFIRACTION1_LEN , 7 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_PFIRACTION1_LEN ); REG64_FLD( PU_PBAIB_STACK2_PFIRACTION1_REG_PFIRACTION1 , 0 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RW , SH_FLD_PFIRACTION1 ); REG64_FLD( PU_PBAIB_STACK2_PFIRACTION1_REG_PFIRACTION1_LEN , 7 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RW , SH_FLD_PFIRACTION1_LEN ); REG64_FLD( PU_PBAIB_STACK1_PFIRACTION1_REG_PFIRACTION1 , 0 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RW , SH_FLD_PFIRACTION1 ); REG64_FLD( PU_PBAIB_STACK1_PFIRACTION1_REG_PFIRACTION1_LEN , 7 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RW , SH_FLD_PFIRACTION1_LEN ); REG64_FLD( PU_PBAIB_STACK5_PFIRMASK_REG_PFIRMASK , 0 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM2_OR , SH_FLD_PFIRMASK ); REG64_FLD( PU_PBAIB_STACK5_PFIRMASK_REG_PFIRMASK_LEN , 7 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM2_OR , SH_FLD_PFIRMASK_LEN ); REG64_FLD( PHB_PFIRMASK_REG_PFIRMASK , 0 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_PFIRMASK ); REG64_FLD( PHB_PFIRMASK_REG_PFIRMASK_LEN , 7 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_PFIRMASK_LEN ); REG64_FLD( PU_PBAIB_STACK2_PFIRMASK_REG_PFIRMASK , 0 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PFIRMASK ); REG64_FLD( PU_PBAIB_STACK2_PFIRMASK_REG_PFIRMASK_LEN , 7 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PFIRMASK_LEN ); REG64_FLD( PU_PBAIB_STACK1_PFIRMASK_REG_PFIRMASK , 0 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PFIRMASK ); REG64_FLD( PU_PBAIB_STACK1_PFIRMASK_REG_PFIRMASK_LEN , 7 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PFIRMASK_LEN ); REG64_FLD( PU_PBAIB_STACK5_PFIR_REG_PFIRPFIR , 0 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM2_OR , SH_FLD_PFIRPFIR ); REG64_FLD( PU_PBAIB_STACK5_PFIR_REG_PFIRPFIR_LEN , 7 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM2_OR , SH_FLD_PFIRPFIR_LEN ); REG64_FLD( PHB_PFIR_REG_PFIRPFIR , 0 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_PFIRPFIR ); REG64_FLD( PHB_PFIR_REG_PFIRPFIR_LEN , 7 , SH_UNT_PHB , SH_ACS_SCOM2_OR , SH_FLD_PFIRPFIR_LEN ); REG64_FLD( PU_PBAIB_STACK2_PFIR_REG_PFIRPFIR , 0 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PFIRPFIR ); REG64_FLD( PU_PBAIB_STACK2_PFIR_REG_PFIRPFIR_LEN , 7 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM2_OR , SH_FLD_PFIRPFIR_LEN ); REG64_FLD( PU_PBAIB_STACK1_PFIR_REG_PFIRPFIR , 0 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PFIRPFIR ); REG64_FLD( PU_PBAIB_STACK1_PFIR_REG_PFIRPFIR_LEN , 7 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM2_OR , SH_FLD_PFIRPFIR_LEN ); REG64_FLD( PEC_STACK2_PHBBAR_REG_PE_PHB_BAR , 0 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , SH_FLD_PE_PHB_BAR ); REG64_FLD( PEC_STACK2_PHBBAR_REG_PE_PHB_BAR_LEN , 42 , SH_UNT_PEC_STACK2, SH_ACS_SCOM , SH_FLD_PE_PHB_BAR_LEN ); REG64_FLD( PEC_STACK1_PHBBAR_REG_PE_PHB_BAR , 0 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , SH_FLD_PE_PHB_BAR ); REG64_FLD( PEC_STACK1_PHBBAR_REG_PE_PHB_BAR_LEN , 42 , SH_UNT_PEC_STACK1, SH_ACS_SCOM , SH_FLD_PE_PHB_BAR_LEN ); REG64_FLD( PHB_PHBBAR_REG_PE_PHB_BAR , 0 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_PHB_BAR ); REG64_FLD( PHB_PHBBAR_REG_PE_PHB_BAR_LEN , 42 , SH_UNT_PHB , SH_ACS_SCOM , SH_FLD_PE_PHB_BAR_LEN ); REG64_FLD( PEC_STACK0_PHBBAR_REG_PE_PHB_BAR , 0 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , SH_FLD_PE_PHB_BAR ); REG64_FLD( PEC_STACK0_PHBBAR_REG_PE_PHB_BAR_LEN , 42 , SH_UNT_PEC_STACK0, SH_ACS_SCOM , SH_FLD_PE_PHB_BAR_LEN ); REG64_FLD( PU_PBAIB_STACK5_PHBRESET_REG_PE_ETU_RESET , 0 , SH_UNT_PU_PBAIB_STACK5, SH_ACS_SCOM_RW , SH_FLD_PE_ETU_RESET ); REG64_FLD( PHB_PHBRESET_REG_PE_ETU_RESET , 0 , SH_UNT_PHB , SH_ACS_SCOM_RW , SH_FLD_PE_ETU_RESET ); REG64_FLD( PU_PBAIB_STACK2_PHBRESET_REG_PE_ETU_RESET , 0 , SH_UNT_PU_PBAIB_STACK2, SH_ACS_SCOM_RW , SH_FLD_PE_ETU_RESET ); REG64_FLD( PU_PBAIB_STACK1_PHBRESET_REG_PE_ETU_RESET , 0 , SH_UNT_PU_PBAIB_STACK1, SH_ACS_SCOM_RW , SH_FLD_PE_ETU_RESET ); REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU0_SM0_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM0_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU0_SM0_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU0_SM0_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU1_SM2_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM2_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU1_SM2_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU1_SM2_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU2_SM3_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM3_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU2_SM3_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU2_SM3_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU1_SM3_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM3_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU1_SM3_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU1_SM3_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU0_SM3_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM3_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU0_SM3_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU0_SM3_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU1_SM1_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM1_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU1_SM1_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU1_SM1_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU2_SM2_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM2_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU2_SM2_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU2_SM2_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU2_SM1_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM1_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU2_SM1_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU2_SM1_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU0_SM2_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM2_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU0_SM2_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU0_SM2_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU2_SM0_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM0_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU2_SM0_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU2_SM0_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU0_SM1_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM1_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU0_SM1_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU0_SM1_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_ENABLE , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ENABLE ); REG64_FLD( PU_NPU1_SM0_PHY_BAR_RESERVED1 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM0_PHY_BAR_RESERVED1_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_GROUP , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP ); REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_GROUP_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_GROUP_LEN ); REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_CHIP , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP ); REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_CHIP_LEN , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_CHIP_LEN ); REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_ADDR , 10 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR ); REG64_FLD( PU_NPU1_SM0_PHY_BAR_CONFIG_ADDR_LEN , 21 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CONFIG_ADDR_LEN ); REG64_FLD( PU_NPU1_SM0_PHY_BAR_RESERVED2 , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ENABLE_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_ENABLE_0 ); REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ID_0 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_ID_0 ); REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ID_0_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_ID_0_LEN ); REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ACTIVITY_0 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_ACTIVITY_0 ); REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_B_CC_ACTIVITY_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_ACTIVITY_0_LEN ); REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ENABLE_1 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_ENABLE_1 ); REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ID_1 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_ID_1 ); REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ID_1_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_ID_1_LEN ); REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ACTIVITY_1 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_ACTIVITY_1 ); REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_C_CC_ACTIVITY_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_ACTIVITY_1_LEN ); REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ENABLE_2 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_ENABLE_2 ); REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ID_2 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_ID_2 ); REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ID_2_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_ID_2_LEN ); REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ACTIVITY_2 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_ACTIVITY_2 ); REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_D_CC_ACTIVITY_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_ACTIVITY_2_LEN ); REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ENABLE_3 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_ENABLE_3 ); REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ID_3 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_ID_3 ); REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ID_3_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_ID_3_LEN ); REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ACTIVITY_3 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_ACTIVITY_3 ); REG64_FLD( PU_PIBI2CM_ATOMIC_LOCK_REG_E_CC_ACTIVITY_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_ACTIVITY_3_LEN ); REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_B_CC_READ_ENABLE_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_READ_ENABLE_0 ); REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_B_CC_WRITE_ENABLE_0 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_WRITE_ENABLE_0 ); REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_C_CC_READ_ENABLE_1 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_READ_ENABLE_1 ); REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_C_CC_WRITE_ENABLE_1 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_WRITE_ENABLE_1 ); REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_D_CC_READ_ENABLE_2 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_READ_ENABLE_2 ); REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_D_CC_WRITE_ENABLE_2 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_WRITE_ENABLE_2 ); REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_E_CC_READ_ENABLE_3 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_READ_ENABLE_3 ); REG64_FLD( PU_PIBI2CM_PROTECT_MODE_REG_E_CC_WRITE_ENABLE_3 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CC_WRITE_ENABLE_3 ); REG64_FLD( PU_PIBMEM_ADDRESS_REGISTER_POINTER , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_POINTER ); REG64_FLD( PU_PIBMEM_ADDRESS_REGISTER_POINTER_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_POINTER_LEN ); REG64_FLD( PU_PIBMEM_ADDRESS_REGISTER_FA_POINTER , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_POINTER ); REG64_FLD( PU_PIBMEM_ADDRESS_REGISTER_FA_POINTER_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_POINTER_LEN ); REG64_FLD( PU_PIBMEM_CONTROL_REGISTER_AUTO_PRE_INCREMENT_PIB , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_AUTO_PRE_INCREMENT_PIB ); REG64_FLD( PU_PIBMEM_CONTROL_REGISTER_AUTO_POST_DECREMENT_PIB , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_AUTO_POST_DECREMENT_PIB ); REG64_FLD( PU_PIBMEM_CONTROL_REGISTER_DISABLE_ECC , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_ECC ); REG64_FLD( PU_PIBMEM_CONTROL_REGISTER_AUTO_PRE_INCREMENT_FACES , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_AUTO_PRE_INCREMENT_FACES ); REG64_FLD( PU_PIBMEM_CONTROL_REGISTER_AUTO_POST_DECREMENT_FACES , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_AUTO_POST_DECREMENT_FACES ); REG64_FLD( PU_PIBMEM_CONTROL_REGISTER_CHKSW_AR012 , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHKSW_AR012 ); REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_0_DATA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA ); REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_0_DATA_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_LEN ); REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_1_DATA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA ); REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_1_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_LEN ); REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_2_DATA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA ); REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_2_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_LEN ); REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_3_DATA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA ); REG64_FLD( PU_PIBMEM_REPAIR_REGISTER_3_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_LEN ); REG64_FLD( PU_PIBMEM_RESET_REGISTER_RESET , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESET ); REG64_FLD( PU_PIBMEM_RESET_REGISTER_RESET_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESET_LEN ); REG64_FLD( PU_PIBMEM_STATUS_REG_ADDR_INVALID_PIB , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDR_INVALID_PIB ); REG64_FLD( PU_PIBMEM_STATUS_REG_WRITE_INVALID_PIB , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_WRITE_INVALID_PIB ); REG64_FLD( PU_PIBMEM_STATUS_REG_READ_INVALID_PIB , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_READ_INVALID_PIB ); REG64_FLD( PU_PIBMEM_STATUS_REG_ECC_UNCORRECTED_ERROR_PIB , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_UNCORRECTED_ERROR_PIB ); REG64_FLD( PU_PIBMEM_STATUS_REG_ECC_CORRECTED_ERROR_PIB , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_CORRECTED_ERROR_PIB ); REG64_FLD( PU_PIBMEM_STATUS_REG_WRITE_RST_INTERRUPT_PIB , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_WRITE_RST_INTERRUPT_PIB ); REG64_FLD( PU_PIBMEM_STATUS_REG_READ_RST_INTERRUPT_PIB , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_READ_RST_INTERRUPT_PIB ); REG64_FLD( PU_PIBMEM_STATUS_REG_FSM_PRESENT_STATE , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_FSM_PRESENT_STATE ); REG64_FLD( PU_PIBMEM_STATUS_REG_FSM_PRESENT_STATE_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_FSM_PRESENT_STATE_LEN ); REG64_FLD( PU_PIBMEM_STATUS_REG_ADDR_INVALID_FACES , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDR_INVALID_FACES ); REG64_FLD( PU_PIBMEM_STATUS_REG_WRITE_INVALID_FACES , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_WRITE_INVALID_FACES ); REG64_FLD( PU_PIBMEM_STATUS_REG_READ_INVALID_FACES , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_READ_INVALID_FACES ); REG64_FLD( PU_PIBMEM_STATUS_REG_ECC_UNCORRECTED_ERROR_FACES , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_UNCORRECTED_ERROR_FACES ); REG64_FLD( PU_PIBMEM_STATUS_REG_ECC_CORRECTED_ERROR_FACES , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_CORRECTED_ERROR_FACES ); REG64_FLD( PU_PIBMEM_STATUS_REG_BAD_ARRAY_ADDRESS_FACES , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAD_ARRAY_ADDRESS_FACES ); REG64_FLD( PU_PIBMEM_STATUS_REG_WRITE_RST_INTERRUPT_FACES , 25 , SH_UNT , SH_ACS_SCOM , SH_FLD_WRITE_RST_INTERRUPT_FACES ); REG64_FLD( PU_PIBMEM_STATUS_REG_READ_RST_INTERRUPT_FACES , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_READ_RST_INTERRUPT_FACES ); REG64_FLD( PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_PIB , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDR_RESET_INTR_PIB ); REG64_FLD( PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_PIB_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDR_RESET_INTR_PIB_LEN ); REG64_FLD( PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_FACES , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDR_RESET_INTR_FACES ); REG64_FLD( PU_PIBMEM_STATUS_REG_ADDR_RESET_INTR_FACES_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDR_RESET_INTR_FACES_LEN ); REG64_FLD( PU_PIB_CMD_REG_RNW , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RNW ); REG64_FLD( PU_PIB_CMD_REG_ADR , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADR ); REG64_FLD( PU_PIB_CMD_REG_ADR_LEN , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADR_LEN ); REG64_FLD( PU_PIB_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_PIB_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_PIB_RESET_REG_RESET , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESET ); REG64_FLD( PU_PIB_RESET_REG_STATE , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_STATE ); REG64_FLD( PU_PIB_RESET_REG_ABORTED_CMD , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_ABORTED_CMD ); REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_EN , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PERFMON_EN ); REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_EN_LEN , 32 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PERFMON_EN_LEN ); REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_READ_TYPE , 32 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PERFMON_READ_TYPE ); REG64_FLD( PEC_PMONCTL_REG_PE_PERFMON_READ_TYPE_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PERFMON_READ_TYPE_LEN ); REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE0 , 36 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PMON_MUX_BYTE0 ); REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE0_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PMON_MUX_BYTE0_LEN ); REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE1 , 40 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PMON_MUX_BYTE1 ); REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE1_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PMON_MUX_BYTE1_LEN ); REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE2 , 44 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PMON_MUX_BYTE2 ); REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE2_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PMON_MUX_BYTE2_LEN ); REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE3 , 48 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PMON_MUX_BYTE3 ); REG64_FLD( PEC_PMONCTL_REG_PE_PMON_MUX_BYTE3_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_PMON_MUX_BYTE3_LEN ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_ENABLE , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER0_ENABLE ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_ENABLE , 1 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER1_ENABLE ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_ENABLE , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER2_ENABLE ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_ENABLE , 3 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER3_ENABLE ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_PRESCALER_SELECT , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_PRESCALER_SELECT ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_PRESCALER_SELECT_LEN , 3 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_PRESCALER_SELECT_LEN ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER_FREEZE_MODE , 7 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER_FREEZE_MODE ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER_RESET_MODE , 8 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER_RESET_MODE ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_EVENT_SELECT , 9 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER0_EVENT_SELECT ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_EVENT_SELECT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER0_EVENT_SELECT_LEN ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_POSEDGE_SELECT , 13 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER0_POSEDGE_SELECT ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_BIT_PAIR_SELECT , 14 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER0_BIT_PAIR_SELECT ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER0_BIT_PAIR_SELECT_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER0_BIT_PAIR_SELECT_LEN ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_EVENT_SELECT , 16 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER1_EVENT_SELECT ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_EVENT_SELECT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER1_EVENT_SELECT_LEN ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_POSEDGE_SELECT , 20 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER1_POSEDGE_SELECT ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_BIT_PAIR_SELECT , 21 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER1_BIT_PAIR_SELECT ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER1_BIT_PAIR_SELECT_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER1_BIT_PAIR_SELECT_LEN ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_EVENT_SELECT , 23 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER2_EVENT_SELECT ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_EVENT_SELECT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER2_EVENT_SELECT_LEN ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_POSEDGE_SELECT , 27 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER2_POSEDGE_SELECT ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_BIT_PAIR_SELECT , 28 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER2_BIT_PAIR_SELECT ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER2_BIT_PAIR_SELECT_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER2_BIT_PAIR_SELECT_LEN ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_EVENT_SELECT , 30 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER3_EVENT_SELECT ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_EVENT_SELECT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER3_EVENT_SELECT_LEN ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_POSEDGE_SELECT , 34 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER3_POSEDGE_SELECT ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_BIT_PAIR_SELECT , 35 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER3_BIT_PAIR_SELECT ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_COUNTER3_BIT_PAIR_SELECT_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_COUNTER3_BIT_PAIR_SELECT_LEN ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_PORT_SELECT , 37 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_PORT_SELECT ); REG64_FLD( CAPP_PMU_CNTRA_CFG_PMUA_PORT_SELECT_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUA_PORT_SELECT_LEN ); REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_0 , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_COUNTERA_0 ); REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_0_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_COUNTERA_0_LEN ); REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_1 , 16 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_COUNTERA_1 ); REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_1_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_COUNTERA_1_LEN ); REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_2 , 32 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_COUNTERA_2 ); REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_2_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_COUNTERA_2_LEN ); REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_3 , 48 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_COUNTERA_3 ); REG64_FLD( CAPP_PMU_CNTRA_REG_COUNTERA_3_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_COUNTERA_3_LEN ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_ENABLE , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER0_ENABLE ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_ENABLE , 1 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER1_ENABLE ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_ENABLE , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER2_ENABLE ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_ENABLE , 3 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER3_ENABLE ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_PRESCALER_SELECT , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_PRESCALER_SELECT ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_PRESCALER_SELECT_LEN , 3 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_PRESCALER_SELECT_LEN ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER_FREEZE_MODE , 7 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER_FREEZE_MODE ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER_RESET_MODE , 8 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER_RESET_MODE ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_EVENT_SELECT , 9 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER0_EVENT_SELECT ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_EVENT_SELECT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER0_EVENT_SELECT_LEN ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_POSEDGE_SELECT , 13 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER0_POSEDGE_SELECT ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_BIT_PAIR_SELECT , 14 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER0_BIT_PAIR_SELECT ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER0_BIT_PAIR_SELECT_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER0_BIT_PAIR_SELECT_LEN ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_EVENT_SELECT , 16 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER1_EVENT_SELECT ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_EVENT_SELECT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER1_EVENT_SELECT_LEN ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_POSEDGE_SELECT , 20 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER1_POSEDGE_SELECT ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_BIT_PAIR_SELECT , 21 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER1_BIT_PAIR_SELECT ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER1_BIT_PAIR_SELECT_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER1_BIT_PAIR_SELECT_LEN ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_EVENT_SELECT , 23 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER2_EVENT_SELECT ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_EVENT_SELECT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER2_EVENT_SELECT_LEN ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_POSEDGE_SELECT , 27 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER2_POSEDGE_SELECT ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_BIT_PAIR_SELECT , 28 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER2_BIT_PAIR_SELECT ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER2_BIT_PAIR_SELECT_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER2_BIT_PAIR_SELECT_LEN ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_EVENT_SELECT , 30 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER3_EVENT_SELECT ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_EVENT_SELECT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER3_EVENT_SELECT_LEN ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_POSEDGE_SELECT , 34 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER3_POSEDGE_SELECT ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_BIT_PAIR_SELECT , 35 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER3_BIT_PAIR_SELECT ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_COUNTER3_BIT_PAIR_SELECT_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_COUNTER3_BIT_PAIR_SELECT_LEN ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_PORT_SELECT , 37 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_PORT_SELECT ); REG64_FLD( CAPP_PMU_CNTRB_CFG_PMUB_PORT_SELECT_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMUB_PORT_SELECT_LEN ); REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_0 , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_COUNTERB_0 ); REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_0_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_COUNTERB_0_LEN ); REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_1 , 16 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_COUNTERB_1 ); REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_1_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_COUNTERB_1_LEN ); REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_2 , 32 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_COUNTERB_2 ); REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_2_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_COUNTERB_2_LEN ); REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_3 , 48 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_COUNTERB_3 ); REG64_FLD( CAPP_PMU_CNTRB_REG_COUNTERB_3_LEN , 16 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_COUNTERB_3_LEN ); REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); REG64_FLD( PU_PPE_XIDBGPRO_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_SIBRC , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC ); REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_SIBRC_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_SIBRC_LEN ); REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_WE , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_WE ); REG64_FLD( PU_PPE_XIRAMDBG_NULL_MSR_LP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_NULL_MSR_LP ); REG64_FLD( PU_PPE_XIRAMDBG_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( PU_PPE_XIRAMDBG_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMRA_SPRG0_LEN ); REG64_FLD( PU_PPE_XIRAMEDR_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMGA_IR ); REG64_FLD( PU_PPE_XIRAMEDR_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_XIRAMGA_IR_LEN ); REG64_FLD( PU_PPE_XIRAMEDR_EDR , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_EDR ); REG64_FLD( PU_PPE_XIRAMEDR_EDR_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_EDR_LEN ); REG64_FLD( PU_PPE_XIRAMGA_IR , 0 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_IR ); REG64_FLD( PU_PPE_XIRAMGA_IR_LEN , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_IR_LEN ); REG64_FLD( PU_PPE_XIRAMGA_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIRAMRA_SPRG0 ); REG64_FLD( PU_PPE_XIRAMGA_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIRAMRA_SPRG0_LEN ); REG64_FLD( PU_PPE_XIRAMRA_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIXCR_XCR ); REG64_FLD( PU_PPE_XIRAMRA_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XIXCR_XCR_LEN ); REG64_FLD( PU_PPE_XIRAMRA_SPRG0 , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_SPRG0 ); REG64_FLD( PU_PPE_XIRAMRA_SPRG0_LEN , 32 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_SPRG0_LEN ); REG64_FLD( PU_PPE_XIXCR_XCR , 1 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XCR ); REG64_FLD( PU_PPE_XIXCR_XCR_LEN , 3 , SH_UNT , SH_ACS_SCOM_WO , SH_FLD_XCR_LEN ); REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_START , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_START ); REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_START_LEN , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_START_LEN ); REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_END , 17 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_END ); REG64_FLD( PU_NPU2_NTL0_PRB_HA_PTR_END_LEN , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_END_LEN ); REG64_FLD( NV_PRB_HA_PTR_RESERVED1 , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( NV_PRB_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( NV_PRB_HA_PTR_START , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_START ); REG64_FLD( NV_PRB_HA_PTR_START_LEN , 7 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_START_LEN ); REG64_FLD( NV_PRB_HA_PTR_RESERVED2 , 12 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( NV_PRB_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( NV_PRB_HA_PTR_END , 17 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_END ); REG64_FLD( NV_PRB_HA_PTR_END_LEN , 7 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_END_LEN ); REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_START , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_START ); REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_START_LEN , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_START_LEN ); REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_END , 17 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_END ); REG64_FLD( PU_NPU2_NTL1_PRB_HA_PTR_END_LEN , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_END_LEN ); REG64_FLD( PEC_PREDV_REG_PE_RD_TIMEOUT_MASK , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_RD_TIMEOUT_MASK ); REG64_FLD( PEC_PREDV_REG_PE_RD_TIMEOUT_MASK_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_RD_TIMEOUT_MASK_LEN ); REG64_FLD( PEC_PREDV_REG_PE_WR_TIMEOUT_MASK , 8 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_WR_TIMEOUT_MASK ); REG64_FLD( PEC_PREDV_REG_PE_WR_TIMEOUT_MASK_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_WR_TIMEOUT_MASK_LEN ); REG64_FLD( PEC_PRE_COUNTER_REG_COUNTER , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COUNTER ); REG64_FLD( PEC_PRE_COUNTER_REG_COUNTER_LEN , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_COUNTER_LEN ); REG64_FLD( PU_PRGM_REGISTER_PRGM_ADDR , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRGM_ADDR ); REG64_FLD( PU_PRGM_REGISTER_PRGM_ADDR_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRGM_ADDR_LEN ); REG64_FLD( PU_PRGM_REGISTER_PRG_BIT_LOCATION , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRG_BIT_LOCATION ); REG64_FLD( PU_PRGM_REGISTER_PRG_BIT_LOCATION_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRG_BIT_LOCATION_LEN ); REG64_FLD( PU_NPU2_NTL0_PRI_CONFIG_NDL , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NDL ); REG64_FLD( PU_NPU2_NTL0_PRI_CONFIG_NDL_LEN , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_NDL_LEN ); REG64_FLD( PU_NPU2_NTL0_PRI_CONFIG_PHY , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_PHY ); REG64_FLD( PU_NPU2_NTL0_PRI_CONFIG_PHY_LEN , 2 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_PHY_LEN ); REG64_FLD( NV_PRI_CONFIG_NDL , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NDL ); REG64_FLD( NV_PRI_CONFIG_NDL_LEN , 2 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_NDL_LEN ); REG64_FLD( NV_PRI_CONFIG_PHY , 2 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_PHY ); REG64_FLD( NV_PRI_CONFIG_PHY_LEN , 2 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_PHY_LEN ); REG64_FLD( PU_NPU2_NTL1_PRI_CONFIG_NDL , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NDL ); REG64_FLD( PU_NPU2_NTL1_PRI_CONFIG_NDL_LEN , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_NDL_LEN ); REG64_FLD( PU_NPU2_NTL1_PRI_CONFIG_PHY , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_PHY ); REG64_FLD( PU_NPU2_NTL1_PRI_CONFIG_PHY_LEN , 2 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_PHY_LEN ); REG64_FLD( PU_PROBE_PROTECT_STATUS_BITS , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_BITS ); REG64_FLD( PU_PROBE_PROTECT_STATUS_BITS_LEN , 42 , SH_UNT , SH_ACS_SCOM , SH_FLD_BITS_LEN ); REG64_FLD( PEC_PROTECT_MODE_REG_READ_ENABLE , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_READ_ENABLE ); REG64_FLD( PEC_PROTECT_MODE_REG_WRITE_ENABLE , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_WRITE_ENABLE ); REG64_FLD( PU_PRV_MISC_TPSBE_TPBR_SBE_INTR , 0 , SH_UNT , SH_ACS_PPE2 , SH_FLD_TPSBE_TPBR_SBE_INTR ); REG64_FLD( PU_PRV_MISC_CHKSW_AR012 , 1 , SH_UNT , SH_ACS_PPE2 , SH_FLD_CHKSW_AR012 ); REG64_FLD( PU_PRV_MISC_RESERVED_18 , 2 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_18 ); REG64_FLD( PU_PRV_MISC_RESERVED_18_LEN , 2 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_18_LEN ); REG64_FLD( PU_PRV_MISC_SBE_EXTERNAL_FIRS , 4 , SH_UNT , SH_ACS_PPE2 , SH_FLD_SBE_EXTERNAL_FIRS ); REG64_FLD( PU_PRV_MISC_SBE_EXTERNAL_FIRS_LEN , 4 , SH_UNT , SH_ACS_PPE2 , SH_FLD_SBE_EXTERNAL_FIRS_LEN ); REG64_FLD( PU_PRV_MISC_RESERVED_17 , 8 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_17 ); REG64_FLD( PU_PRV_MISC_RESERVED_17_LEN , 4 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_17_LEN ); REG64_FLD( PU_PRV_MISC_TPSBE_TPIO_TPM_RESET , 12 , SH_UNT , SH_ACS_PPE2 , SH_FLD_TPSBE_TPIO_TPM_RESET ); REG64_FLD( PU_PRV_MISC_TPSBE_TPOCC_HALT_COMPLEX , 13 , SH_UNT , SH_ACS_PPE2 , SH_FLD_TPSBE_TPOCC_HALT_COMPLEX ); REG64_FLD( PU_PRV_MISC_RESERVED_16 , 14 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_16 ); REG64_FLD( PU_PRV_MISC_RESERVED_16_LEN , 2 , SH_UNT , SH_ACS_PPE2 , SH_FLD_RESERVED_16_LEN ); REG64_FLD( PU_PRV_MISC_I2C_TIMEOUT_VALUE , 16 , SH_UNT , SH_ACS_PPE2 , SH_FLD_I2C_TIMEOUT_VALUE ); REG64_FLD( PU_PRV_MISC_I2C_TIMEOUT_VALUE_LEN , 32 , SH_UNT , SH_ACS_PPE2 , SH_FLD_I2C_TIMEOUT_VALUE_LEN ); REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PCB_WDATA_PARITY , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_PCB_WDATA_PARITY ); REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY , 1 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_PARITY ); REG64_FLD( PU_N3_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_DL_RETURN_WDATA_PARITY ); REG64_FLD( PU_N3_PSCOM_ERROR_MASK_DL_RETURN_P0 , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_DL_RETURN_P0 ); REG64_FLD( PU_N3_PSCOM_ERROR_MASK_UL_RDATA_PARITY , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_UL_RDATA_PARITY ); REG64_FLD( PU_N3_PSCOM_ERROR_MASK_UL_P0 , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_UL_P0 ); REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_PARITY_ON_P2S_MACHINE ); REG64_FLD( PU_N3_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( PU_N3_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( PU_N3_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_PARALLEL_WRITE_NVLD ); REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD , 12 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_PARALLEL_READ_NVLD ); REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_PARALLEL_ADDR_INVALID ); REG64_FLD( PU_N3_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY , 14 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_PCB_COMMAND_PARITY ); REG64_FLD( PU_N3_PSCOM_ERROR_MASK_GENERAL_TIMEOUT , 15 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_GENERAL_TIMEOUT ); REG64_FLD( PU_N3_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( PU_N3_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PCB_WDATA_PARITY , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_PCB_WDATA_PARITY ); REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY , 1 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_PARITY ); REG64_FLD( PU_N1_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_DL_RETURN_WDATA_PARITY ); REG64_FLD( PU_N1_PSCOM_ERROR_MASK_DL_RETURN_P0 , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_DL_RETURN_P0 ); REG64_FLD( PU_N1_PSCOM_ERROR_MASK_UL_RDATA_PARITY , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_UL_RDATA_PARITY ); REG64_FLD( PU_N1_PSCOM_ERROR_MASK_UL_P0 , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_UL_P0 ); REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_PARITY_ON_P2S_MACHINE ); REG64_FLD( PU_N1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( PU_N1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( PU_N1_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_PARALLEL_WRITE_NVLD ); REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD , 12 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_PARALLEL_READ_NVLD ); REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_PARALLEL_ADDR_INVALID ); REG64_FLD( PU_N1_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY , 14 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_PCB_COMMAND_PARITY ); REG64_FLD( PU_N1_PSCOM_ERROR_MASK_GENERAL_TIMEOUT , 15 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_GENERAL_TIMEOUT ); REG64_FLD( PU_N1_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( PU_N1_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( PU_PSCOM_ERROR_MASK_PCB_WDATA_PARITY , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PCB_WDATA_PARITY ); REG64_FLD( PU_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_PARITY ); REG64_FLD( PU_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_DL_RETURN_WDATA_PARITY ); REG64_FLD( PU_PSCOM_ERROR_MASK_DL_RETURN_P0 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_DL_RETURN_P0 ); REG64_FLD( PU_PSCOM_ERROR_MASK_UL_RDATA_PARITY , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_UL_RDATA_PARITY ); REG64_FLD( PU_PSCOM_ERROR_MASK_UL_P0 , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_UL_P0 ); REG64_FLD( PU_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( PU_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_PARITY_ON_P2S_MACHINE ); REG64_FLD( PU_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( PU_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( PU_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( PU_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_PARALLEL_WRITE_NVLD ); REG64_FLD( PU_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_PARALLEL_READ_NVLD ); REG64_FLD( PU_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_PARALLEL_ADDR_INVALID ); REG64_FLD( PU_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_PCB_COMMAND_PARITY ); REG64_FLD( PU_PSCOM_ERROR_MASK_GENERAL_TIMEOUT , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_GENERAL_TIMEOUT ); REG64_FLD( PU_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( PU_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PCB_WDATA_PARITY , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_PCB_WDATA_PARITY ); REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY , 1 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_PARITY ); REG64_FLD( PU_N2_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_DL_RETURN_WDATA_PARITY ); REG64_FLD( PU_N2_PSCOM_ERROR_MASK_DL_RETURN_P0 , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_DL_RETURN_P0 ); REG64_FLD( PU_N2_PSCOM_ERROR_MASK_UL_RDATA_PARITY , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_UL_RDATA_PARITY ); REG64_FLD( PU_N2_PSCOM_ERROR_MASK_UL_P0 , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_UL_P0 ); REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_PARITY_ON_P2S_MACHINE ); REG64_FLD( PU_N2_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( PU_N2_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( PU_N2_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_PARALLEL_WRITE_NVLD ); REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD , 12 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_PARALLEL_READ_NVLD ); REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_PARALLEL_ADDR_INVALID ); REG64_FLD( PU_N2_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY , 14 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_PCB_COMMAND_PARITY ); REG64_FLD( PU_N2_PSCOM_ERROR_MASK_GENERAL_TIMEOUT , 15 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_GENERAL_TIMEOUT ); REG64_FLD( PU_N2_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( PU_N2_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( PEC_PSCOM_ERROR_MASK_PCB_WDATA_PARITY , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PCB_WDATA_PARITY ); REG64_FLD( PEC_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_PARITY ); REG64_FLD( PEC_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DL_RETURN_WDATA_PARITY ); REG64_FLD( PEC_PSCOM_ERROR_MASK_DL_RETURN_P0 , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DL_RETURN_P0 ); REG64_FLD( PEC_PSCOM_ERROR_MASK_UL_RDATA_PARITY , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UL_RDATA_PARITY ); REG64_FLD( PEC_PSCOM_ERROR_MASK_UL_P0 , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UL_P0 ); REG64_FLD( PEC_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( PEC_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PARITY_ON_P2S_MACHINE ); REG64_FLD( PEC_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( PEC_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( PEC_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( PEC_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PARALLEL_WRITE_NVLD ); REG64_FLD( PEC_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PARALLEL_READ_NVLD ); REG64_FLD( PEC_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PARALLEL_ADDR_INVALID ); REG64_FLD( PEC_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PCB_COMMAND_PARITY ); REG64_FLD( PEC_PSCOM_ERROR_MASK_GENERAL_TIMEOUT , 15 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_GENERAL_TIMEOUT ); REG64_FLD( PEC_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( PEC_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PCB_WDATA_PARITY , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_PCB_WDATA_PARITY ); REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PCB_ADDRESS_PARITY , 1 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_PCB_ADDRESS_PARITY ); REG64_FLD( PU_N0_PSCOM_ERROR_MASK_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_DL_RETURN_WDATA_PARITY ); REG64_FLD( PU_N0_PSCOM_ERROR_MASK_DL_RETURN_P0 , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_DL_RETURN_P0 ); REG64_FLD( PU_N0_PSCOM_ERROR_MASK_UL_RDATA_PARITY , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_UL_RDATA_PARITY ); REG64_FLD( PU_N0_PSCOM_ERROR_MASK_UL_P0 , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_UL_P0 ); REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_PARITY_ON_P2S_MACHINE ); REG64_FLD( PU_N0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( PU_N0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( PU_N0_PSCOM_ERROR_MASK_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_PARALLEL_WRITE_NVLD ); REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PARALLEL_READ_NVLD , 12 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_PARALLEL_READ_NVLD ); REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_PARALLEL_ADDR_INVALID ); REG64_FLD( PU_N0_PSCOM_ERROR_MASK_PCB_COMMAND_PARITY , 14 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_PCB_COMMAND_PARITY ); REG64_FLD( PU_N0_PSCOM_ERROR_MASK_GENERAL_TIMEOUT , 15 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_GENERAL_TIMEOUT ); REG64_FLD( PU_N0_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( PU_N0_PSCOM_ERROR_MASK_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( PU_N3_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR ); REG64_FLD( PU_N3_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR , 1 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR ); REG64_FLD( PU_N3_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR ); REG64_FLD( PU_N3_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR ); REG64_FLD( PU_N3_PSCOM_MODE_REG_WATCHDOG_ENABLE , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_WATCHDOG_ENABLE ); REG64_FLD( PU_N3_PSCOM_MODE_REG_SCOM_HANG_LIMIT , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_SCOM_HANG_LIMIT ); REG64_FLD( PU_N3_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_SCOM_HANG_LIMIT_LEN ); REG64_FLD( PU_N3_PSCOM_MODE_REG_FORCE_ALL_RINGS , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_FORCE_ALL_RINGS ); REG64_FLD( PU_N3_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE ); REG64_FLD( PU_N3_PSCOM_MODE_REG_RESERVED_LT , 9 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RESERVED_LT ); REG64_FLD( PU_N3_PSCOM_MODE_REG_RESERVED_LT_LEN , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RESERVED_LT_LEN ); REG64_FLD( PU_N1_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR ); REG64_FLD( PU_N1_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR , 1 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR ); REG64_FLD( PU_N1_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR ); REG64_FLD( PU_N1_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR ); REG64_FLD( PU_N1_PSCOM_MODE_REG_WATCHDOG_ENABLE , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_WATCHDOG_ENABLE ); REG64_FLD( PU_N1_PSCOM_MODE_REG_SCOM_HANG_LIMIT , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_SCOM_HANG_LIMIT ); REG64_FLD( PU_N1_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_SCOM_HANG_LIMIT_LEN ); REG64_FLD( PU_N1_PSCOM_MODE_REG_FORCE_ALL_RINGS , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_FORCE_ALL_RINGS ); REG64_FLD( PU_N1_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE ); REG64_FLD( PU_N1_PSCOM_MODE_REG_RESERVED_LT , 9 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESERVED_LT ); REG64_FLD( PU_N1_PSCOM_MODE_REG_RESERVED_LT_LEN , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESERVED_LT_LEN ); REG64_FLD( PU_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR ); REG64_FLD( PU_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR ); REG64_FLD( PU_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR ); REG64_FLD( PU_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR ); REG64_FLD( PU_PSCOM_MODE_REG_WATCHDOG_ENABLE , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_WATCHDOG_ENABLE ); REG64_FLD( PU_PSCOM_MODE_REG_SCOM_HANG_LIMIT , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_SCOM_HANG_LIMIT ); REG64_FLD( PU_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_SCOM_HANG_LIMIT_LEN ); REG64_FLD( PU_PSCOM_MODE_REG_FORCE_ALL_RINGS , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_FORCE_ALL_RINGS ); REG64_FLD( PU_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE ); REG64_FLD( PU_PSCOM_MODE_REG_RESERVED_LT , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_LT ); REG64_FLD( PU_PSCOM_MODE_REG_RESERVED_LT_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_LT_LEN ); REG64_FLD( PU_N2_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR ); REG64_FLD( PU_N2_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR , 1 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR ); REG64_FLD( PU_N2_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR ); REG64_FLD( PU_N2_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR ); REG64_FLD( PU_N2_PSCOM_MODE_REG_WATCHDOG_ENABLE , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_WATCHDOG_ENABLE ); REG64_FLD( PU_N2_PSCOM_MODE_REG_SCOM_HANG_LIMIT , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_SCOM_HANG_LIMIT ); REG64_FLD( PU_N2_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_SCOM_HANG_LIMIT_LEN ); REG64_FLD( PU_N2_PSCOM_MODE_REG_FORCE_ALL_RINGS , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_FORCE_ALL_RINGS ); REG64_FLD( PU_N2_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE ); REG64_FLD( PU_N2_PSCOM_MODE_REG_RESERVED_LT , 9 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RESERVED_LT ); REG64_FLD( PU_N2_PSCOM_MODE_REG_RESERVED_LT_LEN , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RESERVED_LT_LEN ); REG64_FLD( PEC_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR ); REG64_FLD( PEC_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR ); REG64_FLD( PEC_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR ); REG64_FLD( PEC_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR ); REG64_FLD( PEC_PSCOM_MODE_REG_WATCHDOG_ENABLE , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_WATCHDOG_ENABLE ); REG64_FLD( PEC_PSCOM_MODE_REG_SCOM_HANG_LIMIT , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SCOM_HANG_LIMIT ); REG64_FLD( PEC_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SCOM_HANG_LIMIT_LEN ); REG64_FLD( PEC_PSCOM_MODE_REG_FORCE_ALL_RINGS , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FORCE_ALL_RINGS ); REG64_FLD( PEC_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE ); REG64_FLD( PEC_PSCOM_MODE_REG_RESERVED_LT , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESERVED_LT ); REG64_FLD( PEC_PSCOM_MODE_REG_RESERVED_LT_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESERVED_LT_LEN ); REG64_FLD( PU_N0_PSCOM_MODE_REG_ABORT_ON_PCB_ADDR_PARITY_ERROR , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ABORT_ON_PCB_ADDR_PARITY_ERROR ); REG64_FLD( PU_N0_PSCOM_MODE_REG_ABORT_ON_PCB_WDATA_PARITY_ERROR , 1 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ABORT_ON_PCB_WDATA_PARITY_ERROR ); REG64_FLD( PU_N0_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_P0_ERROR , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ABORT_ON_DL_RETURN_P0_ERROR ); REG64_FLD( PU_N0_PSCOM_MODE_REG_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ABORT_ON_DL_RETURN_WDATA_PARITY_ERROR ); REG64_FLD( PU_N0_PSCOM_MODE_REG_WATCHDOG_ENABLE , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_WATCHDOG_ENABLE ); REG64_FLD( PU_N0_PSCOM_MODE_REG_SCOM_HANG_LIMIT , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_SCOM_HANG_LIMIT ); REG64_FLD( PU_N0_PSCOM_MODE_REG_SCOM_HANG_LIMIT_LEN , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_SCOM_HANG_LIMIT_LEN ); REG64_FLD( PU_N0_PSCOM_MODE_REG_FORCE_ALL_RINGS , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_FORCE_ALL_RINGS ); REG64_FLD( PU_N0_PSCOM_MODE_REG_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_FSM_SELFRESET_ON_STATEVEC_PARITYERROR_ENABLE ); REG64_FLD( PU_N0_PSCOM_MODE_REG_RESERVED_LT , 9 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RESERVED_LT ); REG64_FLD( PU_N0_PSCOM_MODE_REG_RESERVED_LT_LEN , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RESERVED_LT_LEN ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_WDATA_PARITY ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 , 3 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_DL_RETURN_P0 ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_UL_RDATA_PARITY ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 , 5 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_UL_P0 ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_GENERAL_TIMEOUT ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY , 18 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_WDATA_PARITY ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_ADDRESS_PARITY ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 , 21 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRAPPED_DL_RETURN_P0 ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY , 22 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRAPPED_UL_RDATA_PARITY ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 , 23 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRAPPED_UL_P0 ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_READ_NVLD ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_COMMAND_PARITY ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT , 33 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRAPPED_GENERAL_TIMEOUT ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( PU_N3_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_WDATA_PARITY ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 , 3 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_DL_RETURN_P0 ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_UL_RDATA_PARITY ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 , 5 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_UL_P0 ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_GENERAL_TIMEOUT ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY , 18 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_WDATA_PARITY ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_ADDRESS_PARITY ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 , 21 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRAPPED_DL_RETURN_P0 ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY , 22 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRAPPED_UL_RDATA_PARITY ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 , 23 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRAPPED_UL_P0 ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_READ_NVLD ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_COMMAND_PARITY ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT , 33 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRAPPED_GENERAL_TIMEOUT ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( PU_N1_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_WDATA_PARITY ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACCUMULATED_DL_RETURN_P0 ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACCUMULATED_UL_RDATA_PARITY ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACCUMULATED_UL_P0 ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACCUMULATED_GENERAL_TIMEOUT ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_WDATA_PARITY ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_ADDRESS_PARITY ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRAPPED_DL_RETURN_P0 ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRAPPED_UL_RDATA_PARITY ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRAPPED_UL_P0 ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_READ_NVLD ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_COMMAND_PARITY ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT , 33 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRAPPED_GENERAL_TIMEOUT ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( PU_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_WDATA_PARITY ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 , 3 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_DL_RETURN_P0 ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_UL_RDATA_PARITY ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 , 5 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_UL_P0 ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_GENERAL_TIMEOUT ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY , 18 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_WDATA_PARITY ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_ADDRESS_PARITY ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 , 21 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRAPPED_DL_RETURN_P0 ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY , 22 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRAPPED_UL_RDATA_PARITY ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 , 23 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRAPPED_UL_P0 ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_READ_NVLD ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_COMMAND_PARITY ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT , 33 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRAPPED_GENERAL_TIMEOUT ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( PU_N2_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_WDATA_PARITY ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACCUMULATED_DL_RETURN_P0 ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACCUMULATED_UL_RDATA_PARITY ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACCUMULATED_UL_P0 ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACCUMULATED_GENERAL_TIMEOUT ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY , 18 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_WDATA_PARITY ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_ADDRESS_PARITY ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 , 21 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRAPPED_DL_RETURN_P0 ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY , 22 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRAPPED_UL_RDATA_PARITY ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 , 23 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRAPPED_UL_P0 ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_READ_NVLD ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_COMMAND_PARITY ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT , 33 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRAPPED_GENERAL_TIMEOUT ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( PEC_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_WDATA_PARITY , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_WDATA_PARITY ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_ADDRESS_PARITY , 1 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_ADDRESS_PARITY ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_WDATA_PARITY , 2 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_DL_RETURN_WDATA_PARITY ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_DL_RETURN_P0 , 3 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_DL_RETURN_P0 ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_RDATA_PARITY , 4 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_UL_RDATA_PARITY ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_UL_P0 , 5 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_UL_P0 ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE , 6 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARITY_ON_P2S_MACHINE , 7 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARITY_ON_P2S_MACHINE ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 8 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 9 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 10 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_WRITE_NVLD , 11 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_WRITE_NVLD ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_READ_NVLD , 12 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_READ_NVLD ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PARALLEL_ADDR_INVALID , 13 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PARALLEL_ADDR_INVALID ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_PCB_COMMAND_PARITY , 14 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_PCB_COMMAND_PARITY ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_GENERAL_TIMEOUT , 15 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_GENERAL_TIMEOUT ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 17 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ACCUMULATED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_WDATA_PARITY , 18 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_WDATA_PARITY ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_ADDRESS_PARITY , 19 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_ADDRESS_PARITY ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_WDATA_PARITY , 20 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRAPPED_DL_RETURN_WDATA_PARITY ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_DL_RETURN_P0 , 21 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRAPPED_DL_RETURN_P0 ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_RDATA_PARITY , 22 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRAPPED_UL_RDATA_PARITY ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_UL_P0 , 23 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRAPPED_UL_P0 ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_INTERFACE_MACHINE , 24 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRAPPED_PARITY_ON_INTERFACE_MACHINE ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARITY_ON_P2S_MACHINE , 25 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRAPPED_PARITY_ON_P2S_MACHINE ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH , 26 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULCCH ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN , 27 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_DLDCH_RETURN ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH , 28 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRAPPED_TIMEOUT_WHILE_WAITING_FOR_ULDCH ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_WRITE_NVLD , 29 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_WRITE_NVLD ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_READ_NVLD , 30 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_READ_NVLD ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PARALLEL_ADDR_INVALID , 31 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRAPPED_PARALLEL_ADDR_INVALID ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_PCB_COMMAND_PARITY , 32 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRAPPED_PCB_COMMAND_PARITY ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_GENERAL_TIMEOUT , 33 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRAPPED_GENERAL_TIMEOUT ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION , 34 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_ACCESS_VIOLATION ); REG64_FLD( PU_N0_PSCOM_STATUS_ERROR_REG_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER , 35 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_TRAPPED_SATELLITE_ACKNOWLEDGE_INVALID_REGISTER ); REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_ERR_BITS , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIHB2FSP_INJ_ERR_BITS ); REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_ERR_BITS_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIHB2FSP_INJ_ERR_BITS_LEN ); REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_ONCE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIHB2FSP_INJ_ONCE ); REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2FSP_INJ_CONST , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIHB2FSP_INJ_CONST ); REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2PB_INJ_ERR_BITS , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIHB2PB_INJ_ERR_BITS ); REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2PB_INJ_ERR_BITS_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIHB2PB_INJ_ERR_BITS_LEN ); REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2PB_INJ_ONCE , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIHB2PB_INJ_ONCE ); REG64_FLD( PU_PSIHB_DEBUG_REG_PSIHB2PB_INJ_CONST , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIHB2PB_INJ_CONST ); REG64_FLD( PU_PSIHB_DEBUG_REG_TRACE_SEL , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_SEL ); REG64_FLD( PU_PSIHB_DEBUG_REG_TRACE_SEL_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRACE_SEL_LEN ); REG64_FLD( PU_PSIHB_ERROR_MASK_REG_DISABLE_1 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_1 ); REG64_FLD( PU_PSIHB_ERROR_MASK_REG_DISABLE_1_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_1_LEN ); REG64_FLD( PU_PSIHB_ERROR_MASK_REG_INTERRUPT_DISABLE , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_INTERRUPT_DISABLE ); REG64_FLD( PU_PSIHB_ERROR_MASK_REG_INTERRUPT_DISABLE_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_INTERRUPT_DISABLE_LEN ); REG64_FLD( PU_PSIHB_ERROR_MASK_REG_DISABLE_2 , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_2 ); REG64_FLD( PU_PSIHB_ERROR_MASK_REG_DISABLE_2_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_2_LEN ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_PB_ECC_ERR_CE , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PB_ECC_ERR_CE ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_PB_ECC_ERR_UE , 1 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PB_ECC_ERR_UE ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_PB_ECC_ERR_SUE , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PB_ECC_ERR_SUE ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT_FROM_ERROR , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_FROM_ERROR ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT_FROM_FSP , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_FROM_FSP ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_FSP_ECC_ERR_CE , 5 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_FSP_ECC_ERR_CE ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_FSP_ECC_ERR_UE , 6 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_FSP_ECC_ERR_UE ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_ERROR_STATE , 7 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ERROR_STATE ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INVALID_TTYPE , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INVALID_TTYPE ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INVALID_CRESP , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INVALID_CRESP ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_PB_DATA_TIME_OUT , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PB_DATA_TIME_OUT ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_PB_PARITY_ERROR , 11 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PB_PARITY_ERROR ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_FSP_ACCESS_TRUSTED_SPACE , 12 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_FSP_ACCESS_TRUSTED_SPACE ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_UNEXPECTED_PB , 13 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UNEXPECTED_PB ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT_CHANGE_WHILE_ACTIVE , 14 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_CHANGE_WHILE_ACTIVE ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT0_ADDRESS_ERROR , 15 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT0_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT1_ADDRESS_ERROR , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT1_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT2_ADDRESS_ERROR , 17 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT2_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT3_ADDRESS_ERROR , 18 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT3_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT4_ADDRESS_ERROR , 19 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT4_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_INTERRUPT5_ADDRESS_ERROR , 20 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT5_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_TCBR_TP_PSI_GLB_ERR_0 , 21 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_TCBR_TP_PSI_GLB_ERR_0 ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_TCBR_TP_PSI_GLB_ERR_1 , 22 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_TCBR_TP_PSI_GLB_ERR_1 ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_UPSTREAM , 23 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UPSTREAM ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_SPARE , 24 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SPARE ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SPARE_LEN ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_SCOM_ERROR , 27 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SCOM_ERROR ); REG64_FLD( PU_PSIHB_FIR_ACTION0_REG_PARITY_ERROR , 28 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PARITY_ERROR ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_PB_ECC_ERR_CE , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PB_ECC_ERR_CE ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_PB_ECC_ERR_UE , 1 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PB_ECC_ERR_UE ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_PB_ECC_ERR_SUE , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PB_ECC_ERR_SUE ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT_FROM_ERROR , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_FROM_ERROR ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT_FROM_FSP , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_FROM_FSP ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_FSP_ECC_ERR_CE , 5 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_FSP_ECC_ERR_CE ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_FSP_ECC_ERR_UE , 6 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_FSP_ECC_ERR_UE ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_ERROR_STATE , 7 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ERROR_STATE ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INVALID_TTYPE , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INVALID_TTYPE ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INVALID_CRESP , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INVALID_CRESP ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_PB_DATA_TIME_OUT , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PB_DATA_TIME_OUT ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_PB_PARITY_ERROR , 11 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PB_PARITY_ERROR ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_FSP_ACCESS_TRUSTED_SPACE , 12 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_FSP_ACCESS_TRUSTED_SPACE ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_UNEXPECTED_PB , 13 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UNEXPECTED_PB ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT_CHANGE_WHILE_ACTIVE , 14 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT_CHANGE_WHILE_ACTIVE ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT0_ADDRESS_ERROR , 15 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT0_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT1_ADDRESS_ERROR , 16 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT1_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT2_ADDRESS_ERROR , 17 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT2_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT3_ADDRESS_ERROR , 18 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT3_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT4_ADDRESS_ERROR , 19 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT4_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_INTERRUPT5_ADDRESS_ERROR , 20 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INTERRUPT5_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_TCBR_TP_PSI_GLB_ERR_0 , 21 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_TCBR_TP_PSI_GLB_ERR_0 ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_TCBR_TP_PSI_GLB_ERR_1 , 22 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_TCBR_TP_PSI_GLB_ERR_1 ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_UPSTREAM , 23 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_UPSTREAM ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_SPARE , 24 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SPARE ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SPARE_LEN ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_SCOM_ERROR , 27 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SCOM_ERROR ); REG64_FLD( PU_PSIHB_FIR_ACTION1_REG_PARITY_ERROR , 28 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PARITY_ERROR ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_PB_ECC_ERR_CE , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_ECC_ERR_CE ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_PB_ECC_ERR_UE , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_ECC_ERR_UE ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_PB_ECC_ERR_SUE , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_ECC_ERR_SUE ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT_FROM_ERROR , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_FROM_ERROR ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT_FROM_FSP , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_FROM_FSP ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_FSP_ECC_ERR_CE , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FSP_ECC_ERR_CE ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_FSP_ECC_ERR_UE , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FSP_ECC_ERR_UE ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_ERROR_STATE , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ERROR_STATE ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_INVALID_TTYPE , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INVALID_TTYPE ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_INVALID_CRESP , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INVALID_CRESP ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_PB_DATA_TIME_OUT , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_DATA_TIME_OUT ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_PB_PARITY_ERROR , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_PARITY_ERROR ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_FSP_ACCESS_TRUSTED_SPACE , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FSP_ACCESS_TRUSTED_SPACE ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_UNEXPECTED_PB , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UNEXPECTED_PB ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT_CHANGE_WHILE_ACTIVE , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_CHANGE_WHILE_ACTIVE ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT0_ADDRESS_ERROR , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT0_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT1_ADDRESS_ERROR , 16 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT1_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT2_ADDRESS_ERROR , 17 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT2_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT3_ADDRESS_ERROR , 18 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT3_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT4_ADDRESS_ERROR , 19 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT4_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_INTERRUPT5_ADDRESS_ERROR , 20 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT5_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_TCBR_TP_PSI_GLB_ERR_0 , 21 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_TCBR_TP_PSI_GLB_ERR_0 ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_TCBR_TP_PSI_GLB_ERR_1 , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_TCBR_TP_PSI_GLB_ERR_1 ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_UPSTREAM , 23 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UPSTREAM ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_SPARE , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_LEN ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_SCOM_ERROR , 27 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERROR ); REG64_FLD( PU_PSIHB_FIR_MASK_REG_PARITY_ERROR , 28 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERROR ); REG64_FLD( PU_PSIHB_FIR_REG_PB_ECC_ERR_CE , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_ECC_ERR_CE ); REG64_FLD( PU_PSIHB_FIR_REG_PB_ECC_ERR_UE , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_ECC_ERR_UE ); REG64_FLD( PU_PSIHB_FIR_REG_PB_ECC_ERR_SUE , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_ECC_ERR_SUE ); REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT_FROM_ERROR , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_FROM_ERROR ); REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT_FROM_FSP , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_FROM_FSP ); REG64_FLD( PU_PSIHB_FIR_REG_FSP_ECC_ERR_CE , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FSP_ECC_ERR_CE ); REG64_FLD( PU_PSIHB_FIR_REG_FSP_ECC_ERR_UE , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FSP_ECC_ERR_UE ); REG64_FLD( PU_PSIHB_FIR_REG_ERROR_STATE , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_ERROR_STATE ); REG64_FLD( PU_PSIHB_FIR_REG_INVALID_TTYPE , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INVALID_TTYPE ); REG64_FLD( PU_PSIHB_FIR_REG_INVALID_CRESP , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INVALID_CRESP ); REG64_FLD( PU_PSIHB_FIR_REG_PB_DATA_TIME_OUT , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_DATA_TIME_OUT ); REG64_FLD( PU_PSIHB_FIR_REG_PB_PARITY_ERROR , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PB_PARITY_ERROR ); REG64_FLD( PU_PSIHB_FIR_REG_FSP_ACCESS_TRUSTED_SPACE , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_FSP_ACCESS_TRUSTED_SPACE ); REG64_FLD( PU_PSIHB_FIR_REG_UNEXPECTED_PB , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UNEXPECTED_PB ); REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT_CHANGE_WHILE_ACTIVE , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT_CHANGE_WHILE_ACTIVE ); REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT0_ADDRESS_ERROR , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT0_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT1_ADDRESS_ERROR , 16 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT1_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT2_ADDRESS_ERROR , 17 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT2_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT3_ADDRESS_ERROR , 18 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT3_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT4_ADDRESS_ERROR , 19 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT4_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_REG_INTERRUPT5_ADDRESS_ERROR , 20 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INTERRUPT5_ADDRESS_ERROR ); REG64_FLD( PU_PSIHB_FIR_REG_TCBR_TP_PSI_GLB_ERR_0 , 21 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_TCBR_TP_PSI_GLB_ERR_0 ); REG64_FLD( PU_PSIHB_FIR_REG_TCBR_TP_PSI_GLB_ERR_1 , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_TCBR_TP_PSI_GLB_ERR_1 ); REG64_FLD( PU_PSIHB_FIR_REG_UPSTREAM , 23 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UPSTREAM ); REG64_FLD( PU_PSIHB_FIR_REG_SPARE , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE ); REG64_FLD( PU_PSIHB_FIR_REG_SPARE_LEN , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SPARE_LEN ); REG64_FLD( PU_PSIHB_FIR_REG_SCOM_ERROR , 27 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_ERROR ); REG64_FLD( PU_PSIHB_FIR_REG_PARITY_ERROR , 28 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERROR ); REG64_FLD( PU_PSIHB_INTERRUPT_CONTROL_ESB_OR_LSI_INTERRUPTS , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ESB_OR_LSI_INTERRUPTS ); REG64_FLD( PU_PSIHB_INTERRUPT_CONTROL_SM_RESET , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_SM_RESET ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_CMD_ENABLE , 0 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_FSP_CMD_ENABLE ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_MMIO_ENABLE , 1 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_FSP_MMIO_ENABLE ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PHBCSR_SPARE , 2 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PHBCSR_SPARE ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_INT_ENABLE , 3 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_FSP_INT_ENABLE ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_ERR_RSP_ENABLE , 4 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_FSP_ERR_RSP_ENABLE ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSI_LINK_ENABLE , 5 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PSI_LINK_ENABLE ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_RESET , 6 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_FSP_RESET ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIHBC_RESET , 7 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PSIHBC_RESET ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_MMIO_MASK , 8 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_FSP_MMIO_MASK ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_MMIO_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_FSP_MMIO_MASK_LEN ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_CEC_PSI_INTERRUPT , 16 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_CEC_PSI_INTERRUPT ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_INTERRUPT , 17 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_FSP_INTERRUPT ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_LINK_ACTIVE , 18 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_FSP_LINK_ACTIVE ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_OUTBOUND_ACTIVE , 19 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_FSP_OUTBOUND_ACTIVE ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_INBOUND_ACTIVE , 20 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_FSP_INBOUND_ACTIVE ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_LOAD_OUTSTANDING , 21 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PSIFSP_LOAD_OUTSTANDING ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_DMAR_OUTSTANDING , 22 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PSIFSP_DMAR_OUTSTANDING ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_INT_BUSY , 23 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PSIFSP_INT_BUSY ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSI_XMIT_ERROR , 32 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PSI_XMIT_ERROR ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSI_LINK_INACTIVE_TRANS , 33 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PSI_LINK_INACTIVE_TRANS ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_ACK_TIMEOUT , 34 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PSIFSP_ACK_TIMEOUT ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_MMIO_LOAD_TIMEOUT , 35 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PSIFSP_MMIO_LOAD_TIMEOUT ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_MMIO_LENGTH_ERR , 36 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PSIFSP_MMIO_LENGTH_ERR ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_MMIO_ADDR_ERR , 37 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PSIFSP_MMIO_ADDR_ERR ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_MMIO_TYPE_ERR , 38 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PSIFSP_MMIO_TYPE_ERR ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSI_UE , 39 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PSI_UE ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_PERR , 40 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PSIFSP_PERR ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSI_ALERT1 , 41 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PSI_ALERT1 ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSI_ALERT2 , 42 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PSI_ALERT2 ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_DMA_ERR , 43 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PSIFSP_DMA_ERR ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_DMA_ADDR_ERR , 48 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PSIFSP_DMA_ADDR_ERR ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_TCE_EXTENT_ERR , 49 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PSIFSP_TCE_EXTENT_ERR ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_PAGE_FAULT , 50 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PSIFSP_PAGE_FAULT ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_PSIFSP_INV_OP , 51 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_PSIFSP_INV_OP ); REG64_FLD( PU_PSIHB_STATUS_CTL_REG_FSP_INV_READ , 52 , SH_UNT , SH_ACS_SCOM2 , SH_FLD_FSP_INV_READ ); REG64_FLD( PU_PSI_BRIDGE_BAR_REG_BAR , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAR ); REG64_FLD( PU_PSI_BRIDGE_BAR_REG_BAR_LEN , 36 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAR_LEN ); REG64_FLD( PU_PSI_BRIDGE_BAR_REG_EN , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_EN ); REG64_FLD( PU_PSI_BRIDGE_FSP_BAR_REG_BAR , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAR ); REG64_FLD( PU_PSI_BRIDGE_FSP_BAR_REG_BAR_LEN , 36 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAR_LEN ); REG64_FLD( PU_PSI_FSP_MMR_REG_MMR , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_MMR ); REG64_FLD( PU_PSI_FSP_MMR_REG_MMR_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_MMR_LEN ); REG64_FLD( PU_PSI_TCE_ADDR_REG_ADDR , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDR ); REG64_FLD( PU_PSI_TCE_ADDR_REG_ADDR_LEN , 34 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDR_LEN ); REG64_FLD( PU_PSI_TCE_ADDR_REG_ENTRIES , 61 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENTRIES ); REG64_FLD( PU_PSI_TCE_ADDR_REG_ENTRIES_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENTRIES_LEN ); REG64_FLD( CAPP_PSLTTMAP0_VALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_VALID ); REG64_FLD( CAPP_PSLTTMAP0_TTYPE_MATCH , 1 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TTYPE_MATCH ); REG64_FLD( CAPP_PSLTTMAP0_TTYPE_MATCH_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TTYPE_MATCH_LEN ); REG64_FLD( CAPP_PSLTTMAP0_TSIZE_MATCH , 6 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TSIZE_MATCH ); REG64_FLD( CAPP_PSLTTMAP0_TSIZE_MATCH_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TSIZE_MATCH_LEN ); REG64_FLD( CAPP_PSLTTMAP0_TSIZE_MASK , 13 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TSIZE_MASK ); REG64_FLD( CAPP_PSLTTMAP0_TSIZE_MASK_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TSIZE_MASK_LEN ); REG64_FLD( CAPP_PSLTTMAP0_TTYPE_REPLACE , 20 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TTYPE_REPLACE ); REG64_FLD( CAPP_PSLTTMAP0_TTYPE_REPLACE_LEN , 6 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TTYPE_REPLACE_LEN ); REG64_FLD( CAPP_PSLTTMAP1_VALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_VALID ); REG64_FLD( CAPP_PSLTTMAP1_TTYPE_MATCH , 1 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TTYPE_MATCH ); REG64_FLD( CAPP_PSLTTMAP1_TTYPE_MATCH_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TTYPE_MATCH_LEN ); REG64_FLD( CAPP_PSLTTMAP1_TSIZE_MATCH , 6 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TSIZE_MATCH ); REG64_FLD( CAPP_PSLTTMAP1_TSIZE_MATCH_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TSIZE_MATCH_LEN ); REG64_FLD( CAPP_PSLTTMAP1_TSIZE_MASK , 13 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TSIZE_MASK ); REG64_FLD( CAPP_PSLTTMAP1_TSIZE_MASK_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TSIZE_MASK_LEN ); REG64_FLD( CAPP_PSLTTMAP1_TTYPE_REPLACE , 20 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TTYPE_REPLACE ); REG64_FLD( CAPP_PSLTTMAP1_TTYPE_REPLACE_LEN , 6 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TTYPE_REPLACE_LEN ); REG64_FLD( CAPP_PSLTTMAP2_VALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_VALID ); REG64_FLD( CAPP_PSLTTMAP2_TTYPE_MATCH , 1 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TTYPE_MATCH ); REG64_FLD( CAPP_PSLTTMAP2_TTYPE_MATCH_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TTYPE_MATCH_LEN ); REG64_FLD( CAPP_PSLTTMAP2_TSIZE_MATCH , 6 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TSIZE_MATCH ); REG64_FLD( CAPP_PSLTTMAP2_TSIZE_MATCH_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TSIZE_MATCH_LEN ); REG64_FLD( CAPP_PSLTTMAP2_TSIZE_MASK , 13 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TSIZE_MASK ); REG64_FLD( CAPP_PSLTTMAP2_TSIZE_MASK_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TSIZE_MASK_LEN ); REG64_FLD( CAPP_PSLTTMAP2_TTYPE_REPLACE , 20 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TTYPE_REPLACE ); REG64_FLD( CAPP_PSLTTMAP2_TTYPE_REPLACE_LEN , 6 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TTYPE_REPLACE_LEN ); REG64_FLD( CAPP_PSLTTMAP3_VALID , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_VALID ); REG64_FLD( CAPP_PSLTTMAP3_TTYPE_MATCH , 1 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TTYPE_MATCH ); REG64_FLD( CAPP_PSLTTMAP3_TTYPE_MATCH_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TTYPE_MATCH_LEN ); REG64_FLD( CAPP_PSLTTMAP3_TSIZE_MATCH , 6 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TSIZE_MATCH ); REG64_FLD( CAPP_PSLTTMAP3_TSIZE_MATCH_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TSIZE_MATCH_LEN ); REG64_FLD( CAPP_PSLTTMAP3_TSIZE_MASK , 13 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TSIZE_MASK ); REG64_FLD( CAPP_PSLTTMAP3_TSIZE_MASK_LEN , 7 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TSIZE_MASK_LEN ); REG64_FLD( CAPP_PSLTTMAP3_TTYPE_REPLACE , 20 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TTYPE_REPLACE ); REG64_FLD( CAPP_PSLTTMAP3_TTYPE_REPLACE_LEN , 6 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TTYPE_REPLACE_LEN ); REG64_FLD( PU_PSU_HOST_DOORBELL_REG_0 , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_0 ); REG64_FLD( PU_PSU_HOST_DOORBELL_REG_1 , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_1 ); REG64_FLD( PU_PSU_HOST_DOORBELL_REG_2 , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_2 ); REG64_FLD( PU_PSU_HOST_DOORBELL_REG_3 , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_3 ); REG64_FLD( PU_PSU_HOST_DOORBELL_REG_4 , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_4 ); REG64_FLD( PU_PSU_HOST_DOORBELL_REG_5 , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_5 ); REG64_FLD( PU_PSU_HOST_DOORBELL_REG_6 , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_6 ); REG64_FLD( PU_PSU_HOST_DOORBELL_REG_7 , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_7 ); REG64_FLD( PU_PSU_HOST_DOORBELL_REG_8 , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_8 ); REG64_FLD( PU_PSU_HOST_DOORBELL_REG_9 , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_9 ); REG64_FLD( PU_PSU_HOST_DOORBELL_REG_10 , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_10 ); REG64_FLD( PU_PSU_HOST_DOORBELL_REG_11 , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_11 ); REG64_FLD( PU_PSU_HOST_DOORBELL_REG_12 , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_12 ); REG64_FLD( PU_PSU_HOST_DOORBELL_REG_13 , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_13 ); REG64_FLD( PU_PSU_HOST_DOORBELL_REG_14 , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_14 ); REG64_FLD( PU_PSU_HOST_DOORBELL_REG_15 , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_15 ); REG64_FLD( PU_PSU_HOST_SBE_MBOX0_REG_MBOX0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MBOX0 ); REG64_FLD( PU_PSU_HOST_SBE_MBOX0_REG_MBOX0_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_MBOX0_LEN ); REG64_FLD( PU_PSU_HOST_SBE_MBOX1_REG_MBOX1 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MBOX1 ); REG64_FLD( PU_PSU_HOST_SBE_MBOX1_REG_MBOX1_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_MBOX1_LEN ); REG64_FLD( PU_PSU_HOST_SBE_MBOX2_REG_MBOX2 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MBOX2 ); REG64_FLD( PU_PSU_HOST_SBE_MBOX2_REG_MBOX2_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_MBOX2_LEN ); REG64_FLD( PU_PSU_HOST_SBE_MBOX3_REG_MBOX3 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MBOX3 ); REG64_FLD( PU_PSU_HOST_SBE_MBOX3_REG_MBOX3_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_MBOX3_LEN ); REG64_FLD( PU_PSU_HOST_SBE_MBOX4_REG_MBOX4 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MBOX4 ); REG64_FLD( PU_PSU_HOST_SBE_MBOX4_REG_MBOX4_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_MBOX4_LEN ); REG64_FLD( PU_PSU_HOST_SBE_MBOX5_REG_MBOX5 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MBOX5 ); REG64_FLD( PU_PSU_HOST_SBE_MBOX5_REG_MBOX5_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_MBOX5_LEN ); REG64_FLD( PU_PSU_HOST_SBE_MBOX6_REG_MBOX6 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MBOX6 ); REG64_FLD( PU_PSU_HOST_SBE_MBOX6_REG_MBOX6_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_MBOX6_LEN ); REG64_FLD( PU_PSU_HOST_SBE_MBOX7_REG_MBOX7 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MBOX7 ); REG64_FLD( PU_PSU_HOST_SBE_MBOX7_REG_MBOX7_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_MBOX7_LEN ); REG64_FLD( PU_PSU_INSTR0_ACTCYCLECNT_REG_ACTCYCLECNT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACTCYCLECNT ); REG64_FLD( PU_PSU_INSTR0_ACTCYCLECNT_REG_ACTCYCLECNT_LEN , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACTCYCLECNT_LEN ); REG64_FLD( PU_PSU_INSTR0_CYCLECNT_REG_CYCLECNT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CYCLECNT ); REG64_FLD( PU_PSU_INSTR0_CYCLECNT_REG_CYCLECNT_LEN , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_CYCLECNT_LEN ); REG64_FLD( PU_PSU_INSTR0_EVENTCNT_REG_EVENTCNT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_EVENTCNT ); REG64_FLD( PU_PSU_INSTR0_EVENTCNT_REG_EVENTCNT_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_EVENTCNT_LEN ); REG64_FLD( PU_PSU_INSTR0_FILTER_REG_CONTENT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CONTENT ); REG64_FLD( PU_PSU_INSTR0_FILTER_REG_CONTENT_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_CONTENT_LEN ); REG64_FLD( PU_PSU_INSTR0_FILTER_REG_MASK , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASK ); REG64_FLD( PU_PSU_INSTR0_FILTER_REG_MASK_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASK_LEN ); REG64_FLD( PU_PSU_INSTR0_MAXCYCLECNT_REG_MAXCYCLECNT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAXCYCLECNT ); REG64_FLD( PU_PSU_INSTR0_MAXCYCLECNT_REG_MAXCYCLECNT_LEN , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAXCYCLECNT_LEN ); REG64_FLD( PU_PSU_INSTR0_MINCYCLECNT_REG_MINCYCLECNT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MINCYCLECNT ); REG64_FLD( PU_PSU_INSTR0_MINCYCLECNT_REG_MINCYCLECNT_LEN , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_MINCYCLECNT_LEN ); REG64_FLD( PU_PSU_INSTR0_STOP_TIMER_REG_TIMER , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_TIMER ); REG64_FLD( PU_PSU_INSTR0_STOP_TIMER_REG_TIMER_LEN , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_TIMER_LEN ); REG64_FLD( PU_PSU_INSTR1_ACTCYCLECNT_REG_ACTCYCLECNT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACTCYCLECNT ); REG64_FLD( PU_PSU_INSTR1_ACTCYCLECNT_REG_ACTCYCLECNT_LEN , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACTCYCLECNT_LEN ); REG64_FLD( PU_PSU_INSTR1_CYCLECNT_REG_CYCLECNT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CYCLECNT ); REG64_FLD( PU_PSU_INSTR1_CYCLECNT_REG_CYCLECNT_LEN , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_CYCLECNT_LEN ); REG64_FLD( PU_PSU_INSTR1_EVENTCNT_REG_EVENTCNT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_EVENTCNT ); REG64_FLD( PU_PSU_INSTR1_EVENTCNT_REG_EVENTCNT_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_EVENTCNT_LEN ); REG64_FLD( PU_PSU_INSTR1_FILTER_REG_CONTENT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CONTENT ); REG64_FLD( PU_PSU_INSTR1_FILTER_REG_CONTENT_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_CONTENT_LEN ); REG64_FLD( PU_PSU_INSTR1_FILTER_REG_MASK , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASK ); REG64_FLD( PU_PSU_INSTR1_FILTER_REG_MASK_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASK_LEN ); REG64_FLD( PU_PSU_INSTR1_MAXCYCLECNT_REG_MAXCYCLECNT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAXCYCLECNT ); REG64_FLD( PU_PSU_INSTR1_MAXCYCLECNT_REG_MAXCYCLECNT_LEN , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAXCYCLECNT_LEN ); REG64_FLD( PU_PSU_INSTR1_MINCYCLECNT_REG_MINCYCLECNT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MINCYCLECNT ); REG64_FLD( PU_PSU_INSTR1_MINCYCLECNT_REG_MINCYCLECNT_LEN , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_MINCYCLECNT_LEN ); REG64_FLD( PU_PSU_INSTR1_STOP_TIMER_REG_TIMER , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_TIMER ); REG64_FLD( PU_PSU_INSTR1_STOP_TIMER_REG_TIMER_LEN , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_TIMER_LEN ); REG64_FLD( PU_PSU_INSTR2_ACTCYCLECNT_REG_ACTCYCLECNT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACTCYCLECNT ); REG64_FLD( PU_PSU_INSTR2_ACTCYCLECNT_REG_ACTCYCLECNT_LEN , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_ACTCYCLECNT_LEN ); REG64_FLD( PU_PSU_INSTR2_CYCLECNT_REG_CYCLECNT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CYCLECNT ); REG64_FLD( PU_PSU_INSTR2_CYCLECNT_REG_CYCLECNT_LEN , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_CYCLECNT_LEN ); REG64_FLD( PU_PSU_INSTR2_EVENTCNT_REG_EVENTCNT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_EVENTCNT ); REG64_FLD( PU_PSU_INSTR2_EVENTCNT_REG_EVENTCNT_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_EVENTCNT_LEN ); REG64_FLD( PU_PSU_INSTR2_FILTER_REG_CONTENT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CONTENT ); REG64_FLD( PU_PSU_INSTR2_FILTER_REG_CONTENT_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_CONTENT_LEN ); REG64_FLD( PU_PSU_INSTR2_FILTER_REG_MASK , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASK ); REG64_FLD( PU_PSU_INSTR2_FILTER_REG_MASK_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASK_LEN ); REG64_FLD( PU_PSU_INSTR2_MAXCYCLECNT_REG_MAXCYCLECNT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAXCYCLECNT ); REG64_FLD( PU_PSU_INSTR2_MAXCYCLECNT_REG_MAXCYCLECNT_LEN , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAXCYCLECNT_LEN ); REG64_FLD( PU_PSU_INSTR2_MINCYCLECNT_REG_MINCYCLECNT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MINCYCLECNT ); REG64_FLD( PU_PSU_INSTR2_MINCYCLECNT_REG_MINCYCLECNT_LEN , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_MINCYCLECNT_LEN ); REG64_FLD( PU_PSU_INSTR2_STOP_TIMER_REG_TIMER , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_TIMER ); REG64_FLD( PU_PSU_INSTR2_STOP_TIMER_REG_TIMER_LEN , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_TIMER_LEN ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR0_MODE ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_MODE_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR0_MODE_LEN ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOP_TIMER_EN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR0_STOP_TIMER_EN ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOP_ON_ERROR_GT , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR0_STOP_ON_ERROR_GT ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOP_ON_ERROR_GT_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR0_STOP_ON_ERROR_GT_LEN ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_START , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR0_START ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOP , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR0_STOP ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_MODE , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR1_MODE ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_MODE_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR1_MODE_LEN ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOP_TIMER_EN , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR1_STOP_TIMER_EN ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOP_ON_ERROR_GT , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR1_STOP_ON_ERROR_GT ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOP_ON_ERROR_GT_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR1_STOP_ON_ERROR_GT_LEN ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_START , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR1_START ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOP , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR1_STOP ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_MODE , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR2_MODE ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_MODE_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR2_MODE_LEN ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOP_TIMER_EN , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR2_STOP_TIMER_EN ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOP_ON_ERROR_GT , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR2_STOP_ON_ERROR_GT ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOP_ON_ERROR_GT_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR2_STOP_ON_ERROR_GT_LEN ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_START , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR2_START ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOP , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR2_STOP ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_CYCLECNT_RUNNING , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR0_CYCLECNT_RUNNING ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_BUSYCNT_RUNNING , 25 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR0_BUSYCNT_RUNNING ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_CYCLECNT_RUNNING , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR1_CYCLECNT_RUNNING ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_BUSYCNT_RUNNING , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR1_BUSYCNT_RUNNING ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_CYCLECNT_RUNNING , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR2_CYCLECNT_RUNNING ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_BUSYCNT_RUNNING , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR2_BUSYCNT_RUNNING ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_STOPPED_ON_ERROR , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR0_STOPPED_ON_ERROR ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_STOPPED_ON_ERROR , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR1_STOPPED_ON_ERROR ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_STOPPED_ON_ERROR , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR2_STOPPED_ON_ERROR ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR0_RESET , 33 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR0_RESET ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR1_RESET , 34 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR1_RESET ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INSTR2_RESET , 35 , SH_UNT , SH_ACS_SCOM , SH_FLD_INSTR2_RESET ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_INCLUDE_TRAFFIC , 36 , SH_UNT , SH_ACS_SCOM , SH_FLD_INCLUDE_TRAFFIC ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_RESERVED , 37 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_PSU_INSTR_CTRL_STATUS_REG_RESERVED_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_PSU_PIBHIST_2NDLAST_ADDR_TRACE_REG_HIST , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST ); REG64_FLD( PU_PSU_PIBHIST_2NDLAST_ADDR_TRACE_REG_HIST_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST_LEN ); REG64_FLD( PU_PSU_PIBHIST_2NDLAST_REQDATA_TRACE_REG_HIST , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST ); REG64_FLD( PU_PSU_PIBHIST_2NDLAST_REQDATA_TRACE_REG_HIST_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST_LEN ); REG64_FLD( PU_PSU_PIBHIST_2NDLAST_RSPDATA_TRACE_REG_HIST , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST ); REG64_FLD( PU_PSU_PIBHIST_2NDLAST_RSPDATA_TRACE_REG_HIST_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST_LEN ); REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_MANUAL_MODE_EN , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST_MANUAL_MODE_EN ); REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_START_NOT_STOP , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST_START_NOT_STOP ); REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_FREEZE_HISTORY , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST_FREEZE_HISTORY ); REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_RESET_HISTORY , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST_RESET_HISTORY ); REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_TRACE_TRAFFIC , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST_TRACE_TRAFFIC ); REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_STOP_ON_ERROR_GT , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST_STOP_ON_ERROR_GT ); REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_STOP_ON_ERROR_GT_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST_STOP_ON_ERROR_GT_LEN ); REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_RESERVED , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST_RESERVED ); REG64_FLD( PU_PSU_PIBHIST_CTRL_STATUS_REG_HIST_RESERVED_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST_RESERVED_LEN ); REG64_FLD( PU_PSU_PIBHIST_FILTER_REG_HIST_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST_ADDRESS ); REG64_FLD( PU_PSU_PIBHIST_FILTER_REG_HIST_ADDRESS_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST_ADDRESS_LEN ); REG64_FLD( PU_PSU_PIBHIST_FILTER_REG_HIST_MASK , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST_MASK ); REG64_FLD( PU_PSU_PIBHIST_FILTER_REG_HIST_MASK_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST_MASK_LEN ); REG64_FLD( PU_PSU_PIBHIST_LAST_ADDR_TRACE_REG_HIST , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST ); REG64_FLD( PU_PSU_PIBHIST_LAST_ADDR_TRACE_REG_HIST_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST_LEN ); REG64_FLD( PU_PSU_PIBHIST_LAST_REQDATA_TRACE_REG_HIST , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST ); REG64_FLD( PU_PSU_PIBHIST_LAST_REQDATA_TRACE_REG_HIST_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST_LEN ); REG64_FLD( PU_PSU_PIBHIST_LAST_RSPDATA_TRACE_REG_HIST , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST ); REG64_FLD( PU_PSU_PIBHIST_LAST_RSPDATA_TRACE_REG_HIST_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_HIST_LEN ); REG64_FLD( PU_PSU_SBE_DOORBELL_REG_0 , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_0 ); REG64_FLD( PU_PSU_SBE_DOORBELL_REG_1 , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_1 ); REG64_FLD( PU_PSU_SBE_DOORBELL_REG_2 , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_2 ); REG64_FLD( PU_PSU_SBE_DOORBELL_REG_3 , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_3 ); REG64_FLD( PU_PSU_SBE_DOORBELL_REG_4 , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_4 ); REG64_FLD( PU_PSU_SBE_DOORBELL_REG_5 , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_5 ); REG64_FLD( PU_PSU_SBE_DOORBELL_REG_6 , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_6 ); REG64_FLD( PU_PSU_SBE_DOORBELL_REG_7 , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_7 ); REG64_FLD( PU_PSU_SBE_DOORBELL_REG_8 , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_8 ); REG64_FLD( PU_PSU_SBE_DOORBELL_REG_9 , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_9 ); REG64_FLD( PU_PSU_SBE_DOORBELL_REG_10 , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_10 ); REG64_FLD( PU_PSU_SBE_DOORBELL_REG_11 , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_11 ); REG64_FLD( PU_PSU_SBE_DOORBELL_REG_12 , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_12 ); REG64_FLD( PU_PSU_SBE_DOORBELL_REG_13 , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_13 ); REG64_FLD( PU_PSU_SBE_DOORBELL_REG_14 , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_14 ); REG64_FLD( PU_PSU_SBE_DOORBELL_REG_15 , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_15 ); REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP0 , 0 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP0 ); REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP0_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP0_LEN ); REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP1 , 8 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP1 ); REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP1_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP1_LEN ); REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP2 , 16 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP2 ); REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP2_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP2_LEN ); REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP3 , 24 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP3 ); REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP3_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP3_LEN ); REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP4 , 32 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP4 ); REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP4_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP4_LEN ); REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP5 , 40 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP5 ); REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP5_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP5_LEN ); REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP6 , 48 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP6 ); REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP6_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP6_LEN ); REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP7 , 56 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP7 ); REG64_FLD( PU_RCV_ERRLOG0_REG_MALF_ERR_FROM_GROUP7_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP7_LEN ); REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP8 , 0 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP8 ); REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP8_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP8_LEN ); REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP9 , 8 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP9 ); REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP9_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP9_LEN ); REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP10 , 16 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP10 ); REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP10_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP10_LEN ); REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP11 , 24 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP11 ); REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP11_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP11_LEN ); REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP12 , 32 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP12 ); REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP12_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP12_LEN ); REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP13 , 40 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP13 ); REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP13_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP13_LEN ); REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP14 , 48 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP14 ); REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP14_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP14_LEN ); REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP15 , 56 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP15 ); REG64_FLD( PU_RCV_ERRLOG1_REG_MALF_ERR_FROM_GROUP15_LEN , 8 , SH_UNT , SH_ACS_SCOM_WAND, SH_FLD_MALF_ERR_FROM_GROUP15_LEN ); REG64_FLD( PU_NPU0_REM0_IBUF_WSRC , 17 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IBUF_WSRC ); REG64_FLD( PU_NPU0_REM0_IBUF_WSRC_LEN , 5 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IBUF_WSRC_LEN ); REG64_FLD( PU_NPU0_REM0_IBUF_RSRC , 22 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IBUF_RSRC ); REG64_FLD( PU_NPU0_REM0_IBUF_RSRC_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IBUF_RSRC_LEN ); REG64_FLD( PU_NPU0_REM0_IBUF_AIDX , 24 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IBUF_AIDX ); REG64_FLD( PU_NPU0_REM0_IBUF_AIDX_LEN , 8 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IBUF_AIDX_LEN ); REG64_FLD( PU_NPU0_REM0_IBUF_ABANK , 32 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IBUF_ABANK ); REG64_FLD( PU_NPU0_REM0_IBUF_ABANK_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IBUF_ABANK_LEN ); REG64_FLD( PU_NPU0_REM0_OBUF_WSRC , 34 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_OBUF_WSRC ); REG64_FLD( PU_NPU0_REM0_OBUF_WSRC_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_OBUF_WSRC_LEN ); REG64_FLD( PU_NPU0_REM0_OBUF_RSRC , 36 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_OBUF_RSRC ); REG64_FLD( PU_NPU0_REM0_OBUF_RSRC_LEN , 6 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_OBUF_RSRC_LEN ); REG64_FLD( PU_NPU0_REM0_OBUF_AIDX , 42 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_OBUF_AIDX ); REG64_FLD( PU_NPU0_REM0_OBUF_AIDX_LEN , 8 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_OBUF_AIDX_LEN ); REG64_FLD( PU_NPU0_REM0_OBUF_ABANK , 50 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_OBUF_ABANK ); REG64_FLD( PU_NPU0_REM0_OBUF_ABANK_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_OBUF_ABANK_LEN ); REG64_FLD( PU_NPU0_REM0_BBUF_WSRC , 52 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BBUF_WSRC ); REG64_FLD( PU_NPU0_REM0_BBUF_WSRC_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BBUF_WSRC_LEN ); REG64_FLD( PU_NPU0_REM0_BBUF_RSRC , 54 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BBUF_RSRC ); REG64_FLD( PU_NPU0_REM0_BBUF_RSRC_LEN , 2 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BBUF_RSRC_LEN ); REG64_FLD( PU_NPU0_REM0_BBUF_AIDX , 56 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BBUF_AIDX ); REG64_FLD( PU_NPU0_REM0_BBUF_AIDX_LEN , 8 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_BBUF_AIDX_LEN ); REG64_FLD( PU_NPU1_REM0_IBUF_WSRC , 17 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IBUF_WSRC ); REG64_FLD( PU_NPU1_REM0_IBUF_WSRC_LEN , 5 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IBUF_WSRC_LEN ); REG64_FLD( PU_NPU1_REM0_IBUF_RSRC , 22 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IBUF_RSRC ); REG64_FLD( PU_NPU1_REM0_IBUF_RSRC_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IBUF_RSRC_LEN ); REG64_FLD( PU_NPU1_REM0_IBUF_AIDX , 24 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IBUF_AIDX ); REG64_FLD( PU_NPU1_REM0_IBUF_AIDX_LEN , 8 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IBUF_AIDX_LEN ); REG64_FLD( PU_NPU1_REM0_IBUF_ABANK , 32 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IBUF_ABANK ); REG64_FLD( PU_NPU1_REM0_IBUF_ABANK_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IBUF_ABANK_LEN ); REG64_FLD( PU_NPU1_REM0_OBUF_WSRC , 34 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_OBUF_WSRC ); REG64_FLD( PU_NPU1_REM0_OBUF_WSRC_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_OBUF_WSRC_LEN ); REG64_FLD( PU_NPU1_REM0_OBUF_RSRC , 36 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_OBUF_RSRC ); REG64_FLD( PU_NPU1_REM0_OBUF_RSRC_LEN , 6 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_OBUF_RSRC_LEN ); REG64_FLD( PU_NPU1_REM0_OBUF_AIDX , 42 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_OBUF_AIDX ); REG64_FLD( PU_NPU1_REM0_OBUF_AIDX_LEN , 8 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_OBUF_AIDX_LEN ); REG64_FLD( PU_NPU1_REM0_OBUF_ABANK , 50 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_OBUF_ABANK ); REG64_FLD( PU_NPU1_REM0_OBUF_ABANK_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_OBUF_ABANK_LEN ); REG64_FLD( PU_NPU1_REM0_BBUF_WSRC , 52 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BBUF_WSRC ); REG64_FLD( PU_NPU1_REM0_BBUF_WSRC_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BBUF_WSRC_LEN ); REG64_FLD( PU_NPU1_REM0_BBUF_RSRC , 54 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BBUF_RSRC ); REG64_FLD( PU_NPU1_REM0_BBUF_RSRC_LEN , 2 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BBUF_RSRC_LEN ); REG64_FLD( PU_NPU1_REM0_BBUF_AIDX , 56 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BBUF_AIDX ); REG64_FLD( PU_NPU1_REM0_BBUF_AIDX_LEN , 8 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_BBUF_AIDX_LEN ); REG64_FLD( PU_NPU2_REM0_IBUF_WSRC , 17 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IBUF_WSRC ); REG64_FLD( PU_NPU2_REM0_IBUF_WSRC_LEN , 5 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IBUF_WSRC_LEN ); REG64_FLD( PU_NPU2_REM0_IBUF_RSRC , 22 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IBUF_RSRC ); REG64_FLD( PU_NPU2_REM0_IBUF_RSRC_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IBUF_RSRC_LEN ); REG64_FLD( PU_NPU2_REM0_IBUF_AIDX , 24 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IBUF_AIDX ); REG64_FLD( PU_NPU2_REM0_IBUF_AIDX_LEN , 8 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IBUF_AIDX_LEN ); REG64_FLD( PU_NPU2_REM0_IBUF_ABANK , 32 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IBUF_ABANK ); REG64_FLD( PU_NPU2_REM0_IBUF_ABANK_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IBUF_ABANK_LEN ); REG64_FLD( PU_NPU2_REM0_OBUF_WSRC , 34 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_OBUF_WSRC ); REG64_FLD( PU_NPU2_REM0_OBUF_WSRC_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_OBUF_WSRC_LEN ); REG64_FLD( PU_NPU2_REM0_OBUF_RSRC , 36 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_OBUF_RSRC ); REG64_FLD( PU_NPU2_REM0_OBUF_RSRC_LEN , 6 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_OBUF_RSRC_LEN ); REG64_FLD( PU_NPU2_REM0_OBUF_AIDX , 42 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_OBUF_AIDX ); REG64_FLD( PU_NPU2_REM0_OBUF_AIDX_LEN , 8 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_OBUF_AIDX_LEN ); REG64_FLD( PU_NPU2_REM0_OBUF_ABANK , 50 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_OBUF_ABANK ); REG64_FLD( PU_NPU2_REM0_OBUF_ABANK_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_OBUF_ABANK_LEN ); REG64_FLD( PU_NPU2_REM0_BBUF_WSRC , 52 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BBUF_WSRC ); REG64_FLD( PU_NPU2_REM0_BBUF_WSRC_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BBUF_WSRC_LEN ); REG64_FLD( PU_NPU2_REM0_BBUF_RSRC , 54 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BBUF_RSRC ); REG64_FLD( PU_NPU2_REM0_BBUF_RSRC_LEN , 2 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BBUF_RSRC_LEN ); REG64_FLD( PU_NPU2_REM0_BBUF_AIDX , 56 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BBUF_AIDX ); REG64_FLD( PU_NPU2_REM0_BBUF_AIDX_LEN , 8 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_BBUF_AIDX_LEN ); REG64_FLD( PU_NPU0_REM1_PBRX_RTAG , 34 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_PBRX_RTAG ); REG64_FLD( PU_NPU0_REM1_PBRX_RTAG_LEN , 22 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_PBRX_RTAG_LEN ); REG64_FLD( PU_NPU0_REM1_ALU_ADR , 56 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_ALU_ADR ); REG64_FLD( PU_NPU0_REM1_ALU_ADR_LEN , 3 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_ALU_ADR_LEN ); REG64_FLD( PU_NPU0_REM1_ALU_TYPE , 59 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_ALU_TYPE ); REG64_FLD( PU_NPU0_REM1_ALU_TYPE_LEN , 4 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_ALU_TYPE_LEN ); REG64_FLD( PU_NPU0_REM1_ALU_SZ , 63 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_ALU_SZ ); REG64_FLD( PU_NPU1_REM1_PBRX_RTAG , 34 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_PBRX_RTAG ); REG64_FLD( PU_NPU1_REM1_PBRX_RTAG_LEN , 22 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_PBRX_RTAG_LEN ); REG64_FLD( PU_NPU1_REM1_ALU_ADR , 56 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_ALU_ADR ); REG64_FLD( PU_NPU1_REM1_ALU_ADR_LEN , 3 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_ALU_ADR_LEN ); REG64_FLD( PU_NPU1_REM1_ALU_TYPE , 59 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_ALU_TYPE ); REG64_FLD( PU_NPU1_REM1_ALU_TYPE_LEN , 4 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_ALU_TYPE_LEN ); REG64_FLD( PU_NPU1_REM1_ALU_SZ , 63 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_ALU_SZ ); REG64_FLD( PU_NPU2_REM1_PBRX_RTAG , 34 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_PBRX_RTAG ); REG64_FLD( PU_NPU2_REM1_PBRX_RTAG_LEN , 22 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_PBRX_RTAG_LEN ); REG64_FLD( PU_NPU2_REM1_ALU_ADR , 56 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_ALU_ADR ); REG64_FLD( PU_NPU2_REM1_ALU_ADR_LEN , 3 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_ALU_ADR_LEN ); REG64_FLD( PU_NPU2_REM1_ALU_TYPE , 59 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_ALU_TYPE ); REG64_FLD( PU_NPU2_REM1_ALU_TYPE_LEN , 4 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_ALU_TYPE_LEN ); REG64_FLD( PU_NPU2_REM1_ALU_SZ , 63 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_ALU_SZ ); REG64_FLD( PU_RESET_REGISTER_CHICKEN_SWITCH , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHICKEN_SWITCH ); REG64_FLD( PU_RESET_REGISTER_B_CHKSW_AR012_0 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHKSW_AR012_0 ); REG64_FLD( PU_RESET_REGISTER_C_CHKSW_AR012_1 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHKSW_AR012_1 ); REG64_FLD( PU_RESET_REGISTER_D_CHKSW_AR012_2 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHKSW_AR012_2 ); REG64_FLD( PU_RESET_REGISTER_E_CHKSW_AR012_3 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHKSW_AR012_3 ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_RESID_FE_LEN_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESID_FE_LEN_0 ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_RESID_FE_LEN_0_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESID_FE_LEN_0_LEN ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_PEEK_DATA1_0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0 ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_PEEK_DATA1_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0_LEN ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_B_LBUS_PARITY_ERR1_0 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_0 ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_RESID_FE_LEN_1 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESID_FE_LEN_1 ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_RESID_FE_LEN_1_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESID_FE_LEN_1_LEN ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_PEEK_DATA1_1 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1 ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_PEEK_DATA1_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1_LEN ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_C_LBUS_PARITY_ERR1_1 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_1 ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_RESID_FE_LEN_2 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESID_FE_LEN_2 ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_RESID_FE_LEN_2_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESID_FE_LEN_2_LEN ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_PEEK_DATA1_2 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2 ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_PEEK_DATA1_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2_LEN ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_D_LBUS_PARITY_ERR1_2 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_2 ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_RESID_FE_LEN_3 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESID_FE_LEN_3 ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_RESID_FE_LEN_3_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESID_FE_LEN_3_LEN ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_PEEK_DATA1_3 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3 ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_PEEK_DATA1_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3_LEN ); REG64_FLD( PU_RESIDUAL_FRONT_END_BACK_END_LENGTH_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); REG64_FLD( PEC_RFIR_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN0 ); REG64_FLD( PEC_RFIR_LFIR_RECOV_ERR , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_LFIR_RECOV_ERR ); REG64_FLD( PEC_RFIR_IN4 , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN4 ); REG64_FLD( PEC_RFIR_IN5 , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN5 ); REG64_FLD( PEC_RFIR_IN6 , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN6 ); REG64_FLD( PEC_RFIR_IN6_LEN , 20 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN6_LEN ); REG64_FLD( PU_N3_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_DISABLED ); REG64_FLD( PU_N3_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_N3_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); REG64_FLD( PU_N1_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_DISABLED ); REG64_FLD( PU_N1_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_N1_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); REG64_FLD( PU_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLED ); REG64_FLD( PU_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); REG64_FLD( PU_N2_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_DISABLED ); REG64_FLD( PU_N2_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_N2_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); REG64_FLD( PEC_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DISABLED ); REG64_FLD( PEC_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PEC_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); REG64_FLD( PU_N0_RING_FENCE_MASK_LATCH_REG_DISABLED , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_DISABLED ); REG64_FLD( PU_N0_RING_FENCE_MASK_LATCH_REG_ENABLE , 1 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_N0_RING_FENCE_MASK_LATCH_REG_ENABLE_LEN , 15 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_ENABLE_LEN ); REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK0_CLUSTER , 0 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BRK0_CLUSTER ); REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK0_CLUSTER_LEN , 3 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BRK0_CLUSTER_LEN ); REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK1_CLUSTER , 3 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BRK1_CLUSTER ); REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK1_CLUSTER_LEN , 3 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BRK1_CLUSTER_LEN ); REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK2_CLUSTER , 6 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BRK2_CLUSTER ); REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK2_CLUSTER_LEN , 3 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BRK2_CLUSTER_LEN ); REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK3_CLUSTER , 9 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BRK3_CLUSTER ); REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK3_CLUSTER_LEN , 3 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BRK3_CLUSTER_LEN ); REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK4_CLUSTER , 12 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BRK4_CLUSTER ); REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK4_CLUSTER_LEN , 3 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BRK4_CLUSTER_LEN ); REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK5_CLUSTER , 15 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BRK5_CLUSTER ); REG64_FLD( PU_NPU_CTL_RLX_CONFIG_BRK5_CLUSTER_LEN , 3 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_BRK5_CLUSTER_LEN ); REG64_FLD( PU_NPU_CTL_RLX_CONFIG_RESERVED1 , 18 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU_CTL_RLX_CONFIG_RESERVED1_LEN , 2 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU_CTL_RLX_CONFIG_SYNC_BRK , 20 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_SYNC_BRK ); REG64_FLD( PU_NPU_CTL_RLX_CONFIG_SYNC_BRK_LEN , 6 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_SYNC_BRK_LEN ); REG64_FLD( PU_NPU_CTL_RLX_CONFIG_IDIAL_ISSYNC , 26 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_ISSYNC ); REG64_FLD( PU_NPU_CTL_RLX_CONFIG_IDIAL_ISSYNC_LEN , 6 , SH_UNT_PU_NPU_CTL, SH_ACS_SCOM , SH_FLD_IDIAL_ISSYNC_LEN ); REG64_FLD( PU_RNG_FAILED_INT_ENABLE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE ); REG64_FLD( PU_RNG_FAILED_INT_ADDRESS , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDRESS ); REG64_FLD( PU_RNG_FAILED_INT_ADDRESS_LEN , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_START , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_START ); REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_START_LEN , 9 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_START_LEN ); REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_RESERVED2_LEN , 3 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_END , 15 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_END ); REG64_FLD( PU_NPU2_NTL0_RSP_DA_PTR_END_LEN , 9 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_END_LEN ); REG64_FLD( NV_RSP_DA_PTR_RESERVED1 , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( NV_RSP_DA_PTR_RESERVED1_LEN , 3 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( NV_RSP_DA_PTR_START , 3 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_START ); REG64_FLD( NV_RSP_DA_PTR_START_LEN , 9 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_START_LEN ); REG64_FLD( NV_RSP_DA_PTR_RESERVED2 , 12 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( NV_RSP_DA_PTR_RESERVED2_LEN , 3 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( NV_RSP_DA_PTR_END , 15 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_END ); REG64_FLD( NV_RSP_DA_PTR_END_LEN , 9 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_END_LEN ); REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_RESERVED1_LEN , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_START , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_START ); REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_START_LEN , 9 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_START_LEN ); REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_RESERVED2_LEN , 3 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_END , 15 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_END ); REG64_FLD( PU_NPU2_NTL1_RSP_DA_PTR_END_LEN , 9 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_END_LEN ); REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_START , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_START ); REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_START_LEN , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_START_LEN ); REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_END , 17 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_END ); REG64_FLD( PU_NPU2_NTL0_RSP_HA_PTR_END_LEN , 7 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_END_LEN ); REG64_FLD( NV_RSP_HA_PTR_RESERVED1 , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( NV_RSP_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( NV_RSP_HA_PTR_START , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_START ); REG64_FLD( NV_RSP_HA_PTR_START_LEN , 7 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_START_LEN ); REG64_FLD( NV_RSP_HA_PTR_RESERVED2 , 12 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( NV_RSP_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( NV_RSP_HA_PTR_END , 17 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_END ); REG64_FLD( NV_RSP_HA_PTR_END_LEN , 7 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_END_LEN ); REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_RESERVED1 , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_RESERVED1_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED1_LEN ); REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_START , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_START ); REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_START_LEN , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_START_LEN ); REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_RESERVED2 , 12 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED2 ); REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_RESERVED2_LEN , 5 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_RESERVED2_LEN ); REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_END , 17 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_END ); REG64_FLD( PU_NPU2_NTL1_RSP_HA_PTR_END_LEN , 7 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_END_LEN ); REG64_FLD( PU_RX_CTRL_STAT_REG_ENABLE_SCWR_TO_RXRF , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_SCWR_TO_RXRF ); REG64_FLD( PU_RX_CTRL_STAT_REG_DISABLE_ECC_COR_RXRF_PSI , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_ECC_COR_RXRF_PSI ); REG64_FLD( PU_RX_CTRL_STAT_REG_CRC_MODE , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CRC_MODE ); REG64_FLD( PU_RX_CTRL_STAT_REG_ENABLE_SCRD_FR_RXRF , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_SCRD_FR_RXRF ); REG64_FLD( PU_RX_CTRL_STAT_REG_ENABLE_STREAMING_MODE , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_STREAMING_MODE ); REG64_FLD( PU_RX_CTRL_STAT_REG_CHIP_INTERFACEMODE , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHIP_INTERFACEMODE ); REG64_FLD( PU_RX_CTRL_STAT_REG_CHIP_PERSONALISATION , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHIP_PERSONALISATION ); REG64_FLD( PU_RX_MASK_REG_PSIRXINS_RFGSHIFT_PCK , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRXINS_RFGSHIFT_PCK ); REG64_FLD( PU_RX_MASK_REG_PSIRXINS_RZRTMP_PCK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRXINS_RZRTMP_PCK ); REG64_FLD( PU_RX_MASK_REG_PSIRXINS_DATA_PCK , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRXINS_DATA_PCK ); REG64_FLD( PU_RX_MASK_REG_PSIRXEI_SHIFT_PCK , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRXEI_SHIFT_PCK ); REG64_FLD( PU_RX_MASK_REG_PSIRXEI_TRANSMIT_PCK , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRXEI_TRANSMIT_PCK ); REG64_FLD( PU_RX_MASK_REG_PSIRXINS_OVERRUN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRXINS_OVERRUN ); REG64_FLD( PU_RX_MASK_REG_PSIRXBFF_DATA_PCK , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRXBFF_DATA_PCK ); REG64_FLD( PU_RX_MASK_REG_PSIRXBFF_DATAO_PCK , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRXBFF_DATAO_PCK ); REG64_FLD( PU_RX_MASK_REG_PSIRXBFF_RFC_PCK , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRXBFF_RFC_PCK ); REG64_FLD( PU_RX_MASK_REG_PSIRXLC_FSM_PCK , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRXLC_FSM_PCK ); REG64_FLD( PU_RX_MASK_REG_PSIRXLC_DATA_BUFF_PCK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRXLC_DATA_BUFF_PCK ); REG64_FLD( PU_RX_MASK_REG_PSIRXLC_DATA_PCK , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRXLC_DATA_PCK ); REG64_FLD( PU_RX_MASK_REG_PSIRXLC_RADDR_PCK , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRXLC_RADDR_PCK ); REG64_FLD( PU_RX_MASK_REG_PSIRXLC_RCTRL_PCK , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRXLC_RCTRL_PCK ); REG64_FLD( PU_RX_MASK_REG_PSIRXLC_UE_RF , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRXLC_UE_RF ); REG64_FLD( PU_RX_MASK_REG_PSIRXLC_CE_RF , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRXLC_CE_RF ); REG64_FLD( PU_RX_MASK_REG_PSIRXLC_DATA_GXST1_PCK_2N , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRXLC_DATA_GXST1_PCK_2N ); REG64_FLD( PU_RX_MASK_REG_PSIRFACC_RADDR_PCK , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRFACC_RADDR_PCK ); REG64_FLD( PU_RX_MASK_REG_PSIRFACC_RCTRL_PCK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRFACC_RCTRL_PCK ); REG64_FLD( PU_RX_MASK_REG_PSIRFACC_RFSM_PCK , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRFACC_RFSM_PCK ); REG64_FLD( PU_RX_MASK_REG_PSIRFACC_RDL_FSM_PCK , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRFACC_RDL_FSM_PCK ); REG64_FLD( PU_RX_MASK_REG_PSIRFACC_RXSC_PCK , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRFACC_RXSC_PCK ); REG64_FLD( PU_RX_MASK_REG_PSIRFACC_RLINK_STATE_LT_02 , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRFACC_RLINK_STATE_LT_02 ); REG64_FLD( PU_RX_MASK_REG_PSIRFACC_C_RXDATA_RDY_ERR , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRFACC_C_RXDATA_RDY_ERR ); REG64_FLD( PU_RX_PSI_CNTL_PATTERN_CHECK_EN , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERN_CHECK_EN ); REG64_FLD( PU_RX_PSI_CNTL_PATTERN_SEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERN_SEL ); REG64_FLD( PU_RX_PSI_CNTL_PATTERN_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERN_SEL_LEN ); REG64_FLD( PU_RX_PSI_CNTL_CLK_INVERT , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CLK_INVERT ); REG64_FLD( PU_RX_PSI_CNTL_LANE_INVERT , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_LANE_INVERT ); REG64_FLD( PU_RX_PSI_CNTL_PDWN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PDWN ); REG64_FLD( PU_RX_PSI_CNTL_CLK_DLY , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_CLK_DLY ); REG64_FLD( PU_RX_PSI_CNTL_CLK_DLY_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_CLK_DLY_LEN ); REG64_FLD( PU_RX_PSI_CNTL_DATA_DLY , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_DLY ); REG64_FLD( PU_RX_PSI_CNTL_DATA_DLY_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_DLY_LEN ); REG64_FLD( PU_RX_PSI_CNTL_DEGLITCH_CLK_DLY , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_DEGLITCH_CLK_DLY ); REG64_FLD( PU_RX_PSI_CNTL_DEGLITCH_CLK_DLY_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_DEGLITCH_CLK_DLY_LEN ); REG64_FLD( PU_RX_PSI_CNTL_DEGLITCH_DATA_DLY , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_DEGLITCH_DATA_DLY ); REG64_FLD( PU_RX_PSI_CNTL_DEGLITCH_DATA_DLY_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_DEGLITCH_DATA_DLY_LEN ); REG64_FLD( PU_RX_PSI_MODE_VREF , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_VREF ); REG64_FLD( PU_RX_PSI_MODE_VREF_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_VREF_LEN ); REG64_FLD( PU_RX_PSI_MODE_TERM_TEST , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_TERM_TEST ); REG64_FLD( PU_RX_PSI_MODE_TERM_ENC , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_TERM_ENC ); REG64_FLD( PU_RX_PSI_MODE_TERM_ENC_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_TERM_ENC_LEN ); REG64_FLD( PU_RX_PSI_MODE_SPARE , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE ); REG64_FLD( PU_RX_PSI_MODE_SPARE_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); REG64_FLD( PU_RX_PSI_STATUS_LD_UNLD_DLY , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_LD_UNLD_DLY ); REG64_FLD( PU_RX_PSI_STATUS_LD_UNLD_DLY_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_LD_UNLD_DLY_LEN ); REG64_FLD( PU_RX_PSI_STATUS_OVER_OR_UNDERRUN_ERR , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_OVER_OR_UNDERRUN_ERR ); REG64_FLD( PU_RX_PSI_STATUS_CLEAR , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_CLEAR ); REG64_FLD( PU_RX_PSI_STATUS_SPARE , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE ); REG64_FLD( PU_RX_PSI_STATUS_SPARE_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); REG64_FLD( PEC_SCAN_REGION_TYPE_SYSTEM_FAST_INIT , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SYSTEM_FAST_INIT ); REG64_FLD( PEC_SCAN_REGION_TYPE_VITL , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_VITL ); REG64_FLD( PEC_SCAN_REGION_TYPE_PERV , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PERV ); REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT1 , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT1 ); REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT2 , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT2 ); REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT3 , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT3 ); REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT4 , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT4 ); REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT5 , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT5 ); REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT6 , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT6 ); REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT7 , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT7 ); REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT8 , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT8 ); REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT9 , 13 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT9 ); REG64_FLD( PEC_SCAN_REGION_TYPE_UNIT10 , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT10 ); REG64_FLD( PEC_SCAN_REGION_TYPE_FUNC , 48 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FUNC ); REG64_FLD( PEC_SCAN_REGION_TYPE_CFG , 49 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CFG ); REG64_FLD( PEC_SCAN_REGION_TYPE_CCFG_GPTR , 50 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CCFG_GPTR ); REG64_FLD( PEC_SCAN_REGION_TYPE_REGF , 51 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_REGF ); REG64_FLD( PEC_SCAN_REGION_TYPE_LBIST , 52 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_LBIST ); REG64_FLD( PEC_SCAN_REGION_TYPE_ABIST , 53 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ABIST ); REG64_FLD( PEC_SCAN_REGION_TYPE_REPR , 54 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_REPR ); REG64_FLD( PEC_SCAN_REGION_TYPE_TIME , 55 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TIME ); REG64_FLD( PEC_SCAN_REGION_TYPE_BNDY , 56 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_BNDY ); REG64_FLD( PEC_SCAN_REGION_TYPE_FARR , 57 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FARR ); REG64_FLD( PEC_SCAN_REGION_TYPE_CMSK , 58 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CMSK ); REG64_FLD( PEC_SCAN_REGION_TYPE_INEX , 59 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_INEX ); REG64_FLD( PU_SCOM_PPE_CNTL_IORESET , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_IORESET ); REG64_FLD( PU_SCOM_PPE_CNTL_PDWN , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_PDWN ); REG64_FLD( PU_SCOM_PPE_CNTL_INTERRUPT , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_INTERRUPT ); REG64_FLD( PU_SCOM_PPE_CNTL_ARB_ECC_INJECT_ERR , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_ARB_ECC_INJECT_ERR ); REG64_FLD( PU_SCOM_PPE_CNTL_SPARES , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARES ); REG64_FLD( PU_SCOM_PPE_CNTL_SPARES_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARES_LEN ); REG64_FLD( PU_SCOM_PPE_FLAGS_FIELD , 0 , SH_UNT , SH_ACS_SCOM2_CLEAR, SH_FLD_FIELD ); REG64_FLD( PU_SCOM_PPE_FLAGS_FIELD_LEN , 16 , SH_UNT , SH_ACS_SCOM2_CLEAR, SH_FLD_FIELD_LEN ); REG64_FLD( PU_SCOM_PPE_WORK_REG1_WORK1 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_WORK1 ); REG64_FLD( PU_SCOM_PPE_WORK_REG1_WORK1_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_WORK1_LEN ); REG64_FLD( PU_SCOM_PPE_WORK_REG2_WORK2 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_WORK2 ); REG64_FLD( PU_SCOM_PPE_WORK_REG2_WORK2_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_WORK2_LEN ); REG64_FLD( PU_NPU0_SCRATCH0_IDIAL , 0 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU0_SCRATCH0_IDIAL_LEN , 64 , SH_UNT_PU_NPU0 , SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_SCRATCH0_SCRATCH_N , 0 , SH_UNT , SH_ACS_PPE2 , SH_FLD_SCRATCH_N ); REG64_FLD( PU_SCRATCH0_SCRATCH_N_LEN , 64 , SH_UNT , SH_ACS_PPE2 , SH_FLD_SCRATCH_N_LEN ); REG64_FLD( PU_NPU1_SCRATCH0_IDIAL , 0 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU1_SCRATCH0_IDIAL_LEN , 64 , SH_UNT_PU_NPU1 , SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_NPU2_SCRATCH0_IDIAL , 0 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU2_SCRATCH0_IDIAL_LEN , 64 , SH_UNT_PU_NPU2 , SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_NPU2_NTL0_SCRATCH1_IDIAL , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU2_NTL0_SCRATCH1_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_SCRATCH1_SCRATCH_N , 0 , SH_UNT , SH_ACS_PPE2 , SH_FLD_SCRATCH_N ); REG64_FLD( PU_SCRATCH1_SCRATCH_N_LEN , 64 , SH_UNT , SH_ACS_PPE2 , SH_FLD_SCRATCH_N_LEN ); REG64_FLD( NV_SCRATCH1_IDIAL , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( NV_SCRATCH1_IDIAL_LEN , 64 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_NPU2_DAT_SCRATCH1_IDIAL , 0 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU2_DAT_SCRATCH1_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_DAT, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_NPU2_NTL1_SCRATCH1_IDIAL , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU2_NTL1_SCRATCH1_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_NPU1_DAT_SCRATCH1_IDIAL , 0 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU1_DAT_SCRATCH1_IDIAL_LEN , 64 , SH_UNT_PU_NPU1_DAT, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_NPU0_DAT_SCRATCH1_IDIAL , 0 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU0_DAT_SCRATCH1_IDIAL_LEN , 64 , SH_UNT_PU_NPU0_DAT, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_NPU2_NTL0_SCRATCH2_IDIAL , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU2_NTL0_SCRATCH2_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_SCRATCH2_SCRATCH_N , 0 , SH_UNT , SH_ACS_PPE2 , SH_FLD_SCRATCH_N ); REG64_FLD( PU_SCRATCH2_SCRATCH_N_LEN , 64 , SH_UNT , SH_ACS_PPE2 , SH_FLD_SCRATCH_N_LEN ); REG64_FLD( NV_SCRATCH2_IDIAL , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( NV_SCRATCH2_IDIAL_LEN , 64 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_NPU2_NTL1_SCRATCH2_IDIAL , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU2_NTL1_SCRATCH2_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_NPU2_NTL0_SCRATCH3_IDIAL , 0 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU2_NTL0_SCRATCH3_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_NTL0, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_SCRATCH3_SCRATCH_N , 0 , SH_UNT , SH_ACS_PPE2 , SH_FLD_SCRATCH_N ); REG64_FLD( PU_SCRATCH3_SCRATCH_N_LEN , 64 , SH_UNT , SH_ACS_PPE2 , SH_FLD_SCRATCH_N_LEN ); REG64_FLD( NV_SCRATCH3_IDIAL , 0 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( NV_SCRATCH3_IDIAL_LEN , 64 , SH_UNT_NV , SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_NPU2_NTL1_SCRATCH3_IDIAL , 0 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_IDIAL ); REG64_FLD( PU_NPU2_NTL1_SCRATCH3_IDIAL_LEN , 64 , SH_UNT_PU_NPU2_NTL1, SH_ACS_SCOM , SH_FLD_IDIAL_LEN ); REG64_FLD( PU_SECURITY_SWITCH_REGISTER_SECURE_ACCESS , 0 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_SECURE_ACCESS ); REG64_FLD( PU_SECURITY_SWITCH_REGISTER_LATE_LAUNCH_PRIMARY , 1 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_LATE_LAUNCH_PRIMARY ); REG64_FLD( PU_SECURITY_SWITCH_REGISTER_LATE_LAUNCH_SECONDARY , 2 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_LATE_LAUNCH_SECONDARY ); REG64_FLD( PU_SECURITY_SWITCH_REGISTER_LOCAL_QUIESCE_ACHIEVED , 3 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_LOCAL_QUIESCE_ACHIEVED ); REG64_FLD( PU_SECURITY_SWITCH_REGISTER_SEEPROM_UPDATE_LOCK , 4 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_SEEPROM_UPDATE_LOCK ); REG64_FLD( PU_SECURITY_SWITCH_REGISTER_LOCALITY_4_ACCESS , 5 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_LOCALITY_4_ACCESS ); REG64_FLD( PU_SECURITY_SWITCH_REGISTER_SECURE_DEBUG , 6 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_SECURE_DEBUG ); REG64_FLD( PU_SECURITY_SWITCH_REGISTER_CMFSI_ACCESS_PROTCT , 7 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_CMFSI_ACCESS_PROTCT ); REG64_FLD( PU_SECURITY_SWITCH_REGISTER_ABUS_LOCK , 8 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_ABUS_LOCK ); REG64_FLD( PU_SECURITY_SWITCH_REGISTER_NX_RAND_NUM_GEN_LOCK , 9 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_NX_RAND_NUM_GEN_LOCK ); REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_EX_SPARE0 , 10 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_PROT_EX_SPARE0 ); REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_EX_SPARE1 , 11 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_PROT_EX_SPARE1 ); REG64_FLD( PU_SECURITY_SWITCH_REGISTER_I2CM_TPM_DECONFIG_PROTECT , 12 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_I2CM_TPM_DECONFIG_PROTECT ); REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_TP_SPARE0 , 13 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_PROT_TP_SPARE0 ); REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_TP_SPARE1 , 14 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_PROT_TP_SPARE1 ); REG64_FLD( PU_SECURITY_SWITCH_REGISTER_PROT_TP_SPARE2 , 15 , SH_UNT , SH_ACS_SCOM1 , SH_FLD_PROT_TP_SPARE2 ); REG64_FLD( PU_SEND_WC_BASE_ADDR_BAR , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAR ); REG64_FLD( PU_SEND_WC_BASE_ADDR_BAR_LEN , 33 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAR_LEN ); REG64_FLD( PEC_SKITTER_CLKSRC_REG_SKITTER0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SKITTER0 ); REG64_FLD( PEC_SKITTER_CLKSRC_REG_SKITTER0_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SKITTER0_LEN ); REG64_FLD( PEC_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT , 36 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SKITTER0_DELAY_SELECT ); REG64_FLD( PEC_SKITTER_CLKSRC_REG_SKITTER0_DELAY_SELECT_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SKITTER0_DELAY_SELECT_LEN ); REG64_FLD( PEC_SKITTER_FORCE_REG_F_READ , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_F_READ ); REG64_FLD( PEC_SKITTER_MODE_REG_HOLD_SAMPLE , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_HOLD_SAMPLE ); REG64_FLD( PEC_SKITTER_MODE_REG_DISABLE_STICKINESS , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DISABLE_STICKINESS ); REG64_FLD( PEC_SKITTER_MODE_REG_UNUSED1 , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED1 ); REG64_FLD( PEC_SKITTER_MODE_REG_UNUSED1_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED1_LEN ); REG64_FLD( PEC_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_HOLD_DBGTRIG_SEL ); REG64_FLD( PEC_SKITTER_MODE_REG_HOLD_DBGTRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_HOLD_DBGTRIG_SEL_LEN ); REG64_FLD( PEC_SKITTER_MODE_REG_RESET_TRIG_SEL , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESET_TRIG_SEL ); REG64_FLD( PEC_SKITTER_MODE_REG_RESET_TRIG_SEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESET_TRIG_SEL_LEN ); REG64_FLD( PEC_SKITTER_MODE_REG_SAMPLE_GUTS , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SAMPLE_GUTS ); REG64_FLD( PEC_SKITTER_MODE_REG_SAMPLE_GUTS_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SAMPLE_GUTS_LEN ); REG64_FLD( PEC_SKITTER_MODE_REG_HOLD_SAMPLE_WITH_TRIGGER , 44 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_HOLD_SAMPLE_WITH_TRIGGER ); REG64_FLD( PEC_SKITTER_MODE_REG_DATA_V_LT , 45 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DATA_V_LT ); REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_DISABLE_PERV_THOLD_CHECK , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CFG_DISABLE_PERV_THOLD_CHECK ); REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_DISABLE_MALF_PULSE_GEN , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CFG_DISABLE_MALF_PULSE_GEN ); REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_STOP_HANG_CNT_SYS_XSTP , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CFG_STOP_HANG_CNT_SYS_XSTP ); REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_DISABLE_CL_ATOMIC_LOCK , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CFG_DISABLE_CL_ATOMIC_LOCK ); REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_DISABLE_HEARTBEAT , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CFG_DISABLE_HEARTBEAT ); REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_DISABLE_FORCE_TO_ZERO , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CFG_DISABLE_FORCE_TO_ZERO ); REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_PM_DISABLE , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CFG_PM_DISABLE ); REG64_FLD( PEC_SLAVE_CONFIG_REG_CFG_PM_MUX_DISABLE , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CFG_PM_MUX_DISABLE ); REG64_FLD( PEC_SLAVE_CONFIG_REG_ERROR_MASK , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ERROR_MASK ); REG64_FLD( PEC_SLAVE_CONFIG_REG_ERROR_MASK_LEN , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ERROR_MASK_LEN ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CREQ0 ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_PRB0 ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CREQ1 ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_PRB1 ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_XATS ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_PWR0 ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_PWR1 ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CHGRATE ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_MRBGP ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_MRBGP_LEN ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_MRBSP ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_FENCE0 ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_FENCE1 ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_PBLN ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_PBNNG ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_PBRNVG ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_N0REQ ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_N0DGD ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_N1REQ ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_N1DGD ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_MMIO ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_ATSXLATE ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_PBRSP ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_N0RSP ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_N1RSP ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_XARSP ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_SACOLL ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_FREE ); REG64_FLD( PU_NPU0_SM0_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CREQ0 ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_PRB0 ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CREQ1 ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_PRB1 ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_XATS ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_PWR0 ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_PWR1 ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CHGRATE ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_MRBGP ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_MRBGP_LEN ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_MRBSP ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_FENCE0 ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_FENCE1 ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_PBLN ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_PBNNG ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_PBRNVG ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_N0REQ ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_N0DGD ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_N1REQ ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_N1DGD ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_MMIO ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_ATSXLATE ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_PBRSP ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_N0RSP ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_N1RSP ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_XARSP ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_SACOLL ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_FREE ); REG64_FLD( PU_NPU1_SM2_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CREQ0 ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_PRB0 ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CREQ1 ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_PRB1 ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_XATS ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_PWR0 ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_PWR1 ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CHGRATE ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_MRBGP ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_MRBGP_LEN ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_MRBSP ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_FENCE0 ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_FENCE1 ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_PBLN ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_PBNNG ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_PBRNVG ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_N0REQ ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_N0DGD ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_N1REQ ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_N1DGD ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_MMIO ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_ATSXLATE ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_PBRSP ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_N0RSP ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_N1RSP ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_XARSP ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_SACOLL ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_FREE ); REG64_FLD( PU_NPU2_SM3_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CREQ0 ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_PRB0 ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CREQ1 ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_PRB1 ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_XATS ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_PWR0 ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_PWR1 ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CHGRATE ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_MRBGP ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_MRBGP_LEN ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_MRBSP ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_FENCE0 ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_FENCE1 ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_PBLN ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_PBNNG ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_PBRNVG ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_N0REQ ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_N0DGD ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_N1REQ ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_N1DGD ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_MMIO ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_ATSXLATE ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_PBRSP ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_N0RSP ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_N1RSP ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_XARSP ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_SACOLL ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_FREE ); REG64_FLD( PU_NPU1_SM3_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CREQ0 ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_PRB0 ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CREQ1 ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_PRB1 ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_XATS ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_PWR0 ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_PWR1 ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CHGRATE ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_MRBGP ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_MRBGP_LEN ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_MRBSP ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_FENCE0 ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_FENCE1 ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_PBLN ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_PBNNG ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_PBRNVG ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_N0REQ ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_N0DGD ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_N1REQ ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_N1DGD ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_MMIO ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_ATSXLATE ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_PBRSP ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_N0RSP ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_N1RSP ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_XARSP ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_SACOLL ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_FREE ); REG64_FLD( PU_NPU0_SM3_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CREQ0 ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_PRB0 ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CREQ1 ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_PRB1 ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_XATS ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_PWR0 ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_PWR1 ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CHGRATE ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_MRBGP ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_MRBGP_LEN ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_MRBSP ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_FENCE0 ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_FENCE1 ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_PBLN ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_PBNNG ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_PBRNVG ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_N0REQ ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_N0DGD ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_N1REQ ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_N1DGD ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_MMIO ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_ATSXLATE ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_PBRSP ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_N0RSP ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_N1RSP ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_XARSP ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_SACOLL ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_FREE ); REG64_FLD( PU_NPU1_SM1_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CREQ0 ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_PRB0 ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CREQ1 ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_PRB1 ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_XATS ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_PWR0 ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_PWR1 ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CHGRATE ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_MRBGP ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_MRBGP_LEN ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_MRBSP ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_FENCE0 ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_FENCE1 ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_PBLN ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_PBNNG ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_PBRNVG ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_N0REQ ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_N0DGD ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_N1REQ ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_N1DGD ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_MMIO ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_ATSXLATE ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_PBRSP ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_N0RSP ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_N1RSP ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_XARSP ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_SACOLL ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_FREE ); REG64_FLD( PU_NPU2_SM2_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CREQ0 ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_PRB0 ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CREQ1 ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_PRB1 ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_XATS ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_PWR0 ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_PWR1 ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CHGRATE ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_MRBGP ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_MRBGP_LEN ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_MRBSP ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_FENCE0 ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_FENCE1 ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_PBLN ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_PBNNG ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_PBRNVG ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_N0REQ ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_N0DGD ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_N1REQ ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_N1DGD ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_MMIO ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_ATSXLATE ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_PBRSP ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_N0RSP ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_N1RSP ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_XARSP ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_SACOLL ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_FREE ); REG64_FLD( PU_NPU2_SM1_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CREQ0 ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_PRB0 ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CREQ1 ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_PRB1 ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_XATS ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_PWR0 ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_PWR1 ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CHGRATE ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_MRBGP ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_MRBGP_LEN ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_MRBSP ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_FENCE0 ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_FENCE1 ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_PBLN ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_PBNNG ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_PBRNVG ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_N0REQ ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_N0DGD ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_N1REQ ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_N1DGD ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_MMIO ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_ATSXLATE ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_PBRSP ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_N0RSP ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_N1RSP ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_XARSP ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_SACOLL ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_FREE ); REG64_FLD( PU_NPU0_SM2_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CREQ0 ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_PRB0 ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CREQ1 ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_PRB1 ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_XATS ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_PWR0 ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_PWR1 ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CHGRATE ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_MRBGP ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_MRBGP_LEN ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_MRBSP ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_FENCE0 ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_FENCE1 ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_PBLN ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_PBNNG ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_PBRNVG ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_N0REQ ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_N0DGD ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_N1REQ ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_N1DGD ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_MMIO ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_ATSXLATE ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_PBRSP ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_N0RSP ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_N1RSP ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_XARSP ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_SACOLL ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_FREE ); REG64_FLD( PU_NPU2_SM0_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CREQ0 ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_PRB0 ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CREQ1 ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_PRB1 ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_XATS ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_PWR0 ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_PWR1 ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CHGRATE ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_MRBGP ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_MRBGP_LEN ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_MRBSP ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_FENCE0 ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_FENCE1 ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_PBLN ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_PBNNG ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_PBRNVG ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_N0REQ ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_N0DGD ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_N1REQ ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_N1DGD ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_MMIO ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_ATSXLATE ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_PBRSP ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_N0RSP ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_N1RSP ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_XARSP ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_SACOLL ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_FREE ); REG64_FLD( PU_NPU0_SM1_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_CREQ0 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CREQ0 ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_PRB0 , 1 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_PRB0 ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_CREQ1 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CREQ1 ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_PRB1 , 3 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_PRB1 ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_XATS , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_XATS ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_PWR0 , 5 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_PWR0 ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_PWR1 , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_PWR1 ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_CHGRATE , 7 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CHGRATE ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_MRBGP , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_MRBGP ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_MRBGP_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_MRBGP_LEN ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_MRBSP , 12 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_MRBSP ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_MRBSP_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_MRBSP_LEN ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_FENCE0 , 16 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_FENCE0 ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_FENCE0_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_FENCE0_LEN ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_FENCE1 , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_FENCE1 ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_FENCE1_LEN , 4 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_FENCE1_LEN ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_PBLN , 24 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_PBLN ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_PBNNG , 25 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_PBNNG ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_PBRNVG , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_PBRNVG ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_N0REQ , 27 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_N0REQ ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_N0DGD , 28 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_N0DGD ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_N1REQ , 29 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_N1REQ ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_N1DGD , 30 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_N1DGD ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_MMIO , 31 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_MMIO ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_ATSXLATE , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_ATSXLATE ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_PBRSP , 33 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_PBRSP ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_N0RSP , 34 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_N0RSP ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_N1RSP , 35 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_N1RSP ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_XARSP , 36 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_XARSP ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_SACOLL , 37 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_SACOLL ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_FREE , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_FREE ); REG64_FLD( PU_NPU1_SM0_SM_STATUS_RESERVED1 , 39 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_RESERVED1 ); REG64_FLD( PU_SND_MODE_REG_ENABLE_TRC_GLB_TRIG0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_TRC_GLB_TRIG0 ); REG64_FLD( PU_SND_MODE_REG_ENABLE_TRC_GLB_TRIG1 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_TRC_GLB_TRIG1 ); REG64_FLD( PU_SND_MODE_REG_ENABLE_GLB_PULSE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_GLB_PULSE ); REG64_FLD( PU_SND_MODE_REG_SINGLE_OUTSTANDING_CMD , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_SINGLE_OUTSTANDING_CMD ); REG64_FLD( PU_SND_MODE_REG_PROG_REQ_DELAY , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PROG_REQ_DELAY ); REG64_FLD( PU_SND_MODE_REG_PROG_REQ_DELAY_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PROG_REQ_DELAY_LEN ); REG64_FLD( PU_SND_MODE_REG_DISABLE_ERR_CMD , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_ERR_CMD ); REG64_FLD( PU_SND_MODE_REG_DISABLE_HTM_CMD , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_HTM_CMD ); REG64_FLD( PU_SND_MODE_REG_DISABLE_TRACE_CMD , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_TRACE_CMD ); REG64_FLD( PU_SND_MODE_REG_DISABLE_TOD_CMD , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_TOD_CMD ); REG64_FLD( PU_SND_MODE_REG_DISABLE_XSCOM_CMD , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_XSCOM_CMD ); REG64_FLD( PU_SND_MODE_REG_ENABLE_CLR_ERR_CMD , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_CLR_ERR_CMD ); REG64_FLD( PU_SND_MODE_REG_OVERRIDE_PBINIT_ERR_CMD , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_OVERRIDE_PBINIT_ERR_CMD ); REG64_FLD( PU_SND_MODE_REG_OVERRIDE_PBINIT_HTM_CMD , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_OVERRIDE_PBINIT_HTM_CMD ); REG64_FLD( PU_SND_MODE_REG_OVERRIDE_PBINIT_TRACE_CMD , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_OVERRIDE_PBINIT_TRACE_CMD ); REG64_FLD( PU_SND_MODE_REG_OVERRIDE_PBINIT_TOD_CMD , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_OVERRIDE_PBINIT_TOD_CMD ); REG64_FLD( PU_SND_MODE_REG_OVERRIDE_PBINIT_XSCOM_CMD , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_OVERRIDE_PBINIT_XSCOM_CMD ); REG64_FLD( PU_SND_MODE_REG_DISABLE_CHECKSTOP , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_CHECKSTOP ); REG64_FLD( PU_SND_MODE_REG_MANUAL_SET_PB_STOP , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_MANUAL_SET_PB_STOP ); REG64_FLD( PU_SND_MODE_REG_MANUAL_CLR_PB_STOP , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_MANUAL_CLR_PB_STOP ); REG64_FLD( PU_SND_MODE_REG_PB_STOP , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_PB_STOP ); REG64_FLD( PU_SND_MODE_REG_MANUAL_PB_SWITCH_ABCD , 25 , SH_UNT , SH_ACS_SCOM , SH_FLD_MANUAL_PB_SWITCH_ABCD ); REG64_FLD( PU_SND_MODE_REG_ENABLE_RECEIVE_OWN_TRIGGER , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_RECEIVE_OWN_TRIGGER ); REG64_FLD( PU_SND_MODE_REG_ENABLE_RECEIVE_OWN_TRIGGER_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_RECEIVE_OWN_TRIGGER_LEN ); REG64_FLD( PU_SND_MODE_REG_ENABLE_RECEIVE_OWN_TOD , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_RECEIVE_OWN_TOD ); REG64_FLD( PU_SND_MODE_REG_RESET_TOD_STATE , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESET_TOD_STATE ); REG64_FLD( PU_SND_MODE_REG_ENABLE_PB_SWITCH_AB , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_PB_SWITCH_AB ); REG64_FLD( PU_SND_MODE_REG_ENABLE_PB_SWITCH_CD , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_PB_SWITCH_CD ); REG64_FLD( PU_SND_STAT_REG_ERR_CMD_OVERRUN , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERR_CMD_OVERRUN ); REG64_FLD( PU_SND_STAT_REG_TRC_CMD_OVERRUN , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRC_CMD_OVERRUN ); REG64_FLD( PU_SND_STAT_REG_XSC_CMD_OVERRUN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_XSC_CMD_OVERRUN ); REG64_FLD( PU_SND_STAT_REG_HTM_CMD_OVERRUN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_HTM_CMD_OVERRUN ); REG64_FLD( PU_SND_STAT_REG_TOD_CMD_OVERRUN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TOD_CMD_OVERRUN ); REG64_FLD( PU_SND_STAT_REG_CMD_COUNT_ERR , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMD_COUNT_ERR ); REG64_FLD( PU_SND_STAT_REG_PB_OP_HANG_ERR , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PB_OP_HANG_ERR ); REG64_FLD( PU_SND_STAT_REG_INVALID_CRESP_ERR , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_INVALID_CRESP_ERR ); REG64_FLD( PU_SND_STAT_REG_RCV_TTAG_PARITY_ERR , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_RCV_TTAG_PARITY_ERR ); REG64_FLD( PU_SND_STAT_REG_RCV_PB_OP_HANG_ERR , 33 , SH_UNT , SH_ACS_SCOM , SH_FLD_RCV_PB_OP_HANG_ERR ); REG64_FLD( PU_SND_STAT_REG_TOD_HANG_ERR , 34 , SH_UNT , SH_ACS_SCOM , SH_FLD_TOD_HANG_ERR ); REG64_FLD( PU_SND_STAT_REG_RCV_TOD_STATE , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_RCV_TOD_STATE ); REG64_FLD( PU_SND_STAT_REG_RCV_TOD_STATE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_RCV_TOD_STATE_LEN ); REG64_FLD( PEC_SPATTN_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM2_NC , SH_FLD_IN ); REG64_FLD( PEC_SPATTN_IN_LEN , 10 , SH_UNT_PEC , SH_ACS_SCOM2_NC , SH_FLD_IN_LEN ); REG64_FLD( PEC_SPA_MASK_IN , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN ); REG64_FLD( PEC_SPA_MASK_IN_LEN , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN_LEN ); REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_FRAME_SIZE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_FRAME_SIZE ); REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_FRAME_SIZE_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_FRAME_SIZE_LEN ); REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_OUT_COUNT , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_OUT_COUNT ); REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_OUT_COUNT_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_OUT_COUNT_LEN ); REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_IN_DELAY , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_IN_DELAY ); REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_IN_DELAY_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_IN_DELAY_LEN ); REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_IN_COUNT , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_IN_COUNT ); REG64_FLD( PU_SPIMPSS_ADC_CTRL_REG0_HWCTRL_IN_COUNT_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_IN_COUNT_LEN ); REG64_FLD( PU_SPIPSS_100NS_REG_OUT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_OUT ); REG64_FLD( PU_SPIPSS_100NS_REG_OUT_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_OUT_LEN ); REG64_FLD( PU_SPIPSS_ADC_CMD_REG_HWCTRL_START_SAMPLING , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_START_SAMPLING ); REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_FSM_ENABLE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_FSM_ENABLE ); REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_DEVICE , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_DEVICE ); REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_CPOL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_CPOL ); REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_CPHA , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_CPHA ); REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_CLOCK_DIVIDER , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_CLOCK_DIVIDER ); REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_CLOCK_DIVIDER_LEN , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_CLOCK_DIVIDER_LEN ); REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_NR_OF_FRAMES , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_NR_OF_FRAMES ); REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_NR_OF_FRAMES_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_NR_OF_FRAMES_LEN ); REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_HWCTRL_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN ); REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_BUSY_RESPONSE_CODE , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUSY_RESPONSE_CODE ); REG64_FLD( PU_SPIPSS_ADC_CTRL_REG1_BUSY_RESPONSE_CODE_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUSY_RESPONSE_CODE_LEN ); REG64_FLD( PU_SPIPSS_ADC_CTRL_REG2_HWCTRL_INTER_FRAME_DELAY , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_INTER_FRAME_DELAY ); REG64_FLD( PU_SPIPSS_ADC_CTRL_REG2_HWCTRL_INTER_FRAME_DELAY_LEN , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_INTER_FRAME_DELAY_LEN ); REG64_FLD( PU_SPIPSS_ADC_RDATA_REG0_HWCTRL_RDATA0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_RDATA0 ); REG64_FLD( PU_SPIPSS_ADC_RDATA_REG0_HWCTRL_RDATA0_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_RDATA0_LEN ); REG64_FLD( PU_SPIPSS_ADC_RDATA_REG1_HWCTRL_RDATA1 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_RDATA1 ); REG64_FLD( PU_SPIPSS_ADC_RDATA_REG1_HWCTRL_RDATA1_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_RDATA1_LEN ); REG64_FLD( PU_SPIPSS_ADC_RDATA_REG2_HWCTRL_RDATA2 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_RDATA2 ); REG64_FLD( PU_SPIPSS_ADC_RDATA_REG2_HWCTRL_RDATA2_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_RDATA2_LEN ); REG64_FLD( PU_SPIPSS_ADC_RDATA_REG3_HWCTRL_RDATA3 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_RDATA3 ); REG64_FLD( PU_SPIPSS_ADC_RDATA_REG3_HWCTRL_RDATA3_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_RDATA3_LEN ); REG64_FLD( PU_SPIPSS_ADC_RESET_REGISTER_HWCTRL , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL ); REG64_FLD( PU_SPIPSS_ADC_RESET_REGISTER_HWCTRL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_LEN ); REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_HWCTRL_ONGOING , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_ONGOING ); REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_RESERVED_1 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_1 ); REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_RESERVED_2 , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_2 ); REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_RESERVED_3 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_3 ); REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_HWCTRL_INVALID_NUMBER_OF_FRAMES , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_INVALID_NUMBER_OF_FRAMES ); REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_HWCTRL_WRITE_WHILE_FSM_BUSY_ERR , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_WRITE_WHILE_FSM_BUSY_ERR ); REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_RESERVED_6 , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_6 ); REG64_FLD( PU_SPIPSS_ADC_STATUS_REG_HWCTRL_FSM_ERR , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_FSM_ERR ); REG64_FLD( PU_SPIPSS_ADC_WDATA_REG_HWCTRL , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL ); REG64_FLD( PU_SPIPSS_ADC_WDATA_REG_HWCTRL_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_HWCTRL_LEN ); REG64_FLD( PU_SPIPSS_P2S_COMMAND_REG_START , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_START ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_FRAME_SIZE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_FRAME_SIZE ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_FRAME_SIZE_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_FRAME_SIZE_LEN ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_OUT_COUNT1 , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_OUT_COUNT1 ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_OUT_COUNT1_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_OUT_COUNT1_LEN ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_DELAY1 , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_DELAY1 ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_DELAY1_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_DELAY1_LEN ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_COUNT1 , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_COUNT1 ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_COUNT1_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_COUNT1_LEN ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_OUT_COUNT2 , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_OUT_COUNT2 ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_OUT_COUNT2_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_OUT_COUNT2_LEN ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_DELAY2 , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_DELAY2 ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_DELAY2_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_DELAY2_LEN ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_COUNT2 , 36 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_COUNT2 ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG0_IN_COUNT2_LEN , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_COUNT2_LEN ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_BRIDGE_ENABLE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_BRIDGE_ENABLE ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_DEVICE , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_DEVICE ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_CPOL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CPOL ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_CPHA , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CPHA ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_CLOCK_DIVIDER , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CLOCK_DIVIDER ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_CLOCK_DIVIDER_LEN , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_CLOCK_DIVIDER_LEN ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_RESERVED , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_RESERVED_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_NR_OF_FRAMES , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_NR_OF_FRAMES ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_WRITE_WHILE_BRIDGE_BUSY_SCRESP_EN ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_BUSY_RESPONSE_CODE_NO_1 , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUSY_RESPONSE_CODE_NO_1 ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG1_BUSY_RESPONSE_CODE_NO_1_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUSY_RESPONSE_CODE_NO_1_LEN ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG2_INTER_FRAME_DELAY , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_INTER_FRAME_DELAY ); REG64_FLD( PU_SPIPSS_P2S_CTRL_REG2_INTER_FRAME_DELAY_LEN , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_INTER_FRAME_DELAY_LEN ); REG64_FLD( PU_SPIPSS_P2S_RDATA_REG_RDATA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RDATA ); REG64_FLD( PU_SPIPSS_P2S_RDATA_REG_RDATA_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_RDATA_LEN ); REG64_FLD( PU_SPIPSS_P2S_RESET_REGISTER_RESET , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESET ); REG64_FLD( PU_SPIPSS_P2S_RESET_REGISTER_RESET_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESET_LEN ); REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_ONGOING , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ONGOING ); REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_RESERVED_1 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_1 ); REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_RESERVED_2 , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_2 ); REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_RESERVED_3 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_3 ); REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_RESERVED_4 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_4 ); REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_WRITE_WHILE_BRIDGE_BUSY_ERR , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_WRITE_WHILE_BRIDGE_BUSY_ERR ); REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_RESERVED6 , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED6 ); REG64_FLD( PU_SPIPSS_P2S_STATUS_REG_FSM_ERR , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_FSM_ERR ); REG64_FLD( PU_SPIPSS_P2S_WDATA_REG_WDATA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_WDATA ); REG64_FLD( PU_SPIPSS_P2S_WDATA_REG_WDATA_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_WDATA_LEN ); REG64_FLD( PU_SRAM_SRBV0_BOOT_VECTOR_WORD0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BOOT_VECTOR_WORD0 ); REG64_FLD( PU_SRAM_SRBV0_BOOT_VECTOR_WORD0_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BOOT_VECTOR_WORD0_LEN ); REG64_FLD( PU_SRAM_SRBV1_BOOT_VECTOR_WORD1 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BOOT_VECTOR_WORD1 ); REG64_FLD( PU_SRAM_SRBV1_BOOT_VECTOR_WORD1_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BOOT_VECTOR_WORD1_LEN ); REG64_FLD( PU_SRAM_SRBV2_BOOT_VECTOR_WORD2 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BOOT_VECTOR_WORD2 ); REG64_FLD( PU_SRAM_SRBV2_BOOT_VECTOR_WORD2_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BOOT_VECTOR_WORD2_LEN ); REG64_FLD( PU_SRAM_SRBV3_BOOT_VECTOR_WORD3 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BOOT_VECTOR_WORD3 ); REG64_FLD( PU_SRAM_SRBV3_BOOT_VECTOR_WORD3_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BOOT_VECTOR_WORD3_LEN ); REG64_FLD( PU_SRAM_SRCHSW_CHKSW_WRFSM_DLY_DIS , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHKSW_WRFSM_DLY_DIS ); REG64_FLD( PU_SRAM_SRCHSW_CHKSW_ALLOW1_RD , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHKSW_ALLOW1_RD ); REG64_FLD( PU_SRAM_SRCHSW_CHKSW_ALLOW1_WR , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHKSW_ALLOW1_WR ); REG64_FLD( PU_SRAM_SRCHSW_CHKSW_ALLOW1_RDWR , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHKSW_ALLOW1_RDWR ); REG64_FLD( PU_SRAM_SRCHSW_CHKSW_OCI_PARCHK_DIS , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHKSW_OCI_PARCHK_DIS ); REG64_FLD( PU_SRAM_SRCHSW_CHKSW_TANK_RDDATA_PARCHK_DIS , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHKSW_TANK_RDDATA_PARCHK_DIS ); REG64_FLD( PU_SRAM_SRCHSW_CHKSW_SPARE_6 , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHKSW_SPARE_6 ); REG64_FLD( PU_SRAM_SRCHSW_CHKSW_VAL_BE_ADDR_CHK_DIS , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHKSW_VAL_BE_ADDR_CHK_DIS ); REG64_FLD( PU_SRAM_SRCHSW_CHKSW_SO_SPARE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHKSW_SO_SPARE ); REG64_FLD( PU_SRAM_SRCHSW_CHKSW_SO_SPARE_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CHKSW_SO_SPARE_LEN ); REG64_FLD( PU_SRAM_SREAR_ERROR_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_ADDRESS ); REG64_FLD( PU_SRAM_SREAR_ERROR_ADDRESS_LEN , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_ADDRESS_LEN ); REG64_FLD( PU_SRAM_SRMAP_REMAP_SOURCE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_REMAP_SOURCE ); REG64_FLD( PU_SRAM_SRMAP_REMAP_SOURCE_LEN , 14 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_REMAP_SOURCE_LEN ); REG64_FLD( PU_SRAM_SRMAP_REMAP_DEST , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_REMAP_DEST ); REG64_FLD( PU_SRAM_SRMAP_REMAP_DEST_LEN , 14 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_REMAP_DEST_LEN ); REG64_FLD( PU_SRAM_SRMR_ENABLE_REMAP , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_REMAP ); REG64_FLD( PU_SRAM_SRMR_ARB_EN_SEND_ALL_WRITES , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ARB_EN_SEND_ALL_WRITES ); REG64_FLD( PU_SRAM_SRMR_DISABLE_LFSR , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DISABLE_LFSR ); REG64_FLD( PU_SRAM_SRMR_LFSR_FAIRNESS_MASK , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LFSR_FAIRNESS_MASK ); REG64_FLD( PU_SRAM_SRMR_LFSR_FAIRNESS_MASK_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LFSR_FAIRNESS_MASK_LEN ); REG64_FLD( PU_SRAM_SRMR_ERROR_INJECT_ENABLE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERROR_INJECT_ENABLE ); REG64_FLD( PU_SRAM_SRMR_CTL_TRACE_EN , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CTL_TRACE_EN ); REG64_FLD( PU_SRAM_SRMR_CTL_TRACE_SEL , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CTL_TRACE_SEL ); REG64_FLD( PU_SRAM_SRMR_SPARE , 11 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SPARE ); REG64_FLD( PU_SRAM_SRMR_SPARE_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SPARE_LEN ); REG64_FLD( PU_STATUS_REGISTER_ADDR_NVLD , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDR_NVLD ); REG64_FLD( PU_STATUS_REGISTER_WRITE_NVLD , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_WRITE_NVLD ); REG64_FLD( PU_STATUS_REGISTER_READ_NVLD , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_READ_NVLD ); REG64_FLD( PU_STATUS_REGISTER_INVLD_CMD_ERR , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_INVLD_CMD_ERR ); REG64_FLD( PU_STATUS_REGISTER_CORR_ERR , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CORR_ERR ); REG64_FLD( PU_STATUS_REGISTER_UNCORR_ERROR , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNCORR_ERROR ); REG64_FLD( PU_STATUS_REGISTER_DATA_REG_0_31 , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_REG_0_31 ); REG64_FLD( PU_STATUS_REGISTER_DATA_REG_0_31_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_REG_0_31_LEN ); REG64_FLD( PU_STATUS_REGISTER_UNUSED_39_43 , 39 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_39_43 ); REG64_FLD( PU_STATUS_REGISTER_UNUSED_39_43_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_39_43_LEN ); REG64_FLD( PU_STATUS_REGISTER_CTRL_BUSY , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_CTRL_BUSY ); REG64_FLD( PU_STATUS_REGISTER_DCOMP_ERR , 45 , SH_UNT , SH_ACS_SCOM , SH_FLD_DCOMP_ERR ); REG64_FLD( PU_STATUS_REGISTER_INVLD_PRGM_ERR , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_INVLD_PRGM_ERR ); REG64_FLD( PU_STATUS_REGISTER_UNUSED_47_51 , 47 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_47_51 ); REG64_FLD( PU_STATUS_REGISTER_UNUSED_47_51_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_47_51_LEN ); REG64_FLD( PU_STATUS_REGISTER_COMMAND_COMPLETE , 52 , SH_UNT , SH_ACS_SCOM , SH_FLD_COMMAND_COMPLETE ); REG64_FLD( PU_STATUS_REGISTER_UNUSED_53 , 53 , SH_UNT , SH_ACS_SCOM , SH_FLD_UNUSED_53 ); REG64_FLD( PU_STATUS_REGISTER_RDWR_OP_BUSY , 54 , SH_UNT , SH_ACS_SCOM , SH_FLD_RDWR_OP_BUSY ); REG64_FLD( PU_STATUS_REGISTER_DCOMP_ENGINE_BUSY , 55 , SH_UNT , SH_ACS_SCOM , SH_FLD_DCOMP_ENGINE_BUSY ); REG64_FLD( PU_STATUS_REGISTER_RD_DATA_COUNT , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_RD_DATA_COUNT ); REG64_FLD( PU_STATUS_REGISTER_RD_DATA_COUNT_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_RD_DATA_COUNT_LEN ); REG64_FLD( PU_STATUS_REGISTER_B_BUS_ADDR_NVLD_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_ADDR_NVLD_0 ); REG64_FLD( PU_STATUS_REGISTER_B_BUS_WRITE_NVLD_0 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_WRITE_NVLD_0 ); REG64_FLD( PU_STATUS_REGISTER_B_BUS_READ_NVLD_0 , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_READ_NVLD_0 ); REG64_FLD( PU_STATUS_REGISTER_B_BUS_ADDR_P_ERR_0 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_ADDR_P_ERR_0 ); REG64_FLD( PU_STATUS_REGISTER_B_BUS_PAR_ERR_0 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_PAR_ERR_0 ); REG64_FLD( PU_STATUS_REGISTER_B_BUS_LB_PARITY_ERROR_0 , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_LB_PARITY_ERROR_0 ); REG64_FLD( PU_STATUS_REGISTER_B_PIB_DATA0TO7_0 , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_DATA0TO7_0 ); REG64_FLD( PU_STATUS_REGISTER_B_PIB_DATA0TO7_0_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_DATA0TO7_0_LEN ); REG64_FLD( PU_STATUS_REGISTER_B_ECC_CORRECTED_ERROR_0 , 41 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_CORRECTED_ERROR_0 ); REG64_FLD( PU_STATUS_REGISTER_B_ECC_UNCORRECTED_ERROR_0 , 42 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_UNCORRECTED_ERROR_0 ); REG64_FLD( PU_STATUS_REGISTER_B_ECC_CONFIG_ERROR_0 , 43 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_CONFIG_ERROR_0 ); REG64_FLD( PU_STATUS_REGISTER_B_BUS_BUSY_0 , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_BUSY_0 ); REG64_FLD( PU_STATUS_REGISTER_B_BUS_INVALID_COMMAND_0 , 45 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_INVALID_COMMAND_0 ); REG64_FLD( PU_STATUS_REGISTER_B_BUS_PARITY_ERROR_0 , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_PARITY_ERROR_0 ); REG64_FLD( PU_STATUS_REGISTER_B_BUS_BACK_END_OVERRUN_ERROR_0 , 47 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_BACK_END_OVERRUN_ERROR_0 ); REG64_FLD( PU_STATUS_REGISTER_B_BUS_BACK_END_ACCESS_ERROR_0 , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_BACK_END_ACCESS_ERROR_0 ); REG64_FLD( PU_STATUS_REGISTER_B_BUS_ARBITRATION_LOST_ERROR_0 , 49 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_ARBITRATION_LOST_ERROR_0 ); REG64_FLD( PU_STATUS_REGISTER_B_BUS_NACK_RECEIVED_ERROR_0 , 50 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_NACK_RECEIVED_ERROR_0 ); REG64_FLD( PU_STATUS_REGISTER_B_BUS_DATA_REQUEST_0 , 51 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_DATA_REQUEST_0 ); REG64_FLD( PU_STATUS_REGISTER_B_BUS_COMMAND_COMPLETE_0 , 52 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_COMMAND_COMPLETE_0 ); REG64_FLD( PU_STATUS_REGISTER_B_BUS_STOP_ERROR_0 , 53 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_STOP_ERROR_0 ); REG64_FLD( PU_STATUS_REGISTER_B_BUS_I2C_PORT_BUSY_0 , 54 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_I2C_PORT_BUSY_0 ); REG64_FLD( PU_STATUS_REGISTER_B_BUS_I2C_INTERFACE_BUSY_0 , 55 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_I2C_INTERFACE_BUSY_0 ); REG64_FLD( PU_STATUS_REGISTER_B_BUS_FIFO_ENTRY_COUNT_0 , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_FIFO_ENTRY_COUNT_0 ); REG64_FLD( PU_STATUS_REGISTER_B_BUS_FIFO_ENTRY_COUNT_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_FIFO_ENTRY_COUNT_0_LEN ); REG64_FLD( PU_STATUS_REGISTER_C_BUS_ADDR_NVLD_1 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_ADDR_NVLD_1 ); REG64_FLD( PU_STATUS_REGISTER_C_BUS_WRITE_NVLD_1 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_WRITE_NVLD_1 ); REG64_FLD( PU_STATUS_REGISTER_C_BUS_READ_NVLD_1 , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_READ_NVLD_1 ); REG64_FLD( PU_STATUS_REGISTER_C_BUS_ADDR_P_ERR_1 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_ADDR_P_ERR_1 ); REG64_FLD( PU_STATUS_REGISTER_C_BUS_PAR_ERR_1 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_PAR_ERR_1 ); REG64_FLD( PU_STATUS_REGISTER_C_BUS_LB_PARITY_ERROR_1 , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_LB_PARITY_ERROR_1 ); REG64_FLD( PU_STATUS_REGISTER_C_PIB_DATA0TO7_1 , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_DATA0TO7_1 ); REG64_FLD( PU_STATUS_REGISTER_C_PIB_DATA0TO7_1_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_DATA0TO7_1_LEN ); REG64_FLD( PU_STATUS_REGISTER_C_ECC_CORRECTED_ERROR_1 , 41 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_CORRECTED_ERROR_1 ); REG64_FLD( PU_STATUS_REGISTER_C_ECC_UNCORRECTED_ERROR_1 , 42 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_UNCORRECTED_ERROR_1 ); REG64_FLD( PU_STATUS_REGISTER_C_ECC_CONFIG_ERROR_1 , 43 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_CONFIG_ERROR_1 ); REG64_FLD( PU_STATUS_REGISTER_C_BUS_BUSY_1 , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_BUSY_1 ); REG64_FLD( PU_STATUS_REGISTER_C_BUS_INVALID_COMMAND_1 , 45 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_INVALID_COMMAND_1 ); REG64_FLD( PU_STATUS_REGISTER_C_BUS_PARITY_ERROR_1 , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_PARITY_ERROR_1 ); REG64_FLD( PU_STATUS_REGISTER_C_BUS_BACK_END_OVERRUN_ERROR_1 , 47 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_BACK_END_OVERRUN_ERROR_1 ); REG64_FLD( PU_STATUS_REGISTER_C_BUS_BACK_END_ACCESS_ERROR_1 , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_BACK_END_ACCESS_ERROR_1 ); REG64_FLD( PU_STATUS_REGISTER_C_BUS_ARBITRATION_LOST_ERROR_1 , 49 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_ARBITRATION_LOST_ERROR_1 ); REG64_FLD( PU_STATUS_REGISTER_C_BUS_NACK_RECEIVED_ERROR_1 , 50 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_NACK_RECEIVED_ERROR_1 ); REG64_FLD( PU_STATUS_REGISTER_C_BUS_DATA_REQUEST_1 , 51 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_DATA_REQUEST_1 ); REG64_FLD( PU_STATUS_REGISTER_C_BUS_COMMAND_COMPLETE_1 , 52 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_COMMAND_COMPLETE_1 ); REG64_FLD( PU_STATUS_REGISTER_C_BUS_STOP_ERROR_1 , 53 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_STOP_ERROR_1 ); REG64_FLD( PU_STATUS_REGISTER_C_BUS_I2C_PORT_BUSY_1 , 54 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_I2C_PORT_BUSY_1 ); REG64_FLD( PU_STATUS_REGISTER_C_BUS_I2C_INTERFACE_BUSY_1 , 55 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_I2C_INTERFACE_BUSY_1 ); REG64_FLD( PU_STATUS_REGISTER_C_BUS_FIFO_ENTRY_COUNT_1 , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_FIFO_ENTRY_COUNT_1 ); REG64_FLD( PU_STATUS_REGISTER_C_BUS_FIFO_ENTRY_COUNT_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_FIFO_ENTRY_COUNT_1_LEN ); REG64_FLD( PU_STATUS_REGISTER_D_BUS_ADDR_NVLD_2 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_ADDR_NVLD_2 ); REG64_FLD( PU_STATUS_REGISTER_D_BUS_WRITE_NVLD_2 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_WRITE_NVLD_2 ); REG64_FLD( PU_STATUS_REGISTER_D_BUS_READ_NVLD_2 , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_READ_NVLD_2 ); REG64_FLD( PU_STATUS_REGISTER_D_BUS_ADDR_P_ERR_2 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_ADDR_P_ERR_2 ); REG64_FLD( PU_STATUS_REGISTER_D_BUS_PAR_ERR_2 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_PAR_ERR_2 ); REG64_FLD( PU_STATUS_REGISTER_D_BUS_LB_PARITY_ERROR_2 , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_LB_PARITY_ERROR_2 ); REG64_FLD( PU_STATUS_REGISTER_D_PIB_DATA0TO7_2 , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_DATA0TO7_2 ); REG64_FLD( PU_STATUS_REGISTER_D_PIB_DATA0TO7_2_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_DATA0TO7_2_LEN ); REG64_FLD( PU_STATUS_REGISTER_D_ECC_CORRECTED_ERROR_2 , 41 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_CORRECTED_ERROR_2 ); REG64_FLD( PU_STATUS_REGISTER_D_ECC_UNCORRECTED_ERROR_2 , 42 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_UNCORRECTED_ERROR_2 ); REG64_FLD( PU_STATUS_REGISTER_D_ECC_CONFIG_ERROR_2 , 43 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_CONFIG_ERROR_2 ); REG64_FLD( PU_STATUS_REGISTER_D_BUS_BUSY_2 , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_BUSY_2 ); REG64_FLD( PU_STATUS_REGISTER_D_BUS_INVALID_COMMAND_2 , 45 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_INVALID_COMMAND_2 ); REG64_FLD( PU_STATUS_REGISTER_D_BUS_PARITY_ERROR_2 , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_PARITY_ERROR_2 ); REG64_FLD( PU_STATUS_REGISTER_D_BUS_BACK_END_OVERRUN_ERROR_2 , 47 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_BACK_END_OVERRUN_ERROR_2 ); REG64_FLD( PU_STATUS_REGISTER_D_BUS_BACK_END_ACCESS_ERROR_2 , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_BACK_END_ACCESS_ERROR_2 ); REG64_FLD( PU_STATUS_REGISTER_D_BUS_ARBITRATION_LOST_ERROR_2 , 49 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_ARBITRATION_LOST_ERROR_2 ); REG64_FLD( PU_STATUS_REGISTER_D_BUS_NACK_RECEIVED_ERROR_2 , 50 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_NACK_RECEIVED_ERROR_2 ); REG64_FLD( PU_STATUS_REGISTER_D_BUS_DATA_REQUEST_2 , 51 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_DATA_REQUEST_2 ); REG64_FLD( PU_STATUS_REGISTER_D_BUS_COMMAND_COMPLETE_2 , 52 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_COMMAND_COMPLETE_2 ); REG64_FLD( PU_STATUS_REGISTER_D_BUS_STOP_ERROR_2 , 53 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_STOP_ERROR_2 ); REG64_FLD( PU_STATUS_REGISTER_D_BUS_I2C_PORT_BUSY_2 , 54 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_I2C_PORT_BUSY_2 ); REG64_FLD( PU_STATUS_REGISTER_D_BUS_I2C_INTERFACE_BUSY_2 , 55 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_I2C_INTERFACE_BUSY_2 ); REG64_FLD( PU_STATUS_REGISTER_D_BUS_FIFO_ENTRY_COUNT_2 , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_FIFO_ENTRY_COUNT_2 ); REG64_FLD( PU_STATUS_REGISTER_D_BUS_FIFO_ENTRY_COUNT_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_FIFO_ENTRY_COUNT_2_LEN ); REG64_FLD( PU_STATUS_REGISTER_E_BUS_ADDR_NVLD_3 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_ADDR_NVLD_3 ); REG64_FLD( PU_STATUS_REGISTER_E_BUS_WRITE_NVLD_3 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_WRITE_NVLD_3 ); REG64_FLD( PU_STATUS_REGISTER_E_BUS_READ_NVLD_3 , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_READ_NVLD_3 ); REG64_FLD( PU_STATUS_REGISTER_E_BUS_ADDR_P_ERR_3 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_ADDR_P_ERR_3 ); REG64_FLD( PU_STATUS_REGISTER_E_BUS_PAR_ERR_3 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_PAR_ERR_3 ); REG64_FLD( PU_STATUS_REGISTER_E_BUS_LB_PARITY_ERROR_3 , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_LB_PARITY_ERROR_3 ); REG64_FLD( PU_STATUS_REGISTER_E_PIB_DATA0TO7_3 , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_DATA0TO7_3 ); REG64_FLD( PU_STATUS_REGISTER_E_PIB_DATA0TO7_3_LEN , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_DATA0TO7_3_LEN ); REG64_FLD( PU_STATUS_REGISTER_E_ECC_CORRECTED_ERROR_3 , 41 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_CORRECTED_ERROR_3 ); REG64_FLD( PU_STATUS_REGISTER_E_ECC_UNCORRECTED_ERROR_3 , 42 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_UNCORRECTED_ERROR_3 ); REG64_FLD( PU_STATUS_REGISTER_E_ECC_CONFIG_ERROR_3 , 43 , SH_UNT , SH_ACS_SCOM , SH_FLD_ECC_CONFIG_ERROR_3 ); REG64_FLD( PU_STATUS_REGISTER_E_BUS_BUSY_3 , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_BUSY_3 ); REG64_FLD( PU_STATUS_REGISTER_E_BUS_INVALID_COMMAND_3 , 45 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_INVALID_COMMAND_3 ); REG64_FLD( PU_STATUS_REGISTER_E_BUS_PARITY_ERROR_3 , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_PARITY_ERROR_3 ); REG64_FLD( PU_STATUS_REGISTER_E_BUS_BACK_END_OVERRUN_ERROR_3 , 47 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_BACK_END_OVERRUN_ERROR_3 ); REG64_FLD( PU_STATUS_REGISTER_E_BUS_BACK_END_ACCESS_ERROR_3 , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_BACK_END_ACCESS_ERROR_3 ); REG64_FLD( PU_STATUS_REGISTER_E_BUS_ARBITRATION_LOST_ERROR_3 , 49 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_ARBITRATION_LOST_ERROR_3 ); REG64_FLD( PU_STATUS_REGISTER_E_BUS_NACK_RECEIVED_ERROR_3 , 50 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_NACK_RECEIVED_ERROR_3 ); REG64_FLD( PU_STATUS_REGISTER_E_BUS_DATA_REQUEST_3 , 51 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_DATA_REQUEST_3 ); REG64_FLD( PU_STATUS_REGISTER_E_BUS_COMMAND_COMPLETE_3 , 52 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_COMMAND_COMPLETE_3 ); REG64_FLD( PU_STATUS_REGISTER_E_BUS_STOP_ERROR_3 , 53 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_STOP_ERROR_3 ); REG64_FLD( PU_STATUS_REGISTER_E_BUS_I2C_PORT_BUSY_3 , 54 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_I2C_PORT_BUSY_3 ); REG64_FLD( PU_STATUS_REGISTER_E_BUS_I2C_INTERFACE_BUSY_3 , 55 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_I2C_INTERFACE_BUSY_3 ); REG64_FLD( PU_STATUS_REGISTER_E_BUS_FIFO_ENTRY_COUNT_3 , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_FIFO_ENTRY_COUNT_3 ); REG64_FLD( PU_STATUS_REGISTER_E_BUS_FIFO_ENTRY_COUNT_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUS_FIFO_ENTRY_COUNT_3_LEN ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_INVALID_CMD_0 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_INVALID_CMD_0 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_LBUS_PARITY_ERROR_0 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERROR_0 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_BE_OV_ERROR_0 , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_BE_OV_ERROR_0 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_BE_ACC_ERROR_0 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_BE_ACC_ERROR_0 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_ARBITRATION_LOST_ERROR_0 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_ARBITRATION_LOST_ERROR_0 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_NACK_RECEIVED_ERROR_0 , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_NACK_RECEIVED_ERROR_0 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_DATA_REQUEST_0 , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_REQUEST_0 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_STOP_ERROR_0 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_STOP_ERROR_0 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_BUSY , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUSY ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_SELF_BUSY_0 , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_SELF_BUSY_0 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_FIFO_ENTRY_COUNT_0 , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_ENTRY_COUNT_0 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_FIFO_ENTRY_COUNT_0_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_ENTRY_COUNT_0_LEN ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_PEEK_DATA1_0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_PEEK_DATA1_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0_LEN ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_LBUS_PARITY_ERR1_0 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_0 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_I2CM_STEERED_INTERRUPTS_0 , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_I2CM_STEERED_INTERRUPTS_0 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_B_I2CM_STEERED_INTERRUPTS_0_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_I2CM_STEERED_INTERRUPTS_0_LEN ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_INVALID_CMD_1 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_INVALID_CMD_1 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_LBUS_PARITY_ERROR_1 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERROR_1 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_BE_OV_ERROR_1 , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_BE_OV_ERROR_1 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_BE_ACC_ERROR_1 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_BE_ACC_ERROR_1 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_ARBITRATION_LOST_ERROR_1 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_ARBITRATION_LOST_ERROR_1 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_NACK_RECEIVED_ERROR_1 , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_NACK_RECEIVED_ERROR_1 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_DATA_REQUEST_1 , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_REQUEST_1 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_STOP_ERROR_1 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_STOP_ERROR_1 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_BUSY , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUSY ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_SELF_BUSY_1 , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_SELF_BUSY_1 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_FIFO_ENTRY_COUNT_1 , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_ENTRY_COUNT_1 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_FIFO_ENTRY_COUNT_1_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_ENTRY_COUNT_1_LEN ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_PEEK_DATA1_1 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_PEEK_DATA1_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1_LEN ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_LBUS_PARITY_ERR1_1 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_1 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_I2CM_STEERED_INTERRUPTS_1 , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_I2CM_STEERED_INTERRUPTS_1 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_C_I2CM_STEERED_INTERRUPTS_1_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_I2CM_STEERED_INTERRUPTS_1_LEN ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_INVALID_CMD_2 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_INVALID_CMD_2 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_LBUS_PARITY_ERROR_2 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERROR_2 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_BE_OV_ERROR_2 , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_BE_OV_ERROR_2 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_BE_ACC_ERROR_2 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_BE_ACC_ERROR_2 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_ARBITRATION_LOST_ERROR_2 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_ARBITRATION_LOST_ERROR_2 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_NACK_RECEIVED_ERROR_2 , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_NACK_RECEIVED_ERROR_2 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_DATA_REQUEST_2 , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_REQUEST_2 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_STOP_ERROR_2 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_STOP_ERROR_2 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_BUSY , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUSY ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_SELF_BUSY_2 , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_SELF_BUSY_2 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_FIFO_ENTRY_COUNT_2 , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_ENTRY_COUNT_2 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_FIFO_ENTRY_COUNT_2_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_ENTRY_COUNT_2_LEN ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_PEEK_DATA1_2 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_PEEK_DATA1_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2_LEN ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_LBUS_PARITY_ERR1_2 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_2 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_I2CM_STEERED_INTERRUPTS_2 , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_I2CM_STEERED_INTERRUPTS_2 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_D_I2CM_STEERED_INTERRUPTS_2_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_I2CM_STEERED_INTERRUPTS_2_LEN ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_INVALID_CMD_3 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_INVALID_CMD_3 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_LBUS_PARITY_ERROR_3 , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERROR_3 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_BE_OV_ERROR_3 , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_BE_OV_ERROR_3 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_BE_ACC_ERROR_3 , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_BE_ACC_ERROR_3 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_ARBITRATION_LOST_ERROR_3 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_ARBITRATION_LOST_ERROR_3 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_NACK_RECEIVED_ERROR_3 , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_NACK_RECEIVED_ERROR_3 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_DATA_REQUEST_3 , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_REQUEST_3 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_STOP_ERROR_3 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_STOP_ERROR_3 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_BUSY , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_BUSY ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_SELF_BUSY_3 , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_SELF_BUSY_3 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_FIFO_ENTRY_COUNT_3 , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_ENTRY_COUNT_3 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_FIFO_ENTRY_COUNT_3_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_FIFO_ENTRY_COUNT_3_LEN ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_PEEK_DATA1_3 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_PEEK_DATA1_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3_LEN ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_I2CM_STEERED_INTERRUPTS_3 , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_I2CM_STEERED_INTERRUPTS_3 ); REG64_FLD( PU_STATUS_REGISTER_ENGINE_E_I2CM_STEERED_INTERRUPTS_3_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_I2CM_STEERED_INTERRUPTS_3_LEN ); REG64_FLD( PEC_SUM_MASK_REG_SMASK_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SMASK_IN0 ); REG64_FLD( PEC_SUM_MASK_REG_SMASK_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SMASK_IN1 ); REG64_FLD( PEC_SUM_MASK_REG_SMASK_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SMASK_IN2 ); REG64_FLD( PEC_SUM_MASK_REG_SMASK_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SMASK_IN3 ); REG64_FLD( PEC_SUM_MASK_REG_SMASK_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SMASK_IN4 ); REG64_FLD( PU_SU_CRB_KILL_REQ_ENABLE , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE ); REG64_FLD( PU_SU_CRB_KILL_REQ_DONE , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DONE ); REG64_FLD( PU_SU_CRB_KILL_REQ_SUMMARY , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SUMMARY ); REG64_FLD( PU_SU_CRB_KILL_REQ_DISPATCH_SLOT_KILLED_CNT , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DISPATCH_SLOT_KILLED_CNT ); REG64_FLD( PU_SU_CRB_KILL_REQ_DISPATCH_SLOT_KILLED_CNT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DISPATCH_SLOT_KILLED_CNT_LEN ); REG64_FLD( PU_SU_CRB_KILL_REQ_PREFETCH_CHANNEL_CNT , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PREFETCH_CHANNEL_CNT ); REG64_FLD( PU_SU_CRB_KILL_REQ_PREFETCH_CHANNEL_CNT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PREFETCH_CHANNEL_CNT_LEN ); REG64_FLD( PU_SU_CRB_KILL_REQ_ACTIVE_CHANNEL_CNT , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTIVE_CHANNEL_CNT ); REG64_FLD( PU_SU_CRB_KILL_REQ_ACTIVE_CHANNEL_CNT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTIVE_CHANNEL_CNT_LEN ); REG64_FLD( PU_SU_CRB_KILL_REQ_SWC_VALUE , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SWC_VALUE ); REG64_FLD( PU_SU_CRB_KILL_REQ_SWC_VALUE_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SWC_VALUE_LEN ); REG64_FLD( PU_SU_DMA_ERROR_REPORT_0_0 , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_0 ); REG64_FLD( PU_SU_DMA_ERROR_REPORT_0_0_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_0_LEN ); REG64_FLD( PU_SU_DMA_ERROR_REPORT_1_1 , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_1 ); REG64_FLD( PU_SU_DMA_ERROR_REPORT_1_1_LEN , 17 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_1_LEN ); REG64_FLD( PU_SU_ENGINE_ENABLE_ALLOW_CRYPTO , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ALLOW_CRYPTO ); REG64_FLD( PU_SU_ENGINE_ENABLE_CH3_SYM , 57 , SH_UNT , SH_ACS_SCOM , SH_FLD_CH3_SYM ); REG64_FLD( PU_SU_ENGINE_ENABLE_CH2_SYM , 58 , SH_UNT , SH_ACS_SCOM , SH_FLD_CH2_SYM ); REG64_FLD( PU_SU_ENGINE_ENABLE_CH4_GZIP , 61 , SH_UNT , SH_ACS_SCOM , SH_FLD_CH4_GZIP ); REG64_FLD( PU_SU_ENGINE_ENABLE_CH1_EFT , 62 , SH_UNT , SH_ACS_SCOM , SH_FLD_CH1_EFT ); REG64_FLD( PU_SU_ENGINE_ENABLE_CH0_EFT , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_CH0_EFT ); REG64_FLD( PU_SU_ERAT_ERROR_RPT_RPT , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RPT ); REG64_FLD( PU_SU_ERAT_ERROR_RPT_RPT_LEN , 48 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RPT_LEN ); REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_GZIPCOMP_MAX_INRD , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GZIPCOMP_MAX_INRD ); REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_GZIPCOMP_MAX_INRD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GZIPCOMP_MAX_INRD_LEN ); REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_GZIPDECOMP_MAX_INRD , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GZIPDECOMP_MAX_INRD ); REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_GZIPDECOMP_MAX_INRD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GZIPDECOMP_MAX_INRD_LEN ); REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_GZIP_COMP_PREFETCH_ENABLE , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GZIP_COMP_PREFETCH_ENABLE ); REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_GZIP_DECOMP_PREFETCH_ENABLE , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GZIP_DECOMP_PREFETCH_ENABLE ); REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_EFT_COMP_PREFETCH_ENABLE , 23 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EFT_COMP_PREFETCH_ENABLE ); REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_EFT_DECOMP_PREFETCH_ENABLE , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EFT_DECOMP_PREFETCH_ENABLE ); REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_SYM_MAX_INRD , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SYM_MAX_INRD ); REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_SYM_MAX_INRD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SYM_MAX_INRD_LEN ); REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_EFTCOMP_MAX_INRD , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EFTCOMP_MAX_INRD ); REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_EFTCOMP_MAX_INRD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EFTCOMP_MAX_INRD_LEN ); REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_EFTDECOMP_MAX_INRD , 37 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EFTDECOMP_MAX_INRD ); REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_EFTDECOMP_MAX_INRD_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EFTDECOMP_MAX_INRD_LEN ); REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_SYM_CPB_CHECK_DISABLE , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SYM_CPB_CHECK_DISABLE ); REG64_FLD( PU_SU_INBOUND_WRITE_CONTROL_EFT_SPBC_ENABLE , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EFT_SPBC_ENABLE ); REG64_FLD( PU_SU_PERFMON_CONTROL_0_LPID , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LPID ); REG64_FLD( PU_SU_PERFMON_CONTROL_0_LPID_LEN , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LPID_LEN ); REG64_FLD( PU_SU_PERFMON_CONTROL_0_LPID_MASK , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LPID_MASK ); REG64_FLD( PU_SU_PERFMON_CONTROL_0_LPID_MASK_LEN , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LPID_MASK_LEN ); REG64_FLD( PU_SU_PERFMON_CONTROL_0_PID , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PID ); REG64_FLD( PU_SU_PERFMON_CONTROL_0_PID_LEN , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PID_LEN ); REG64_FLD( PU_SU_PERFMON_CONTROL_0_PID_MASK , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PID_MASK ); REG64_FLD( PU_SU_PERFMON_CONTROL_0_PID_MASK_LEN , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PID_MASK_LEN ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_GZIP_FC_SELECT , 27 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GZIP_FC_SELECT ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_GZIP_FC_SELECT_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GZIP_FC_SELECT_LEN ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_842_FC_SELECT , 29 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_842_FC_SELECT ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_842_FC_SELECT_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_842_FC_SELECT_LEN ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_DMA_MUX_SELECT , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_MUX_SELECT ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_DMA_MUX_SELECT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_MUX_SELECT_LEN ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_EFT_MUX_SELECT , 35 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EFT_MUX_SELECT ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_EFT_MUX_SELECT_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EFT_MUX_SELECT_LEN ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_GZIP_MUX_SELECT , 38 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GZIP_MUX_SELECT ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_GZIP_MUX_SELECT_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GZIP_MUX_SELECT_LEN ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_ERAT_MUX_SELECT , 41 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERAT_MUX_SELECT ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_ERAT_MUX_SELECT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ERAT_MUX_SELECT_LEN ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_UMAC_MUX_SELECT , 45 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_UMAC_MUX_SELECT ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_UMAC_MUX_SELECT_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_UMAC_MUX_SELECT_LEN ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_PBI_MUX_SELECT , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBI_MUX_SELECT ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_PBI_MUX_SELECT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBI_MUX_SELECT_LEN ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_SHA_LATENCY_CFG , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SHA_LATENCY_CFG ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_MD5_LATENCY_CFG , 54 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MD5_LATENCY_CFG ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_AES_LATENCY_CFG , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_AES_LATENCY_CFG ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_AESSHA_LATENCY_CFG , 58 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_AESSHA_LATENCY_CFG ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_GZIP_LATENCY_CFG , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_GZIP_LATENCY_CFG ); REG64_FLD( PU_SU_PERFMON_CONTROL_1_842_LATENCY_CFG , 62 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_842_LATENCY_CFG ); REG64_FLD( PU_SU_STATUS_HMI_ACTIVE , 54 , SH_UNT , SH_ACS_SCOM , SH_FLD_HMI_ACTIVE ); REG64_FLD( PU_SU_STATUS_PBI_IDLE , 55 , SH_UNT , SH_ACS_SCOM , SH_FLD_PBI_IDLE ); REG64_FLD( PU_SU_STATUS_DMA_CH0_IDLE , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_CH0_IDLE ); REG64_FLD( PU_SU_STATUS_DMA_CH1_IDLE , 57 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_CH1_IDLE ); REG64_FLD( PU_SU_STATUS_DMA_CH2_IDLE , 58 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_CH2_IDLE ); REG64_FLD( PU_SU_STATUS_DMA_CH3_IDLE , 59 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_CH3_IDLE ); REG64_FLD( PU_SU_STATUS_DMA_CH4_IDLE , 60 , SH_UNT , SH_ACS_SCOM , SH_FLD_DMA_CH4_IDLE ); REG64_FLD( PU_SU_UMAC_ERROR_RPT_RPT , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RPT ); REG64_FLD( PU_SU_UMAC_ERROR_RPT_RPT_LEN , 56 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RPT_LEN ); REG64_FLD( PU_SU_UMAC_ERROR_RPT1_RPT1 , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RPT1 ); REG64_FLD( PU_SU_UMAC_ERROR_RPT1_RPT1_LEN , 6 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RPT1_LEN ); REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LPID ); REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LPID_LEN ); REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_PID ); REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_PID_LEN ); REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_TID ); REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_TID_LEN ); REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_ENABLE ); REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_BAR_PRIORITY , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY ); REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LEN ); REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE , 54 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_SIZE ); REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_SIZE_LEN ); REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_READ_OFFSET ); REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_READ_OFFSET_LEN ); REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_QUEUED ); REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_QUEUED_LEN ); REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_PRIMAX ); REG64_FLD( PU_SYM_HI_PRIOR_RCV_FIFO_CNTL_PRIORITY_PRIMAX_LEN , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_PRIMAX_LEN ); REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LPID ); REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_LPID_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LPID_LEN ); REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_PID ); REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_PID_LEN , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_PID_LEN ); REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID , 44 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_TID ); REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_TID_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_TID_LEN ); REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_ASB_PRIORITY_ENABLE , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_ENABLE ); REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_BAR_PRIORITY , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY ); REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_LEN , 46 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_LEN ); REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE , 54 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_SIZE ); REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_BAR_PRIORITY_SIZE_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_SIZE_LEN ); REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_READ_OFFSET ); REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_READ_OFFSET_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_READ_OFFSET_LEN ); REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_QUEUED ); REG64_FLD( PU_SYM_LO_PRIOR_RCV_FIFO_CNTL_PRIORITY_QUEUED_LEN , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_PRIORITY_QUEUED_LEN ); REG64_FLD( PU_SYM_MAX_BYTE_CNT_LIMIT , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LIMIT ); REG64_FLD( PU_SYM_MAX_BYTE_CNT_LIMIT_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_LIMIT_LEN ); REG64_FLD( PU_SYM_MAX_BYTE_CNT_SRC_DDE , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRC_DDE ); REG64_FLD( PU_SYM_MAX_BYTE_CNT_SRC_DDE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SRC_DDE_LEN ); REG64_FLD( PU_SYM_MAX_BYTE_CNT_TARGET_DDE , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_TARGET_DDE ); REG64_FLD( PU_SYM_MAX_BYTE_CNT_TARGET_DDE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_TARGET_DDE_LEN ); REG64_FLD( PEC_SYNC_CONFIG_PULSE_DELAY , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PULSE_DELAY ); REG64_FLD( PEC_SYNC_CONFIG_PULSE_DELAY_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PULSE_DELAY_LEN ); REG64_FLD( PEC_SYNC_CONFIG_LISTEN_TO_PULSE_DIS , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_LISTEN_TO_PULSE_DIS ); REG64_FLD( PEC_SYNC_CONFIG_PULSE_INPUT_SEL , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PULSE_INPUT_SEL ); REG64_FLD( PEC_SYNC_CONFIG_USE_FOR_SCAN , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_USE_FOR_SCAN ); REG64_FLD( PEC_SYNC_CONFIG_CLEAR_CHIPLET_IS_ALIGNED , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CLEAR_CHIPLET_IS_ALIGNED ); REG64_FLD( PEC_SYNC_CONFIG_UNIT_REGION_CLKCMD_DISABLE , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT_REGION_CLKCMD_DISABLE ); REG64_FLD( PEC_SYNC_CONFIG_DISABLE_PCB_ITR , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DISABLE_PCB_ITR ); REG64_FLD( PEC_SYNC_CONFIG_ENABLE_VITL_ALIGN_CHECK , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ENABLE_VITL_ALIGN_CHECK ); REG64_FLD( PEC_SYNC_CONFIG_UNUSED1119 , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED1119 ); REG64_FLD( PEC_SYNC_CONFIG_UNUSED1119_LEN , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED1119_LEN ); REG64_FLD( PU_SYNC_FIR_ACTION0_REG_INVALID_TRANSFER_SIZE , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INVALID_TRANSFER_SIZE ); REG64_FLD( PU_SYNC_FIR_ACTION0_REG_INVALID_COMMAND , 1 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INVALID_COMMAND ); REG64_FLD( PU_SYNC_FIR_ACTION0_REG_INVALID_ADDRESS_ALIGNMENT , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INVALID_ADDRESS_ALIGNMENT ); REG64_FLD( PU_SYNC_FIR_ACTION0_REG_OPB_ERROR , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OPB_ERROR ); REG64_FLD( PU_SYNC_FIR_ACTION0_REG_OPB_TIMEOUT , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OPB_TIMEOUT ); REG64_FLD( PU_SYNC_FIR_ACTION0_REG_OPB_MASTER_HANG_TIMEOUT , 5 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OPB_MASTER_HANG_TIMEOUT ); REG64_FLD( PU_SYNC_FIR_ACTION0_REG_CMD_BUFFER_PAR_ERR , 6 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CMD_BUFFER_PAR_ERR ); REG64_FLD( PU_SYNC_FIR_ACTION0_REG_DAT_BUFFER_PAR_ERR , 7 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DAT_BUFFER_PAR_ERR ); REG64_FLD( PU_SYNC_FIR_ACTION0_REG_RETURNQ_ERR , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RETURNQ_ERR ); REG64_FLD( PU_SYNC_FIR_ACTION0_REG_RESERVED , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RESERVED ); REG64_FLD( PU_SYNC_FIR_ACTION0_REG_SCOM_PARITY_ERR2 , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SCOM_PARITY_ERR2 ); REG64_FLD( PU_SYNC_FIR_ACTION0_REG_SCOM_PARITY_ERR , 11 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SCOM_PARITY_ERR ); REG64_FLD( PU_SYNC_FIR_ACTION1_REG_INVALID_TRANSFER_SIZE , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INVALID_TRANSFER_SIZE ); REG64_FLD( PU_SYNC_FIR_ACTION1_REG_INVALID_COMMAND , 1 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INVALID_COMMAND ); REG64_FLD( PU_SYNC_FIR_ACTION1_REG_INVALID_ADDRESS_ALIGNMENT , 2 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_INVALID_ADDRESS_ALIGNMENT ); REG64_FLD( PU_SYNC_FIR_ACTION1_REG_OPB_ERROR , 3 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OPB_ERROR ); REG64_FLD( PU_SYNC_FIR_ACTION1_REG_OPB_TIMEOUT , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OPB_TIMEOUT ); REG64_FLD( PU_SYNC_FIR_ACTION1_REG_OPB_MASTER_HANG_TIMEOUT , 5 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_OPB_MASTER_HANG_TIMEOUT ); REG64_FLD( PU_SYNC_FIR_ACTION1_REG_CMD_BUFFER_PAR_ERR , 6 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CMD_BUFFER_PAR_ERR ); REG64_FLD( PU_SYNC_FIR_ACTION1_REG_DAT_BUFFER_PAR_ERR , 7 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DAT_BUFFER_PAR_ERR ); REG64_FLD( PU_SYNC_FIR_ACTION1_REG_RETURNQ_ERR , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RETURNQ_ERR ); REG64_FLD( PU_SYNC_FIR_ACTION1_REG_RESERVED , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RESERVED ); REG64_FLD( PU_SYNC_FIR_ACTION1_REG_SCOM_PARITY_ERR2 , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SCOM_PARITY_ERR2 ); REG64_FLD( PU_SYNC_FIR_ACTION1_REG_SCOM_PARITY_ERR , 11 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_SCOM_PARITY_ERR ); REG64_FLD( PU_SYNC_FIR_MASK_REG_INVALID_TRANSFER_SIZE , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INVALID_TRANSFER_SIZE ); REG64_FLD( PU_SYNC_FIR_MASK_REG_INVALID_COMMAND , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INVALID_COMMAND ); REG64_FLD( PU_SYNC_FIR_MASK_REG_INVALID_ADDRESS_ALIGNMENT , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INVALID_ADDRESS_ALIGNMENT ); REG64_FLD( PU_SYNC_FIR_MASK_REG_OPB_ERROR , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OPB_ERROR ); REG64_FLD( PU_SYNC_FIR_MASK_REG_OPB_TIMEOUT , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OPB_TIMEOUT ); REG64_FLD( PU_SYNC_FIR_MASK_REG_OPB_MASTER_HANG_TIMEOUT , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OPB_MASTER_HANG_TIMEOUT ); REG64_FLD( PU_SYNC_FIR_MASK_REG_CMD_BUFFER_PAR_ERR , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CMD_BUFFER_PAR_ERR ); REG64_FLD( PU_SYNC_FIR_MASK_REG_DAT_BUFFER_PAR_ERR , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DAT_BUFFER_PAR_ERR ); REG64_FLD( PU_SYNC_FIR_MASK_REG_RETURNQ_ERR , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RETURNQ_ERR ); REG64_FLD( PU_SYNC_FIR_MASK_REG_RESERVED , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED ); REG64_FLD( PU_SYNC_FIR_MASK_REG_SCOM_PARITY_ERR2 , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PARITY_ERR2 ); REG64_FLD( PU_SYNC_FIR_MASK_REG_SCOM_PARITY_ERR , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_PARITY_ERR ); REG64_FLD( PU_SYNC_FIR_REG_INVALID_TRANSFER_SIZE , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INVALID_TRANSFER_SIZE ); REG64_FLD( PU_SYNC_FIR_REG_INVALID_COMMAND , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INVALID_COMMAND ); REG64_FLD( PU_SYNC_FIR_REG_INVALID_ADDRESS_ALIGNMENT , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INVALID_ADDRESS_ALIGNMENT ); REG64_FLD( PU_SYNC_FIR_REG_OPB_ERROR , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OPB_ERROR ); REG64_FLD( PU_SYNC_FIR_REG_OPB_TIMEOUT , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OPB_TIMEOUT ); REG64_FLD( PU_SYNC_FIR_REG_OPB_MASTER_HANG_TIMEOUT , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_OPB_MASTER_HANG_TIMEOUT ); REG64_FLD( PU_SYNC_FIR_REG_CMD_BUFFER_PAR_ERR , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CMD_BUFFER_PAR_ERR ); REG64_FLD( PU_SYNC_FIR_REG_DAT_BUFFER_PAR_ERR , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DAT_BUFFER_PAR_ERR ); REG64_FLD( PU_SYNC_FIR_REG_RETURNQ_ERR , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RETURNQ_ERR ); REG64_FLD( PU_SYNC_FIR_REG_RESERVED , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RESERVED ); REG64_FLD( PU_SYNC_FIR_REG_PARITY_ERR2 , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERR2 ); REG64_FLD( PU_SYNC_FIR_REG_PARITY_ERR , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PARITY_ERR ); REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_ALL , 0 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_INVALIDATE_ALL ); REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_ONE , 2 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_INVALIDATE_ONE ); REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_PE_NUMBER , 4 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_INVALIDATE_PE_NUMBER ); REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_PE_NUMBER_LEN , 4 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_INVALIDATE_PE_NUMBER_LEN ); REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_ADDRESS , 15 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_INVALIDATE_ADDRESS ); REG64_FLD( PU_NPU_SM1_TCE_KILL_INVALIDATE_ADDRESS_LEN , 37 , SH_UNT_PU_NPU_SM1, SH_ACS_SCOM , SH_FLD_INVALIDATE_ADDRESS_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCMC01_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCMC01_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCMC23_FAST_TRA0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCMC23_FAST_TRA1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN0_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN0_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN1_TRA4_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN2_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN2_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA0_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA1_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA1_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA2_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA2_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA3_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA3_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA4_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA5_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PU_TCN3_TRA5_TR1_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_HI_DATA_REG_DATA , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_HI_DATA_REG_DATA_LEN , 64 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_DATA , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_DATA ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_DATA_LEN , 32 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_DATA_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS , 32 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_ADDRESS ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_ADDRESS_LEN , 10 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_ADDRESS_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK , 42 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_LEN , 9 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_LAST_BANK_VALID , 51 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_LAST_BANK_VALID ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_WRITE_ON_RUN , 52 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_WRITE_ON_RUN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_RUNNING , 53 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_RUNNING ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS , 54 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_LO_DATA_REG_HOLD_ADDRESS_LEN , 10 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_HOLD_ADDRESS_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRCTRL_CONFIG_STORE_ON_TRIG_MODE_LEN , 22 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_STORE_ON_TRIG_MODE_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63 , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63 ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_0_CMP_MSK_LT_B_TO_63_LEN , 64 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_TO_63_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87 , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87 ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_1_CMP_MSK_LT_B_64_TO_87_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_CMP_MSK_LT_B_64_TO_87_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PATTERNA ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNA_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PATTERNA_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PATTERNB ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_2_PATTERNB_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PATTERNB_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PATTERNC ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERNC_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PATTERNC_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PATTERND ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_3_PATTERND_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PATTERND_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MASKA ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKA_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MASKA_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MASKB ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_4_MASKB_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MASKB_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MASKC ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKC_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MASKC_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MASKD ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_5_MASKD_LEN , 24 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MASKD_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_DISABLE_COMPRESSION , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DISABLE_COMPRESSION ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_ERROR_BIT_COMPRESSION_CARE_MASK , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_ERROR_BIT_COMPRESSION_CARE_MASK ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHA_MUXSEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MATCHA_MUXSEL_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHB_MUXSEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MATCHB_MUXSEL_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHC_MUXSEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MATCHC_MUXSEL_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCHD_MUXSEL_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MATCHD_MUXSEL_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_OR_MASK_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIG0_OR_MASK_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_AND_MASK_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIG0_AND_MASK_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK , 18 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_OR_MASK_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIG1_OR_MASK_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK , 22 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_AND_MASK_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIG1_AND_MASK_LEN ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG0_NOT_MODE , 26 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIG0_NOT_MODE ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_TRIG1_NOT_MODE , 27 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIG1_NOT_MODE ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE , 28 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE ); REG64_FLD( PEC_TCPCI0_TRA0_TR0_TRACE_TRDATA_CONFIG_9_MATCH_NOT_MODE_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MATCH_NOT_MODE_LEN ); REG64_FLD( PU_NPU_SM2_TEST_CERR_ATR_ERR_INJ_PEND , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATR_ERR_INJ_PEND ); REG64_FLD( PU_NPU_SM2_TEST_CERR_MAP_ERR_INJ_PEND , 1 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_MAP_ERR_INJ_PEND ); REG64_FLD( PU_NPU_SM2_TEST_CERR_REGSEL , 56 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_REGSEL ); REG64_FLD( PU_NPU_SM2_TEST_CERR_REGSEL_LEN , 2 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_REGSEL_LEN ); REG64_FLD( PU_NPU_SM2_TEST_CERR_BITSEL , 58 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_BITSEL ); REG64_FLD( PU_NPU_SM2_TEST_CERR_BITSEL_LEN , 6 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_BITSEL_LEN ); REG64_FLD( CAPP_TFMR_CHIP_TOD_STATUS , 47 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_CHIP_TOD_STATUS ); REG64_FLD( CAPP_TFMR_CHIP_TOD_STATUS_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_CHIP_TOD_STATUS_LEN ); REG64_FLD( PEC_THERM_MODE_REG_DIS_CPM_BUBBLE_CORR , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DIS_CPM_BUBBLE_CORR ); REG64_FLD( PEC_THERM_MODE_REG_FORCE_THRES_ACT , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_FORCE_THRES_ACT ); REG64_FLD( PEC_THERM_MODE_REG_THRES_TRIP_ENA , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_THRES_TRIP_ENA ); REG64_FLD( PEC_THERM_MODE_REG_THRES_TRIP_ENA_LEN , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_THRES_TRIP_ENA_LEN ); REG64_FLD( PEC_THERM_MODE_REG_DTS_SAMPLE_ENA , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DTS_SAMPLE_ENA ); REG64_FLD( PEC_THERM_MODE_REG_SAMPLE_PULSE_CNT , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SAMPLE_PULSE_CNT ); REG64_FLD( PEC_THERM_MODE_REG_SAMPLE_PULSE_CNT_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_SAMPLE_PULSE_CNT_LEN ); REG64_FLD( PEC_THERM_MODE_REG_THRES_ENA , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_THRES_ENA ); REG64_FLD( PEC_THERM_MODE_REG_THRES_ENA_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_THRES_ENA_LEN ); REG64_FLD( PEC_THERM_MODE_REG_DTS_TRIGGER , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DTS_TRIGGER ); REG64_FLD( PEC_THERM_MODE_REG_DTS_TRIGGER_SEL , 13 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DTS_TRIGGER_SEL ); REG64_FLD( PEC_THERM_MODE_REG_THRES_OVERFLOW_MASK , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_THRES_OVERFLOW_MASK ); REG64_FLD( PEC_THERM_MODE_REG_UNUSED , 15 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( PEC_THERM_MODE_REG_DTS_READ_SEL , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DTS_READ_SEL ); REG64_FLD( PEC_THERM_MODE_REG_DTS_READ_SEL_LEN , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DTS_READ_SEL_LEN ); REG64_FLD( PEC_THERM_MODE_REG_DTS_ENABLE_L1 , 20 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DTS_ENABLE_L1 ); REG64_FLD( PEC_THERM_MODE_REG_DTS_ENABLE_L1_LEN , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DTS_ENABLE_L1_LEN ); REG64_FLD( PEC_TIMESTAMP_COUNTER_READ_VALUE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_VALUE ); REG64_FLD( PEC_TIMESTAMP_COUNTER_READ_VALUE_LEN , 44 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_VALUE_LEN ); REG64_FLD( PEC_TIMESTAMP_COUNTER_READ_OVERFLOW_ERR , 44 , SH_UNT_PEC , SH_ACS_SCOM_RO , SH_FLD_OVERFLOW_ERR ); REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_TIMEOUT , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_IN_TIMEOUT ); REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_SEQ_ERR , 1 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_IN_SEQ_ERR ); REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_SEQ_PERR , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_IN_SEQ_PERR ); REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_BAD_OP_ERR , 3 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_IN_BAD_OP_ERR ); REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_SNP_ADDR_PERR , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_IN_SNP_ADDR_PERR ); REG64_FLD( CAPP_TLBI_ERROR_REPORT_IN_SNP_TTAG_PERR , 5 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_IN_SNP_TTAG_PERR ); REG64_FLD( PU_TOD_CMD_REG_ADR , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADR ); REG64_FLD( PU_TOD_CMD_REG_ADR_LEN , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADR_LEN ); REG64_FLD( PU_TOD_DATA_RCV_REG_PCB , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PCB ); REG64_FLD( PU_TOD_DATA_RCV_REG_PCB_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_PCB_LEN ); REG64_FLD( PU_TOD_DATA_SND_REG_PCB , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PCB ); REG64_FLD( PU_TOD_DATA_SND_REG_PCB_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PCB_LEN ); REG64_FLD( CAPP_TOD_SYNC000_TIMEBASE , 55 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TIMEBASE ); REG64_FLD( CAPP_TOD_SYNC000_TIMEBASE_LEN , 5 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TIMEBASE_LEN ); REG64_FLD( CAPP_TOD_SYNC000_CHIP_STATUS , 60 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_CHIP_STATUS ); REG64_FLD( CAPP_TOD_SYNC000_CHIP_STATUS_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_CHIP_STATUS_LEN ); REG64_FLD( PU_TRUST_CONTROL_FSP_TCE_ENABLE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_FSP_TCE_ENABLE ); REG64_FLD( PEC_TUNNEL_BAR_REG_PE , 0 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE ); REG64_FLD( PEC_TUNNEL_BAR_REG_PE_LEN , 43 , SH_UNT_PEC , SH_ACS_SCOM_RW , SH_FLD_PE_LEN ); REG64_FLD( PU_TX_CTRL_STAT_REG_ENABLE_SCWR_TO_TXRF , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_SCWR_TO_TXRF ); REG64_FLD( PU_TX_CTRL_STAT_REG_DISABLE_ECC_COR_GXC_PSI , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_ECC_COR_GXC_PSI ); REG64_FLD( PU_TX_CTRL_STAT_REG_DISABLE_ECC_COR_TXRF_PSI , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_ECC_COR_TXRF_PSI ); REG64_FLD( PU_TX_CTRL_STAT_REG_CRC_MODE , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CRC_MODE ); REG64_FLD( PU_TX_CTRL_STAT_REG_CHIP_PERSONALISATION , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHIP_PERSONALISATION ); REG64_FLD( PU_TX_CTRL_STAT_REG_ENABLE_STREAMING_MODE , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_ENABLE_STREAMING_MODE ); REG64_FLD( PU_TX_CTRL_STAT_REG_CHIP_INTERFACEMODE , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_CHIP_INTERFACEMODE ); REG64_FLD( PU_TX_CTRL_STAT_REG_DISABLE_TIMEOUT_AND_RETRY , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_DISABLE_TIMEOUT_AND_RETRY ); REG64_FLD( PU_TX_CTRL_STAT_REG_FENCE_IO_INTERFACE , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FENCE_IO_INTERFACE ); REG64_FLD( PU_TX_CTRL_STAT_REG_FENCE_GX_INTERFACE , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_FENCE_GX_INTERFACE ); REG64_FLD( PU_TX_CTRL_STAT_REG_GX_ENABLE_OVERWRITE , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_GX_ENABLE_OVERWRITE ); REG64_FLD( PU_TX_MASK_REG_PSITXINS_DATA_PCK , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXINS_DATA_PCK ); REG64_FLD( PU_TX_MASK_REG_PSITXINS_TZRTMP_PCK , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXINS_TZRTMP_PCK ); REG64_FLD( PU_TX_MASK_REG_PSITXEI_SHIFT_PCK , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXEI_SHIFT_PCK ); REG64_FLD( PU_TX_MASK_REG_PSITXEI_TRANSMIT_PCK , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXEI_TRANSMIT_PCK ); REG64_FLD( PU_TX_MASK_REG_PSITXINS_PARITY , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXINS_PARITY ); REG64_FLD( PU_TX_MASK_REG_PSITXINS_UNDERRUN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXINS_UNDERRUN ); REG64_FLD( PU_TX_MASK_REG_PSITXBFF_DATA_PCK , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXBFF_DATA_PCK ); REG64_FLD( PU_TX_MASK_REG_PSITXBFF_TDO_PCK , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXBFF_TDO_PCK ); REG64_FLD( PU_TX_MASK_REG_PSITXBFF_TFC_PCK , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXBFF_TFC_PCK ); REG64_FLD( PU_TX_MASK_REG_PSITXLC_FSM_PCK , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXLC_FSM_PCK ); REG64_FLD( PU_TX_MASK_REG_PSITXLC_DATA_BUFF_PCK , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXLC_DATA_BUFF_PCK ); REG64_FLD( PU_TX_MASK_REG_PSITXLC_TDO_PCK , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXLC_TDO_PCK ); REG64_FLD( PU_TX_MASK_REG_PSITXLC_TADDR_PCK , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXLC_TADDR_PCK ); REG64_FLD( PU_TX_MASK_REG_PSITXLC_TCTRL_PCK , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXLC_TCTRL_PCK ); REG64_FLD( PU_TX_MASK_REG_PSITXLC_UE_RF , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXLC_UE_RF ); REG64_FLD( PU_TX_MASK_REG_PSITXLC_CE_RF , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXLC_CE_RF ); REG64_FLD( PU_TX_MASK_REG_PSITXLC_UE_GX_2N , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXLC_UE_GX_2N ); REG64_FLD( PU_TX_MASK_REG_PSITXLC_CE_GX_2N , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXLC_CE_GX_2N ); REG64_FLD( PU_TX_MASK_REG_PSITXLC_DATA_GXST2_PCK_2N , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXLC_DATA_GXST2_PCK_2N ); REG64_FLD( PU_TX_MASK_REG_PSITXLC_DATA_GXST3_PCK_2N , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSITXLC_DATA_GXST3_PCK_2N ); REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TADDR_PCK , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRFACC_TADDR_PCK ); REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TCTRL_PCK , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRFACC_TCTRL_PCK ); REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TDL_CMD_CTRL_PCK , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRFACC_TDL_CMD_CTRL_PCK ); REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TDL_RSP_CTRL_PCK , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRFACC_TDL_RSP_CTRL_PCK ); REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TFSM_PCK , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRFACC_TFSM_PCK ); REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TDL_FSM_PCK , 25 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRFACC_TDL_FSM_PCK ); REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TXSC_PCK , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRFACC_TXSC_PCK ); REG64_FLD( PU_TX_MASK_REG_PSIRFACC_TDL_RETRY_ERR , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_PSIRFACC_TDL_RETRY_ERR ); REG64_FLD( PU_TX_PSI_CNTL_DRV_PATTERN_EN , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_DRV_PATTERN_EN ); REG64_FLD( PU_TX_PSI_CNTL_PATTERN_SEL , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERN_SEL ); REG64_FLD( PU_TX_PSI_CNTL_PATTERN_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PATTERN_SEL_LEN ); REG64_FLD( PU_TX_PSI_CNTL_CLK_QUIESCE_P , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CLK_QUIESCE_P ); REG64_FLD( PU_TX_PSI_CNTL_CLK_QUIESCE_P_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CLK_QUIESCE_P_LEN ); REG64_FLD( PU_TX_PSI_CNTL_CLK_QUIESCE_N , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_CLK_QUIESCE_N ); REG64_FLD( PU_TX_PSI_CNTL_CLK_QUIESCE_N_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CLK_QUIESCE_N_LEN ); REG64_FLD( PU_TX_PSI_CNTL_LANE_QUIESCE , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_LANE_QUIESCE ); REG64_FLD( PU_TX_PSI_CNTL_LANE_QUIESCE_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_LANE_QUIESCE_LEN ); REG64_FLD( PU_TX_PSI_CNTL_CLK_INVERT , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_CLK_INVERT ); REG64_FLD( PU_TX_PSI_CNTL_LANE_INVERT , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_LANE_INVERT ); REG64_FLD( PU_TX_PSI_CNTL_PDWN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_PDWN ); REG64_FLD( PU_TX_PSI_CNTL_BIST_EN , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_BIST_EN ); REG64_FLD( PU_TX_PSI_CNTL_SPARE , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE ); REG64_FLD( PU_TX_PSI_CNTL_SPARE_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); REG64_FLD( PU_TX_PSI_MODE_PC_TEST , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_PC_TEST ); REG64_FLD( PU_TX_PSI_MODE_MAIN_SLICE_EN_ENC , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAIN_SLICE_EN_ENC ); REG64_FLD( PU_TX_PSI_MODE_MAIN_SLICE_EN_ENC_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MAIN_SLICE_EN_ENC_LEN ); REG64_FLD( PU_TX_PSI_MODE_PC_SLICE_EN_ENC , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_PC_SLICE_EN_ENC ); REG64_FLD( PU_TX_PSI_MODE_PC_SLICE_EN_ENC_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_PC_SLICE_EN_ENC_LEN ); REG64_FLD( PU_TX_PSI_MODE_SLEWCTL , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_SLEWCTL ); REG64_FLD( PU_TX_PSI_MODE_SLEWCTL_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_SLEWCTL_LEN ); REG64_FLD( PU_TX_PSI_MODE_PVTNL_ENC , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_PVTNL_ENC ); REG64_FLD( PU_TX_PSI_MODE_PVTNL_ENC_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PVTNL_ENC_LEN ); REG64_FLD( PU_TX_PSI_MODE_PVTPL_ENC , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_PVTPL_ENC ); REG64_FLD( PU_TX_PSI_MODE_PVTPL_ENC_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_PVTPL_ENC_LEN ); REG64_FLD( PU_TX_PSI_STATUS_SPARE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE ); REG64_FLD( PU_TX_PSI_STATUS_SPARE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); REG64_FLD( PU_TX_PSI_STATUS_BIST_ERROR , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_BIST_ERROR ); REG64_FLD( PU_TX_PSI_STATUS_BIST_ERROR_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_BIST_ERROR_LEN ); REG64_FLD( PU_TX_TO_RT_REG_TIMEOUT_VALUE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_TIMEOUT_VALUE ); REG64_FLD( PU_TX_TO_RT_REG_TIMEOUT_VALUE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_TIMEOUT_VALUE_LEN ); REG64_FLD( PU_TX_TO_RT_REG_RETRY_VALUE , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_RETRY_VALUE ); REG64_FLD( PU_TX_TO_RT_REG_RETRY_VALUE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_RETRY_VALUE_LEN ); REG64_FLD( PU_UMAC_STATUS_CONTROL_CRB_READS_ENBL , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CRB_READS_ENBL ); REG64_FLD( PU_UMAC_STATUS_CONTROL_CRB_READS_HALTED , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_CRB_READS_HALTED ); REG64_FLD( PU_UMAC_STATUS_CONTROL_IDLE , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_IDLE ); REG64_FLD( PU_UMAC_STATUS_CONTROL_QUIESCE_REQUEST , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_QUIESCE_REQUEST ); REG64_FLD( PU_UMAC_STATUS_CONTROL_QUIESCE_ACHEIVED , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_QUIESCE_ACHEIVED ); REG64_FLD( PU_UMAC_STATUS_CONTROL_QUIESCE_FAILED , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_QUIESCE_FAILED ); REG64_FLD( PU_UMAC_STATUS_CONTROL_QUIESCED , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_QUIESCED ); REG64_FLD( PU_UMAC_STATUS_CONTROL_PASTE_ADDR_ALIGN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PASTE_ADDR_ALIGN ); REG64_FLD( PU_VAS_BUFCTL_TOTAL_FREE_BUF_COUNT , 49 , SH_UNT , SH_ACS_SCOM , SH_FLD_TOTAL_FREE_BUF_COUNT ); REG64_FLD( PU_VAS_BUFCTL_TOTAL_FREE_BUF_COUNT_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_TOTAL_FREE_BUF_COUNT_LEN ); REG64_FLD( PU_VAS_BUFCTL_CONSUMED_BUF_COUNT , 57 , SH_UNT , SH_ACS_SCOM , SH_FLD_CONSUMED_BUF_COUNT ); REG64_FLD( PU_VAS_BUFCTL_CONSUMED_BUF_COUNT_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_CONSUMED_BUF_COUNT_LEN ); REG64_FLD( PU_VAS_CAMDATA0_CAM_DISPLAY_REG_0 , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CAM_DISPLAY_REG_0 ); REG64_FLD( PU_VAS_CAMDATA0_CAM_DISPLAY_REG_0_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CAM_DISPLAY_REG_0_LEN ); REG64_FLD( PU_VAS_CAMDATA1_CAM_DISPLAY_REG_1 , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CAM_DISPLAY_REG_1 ); REG64_FLD( PU_VAS_CAMDATA1_CAM_DISPLAY_REG_1_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_CAM_DISPLAY_REG_1_LEN ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_RESET , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_RESET ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT4 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT4 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT5 , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT5 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT6 , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT6 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT7 , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT7 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT8 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT8 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT9 , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT9 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT10 , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT10 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT11 , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT11 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT12 , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT12 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT13 , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT13 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT14 , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT14 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT15 , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT15 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT16 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT16 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT17 , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT17 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT18 , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT18 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT19 , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT19 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT20 , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT20 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT21 , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT21 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT22 , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT22 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT23 , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT23 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT24 , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT24 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT25 , 25 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT25 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT26 , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT26 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT27 , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT27 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT28 , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT28 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT29 , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT29 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT30 , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT30 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT31 , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT31 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT32 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT32 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT33 , 33 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT33 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT34 , 34 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT34 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT35 , 35 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT35 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT36 , 36 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT36 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT37 , 37 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT37 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT38 , 38 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT38 ); REG64_FLD( PU_VAS_CQERRRPT_CQ_CERR_BIT39 , 39 , SH_UNT , SH_ACS_SCOM , SH_FLD_CQ_CERR_BIT39 ); REG64_FLD( PU_VAS_DBGCONT_TRACE_BUS_BITS_0_63 , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_TRACE_BUS_BITS_0_63 ); REG64_FLD( PU_VAS_DBGCONT_TRACE_BUS_BITS_0_63_LEN , 64 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_TRACE_BUS_BITS_0_63_LEN ); REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRACE_DATA_LO , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SEL_RG_TRACE_DATA_LO ); REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRACE_DATA_LO_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SEL_RG_TRACE_DATA_LO_LEN ); REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRACE_DATA_HI , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SEL_RG_TRACE_DATA_HI ); REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRACE_DATA_HI_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SEL_RG_TRACE_DATA_HI_LEN ); REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRIGGERS_01 , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SEL_RG_TRIGGERS_01 ); REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRIGGERS_01_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SEL_RG_TRIGGERS_01_LEN ); REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRIGGERS_23 , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SEL_RG_TRIGGERS_23 ); REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_TRIGGERS_23_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SEL_RG_TRIGGERS_23_LEN ); REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_GROUP_SEL_LO , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IN_TRACE_GROUP_SEL_LO ); REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_GROUP_SEL_LO_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IN_TRACE_GROUP_SEL_LO_LEN ); REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_GROUP_SEL_HI , 11 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IN_TRACE_GROUP_SEL_HI ); REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_GROUP_SEL_HI_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IN_TRACE_GROUP_SEL_HI_LEN ); REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_TRIGGER_SEL_01 , 14 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IN_TRACE_TRIGGER_SEL_01 ); REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_TRIGGER_SEL_01_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IN_TRACE_TRIGGER_SEL_01_LEN ); REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_TRIGGER_SEL_23 , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IN_TRACE_TRIGGER_SEL_23 ); REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_TRIGGER_SEL_23_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IN_TRACE_TRIGGER_SEL_23_LEN ); REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_GROUP_SEL_LO , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RG_TRACE_GROUP_SEL_LO ); REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_GROUP_SEL_LO_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RG_TRACE_GROUP_SEL_LO_LEN ); REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_GROUP_SEL_HI , 23 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RG_TRACE_GROUP_SEL_HI ); REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_GROUP_SEL_HI_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RG_TRACE_GROUP_SEL_HI_LEN ); REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_TRIGGER_SEL_01 , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RG_TRACE_TRIGGER_SEL_01 ); REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_TRIGGER_SEL_01_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RG_TRACE_TRIGGER_SEL_01_LEN ); REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_TRIGGER_SEL_23 , 29 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RG_TRACE_TRIGGER_SEL_23 ); REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_TRIGGER_SEL_23_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RG_TRACE_TRIGGER_SEL_23_LEN ); REG64_FLD( PU_VAS_DBGNORTH_ENABLE_IN_TRACE , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_IN_TRACE ); REG64_FLD( PU_VAS_DBGNORTH_ENABLE_RG_TRACE , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_RG_TRACE ); REG64_FLD( PU_VAS_DBGNORTH_DBG_NORTH_UNUSED_BITS0 , 34 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DBG_NORTH_UNUSED_BITS0 ); REG64_FLD( PU_VAS_DBGNORTH_DBG_NORTH_UNUSED_BITS0_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DBG_NORTH_UNUSED_BITS0_LEN ); REG64_FLD( PU_VAS_DBGNORTH_SEL_RG_PMU_DATA , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SEL_RG_PMU_DATA ); REG64_FLD( PU_VAS_DBGNORTH_DBG_NORTH_UNUSED_BITS1 , 37 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DBG_NORTH_UNUSED_BITS1 ); REG64_FLD( PU_VAS_DBGNORTH_DBG_NORTH_UNUSED_BITS1_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DBG_NORTH_UNUSED_BITS1_LEN ); REG64_FLD( PU_VAS_DBGNORTH_ENABLE_IN_PMU_COUNTING , 40 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_IN_PMU_COUNTING ); REG64_FLD( PU_VAS_DBGNORTH_ENABLE_RG_PMU_COUNTING , 41 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_RG_PMU_COUNTING ); REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_INT_DATA_LO , 42 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IN_TRACE_INT_DATA_LO ); REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_INT_DATA_HI , 43 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IN_TRACE_INT_DATA_HI ); REG64_FLD( PU_VAS_DBGNORTH_EG_TRACE_INT_DATA_LO , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_INT_DATA_LO ); REG64_FLD( PU_VAS_DBGNORTH_EG_TRACE_INT_DATA_HI , 45 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_INT_DATA_HI ); REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_INT_DATA_LO , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RG_TRACE_INT_DATA_LO ); REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_INT_DATA_HI , 47 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RG_TRACE_INT_DATA_HI ); REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_INT_TRIG_01 , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IN_TRACE_INT_TRIG_01 ); REG64_FLD( PU_VAS_DBGNORTH_IN_TRACE_INT_TRIG_23 , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_IN_TRACE_INT_TRIG_23 ); REG64_FLD( PU_VAS_DBGNORTH_EG_TRACE_INT_TRIG_01 , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_INT_TRIG_01 ); REG64_FLD( PU_VAS_DBGNORTH_EG_TRACE_INT_TRIG_23 , 51 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_INT_TRIG_23 ); REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_INT_TRIG_01 , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RG_TRACE_INT_TRIG_01 ); REG64_FLD( PU_VAS_DBGNORTH_RG_TRACE_INT_TRIG_23 , 53 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RG_TRACE_INT_TRIG_23 ); REG64_FLD( PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_DATA_LO , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PASS_WC_INT_TRACE_DATA_LO ); REG64_FLD( PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_DATA_HI , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PASS_WC_INT_TRACE_DATA_HI ); REG64_FLD( PU_VAS_DBGSOUTH_PASS_CQ_INT_TRACE_DATA_LO , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PASS_CQ_INT_TRACE_DATA_LO ); REG64_FLD( PU_VAS_DBGSOUTH_PASS_CQ_INT_TRACE_DATA_HI , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PASS_CQ_INT_TRACE_DATA_HI ); REG64_FLD( PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_TRIG_01 , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PASS_WC_INT_TRACE_TRIG_01 ); REG64_FLD( PU_VAS_DBGSOUTH_PASS_WC_INT_TRACE_TRIG_23 , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PASS_WC_INT_TRACE_TRIG_23 ); REG64_FLD( PU_VAS_DBGSOUTH_PASS_CQ_INT_TRACE_TRIG_01 , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PASS_CQ_INT_TRACE_TRIG_01 ); REG64_FLD( PU_VAS_DBGSOUTH_PASS_CQ_INT_TRACE_TRIG_23 , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PASS_CQ_INT_TRACE_TRIG_23 ); REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_LO , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_GROUP_SEL_LO ); REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_LO_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_GROUP_SEL_LO_LEN ); REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_HI , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_GROUP_SEL_HI ); REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_GROUP_SEL_HI_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_GROUP_SEL_HI_LEN ); REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_01 , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_TRIGGER_SEL_01 ); REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_01_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_TRIGGER_SEL_01_LEN ); REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_23 , 18 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_TRIGGER_SEL_23 ); REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_TRIGGER_SEL_23_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_TRIGGER_SEL_23_LEN ); REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_GROUP_SEL_LO , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WC_TRACE_GROUP_SEL_LO ); REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_GROUP_SEL_LO_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WC_TRACE_GROUP_SEL_LO_LEN ); REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_GROUP_SEL_HI , 23 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WC_TRACE_GROUP_SEL_HI ); REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_GROUP_SEL_HI_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WC_TRACE_GROUP_SEL_HI_LEN ); REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_TRIGGER_SEL_01 , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WC_TRACE_TRIGGER_SEL_01 ); REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_TRIGGER_SEL_01_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WC_TRACE_TRIGGER_SEL_01_LEN ); REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_TRIGGER_SEL_23 , 29 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WC_TRACE_TRIGGER_SEL_23 ); REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_TRIGGER_SEL_23_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WC_TRACE_TRIGGER_SEL_23_LEN ); REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_GROUP_SEL_LO , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CQ_TRACE_GROUP_SEL_LO ); REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_GROUP_SEL_LO_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CQ_TRACE_GROUP_SEL_LO_LEN ); REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_GROUP_SEL_HI , 35 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CQ_TRACE_GROUP_SEL_HI ); REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_GROUP_SEL_HI_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CQ_TRACE_GROUP_SEL_HI_LEN ); REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_TRIGGER_SEL_01 , 38 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CQ_TRACE_TRIGGER_SEL_01 ); REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_TRIGGER_SEL_01_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CQ_TRACE_TRIGGER_SEL_01_LEN ); REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_TRIGGER_SEL_23 , 41 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CQ_TRACE_TRIGGER_SEL_23 ); REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_TRIGGER_SEL_23_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CQ_TRACE_TRIGGER_SEL_23_LEN ); REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_EG_TRACE , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_EG_TRACE ); REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_WC_TRACE , 45 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_WC_TRACE ); REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_CQ_TRACE , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_CQ_TRACE ); REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_INT_DATA_LO , 47 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WC_TRACE_INT_DATA_LO ); REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_INT_DATA_HI , 48 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WC_TRACE_INT_DATA_HI ); REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_INT_DATA_LO , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_INT_DATA_LO ); REG64_FLD( PU_VAS_DBGSOUTH_PASS_CQ_INT_PMU_DATA_LO , 50 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PASS_CQ_INT_PMU_DATA_LO ); REG64_FLD( PU_VAS_DBGSOUTH_PASS_CQ_INT_PMU_DATA_HI , 51 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PASS_CQ_INT_PMU_DATA_HI ); REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_EG_PMU_COUNTING , 52 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_EG_PMU_COUNTING ); REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_INT_DATA_HI , 53 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_INT_DATA_HI ); REG64_FLD( PU_VAS_DBGSOUTH_ENABLE_CQ_PMU_COUNTING , 54 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ENABLE_CQ_PMU_COUNTING ); REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_INT_DATA_LO , 55 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CQ_TRACE_INT_DATA_LO ); REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_INT_DATA_HI , 56 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CQ_TRACE_INT_DATA_HI ); REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_INT_TRIG_01 , 57 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WC_TRACE_INT_TRIG_01 ); REG64_FLD( PU_VAS_DBGSOUTH_WC_TRACE_INT_TRIG_23 , 58 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WC_TRACE_INT_TRIG_23 ); REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_INT_TRIG_01 , 59 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_INT_TRIG_01 ); REG64_FLD( PU_VAS_DBGSOUTH_EG_TRACE_INT_TRIG_23 , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_EG_TRACE_INT_TRIG_23 ); REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_INT_TRIG_01 , 61 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CQ_TRACE_INT_TRIG_01 ); REG64_FLD( PU_VAS_DBGSOUTH_CQ_TRACE_INT_TRIG_23 , 62 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CQ_TRACE_INT_TRIG_23 ); REG64_FLD( PU_VAS_DBGTRIG_TRACE_BUS_BITS_64_87 , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_TRACE_BUS_BITS_64_87 ); REG64_FLD( PU_VAS_DBGTRIG_TRACE_BUS_BITS_64_87_LEN , 24 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_TRACE_BUS_BITS_64_87_LEN ); REG64_FLD( PU_VAS_DBGTRIG_TRACE_BUS_TRIGGER_BITS , 24 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_TRACE_BUS_TRIGGER_BITS ); REG64_FLD( PU_VAS_DBGTRIG_TRACE_BUS_TRIGGER_BITS_LEN , 4 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_TRACE_BUS_TRIGGER_BITS_LEN ); REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_RESET , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_EG_CERR_RESET ); REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT4 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_EG_CERR_BIT4 ); REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT5 , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_EG_CERR_BIT5 ); REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT6 , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_EG_CERR_BIT6 ); REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT7 , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_EG_CERR_BIT7 ); REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT8 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_EG_CERR_BIT8 ); REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT9 , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_EG_CERR_BIT9 ); REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT10 , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_EG_CERR_BIT10 ); REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_BIT11 , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_EG_CERR_BIT11 ); REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_UNUSEDBITS , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_EG_CERR_UNUSEDBITS ); REG64_FLD( PU_VAS_EGERRRPT_EG_CERR_UNUSEDBITS_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_EG_CERR_UNUSEDBITS_LEN ); REG64_FLD( PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_ENA , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_NORTH_WC_ENA ); REG64_FLD( PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_TYP , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_NORTH_WC_TYP ); REG64_FLD( PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_FRQ , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_NORTH_WC_FRQ ); REG64_FLD( PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_UNUSED , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_NORTH_WC_UNUSED ); REG64_FLD( PU_VAS_ERRINJNO_ECC_ERR_INJ_NORTH_WC_UNUSED_LEN , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_NORTH_WC_UNUSED_LEN ); REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_WC_ENA , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_SOUTH_WC_ENA ); REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_WC_TYP , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_SOUTH_WC_TYP ); REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_WC_FRQ , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_SOUTH_WC_FRQ ); REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_WC_SEL , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_SOUTH_WC_SEL ); REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_WC_SEL_LEN , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_SOUTH_WC_SEL_LEN ); REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_EG_ENA , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_SOUTH_EG_ENA ); REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_EG_TYP , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_SOUTH_EG_TYP ); REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_EG_FRQ , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_SOUTH_EG_FRQ ); REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_EG_SEL , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_SOUTH_EG_SEL ); REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_UNUSED , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_SOUTH_UNUSED ); REG64_FLD( PU_VAS_ERRINJSO_ECC_ERR_INJ_SOUTH_UNUSED_LEN , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ECC_ERR_INJ_SOUTH_UNUSED_LEN ); REG64_FLD( PU_VAS_FIR_ACTION0_REG_ACTION0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION0 ); REG64_FLD( PU_VAS_FIR_ACTION0_REG_ACTION0_LEN , 54 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION0_LEN ); REG64_FLD( PU_VAS_FIR_ACTION1_REG_ACTION1 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION1 ); REG64_FLD( PU_VAS_FIR_ACTION1_REG_ACTION1_LEN , 54 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ACTION1_LEN ); REG64_FLD( PU_VAS_FIR_MASK_REG_EG_LOGIC_HW_ERROR , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_EG_LOGIC_HW_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_IN_LOGIC_HW_ERROR , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IN_LOGIC_HW_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_LOGIC_HW_ERROR , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_LOGIC_HW_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_WC_LOGIC_HW_ERROR , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WC_LOGIC_HW_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_RG_LOGIC_HW_ERROR , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RG_LOGIC_HW_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_PARITY_ERROR , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_PARITY_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_RD_ADDR_ERROR , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_RD_ADDR_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_WR_ADDR_ERROR , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_WR_ADDR_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_EG_ECC_CE_ERROR , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_EG_ECC_CE_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_IN_ECC_CE_ERROR , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IN_ECC_CE_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_ECC_CE_ERROR , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_ECC_CE_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_WC_ECC_CE_ERROR , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WC_ECC_CE_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_RG_ECC_CE_ERROR , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RG_ECC_CE_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_OB_CE_ERROR , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_OB_CE_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_OB_UE_ERROR , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_OB_UE_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_MASTER_FSM_HANG , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_MASTER_FSM_HANG ); REG64_FLD( PU_VAS_FIR_MASK_REG_EG_ECC_UE_ERROR , 16 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_EG_ECC_UE_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_IN_ECC_UE_ERROR , 17 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IN_ECC_UE_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_ECC_UE_ERROR , 18 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_ECC_UE_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_WC_ECC_UE_ERROR , 19 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WC_ECC_UE_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_RG_ECC_UE_ERROR , 20 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RG_ECC_UE_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_IN_PARITY_ERROR , 21 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IN_PARITY_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_IN_SW_CAST_ERROR , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IN_SW_CAST_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_EG_ECC_SUE_ERROR , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_EG_ECC_SUE_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_IN_ECC_SUE_ERROR , 25 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IN_ECC_SUE_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_ECC_SUE_ERROR , 26 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_ECC_SUE_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_WC_ECC_SUE_ERROR , 27 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WC_ECC_SUE_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_RG_ECC_SUE_ERROR , 28 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RG_ECC_SUE_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_RD_LINK_ERROR , 29 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_RD_LINK_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_WR_LINK_ERROR , 30 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_WR_LINK_ERROR ); REG64_FLD( PU_VAS_FIR_MASK_REG_CQ_PB_LINK_ABORT , 31 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_LINK_ABORT ); REG64_FLD( PU_VAS_FIR_MASK_REG_MMIO_HYP_RD_ADDR_ERR , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MMIO_HYP_RD_ADDR_ERR ); REG64_FLD( PU_VAS_FIR_MASK_REG_MMIO_OS_RD_ADDR_ERR , 33 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MMIO_OS_RD_ADDR_ERR ); REG64_FLD( PU_VAS_FIR_MASK_REG_MMIO_HYP_WR_ADDR_ERR , 34 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MMIO_HYP_WR_ADDR_ERR ); REG64_FLD( PU_VAS_FIR_MASK_REG_MMIO_OS_WR_ADDR_ERR , 35 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MMIO_OS_WR_ADDR_ERR ); REG64_FLD( PU_VAS_FIR_MASK_REG_MMIO_NON8B_HYP_ERR , 36 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MMIO_NON8B_HYP_ERR ); REG64_FLD( PU_VAS_FIR_MASK_REG_MMIO_NON8B_OS_ERR , 37 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MMIO_NON8B_OS_ERR ); REG64_FLD( PU_VAS_FIR_MASK_REG_WM_WIN_NOT_OPEN_ERR , 38 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WM_WIN_NOT_OPEN_ERR ); REG64_FLD( PU_VAS_FIR_MASK_REG_WM_MULTIHIT_ERR , 39 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WM_MULTIHIT_ERR ); REG64_FLD( PU_VAS_FIR_MASK_REG_PG_MIG_DISABLED_ERR , 40 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PG_MIG_DISABLED_ERR ); REG64_FLD( PU_VAS_FIR_MASK_REG_PG_MIG_SIZE_MISMATCH_ERR , 41 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PG_MIG_SIZE_MISMATCH_ERR ); REG64_FLD( PU_VAS_FIR_MASK_REG_NOTIFY_FAILED_ERR , 42 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_NOTIFY_FAILED_ERR ); REG64_FLD( PU_VAS_FIR_MASK_REG_WR_MON_NOT_DISABLED_ERR , 43 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WR_MON_NOT_DISABLED_ERR ); REG64_FLD( PU_VAS_FIR_MASK_REG_REJECTED_PASTE_CMD , 44 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_REJECTED_PASTE_CMD ); REG64_FLD( PU_VAS_FIR_MASK_REG_DATA_HANG_DETECTED , 45 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DATA_HANG_DETECTED ); REG64_FLD( PU_VAS_FIR_MASK_REG_INCOMING_PB_PARITY_ERR , 46 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INCOMING_PB_PARITY_ERR ); REG64_FLD( PU_VAS_FIR_MASK_REG_SCOM1_SAT_ERR , 47 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM1_SAT_ERR ); REG64_FLD( PU_VAS_FIR_MASK_REG_NX_LOCAL_XSTOP , 48 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_NX_LOCAL_XSTOP ); REG64_FLD( PU_VAS_FIR_MASK_REG_SCOM_MMIO_ADDR_ERR , 49 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_MMIO_ADDR_ERR ); REG64_FLD( PU_VAS_FIR_MASK_REG_UNUSED50 , 50 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UNUSED50 ); REG64_FLD( PU_VAS_FIR_MASK_REG_UNUSED51 , 51 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UNUSED51 ); REG64_FLD( PU_VAS_FIR_MASK_REG_SCOMFIR_INT_ERR_0 , 52 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOMFIR_INT_ERR_0 ); REG64_FLD( PU_VAS_FIR_MASK_REG_SCOMFIR_INT_ERR_1 , 53 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOMFIR_INT_ERR_1 ); REG64_FLD( PU_VAS_FIR_REG_EG_LOGIC_HW_ERROR , 0 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_EG_LOGIC_HW_ERROR ); REG64_FLD( PU_VAS_FIR_REG_IN_LOGIC_HW_ERROR , 1 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IN_LOGIC_HW_ERROR ); REG64_FLD( PU_VAS_FIR_REG_CQ_LOGIC_HW_ERROR , 2 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_LOGIC_HW_ERROR ); REG64_FLD( PU_VAS_FIR_REG_WC_LOGIC_HW_ERROR , 3 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WC_LOGIC_HW_ERROR ); REG64_FLD( PU_VAS_FIR_REG_RG_LOGIC_HW_ERROR , 4 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RG_LOGIC_HW_ERROR ); REG64_FLD( PU_VAS_FIR_REG_CQ_PB_PARITY_ERROR , 5 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_PARITY_ERROR ); REG64_FLD( PU_VAS_FIR_REG_CQ_PB_RD_ADDR_ERROR , 6 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_RD_ADDR_ERROR ); REG64_FLD( PU_VAS_FIR_REG_CQ_PB_WR_ADDR_ERROR , 7 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_WR_ADDR_ERROR ); REG64_FLD( PU_VAS_FIR_REG_EG_ECC_CE_ERROR , 8 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_EG_ECC_CE_ERROR ); REG64_FLD( PU_VAS_FIR_REG_IN_ECC_CE_ERROR , 9 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IN_ECC_CE_ERROR ); REG64_FLD( PU_VAS_FIR_REG_CQ_ECC_CE_ERROR , 10 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_ECC_CE_ERROR ); REG64_FLD( PU_VAS_FIR_REG_WC_ECC_CE_ERROR , 11 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WC_ECC_CE_ERROR ); REG64_FLD( PU_VAS_FIR_REG_RG_ECC_CE_ERROR , 12 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RG_ECC_CE_ERROR ); REG64_FLD( PU_VAS_FIR_REG_CQ_PB_OB_CE_ERROR , 13 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_OB_CE_ERROR ); REG64_FLD( PU_VAS_FIR_REG_CQ_PB_OB_UE_ERROR , 14 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_OB_UE_ERROR ); REG64_FLD( PU_VAS_FIR_REG_CQ_PB_MASTER_FSM_HANG , 15 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_MASTER_FSM_HANG ); REG64_FLD( PU_VAS_FIR_REG_EG_ECC_UE_ERROR , 16 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_EG_ECC_UE_ERROR ); REG64_FLD( PU_VAS_FIR_REG_IN_ECC_UE_ERROR , 17 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IN_ECC_UE_ERROR ); REG64_FLD( PU_VAS_FIR_REG_CQ_ECC_UE_ERROR , 18 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_ECC_UE_ERROR ); REG64_FLD( PU_VAS_FIR_REG_WC_ECC_UE_ERROR , 19 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WC_ECC_UE_ERROR ); REG64_FLD( PU_VAS_FIR_REG_RG_ECC_UE_ERROR , 20 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RG_ECC_UE_ERROR ); REG64_FLD( PU_VAS_FIR_REG_IN_PARITY_ERROR , 21 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IN_PARITY_ERROR ); REG64_FLD( PU_VAS_FIR_REG_IN_SW_CAST_ERROR , 22 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IN_SW_CAST_ERROR ); REG64_FLD( PU_VAS_FIR_REG_EG_ECC_SUE_ERROR , 24 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_EG_ECC_SUE_ERROR ); REG64_FLD( PU_VAS_FIR_REG_IN_ECC_SUE_ERROR , 25 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_IN_ECC_SUE_ERROR ); REG64_FLD( PU_VAS_FIR_REG_CQ_ECC_SUE_ERROR , 26 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_ECC_SUE_ERROR ); REG64_FLD( PU_VAS_FIR_REG_WC_ECC_SUE_ERROR , 27 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WC_ECC_SUE_ERROR ); REG64_FLD( PU_VAS_FIR_REG_RG_ECC_SUE_ERROR , 28 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_RG_ECC_SUE_ERROR ); REG64_FLD( PU_VAS_FIR_REG_CQ_PB_RD_LINK_ERROR , 29 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_RD_LINK_ERROR ); REG64_FLD( PU_VAS_FIR_REG_CQ_PB_WR_LINK_ERROR , 30 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_WR_LINK_ERROR ); REG64_FLD( PU_VAS_FIR_REG_CQ_PB_LINK_ABORT , 31 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_CQ_PB_LINK_ABORT ); REG64_FLD( PU_VAS_FIR_REG_MMIO_HYP_RD_ADDR_ERR , 32 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MMIO_HYP_RD_ADDR_ERR ); REG64_FLD( PU_VAS_FIR_REG_MMIO_OS_RD_ADDR_ERR , 33 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MMIO_OS_RD_ADDR_ERR ); REG64_FLD( PU_VAS_FIR_REG_MMIO_HYP_WR_ADDR_ERR , 34 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MMIO_HYP_WR_ADDR_ERR ); REG64_FLD( PU_VAS_FIR_REG_MMIO_OS_WR_ADDR_ERR , 35 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MMIO_OS_WR_ADDR_ERR ); REG64_FLD( PU_VAS_FIR_REG_MMIO_NON8B_HYP_ERR , 36 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MMIO_NON8B_HYP_ERR ); REG64_FLD( PU_VAS_FIR_REG_MMIO_NON8B_OS_ERR , 37 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_MMIO_NON8B_OS_ERR ); REG64_FLD( PU_VAS_FIR_REG_WM_WIN_NOT_OPEN_ERR , 38 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WM_WIN_NOT_OPEN_ERR ); REG64_FLD( PU_VAS_FIR_REG_WM_MULTIHIT_ERR , 39 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WM_MULTIHIT_ERR ); REG64_FLD( PU_VAS_FIR_REG_PG_MIG_DISABLED_ERR , 40 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PG_MIG_DISABLED_ERR ); REG64_FLD( PU_VAS_FIR_REG_PG_MIG_SIZE_MISMATCH_ERR , 41 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_PG_MIG_SIZE_MISMATCH_ERR ); REG64_FLD( PU_VAS_FIR_REG_NOTIFY_FAILED_ERR , 42 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_NOTIFY_FAILED_ERR ); REG64_FLD( PU_VAS_FIR_REG_WR_MON_NOT_DISABLED_ERR , 43 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_WR_MON_NOT_DISABLED_ERR ); REG64_FLD( PU_VAS_FIR_REG_REJECTED_PASTE_CMD , 44 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_REJECTED_PASTE_CMD ); REG64_FLD( PU_VAS_FIR_REG_DATA_HANG_DETECTED , 45 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_DATA_HANG_DETECTED ); REG64_FLD( PU_VAS_FIR_REG_INCOMING_PB_PARITY_ERR , 46 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_INCOMING_PB_PARITY_ERR ); REG64_FLD( PU_VAS_FIR_REG_SCOM1_SAT_ERR , 47 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM1_SAT_ERR ); REG64_FLD( PU_VAS_FIR_REG_NX_LOCAL_XSTOP , 48 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_NX_LOCAL_XSTOP ); REG64_FLD( PU_VAS_FIR_REG_SCOM_MMIO_ADDR_ERR , 49 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOM_MMIO_ADDR_ERR ); REG64_FLD( PU_VAS_FIR_REG_UNUSED50 , 50 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UNUSED50 ); REG64_FLD( PU_VAS_FIR_REG_UNUSED51 , 51 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_UNUSED51 ); REG64_FLD( PU_VAS_FIR_REG_SCOMFIR_INT_ERR_0 , 52 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOMFIR_INT_ERR_0 ); REG64_FLD( PU_VAS_FIR_REG_SCOMFIR_INT_ERR_1 , 53 , SH_UNT , SH_ACS_SCOM2_OR , SH_FLD_SCOMFIR_INT_ERR_1 ); REG64_FLD( PU_VAS_FIR_WOF_REG_WOF , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF ); REG64_FLD( PU_VAS_FIR_WOF_REG_WOF_LEN , 54 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_WOF_LEN ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_RESET , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_RESET ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT4 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT4 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT5 , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT5 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT6 , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT6 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT7 , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT7 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT8 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT8 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT9 , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT9 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT10 , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT10 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT11 , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT11 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT12 , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT12 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT13 , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT13 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT14 , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT14 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT15 , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT15 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT16 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT16 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT17 , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT17 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT18 , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT18 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT19 , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT19 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT20 , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT20 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT21 , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT21 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT22 , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT22 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT23 , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT23 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT24 , 24 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT24 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT25 , 25 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT25 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT26 , 26 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT26 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT27 , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT27 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT28 , 28 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT28 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT29 , 29 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT29 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT30 , 30 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT30 ); REG64_FLD( PU_VAS_INERRRPT_IN_CERR_BIT31 , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_IN_CERR_BIT31 ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_4VS64 , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_4VS64 ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_ACCEPT_PASTE , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_ACCEPT_PASTE ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_ENABLE_WRMON , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_ENABLE_WRMON ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_DISABLE_PUSH2MEM_LIMIT , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_DISABLE_PUSH2MEM_LIMIT ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_QUIESCE_REQUEST , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_QUIESCE_REQUEST ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_PREFETCH_DISABLE , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_PREFETCH_DISABLE ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_UNUSED_BITS , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_UNUSED_BITS ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_UNUSED_BITS_LEN , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_UNUSED_BITS_LEN ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_INVALIDATE_CAM_LOC , 47 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_INVALIDATE_CAM_LOC ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_INVALIDATE_CAM_ALL , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_INVALIDATE_CAM_ALL ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_CAM_LOCATION , 49 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_CAM_LOCATION ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_CAM_LOCATION_LEN , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_CAM_LOCATION_LEN ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_CAM_INVAL_DONE , 56 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_CAM_INVAL_DONE ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_UNUSED_BITS2 , 57 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_UNUSED_BITS2 ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_HMI_ACTIVE , 58 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_HMI_ACTIVE ); REG64_FLD( PU_VAS_MISCCTL_MISC_CTL_RG_IS_IDLE , 59 , SH_UNT , SH_ACS_SCOM , SH_FLD_MISC_CTL_RG_IS_IDLE ); REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_INIT , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_MMIO_CTL_INIT ); REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_COMP , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_MMIO_CTL_COMP ); REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_OPTYPE , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_MMIO_CTL_OPTYPE ); REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_ACTYPE , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_MMIO_CTL_ACTYPE ); REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_OP_ERR , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_MMIO_CTL_OP_ERR ); REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_UNUSED , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_MMIO_CTL_UNUSED ); REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_UNUSED_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_MMIO_CTL_UNUSED_LEN ); REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_OFFSET , 36 , SH_UNT , SH_ACS_SCOM , SH_FLD_MMIO_CTL_OFFSET ); REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_OFFSET_LEN , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_MMIO_CTL_OFFSET_LEN ); REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_WINID , 48 , SH_UNT , SH_ACS_SCOM , SH_FLD_MMIO_CTL_WINID ); REG64_FLD( PU_VAS_MMIOCTL_MMIO_CTL_WINID_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_MMIO_CTL_WINID_LEN ); REG64_FLD( PU_VAS_MMIODATA_MMIO_DATA , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MMIO_DATA ); REG64_FLD( PU_VAS_MMIODATA_MMIO_DATA_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_MMIO_DATA_LEN ); REG64_FLD( PU_VAS_MMIOECC_MMIO_ECC , 0 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MMIO_ECC ); REG64_FLD( PU_VAS_MMIOECC_MMIO_ECC_LEN , 8 , SH_UNT , SH_ACS_SCOM_RO , SH_FLD_MMIO_ECC_LEN ); REG64_FLD( PU_VAS_MMIO_BASE_ADDR_BAR , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAR ); REG64_FLD( PU_VAS_MMIO_BASE_ADDR_BAR_LEN , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAR_LEN ); REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_EPSILON , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_0_EPSILON ); REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_EPSILON_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_0_EPSILON_LEN ); REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_HANG_POLL_MAX_CNT , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_0_HANG_POLL_MAX_CNT ); REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_HANG_POLL_MAX_CNT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_0_HANG_POLL_MAX_CNT_LEN ); REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_UNUSED1 , 11 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_0_UNUSED1 ); REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_UNUSED1_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_0_UNUSED1_LEN ); REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_HANG_NX_MAX_CNT , 15 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_0_HANG_NX_MAX_CNT ); REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_HANG_NX_MAX_CNT_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_0_HANG_NX_MAX_CNT_LEN ); REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_DISABLE_WR_RD_PUSH , 19 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_0_DISABLE_WR_RD_PUSH ); REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_INJ_CE , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_0_INJ_CE ); REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_INJ_UE , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_0_INJ_UE ); REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_INJ_SUE , 22 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_0_INJ_SUE ); REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_INJ_ARRAY_SEL , 23 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_0_INJ_ARRAY_SEL ); REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_INJ_FREQ , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_0_INJ_FREQ ); REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_UNUSED2 , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_0_UNUSED2 ); REG64_FLD( PU_VAS_PBCFG0_PBCFG_0_UNUSED2_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_0_UNUSED2_LEN ); REG64_FLD( PU_VAS_PBCFG1_DISABLE_LN_WR , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DISABLE_LN_WR ); REG64_FLD( PU_VAS_PBCFG1_DISABLE_G_WR , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DISABLE_G_WR ); REG64_FLD( PU_VAS_PBCFG1_DISABLE_VG_WR , 2 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DISABLE_VG_WR ); REG64_FLD( PU_VAS_PBCFG1_DISABLE_NN_WR , 3 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DISABLE_NN_WR ); REG64_FLD( PU_VAS_PBCFG1_DISABLE_LN_RD , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DISABLE_LN_RD ); REG64_FLD( PU_VAS_PBCFG1_DISABLE_G_RD , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DISABLE_G_RD ); REG64_FLD( PU_VAS_PBCFG1_DISABLE_VG_RD , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DISABLE_VG_RD ); REG64_FLD( PU_VAS_PBCFG1_DISABLE_NN_RD , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DISABLE_NN_RD ); REG64_FLD( PU_VAS_PBCFG1_PBCFG_1_UNUSED1 , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_1_UNUSED1 ); REG64_FLD( PU_VAS_PBCFG1_PBCFG_1_UNUSED1_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_1_UNUSED1_LEN ); REG64_FLD( PU_VAS_PBCFG1_RD_GO_M_QOS , 12 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RD_GO_M_QOS ); REG64_FLD( PU_VAS_PBCFG1_ADDR_BAR_MODE , 13 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_ADDR_BAR_MODE ); REG64_FLD( PU_VAS_PBCFG1_SKIP_G , 14 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_SKIP_G ); REG64_FLD( PU_VAS_PBCFG1_HANG_SM_ON_ARE , 15 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HANG_SM_ON_ARE ); REG64_FLD( PU_VAS_PBCFG1_HANG_SM_ON_LINK_FAIL , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_HANG_SM_ON_LINK_FAIL ); REG64_FLD( PU_VAS_PBCFG1_CFG_PUMP_MODE , 17 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CFG_PUMP_MODE ); REG64_FLD( PU_VAS_PBCFG1_DMA_WR_NOT_INJ , 18 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_WR_NOT_INJ ); REG64_FLD( PU_VAS_PBCFG1_DMA_PART_WR_NOT_INJ , 19 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_PART_WR_NOT_INJ ); REG64_FLD( PU_VAS_PBCFG1_DMA_RD_VG_RST_TMASK , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_RD_VG_RST_TMASK ); REG64_FLD( PU_VAS_PBCFG1_DMA_RD_VG_RST_TMASK_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_RD_VG_RST_TMASK_LEN ); REG64_FLD( PU_VAS_PBCFG1_DMA_WR_VG_RST_TMASK , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_WR_VG_RST_TMASK ); REG64_FLD( PU_VAS_PBCFG1_DMA_WR_VG_RST_TMASK_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_WR_VG_RST_TMASK_LEN ); REG64_FLD( PU_VAS_PBCFG1_PBCFG_1_UNUSED2 , 36 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_1_UNUSED2 ); REG64_FLD( PU_VAS_PBCFG1_PBCFG_1_UNUSED2_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PBCFG_1_UNUSED2_LEN ); REG64_FLD( PU_VAS_PGMIG1_PGMIGR1_VAL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR1_VAL ); REG64_FLD( PU_VAS_PGMIG1_PGMIGR1_BAR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR1_BAR ); REG64_FLD( PU_VAS_PGMIG1_PGMIGR1_BAR_LEN , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR1_BAR_LEN ); REG64_FLD( PU_VAS_PGMIG1_PGMIGR1_PGSZ , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR1_PGSZ ); REG64_FLD( PU_VAS_PGMIG1_PGMIGR1_PGSZ_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR1_PGSZ_LEN ); REG64_FLD( PU_VAS_PGMIG2_PGMIGR2_VAL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR2_VAL ); REG64_FLD( PU_VAS_PGMIG2_PGMIGR2_BAR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR2_BAR ); REG64_FLD( PU_VAS_PGMIG2_PGMIGR2_BAR_LEN , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR2_BAR_LEN ); REG64_FLD( PU_VAS_PGMIG2_PGMIGR2_PGSZ , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR2_PGSZ ); REG64_FLD( PU_VAS_PGMIG2_PGMIGR2_PGSZ_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR2_PGSZ_LEN ); REG64_FLD( PU_VAS_PGMIG3_PGMIGR3_VAL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR3_VAL ); REG64_FLD( PU_VAS_PGMIG3_PGMIGR3_BAR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR3_BAR ); REG64_FLD( PU_VAS_PGMIG3_PGMIGR3_BAR_LEN , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR3_BAR_LEN ); REG64_FLD( PU_VAS_PGMIG3_PGMIGR3_PGSZ , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR3_PGSZ ); REG64_FLD( PU_VAS_PGMIG3_PGMIGR3_PGSZ_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR3_PGSZ_LEN ); REG64_FLD( PU_VAS_PGMIG4_PGMIGR4_VAL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR4_VAL ); REG64_FLD( PU_VAS_PGMIG4_PGMIGR4_BAR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR4_BAR ); REG64_FLD( PU_VAS_PGMIG4_PGMIGR4_BAR_LEN , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR4_BAR_LEN ); REG64_FLD( PU_VAS_PGMIG4_PGMIGR4_PGSZ , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR4_PGSZ ); REG64_FLD( PU_VAS_PGMIG4_PGMIGR4_PGSZ_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR4_PGSZ_LEN ); REG64_FLD( PU_VAS_PGMIG5_PGMIGR5_VAL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR5_VAL ); REG64_FLD( PU_VAS_PGMIG5_PGMIGR5_BAR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR5_BAR ); REG64_FLD( PU_VAS_PGMIG5_PGMIGR5_BAR_LEN , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR5_BAR_LEN ); REG64_FLD( PU_VAS_PGMIG5_PGMIGR5_PGSZ , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR5_PGSZ ); REG64_FLD( PU_VAS_PGMIG5_PGMIGR5_PGSZ_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR5_PGSZ_LEN ); REG64_FLD( PU_VAS_PGMIG6_PGMIGR6_VAL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR6_VAL ); REG64_FLD( PU_VAS_PGMIG6_PGMIGR6_BAR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR6_BAR ); REG64_FLD( PU_VAS_PGMIG6_PGMIGR6_BAR_LEN , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR6_BAR_LEN ); REG64_FLD( PU_VAS_PGMIG6_PGMIGR6_PGSZ , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR6_PGSZ ); REG64_FLD( PU_VAS_PGMIG6_PGMIGR6_PGSZ_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR6_PGSZ_LEN ); REG64_FLD( PU_VAS_PGMIG7_PGMIGR7_VAL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR7_VAL ); REG64_FLD( PU_VAS_PGMIG7_PGMIGR7_BAR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR7_BAR ); REG64_FLD( PU_VAS_PGMIG7_PGMIGR7_BAR_LEN , 46 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR7_BAR_LEN ); REG64_FLD( PU_VAS_PGMIG7_PGMIGR7_PGSZ , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR7_PGSZ ); REG64_FLD( PU_VAS_PGMIG7_PGMIGR7_PGSZ_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PGMIGR7_PGSZ_LEN ); REG64_FLD( PU_VAS_PMCNTL_PU_BIT_ENABLES , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PU_BIT_ENABLES ); REG64_FLD( PU_VAS_PMCNTL_PU_BIT_ENABLES_LEN , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PU_BIT_ENABLES_LEN ); REG64_FLD( PU_VAS_PMCNTL_PU_CNTL_UNUSED , 32 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PU_CNTL_UNUSED ); REG64_FLD( PU_VAS_PMCNTL_PU_CNTL_UNUSED_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_PU_CNTL_UNUSED_LEN ); REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_RESET , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RG_CERR_RESET ); REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT4 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_RG_CERR_BIT4 ); REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT5 , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_RG_CERR_BIT5 ); REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT6 , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_RG_CERR_BIT6 ); REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT7 , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_RG_CERR_BIT7 ); REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT8 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_RG_CERR_BIT8 ); REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT9 , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_RG_CERR_BIT9 ); REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT10 , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_RG_CERR_BIT10 ); REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT11 , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_RG_CERR_BIT11 ); REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT12 , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_RG_CERR_BIT12 ); REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_BIT13 , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_RG_CERR_BIT13 ); REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_UNUSED_BITS , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_RG_CERR_UNUSED_BITS ); REG64_FLD( PU_VAS_RGERRRPT_RG_CERR_UNUSED_BITS_LEN , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_RG_CERR_UNUSED_BITS_LEN ); REG64_FLD( PU_VAS_RMABAR_RMA_BAR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RMA_BAR ); REG64_FLD( PU_VAS_RMABAR_RMA_BAR_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RMA_BAR_LEN ); REG64_FLD( PU_VAS_RMABARM_RMA_BAR_MASK , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RMA_BAR_MASK ); REG64_FLD( PU_VAS_RMABARM_RMA_BAR_MASK_LEN , 44 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_RMA_BAR_MASK_LEN ); REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_DISABLE_WC_SCRUB , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_SOUTH_CTL_DISABLE_WC_SCRUB ); REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_DISABLE_WC_ECC , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_SOUTH_CTL_DISABLE_WC_ECC ); REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_EG_SINGLE_THREAD , 2 , SH_UNT , SH_ACS_SCOM , SH_FLD_SOUTH_CTL_EG_SINGLE_THREAD ); REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_EG_WM_CTX_UPDATE_MODE , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_SOUTH_CTL_EG_WM_CTX_UPDATE_MODE ); REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_EG_STAMP_DEBUG , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_SOUTH_CTL_EG_STAMP_DEBUG ); REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_EN_FAST_SCRUB , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_SOUTH_CTL_EN_FAST_SCRUB ); REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_DIS_SIMULT_RD_WR , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_SOUTH_CTL_DIS_SIMULT_RD_WR ); REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_ENA_NOTIFY_ORDER , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_SOUTH_CTL_ENA_NOTIFY_ORDER ); REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_WC_IDLE_BIT , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_SOUTH_CTL_WC_IDLE_BIT ); REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_CQ_IDLE_BIT , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_SOUTH_CTL_CQ_IDLE_BIT ); REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_EG_IDLE_BIT , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_SOUTH_CTL_EG_IDLE_BIT ); REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_UNUSED , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_SOUTH_CTL_UNUSED ); REG64_FLD( PU_VAS_SOUTHCTL_SOUTH_CTL_UNUSED_LEN , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_SOUTH_CTL_UNUSED_LEN ); REG64_FLD( PU_VAS_UWMBAR_BASE_ADDR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BASE_ADDR ); REG64_FLD( PU_VAS_UWMBAR_BASE_ADDR_LEN , 28 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BASE_ADDR_LEN ); REG64_FLD( PU_VAS_WCBSBAR_WC_BS_BAR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WC_BS_BAR ); REG64_FLD( PU_VAS_WCBSBAR_WC_BS_BAR_LEN , 33 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WC_BS_BAR_LEN ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_RESET , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_RESET ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT4 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_BIT4 ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT5 , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_BIT5 ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT6 , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_BIT6 ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT7 , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_BIT7 ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT8 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_BIT8 ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT9 , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_BIT9 ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT10 , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_BIT10 ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT11 , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_BIT11 ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT12 , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_BIT12 ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT13 , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_BIT13 ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT14 , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_BIT14 ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT15 , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_BIT15 ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT16 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_BIT16 ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT17 , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_BIT17 ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT18 , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_BIT18 ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT19 , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_BIT19 ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT20 , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_BIT20 ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT21 , 21 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_BIT21 ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT22 , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_BIT22 ); REG64_FLD( PU_VAS_WCERRRPT_WC_CERR_BIT23 , 23 , SH_UNT , SH_ACS_SCOM , SH_FLD_WC_CERR_BIT23 ); REG64_FLD( PU_VAS_WCMBAR_BASE_ADDR , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BASE_ADDR ); REG64_FLD( PU_VAS_WCMBAR_BASE_ADDR_LEN , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_BASE_ADDR_LEN ); REG64_FLD( PU_VAS_WRMON0BAR_WRMON_BAR0_BA , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR0_BA ); REG64_FLD( PU_VAS_WRMON0BAR_WRMON_BAR0_BA_LEN , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR0_BA_LEN ); REG64_FLD( PU_VAS_WRMON0BAR_WRMON_BAR0_SIZE , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR0_SIZE ); REG64_FLD( PU_VAS_WRMON0BAR_WRMON_BAR0_SIZE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR0_SIZE_LEN ); REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_VAL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP0_VAL ); REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TTYPEDIS , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP0_TTYPEDIS ); REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TTYPEDIS_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP0_TTYPEDIS_LEN ); REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_UNUSED , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP0_UNUSED ); REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_ENADTTYPE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP0_ENADTTYPE ); REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TTYPE , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP0_TTYPE ); REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TTYPE_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP0_TTYPE_LEN ); REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TSIZE , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP0_TSIZE ); REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TSIZE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP0_TSIZE_LEN ); REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TTYPEMSK , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP0_TTYPEMSK ); REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TTYPEMSK_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP0_TTYPEMSK_LEN ); REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TSIZEMSK , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP0_TSIZEMSK ); REG64_FLD( PU_VAS_WRMON0CMP_WRMON_CMP0_TSIZEMSK_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP0_TSIZEMSK_LEN ); REG64_FLD( PU_VAS_WRMON0WID_WRMON_WID0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_WID0 ); REG64_FLD( PU_VAS_WRMON0WID_WRMON_WID0_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_WID0_LEN ); REG64_FLD( PU_VAS_WRMON1BAR_WRMON_BAR1_BA , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR1_BA ); REG64_FLD( PU_VAS_WRMON1BAR_WRMON_BAR1_BA_LEN , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR1_BA_LEN ); REG64_FLD( PU_VAS_WRMON1BAR_WRMON_BAR1_SIZE , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR1_SIZE ); REG64_FLD( PU_VAS_WRMON1BAR_WRMON_BAR1_SIZE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR1_SIZE_LEN ); REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_VAL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP1_VAL ); REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TTYPEDIS , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP1_TTYPEDIS ); REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TTYPEDIS_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP1_TTYPEDIS_LEN ); REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_UNUSED , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP1_UNUSED ); REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_ENADTTYPE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP1_ENADTTYPE ); REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TTYPE , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP1_TTYPE ); REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TTYPE_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP1_TTYPE_LEN ); REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TSIZE , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP1_TSIZE ); REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TSIZE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP1_TSIZE_LEN ); REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TTYPEMSK , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP1_TTYPEMSK ); REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TTYPEMSK_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP1_TTYPEMSK_LEN ); REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TSIZEMSK , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP1_TSIZEMSK ); REG64_FLD( PU_VAS_WRMON1CMP_WRMON_CMP1_TSIZEMSK_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP1_TSIZEMSK_LEN ); REG64_FLD( PU_VAS_WRMON1WID_WRMON_WID1 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_WID1 ); REG64_FLD( PU_VAS_WRMON1WID_WRMON_WID1_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_WID1_LEN ); REG64_FLD( PU_VAS_WRMON2BAR_WRMON_BAR2_BA , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR2_BA ); REG64_FLD( PU_VAS_WRMON2BAR_WRMON_BAR2_BA_LEN , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR2_BA_LEN ); REG64_FLD( PU_VAS_WRMON2BAR_WRMON_BAR2_SIZE , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR2_SIZE ); REG64_FLD( PU_VAS_WRMON2BAR_WRMON_BAR2_SIZE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR2_SIZE_LEN ); REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_VAL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP2_VAL ); REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TTYPEDIS , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP2_TTYPEDIS ); REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TTYPEDIS_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP2_TTYPEDIS_LEN ); REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_UNUSED , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP2_UNUSED ); REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_ENADTTYPE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP2_ENADTTYPE ); REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TTYPE , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP2_TTYPE ); REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TTYPE_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP2_TTYPE_LEN ); REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TSIZE , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP2_TSIZE ); REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TSIZE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP2_TSIZE_LEN ); REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TTYPEMSK , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP2_TTYPEMSK ); REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TTYPEMSK_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP2_TTYPEMSK_LEN ); REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TSIZEMSK , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP2_TSIZEMSK ); REG64_FLD( PU_VAS_WRMON2CMP_WRMON_CMP2_TSIZEMSK_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP2_TSIZEMSK_LEN ); REG64_FLD( PU_VAS_WRMON2WID_WRMON_WID2 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_WID2 ); REG64_FLD( PU_VAS_WRMON2WID_WRMON_WID2_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_WID2_LEN ); REG64_FLD( PU_VAS_WRMON3BAR_WRMON_BAR3_BA , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR3_BA ); REG64_FLD( PU_VAS_WRMON3BAR_WRMON_BAR3_BA_LEN , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR3_BA_LEN ); REG64_FLD( PU_VAS_WRMON3BAR_WRMON_BAR3_SIZE , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR3_SIZE ); REG64_FLD( PU_VAS_WRMON3BAR_WRMON_BAR3_SIZE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR3_SIZE_LEN ); REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_VAL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP3_VAL ); REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TTYPEDIS , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP3_TTYPEDIS ); REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TTYPEDIS_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP3_TTYPEDIS_LEN ); REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_UNUSED , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP3_UNUSED ); REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_ENADTTYPE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP3_ENADTTYPE ); REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TTYPE , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP3_TTYPE ); REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TTYPE_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP3_TTYPE_LEN ); REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TSIZE , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP3_TSIZE ); REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TSIZE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP3_TSIZE_LEN ); REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TTYPEMSK , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP3_TTYPEMSK ); REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TTYPEMSK_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP3_TTYPEMSK_LEN ); REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TSIZEMSK , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP3_TSIZEMSK ); REG64_FLD( PU_VAS_WRMON3CMP_WRMON_CMP3_TSIZEMSK_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP3_TSIZEMSK_LEN ); REG64_FLD( PU_VAS_WRMON3WID_WRMON_WID3 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_WID3 ); REG64_FLD( PU_VAS_WRMON3WID_WRMON_WID3_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_WID3_LEN ); REG64_FLD( PU_VAS_WRMON4BAR_WRMON_BAR4_BA , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR4_BA ); REG64_FLD( PU_VAS_WRMON4BAR_WRMON_BAR4_BA_LEN , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR4_BA_LEN ); REG64_FLD( PU_VAS_WRMON4BAR_WRMON_BAR4_SIZE , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR4_SIZE ); REG64_FLD( PU_VAS_WRMON4BAR_WRMON_BAR4_SIZE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR4_SIZE_LEN ); REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_VAL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP4_VAL ); REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TTYPEDIS , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP4_TTYPEDIS ); REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TTYPEDIS_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP4_TTYPEDIS_LEN ); REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_UNUSED , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP4_UNUSED ); REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_ENADTTYPE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP4_ENADTTYPE ); REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TTYPE , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP4_TTYPE ); REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TTYPE_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP4_TTYPE_LEN ); REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TSIZE , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP4_TSIZE ); REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TSIZE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP4_TSIZE_LEN ); REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TTYPEMSK , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP4_TTYPEMSK ); REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TTYPEMSK_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP4_TTYPEMSK_LEN ); REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TSIZEMSK , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP4_TSIZEMSK ); REG64_FLD( PU_VAS_WRMON4CMP_WRMON_CMP4_TSIZEMSK_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP4_TSIZEMSK_LEN ); REG64_FLD( PU_VAS_WRMON4WID_WRMON_WID4 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_WID4 ); REG64_FLD( PU_VAS_WRMON4WID_WRMON_WID4_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_WID4_LEN ); REG64_FLD( PU_VAS_WRMON5BAR_WRMON_BAR5_BA , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR5_BA ); REG64_FLD( PU_VAS_WRMON5BAR_WRMON_BAR5_BA_LEN , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR5_BA_LEN ); REG64_FLD( PU_VAS_WRMON5BAR_WRMON_BAR5_SIZE , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR5_SIZE ); REG64_FLD( PU_VAS_WRMON5BAR_WRMON_BAR5_SIZE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR5_SIZE_LEN ); REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_VAL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP5_VAL ); REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TTYPEDIS , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP5_TTYPEDIS ); REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TTYPEDIS_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP5_TTYPEDIS_LEN ); REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_UNUSED , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP5_UNUSED ); REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_ENADTTYPE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP5_ENADTTYPE ); REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TTYPE , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP5_TTYPE ); REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TTYPE_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP5_TTYPE_LEN ); REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TSIZE , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP5_TSIZE ); REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TSIZE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP5_TSIZE_LEN ); REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TTYPEMSK , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP5_TTYPEMSK ); REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TTYPEMSK_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP5_TTYPEMSK_LEN ); REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TSIZEMSK , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP5_TSIZEMSK ); REG64_FLD( PU_VAS_WRMON5CMP_WRMON_CMP5_TSIZEMSK_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP5_TSIZEMSK_LEN ); REG64_FLD( PU_VAS_WRMON5WID_WRMON_WID5 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_WID5 ); REG64_FLD( PU_VAS_WRMON5WID_WRMON_WID5_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_WID5_LEN ); REG64_FLD( PU_VAS_WRMON6BAR_WRMON_BAR6_BA , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR6_BA ); REG64_FLD( PU_VAS_WRMON6BAR_WRMON_BAR6_BA_LEN , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR6_BA_LEN ); REG64_FLD( PU_VAS_WRMON6BAR_WRMON_BAR6_SIZE , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR6_SIZE ); REG64_FLD( PU_VAS_WRMON6BAR_WRMON_BAR6_SIZE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR6_SIZE_LEN ); REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_VAL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP6_VAL ); REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TTYPEDIS , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP6_TTYPEDIS ); REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TTYPEDIS_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP6_TTYPEDIS_LEN ); REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_UNUSED , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP6_UNUSED ); REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_ENADTTYPE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP6_ENADTTYPE ); REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TTYPE , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP6_TTYPE ); REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TTYPE_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP6_TTYPE_LEN ); REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TSIZE , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP6_TSIZE ); REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TSIZE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP6_TSIZE_LEN ); REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TTYPEMSK , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP6_TTYPEMSK ); REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TTYPEMSK_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP6_TTYPEMSK_LEN ); REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TSIZEMSK , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP6_TSIZEMSK ); REG64_FLD( PU_VAS_WRMON6CMP_WRMON_CMP6_TSIZEMSK_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP6_TSIZEMSK_LEN ); REG64_FLD( PU_VAS_WRMON6WID_WRMON_WID6 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_WID6 ); REG64_FLD( PU_VAS_WRMON6WID_WRMON_WID6_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_WID6_LEN ); REG64_FLD( PU_VAS_WRMON7BAR_WRMON_BAR7_BA , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR7_BA ); REG64_FLD( PU_VAS_WRMON7BAR_WRMON_BAR7_BA_LEN , 49 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR7_BA_LEN ); REG64_FLD( PU_VAS_WRMON7BAR_WRMON_BAR7_SIZE , 60 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR7_SIZE ); REG64_FLD( PU_VAS_WRMON7BAR_WRMON_BAR7_SIZE_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_BAR7_SIZE_LEN ); REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_VAL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP7_VAL ); REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TTYPEDIS , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP7_TTYPEDIS ); REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TTYPEDIS_LEN , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP7_TTYPEDIS_LEN ); REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_UNUSED , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP7_UNUSED ); REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_ENADTTYPE , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP7_ENADTTYPE ); REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TTYPE , 9 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP7_TTYPE ); REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TTYPE_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP7_TTYPE_LEN ); REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TSIZE , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP7_TSIZE ); REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TSIZE_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP7_TSIZE_LEN ); REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TTYPEMSK , 24 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP7_TTYPEMSK ); REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TTYPEMSK_LEN , 7 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP7_TTYPEMSK_LEN ); REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TSIZEMSK , 31 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP7_TSIZEMSK ); REG64_FLD( PU_VAS_WRMON7CMP_WRMON_CMP7_TSIZEMSK_LEN , 8 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_CMP7_TSIZEMSK_LEN ); REG64_FLD( PU_VAS_WRMON7WID_WRMON_WID7 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_WID7 ); REG64_FLD( PU_VAS_WRMON7WID_WRMON_WID7_LEN , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_WRMON_WID7_LEN ); REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH0_TIMER_ENBL , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH0_TIMER_ENBL ); REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH0_REF_DIV , 1 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH0_REF_DIV ); REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH0_REF_DIV_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH0_REF_DIV_LEN ); REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH1_TIMER_ENBL , 5 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH1_TIMER_ENBL ); REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH1_REF_DIV , 6 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH1_REF_DIV ); REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH1_REF_DIV_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH1_REF_DIV_LEN ); REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH2_TIMER_ENBL , 10 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH2_TIMER_ENBL ); REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH2_REF_DIV , 11 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH2_REF_DIV ); REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH2_REF_DIV_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH2_REF_DIV_LEN ); REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH3_TIMER_ENBL , 15 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH3_TIMER_ENBL ); REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH3_REF_DIV , 16 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH3_REF_DIV ); REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH3_REF_DIV_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH3_REF_DIV_LEN ); REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH4_TIMER_ENBL , 20 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH4_TIMER_ENBL ); REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH4_REF_DIV , 21 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH4_REF_DIV ); REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_CH4_REF_DIV_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_CH4_REF_DIV_LEN ); REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_DMA_TIMER_ENBL , 25 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_TIMER_ENBL ); REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_DMA_TIMER_REF_DIV , 26 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_TIMER_REF_DIV ); REG64_FLD( PU_WATCHDOG_HANG_TIMERS_CNTL_DMA_TIMER_REF_DIV_LEN , 4 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DMA_TIMER_REF_DIV_LEN ); REG64_FLD( PU_WATER_MARK_REGISTER_B_WATERMARK_REG_0 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_WATERMARK_REG_0 ); REG64_FLD( PU_WATER_MARK_REGISTER_B_WATERMARK_REG_0_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_WATERMARK_REG_0_LEN ); REG64_FLD( PU_WATER_MARK_REGISTER_B_PEEK_DATA1_0 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0 ); REG64_FLD( PU_WATER_MARK_REGISTER_B_PEEK_DATA1_0_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_0_LEN ); REG64_FLD( PU_WATER_MARK_REGISTER_B_LBUS_PARITY_ERR1_0 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_0 ); REG64_FLD( PU_WATER_MARK_REGISTER_C_WATERMARK_REG_1 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_WATERMARK_REG_1 ); REG64_FLD( PU_WATER_MARK_REGISTER_C_WATERMARK_REG_1_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_WATERMARK_REG_1_LEN ); REG64_FLD( PU_WATER_MARK_REGISTER_C_PEEK_DATA1_1 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1 ); REG64_FLD( PU_WATER_MARK_REGISTER_C_PEEK_DATA1_1_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_1_LEN ); REG64_FLD( PU_WATER_MARK_REGISTER_C_LBUS_PARITY_ERR1_1 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_1 ); REG64_FLD( PU_WATER_MARK_REGISTER_D_WATERMARK_REG_2 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_WATERMARK_REG_2 ); REG64_FLD( PU_WATER_MARK_REGISTER_D_WATERMARK_REG_2_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_WATERMARK_REG_2_LEN ); REG64_FLD( PU_WATER_MARK_REGISTER_D_PEEK_DATA1_2 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2 ); REG64_FLD( PU_WATER_MARK_REGISTER_D_PEEK_DATA1_2_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_2_LEN ); REG64_FLD( PU_WATER_MARK_REGISTER_D_LBUS_PARITY_ERR1_2 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_2 ); REG64_FLD( PU_WATER_MARK_REGISTER_E_WATERMARK_REG_3 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_WATERMARK_REG_3 ); REG64_FLD( PU_WATER_MARK_REGISTER_E_WATERMARK_REG_3_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_WATERMARK_REG_3_LEN ); REG64_FLD( PU_WATER_MARK_REGISTER_E_PEEK_DATA1_3 , 32 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3 ); REG64_FLD( PU_WATER_MARK_REGISTER_E_PEEK_DATA1_3_LEN , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_PEEK_DATA1_3_LEN ); REG64_FLD( PU_WATER_MARK_REGISTER_E_LBUS_PARITY_ERR1_3 , 40 , SH_UNT , SH_ACS_SCOM , SH_FLD_LBUS_PARITY_ERR1_3 ); REG64_FLD( PU_N3_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RING_LOCKING ); REG64_FLD( PU_N3_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RESERVED_RING_LOCKING ); REG64_FLD( PU_N1_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RING_LOCKING ); REG64_FLD( PU_N1_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RESERVED_RING_LOCKING ); REG64_FLD( PU_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RING_LOCKING ); REG64_FLD( PU_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESERVED_RING_LOCKING ); REG64_FLD( PU_N2_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RING_LOCKING ); REG64_FLD( PU_N2_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RESERVED_RING_LOCKING ); REG64_FLD( PEC_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RING_LOCKING ); REG64_FLD( PEC_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RESERVED_RING_LOCKING ); REG64_FLD( PU_N0_WRITE_PROTECT_ENABLE_REG_RING_LOCKING , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RING_LOCKING ); REG64_FLD( PU_N0_WRITE_PROTECT_ENABLE_REG_RESERVED_RING_LOCKING , 1 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RESERVED_RING_LOCKING ); REG64_FLD( PU_N3_WRITE_PROTECT_RINGS_REG_RINGS , 0 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RINGS ); REG64_FLD( PU_N3_WRITE_PROTECT_RINGS_REG_RINGS_LEN , 16 , SH_UNT_PU_N3 , SH_ACS_SCOM , SH_FLD_RINGS_LEN ); REG64_FLD( PU_N1_WRITE_PROTECT_RINGS_REG_RINGS , 0 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RINGS ); REG64_FLD( PU_N1_WRITE_PROTECT_RINGS_REG_RINGS_LEN , 16 , SH_UNT_PU_N1 , SH_ACS_SCOM , SH_FLD_RINGS_LEN ); REG64_FLD( PU_WRITE_PROTECT_RINGS_REG_RINGS , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_RINGS ); REG64_FLD( PU_WRITE_PROTECT_RINGS_REG_RINGS_LEN , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_RINGS_LEN ); REG64_FLD( PU_N2_WRITE_PROTECT_RINGS_REG_RINGS , 0 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RINGS ); REG64_FLD( PU_N2_WRITE_PROTECT_RINGS_REG_RINGS_LEN , 16 , SH_UNT_PU_N2 , SH_ACS_SCOM , SH_FLD_RINGS_LEN ); REG64_FLD( PEC_WRITE_PROTECT_RINGS_REG_RINGS , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RINGS ); REG64_FLD( PEC_WRITE_PROTECT_RINGS_REG_RINGS_LEN , 16 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_RINGS_LEN ); REG64_FLD( PU_N0_WRITE_PROTECT_RINGS_REG_RINGS , 0 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RINGS ); REG64_FLD( PU_N0_WRITE_PROTECT_RINGS_REG_RINGS_LEN , 16 , SH_UNT_PU_N0 , SH_ACS_SCOM , SH_FLD_RINGS_LEN ); REG64_FLD( PEC_XFIR_IN0 , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN0 ); REG64_FLD( PEC_XFIR_IN1 , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN1 ); REG64_FLD( PEC_XFIR_IN2 , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN2 ); REG64_FLD( PEC_XFIR_IN3 , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN3 ); REG64_FLD( PEC_XFIR_IN4 , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN4 ); REG64_FLD( PEC_XFIR_IN5 , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN5 ); REG64_FLD( PEC_XFIR_IN6 , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN6 ); REG64_FLD( PEC_XFIR_IN6_LEN , 20 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN6_LEN ); REG64_FLD( PEC_XFIR_IN26 , 26 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_IN26 ); REG64_FLD( CAPP_XPT_CONTROL_SEND_PACKET_TIMER_VALUE , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SEND_PACKET_TIMER_VALUE ); REG64_FLD( CAPP_XPT_CONTROL_SEND_PACKET_TIMER_VALUE_LEN , 10 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SEND_PACKET_TIMER_VALUE_LEN ); REG64_FLD( CAPP_XPT_CONTROL_CI_STORE_BUFFER_THRESHOLD , 10 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_CI_STORE_BUFFER_THRESHOLD ); REG64_FLD( CAPP_XPT_CONTROL_CI_STORE_BUFFER_THRESHOLD_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_CI_STORE_BUFFER_THRESHOLD_LEN ); REG64_FLD( CAPP_XPT_CONTROL_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS , 14 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS ); REG64_FLD( CAPP_XPT_CONTROL_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_MAX_LPC_DATA_PBH0_CI_STORE_BUFFERS_LEN ); REG64_FLD( CAPP_XPT_CONTROL_TLBI_DATA_POLL_PULSE_DIV , 18 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TLBI_DATA_POLL_PULSE_DIV ); REG64_FLD( CAPP_XPT_CONTROL_TLBI_DATA_POLL_PULSE_DIV_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TLBI_DATA_POLL_PULSE_DIV_LEN ); REG64_FLD( CAPP_XPT_CONTROL_SN_WRT_DBUF_MAX_CREDIT , 22 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SN_WRT_DBUF_MAX_CREDIT ); REG64_FLD( CAPP_XPT_CONTROL_SN_WRT_DBUF_MAX_CREDIT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SN_WRT_DBUF_MAX_CREDIT_LEN ); REG64_FLD( CAPP_XPT_CONTROL_RESERVED , 26 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_RESERVED ); REG64_FLD( CAPP_XPT_CONTROL_RESERVED_LEN , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_RESERVED_LEN ); REG64_FLD( CAPP_XPT_CONTROL_SN_MSG_MAX_CREDIT , 28 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SN_MSG_MAX_CREDIT ); REG64_FLD( CAPP_XPT_CONTROL_SN_MSG_MAX_CREDIT_LEN , 9 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SN_MSG_MAX_CREDIT_LEN ); REG64_FLD( CAPP_XPT_CONTROL_BENIGN_PTR_DATA , 37 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_BENIGN_PTR_DATA ); REG64_FLD( CAPP_XPT_CONTROL_TLBIE_STALL_EN , 38 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TLBIE_STALL_EN ); REG64_FLD( CAPP_XPT_CONTROL_TLBIE_STALL_THRESHOLD , 39 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TLBIE_STALL_THRESHOLD ); REG64_FLD( CAPP_XPT_CONTROL_TLBIE_STALL_THRESHOLD_LEN , 3 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TLBIE_STALL_THRESHOLD_LEN ); REG64_FLD( CAPP_XPT_CONTROL_TLBIE_STALL_CMPLT_CNT , 42 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TLBIE_STALL_CMPLT_CNT ); REG64_FLD( CAPP_XPT_CONTROL_TLBIE_STALL_CMPLT_CNT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TLBIE_STALL_CMPLT_CNT_LEN ); REG64_FLD( CAPP_XPT_CONTROL_TLBIE_STALL_DELAY_CNT , 46 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TLBIE_STALL_DELAY_CNT ); REG64_FLD( CAPP_XPT_CONTROL_TLBIE_STALL_DELAY_CNT_LEN , 8 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TLBIE_STALL_DELAY_CNT_LEN ); REG64_FLD( CAPP_XPT_CONTROL_CI_BUFF_MIN , 58 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_CI_BUFF_MIN ); REG64_FLD( CAPP_XPT_CONTROL_CI_BUFF_MIN_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_CI_BUFF_MIN_LEN ); REG64_FLD( CAPP_XPT_CONTROL_CI_BUFF_AVAIL , 62 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_CI_BUFF_AVAIL ); REG64_FLD( CAPP_XPT_CONTROL_LOAD_CI_BUFF , 63 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_LOAD_CI_BUFF ); REG64_FLD( CAPP_XPT_ERROR_REPORT_PSL_CMD_UE_ERRHOLD , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PSL_CMD_UE_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_PSL_CMD_SUE_ERRHOLD , 1 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PSL_CMD_SUE_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_SC_RDATA_PARITY_ERRHOLD , 2 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SC_RDATA_PARITY_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_APC_SC_RDATA_PARITY_ERRHOLD , 3 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APC_SC_RDATA_PARITY_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_SN_SC_RDATA_PARITY_ERRHOLD , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SN_SC_RDATA_PARITY_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_NX_DATA_RTAG_PARITY_ERRHOLD , 5 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_NX_DATA_RTAG_PARITY_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_ECC_CE_ERRHOLD , 6 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_NXPBXPT_PBRCV_ECC_CE_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_ECC_UE_ERRHOLD , 7 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_NXPBXPT_PBRCV_ECC_UE_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_ECC_SUE_ERRHOLD , 8 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_NXPBXPT_PBRCV_ECC_SUE_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_DBG_CTL_REG_PARITY_ERRHOLD , 9 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_DBG_CTL_REG_PARITY_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_CFG_REG_PARITY_ERRHOLD , 10 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_CFG_REG_PARITY_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_CAPP_ERR_STAT_CTL_REG_PARITY_ERRHOLD , 11 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_CAPP_ERR_STAT_CTL_REG_PARITY_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_PMU_CNTRA_CFG_REG_PARITY_ERRHOLD , 12 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMU_CNTRA_CFG_REG_PARITY_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_PMU_CNTRB_CFG_REG_PARITY_ERRHOLD , 13 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMU_CNTRB_CFG_REG_PARITY_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_PMU_EVENT_SEL_REG_PARITY_ERRHOLD , 14 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMU_EVENT_SEL_REG_PARITY_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_PE0_CXA_LINKDOWN_ERRHOLD , 15 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PE0_CXA_LINKDOWN_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_PE1_CXA_LINKDOWN_ERRHOLD , 16 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PE1_CXA_LINKDOWN_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_SB_SCOM_ERRHOLD , 17 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SB_SCOM_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_PBXMIT_MSGQ_SEQ_ERRHOLD , 18 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PBXMIT_MSGQ_SEQ_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_PBXMIT_DXMIT_SEQ_ERRHOLD , 19 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PBXMIT_DXMIT_SEQ_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_EPH_REC_TMR_CNTL_REG_PARITY_ERRHOLD , 20 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_EPH_REC_TMR_CNTL_REG_PARITY_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_RCS_RECOVERY_FAILED_ERRHOLD , 21 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_RCS_RECOVERY_FAILED_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_RCS_STATE_MACHINE_ERRHOLD , 22 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_RCS_STATE_MACHINE_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_LNK_RSP_ECC_UE_ERRHOLD , 23 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_NXPBXPT_PBRCV_LNK_RSP_ECC_UE_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_NXPBXPT_PBRCV_LNK_RSP_ECC_SUE_ERRHOLD , 24 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_NXPBXPT_PBRCV_LNK_RSP_ECC_SUE_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_LNK_RSP_PKT_DISCARDED_ERRHOLD , 25 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_LNK_RSP_PKT_DISCARDED_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_SECURE_LNK_RSP_PKT_NOT_VALID_ERRHOLD , 26 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SECURE_LNK_RSP_PKT_NOT_VALID_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_SECURE_LNK_SCOM_CONFLICT_ERRHOLD , 27 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SECURE_LNK_SCOM_CONFLICT_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_UNSOLICITED_DATA_RCV_ERRHOLD , 28 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_UNSOLICITED_DATA_RCV_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_AS_RCMD0_PARITY_ERR_ERRHOLD , 29 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_AS_RCMD0_PARITY_ERR_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_AS_REGS_PARITY_ERR_ERRHOLD , 30 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_AS_REGS_PARITY_ERR_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_AS_SM_ERRHOLD , 31 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_AS_SM_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_AS_REG_RDATA_PERR_ERRHOLD , 32 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_AS_REG_RDATA_PERR_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_DFS_SM_ERRHOLD , 33 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_DFS_SM_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_FIR_ERR_ERRHOLD , 34 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TB_FIR_ERR_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_CMD_DISCARDED_ERRHOLD , 35 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TB_CMD_DISCARDED_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_REG_RDATA_PERR_ERRHOLD , 36 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TB_REG_RDATA_PERR_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_RNG_WR_ENBL_REG_PERR_ERRHOLD , 37 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_RNG_WR_ENBL_REG_PERR_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_SSA_ECC_HI_UE_ERRHOLD , 38 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SSA_ECC_HI_UE_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_SSA_ECC_HI_CE_ERRHOLD , 39 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SSA_ECC_HI_CE_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_SSA_ECC_HI_SUE_ERRHOLD , 40 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SSA_ECC_HI_SUE_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_SSA_ECC_LO_SUE_ERRHOLD , 41 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SSA_ECC_LO_SUE_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_SSA_ECC_LO_CE_ERRHOLD , 42 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SSA_ECC_LO_CE_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_SSA_ECC_LO_UE_ERRHOLD , 43 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_SSA_ECC_LO_UE_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_CXACQPB_MUX_ECC_CE_ERRHOLD , 44 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_CXACQPB_MUX_ECC_CE_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_CXACQPB_MUX_ECC_UE_ERRHOLD , 45 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_CXACQPB_MUX_ECC_UE_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_APC0_SC_RDATA_PARITY_ERRHOLD , 46 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_APC0_SC_RDATA_PARITY_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_CREDIT_TIMEOUT_ERRHOLD , 47 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_CREDIT_TIMEOUT_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_TLBI_SC_RDATA_PARITY_ERRHOLD , 48 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TLBI_SC_RDATA_PARITY_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_TLBI_REGS_PARITY_ERRHOLD , 49 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TLBI_REGS_PARITY_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_RCS_RECOVERY_TIMEOUT_ERRHOLD , 50 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_RCS_RECOVERY_TIMEOUT_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST0_BADIN_ERRHOLD , 51 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TBST0_BADIN_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST6_BADIN_ERRHOLD , 52 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TBST6_BADIN_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST7_BADIN_ERRHOLD , 53 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TBST7_BADIN_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_TWO_TFMRCMDS_ERR_ERRHOLD , 54 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TWO_TFMRCMDS_ERR_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_MISSING_SYNC_ERRHOLD , 55 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TB_MISSING_SYNC_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_MISSING_STEP_ERRHOLD , 56 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TB_MISSING_STEP_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_TB_RESIDUE_ERR_ERRHOLD , 57 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TB_RESIDUE_ERR_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_TX_TFMR_CORRUPT_ERRHOLD , 58 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TX_TFMR_CORRUPT_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST_CORRUPT_ERRHOLD , 59 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TBST_CORRUPT_ERRHOLD ); REG64_FLD( CAPP_XPT_ERROR_REPORT_TBST9_BADIN_ERRHOLD , 60 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_TBST9_BADIN_ERRHOLD ); REG64_FLD( CAPP_XPT_PMU_EVENTS_SEL_PMON_GROUP_SELECT , 0 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMON_GROUP_SELECT ); REG64_FLD( CAPP_XPT_PMU_EVENTS_SEL_PMON_GROUP_SELECT_LEN , 4 , SH_UNT_CAPP , SH_ACS_SCOM , SH_FLD_PMON_GROUP_SELECT_LEN ); REG64_FLD( PU_XSCOM_BASE_REG_FBC , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC ); REG64_FLD( PU_XSCOM_BASE_REG_FBC_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_LEN ); REG64_FLD( PU_XSCOM_BASE_REG_FBC_RESET , 61 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_RESET ); REG64_FLD( PU_XSCOM_BASE_REG_FBC_DISABLE , 62 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_DISABLE ); REG64_FLD( PU_XSCOM_BASE_REG_FBC_DISABLE_LOCAL_SHORTCUT , 63 , SH_UNT , SH_ACS_SCOM , SH_FLD_FBC_DISABLE_LOCAL_SHORTCUT ); REG64_FLD( PU_XSCOM_DAT0_REG_DAT0 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DAT0 ); REG64_FLD( PU_XSCOM_DAT0_REG_DAT0_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DAT0_LEN ); REG64_FLD( PU_XSCOM_DAT1_REG_DAT1 , 0 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DAT1 ); REG64_FLD( PU_XSCOM_DAT1_REG_DAT1_LEN , 64 , SH_UNT , SH_ACS_SCOM_RW , SH_FLD_DAT1_LEN ); REG64_FLD( PU_XSCOM_ERR_REG_ADDRESS , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_ADDRESS ); REG64_FLD( PU_XSCOM_ERR_REG_TSIZE , 1 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_TSIZE ); REG64_FLD( PU_XSCOM_ERR_REG_RC_TTAG_PAR , 2 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_RC_TTAG_PAR ); REG64_FLD( PU_XSCOM_ERR_REG_CR_TTAG_PAR , 3 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_CR_TTAG_PAR ); REG64_FLD( PU_XSCOM_ERR_REG_CR_ATAG_PAR , 4 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_CR_ATAG_PAR ); REG64_FLD( PU_XSCOM_ERR_REG_RC_ADDR_PAR , 5 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_RC_ADDR_PAR ); REG64_FLD( PU_XSCOM_ERR_REG_PB_ECC_CE , 8 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_PB_ECC_CE ); REG64_FLD( PU_XSCOM_ERR_REG_PB_ECC_UE , 9 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_PB_ECC_UE ); REG64_FLD( PU_XSCOM_ERR_REG_PB_ECC_SUE , 10 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_PB_ECC_SUE ); REG64_FLD( PU_XSCOM_ERR_REG_RTAG_PARITY , 11 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_RTAG_PARITY ); REG64_FLD( PU_XSCOM_ERR_REG_CRESP_HANG , 12 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_CRESP_HANG ); REG64_FLD( PU_XSCOM_ERR_REG_PIB_HANG , 13 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_PIB_HANG ); REG64_FLD( PU_XSCOM_ERR_REG_PBDATA_HANG , 14 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_PBDATA_HANG ); REG64_FLD( PU_XSCOM_ERR_REG_ADS_HANG , 15 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_ADS_HANG ); REG64_FLD( PU_XSCOM_ERR_REG_FSM_PERR , 16 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_FSM_PERR ); REG64_FLD( PU_XSCOM_ERR_REG_SPARE0 , 17 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_SPARE0 ); REG64_FLD( PU_XSCOM_ERR_REG_SPARE1 , 18 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_SPARE1 ); REG64_FLD( PU_XSCOM_ERR_REG_UNEXPECT_DATA , 19 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_UNEXPECT_DATA ); REG64_FLD( PU_XSCOM_ERR_REG_ILL_CRESP , 20 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_ILL_CRESP ); REG64_FLD( PU_XSCOM_LOG_REG_CMD_IN_PROG , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMD_IN_PROG ); REG64_FLD( PU_XSCOM_LOG_REG_CMD_STATUS , 1 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMD_STATUS ); REG64_FLD( PU_XSCOM_LOG_REG_CMD_STATUS_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_CMD_STATUS_LEN ); REG64_FLD( PU_XSCOM_LOG_REG_WRITE_CMD , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_WRITE_CMD ); REG64_FLD( PU_XSCOM_LOG_REG_ADDR_TAG , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDR_TAG ); REG64_FLD( PU_XSCOM_LOG_REG_ADDR_TAG_LEN , 22 , SH_UNT , SH_ACS_SCOM , SH_FLD_ADDR_TAG_LEN ); REG64_FLD( PU_XSCOM_LOG_REG_THR_ID , 27 , SH_UNT , SH_ACS_SCOM , SH_FLD_THR_ID ); REG64_FLD( PU_XSCOM_LOG_REG_THR_ID_LEN , 3 , SH_UNT , SH_ACS_SCOM , SH_FLD_THR_ID_LEN ); REG64_FLD( PU_XSCOM_LOG_REG_PIB_COMPONENT_BUSY , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_COMPONENT_BUSY ); REG64_FLD( PU_XSCOM_LOG_REG_PIB_ADDR , 33 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_ADDR ); REG64_FLD( PU_XSCOM_LOG_REG_PIB_ADDR_LEN , 31 , SH_UNT , SH_ACS_SCOM , SH_FLD_PIB_ADDR_LEN ); REG64_FLD( PU_XSCOM_MODE_REG_SPARE , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE ); REG64_FLD( PU_XSCOM_MODE_REG_SPARE_LEN , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_SPARE_LEN ); REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR1 , 4 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAR_PIB_ON_ERROR1 ); REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR2 , 5 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAR_PIB_ON_ERROR2 ); REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR3 , 6 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAR_PIB_ON_ERROR3 ); REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR4 , 7 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAR_PIB_ON_ERROR4 ); REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR5 , 8 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAR_PIB_ON_ERROR5 ); REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR6 , 9 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAR_PIB_ON_ERROR6 ); REG64_FLD( PU_XSCOM_MODE_REG_BAR_PIB_ON_ERROR7 , 10 , SH_UNT , SH_ACS_SCOM , SH_FLD_BAR_PIB_ON_ERROR7 ); REG64_FLD( PU_XSCOM_MODE_REG_HANG_PIB_RESET , 11 , SH_UNT , SH_ACS_SCOM , SH_FLD_HANG_PIB_RESET ); REG64_FLD( PU_XSCOM_MODE_REG_HANG_RESET , 12 , SH_UNT , SH_ACS_SCOM , SH_FLD_HANG_RESET ); REG64_FLD( PU_XSCOM_MODE_REG_RESET_ON_PARITY , 13 , SH_UNT , SH_ACS_SCOM , SH_FLD_RESET_ON_PARITY ); REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR1 , 14 , SH_UNT , SH_ACS_SCOM , SH_FLD_FREEZE_LOG_ON_ERROR1 ); REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR2 , 15 , SH_UNT , SH_ACS_SCOM , SH_FLD_FREEZE_LOG_ON_ERROR2 ); REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR3 , 16 , SH_UNT , SH_ACS_SCOM , SH_FLD_FREEZE_LOG_ON_ERROR3 ); REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR4 , 17 , SH_UNT , SH_ACS_SCOM , SH_FLD_FREEZE_LOG_ON_ERROR4 ); REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR5 , 18 , SH_UNT , SH_ACS_SCOM , SH_FLD_FREEZE_LOG_ON_ERROR5 ); REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR6 , 19 , SH_UNT , SH_ACS_SCOM , SH_FLD_FREEZE_LOG_ON_ERROR6 ); REG64_FLD( PU_XSCOM_MODE_REG_FREEZE_LOG_ON_ERROR7 , 20 , SH_UNT , SH_ACS_SCOM , SH_FLD_FREEZE_LOG_ON_ERROR7 ); REG64_FLD( PU_XSCOM_RCVED_STAT_REG_DONE , 0 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_DONE ); REG64_FLD( PU_XSCOM_RCVED_STAT_REG_RESULT , 1 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_RESULT ); REG64_FLD( PU_XSCOM_RCVED_STAT_REG_RESULT_LEN , 3 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_RESULT_LEN ); REG64_FLD( PU_XSCOM_RCVED_STAT_REG_COREID , 4 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COREID ); REG64_FLD( PU_XSCOM_RCVED_STAT_REG_COREID_LEN , 6 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_COREID_LEN ); REG64_FLD( PU_XSCOM_RCVED_STAT_REG_THRID , 10 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_THRID ); REG64_FLD( PU_XSCOM_RCVED_STAT_REG_THRID_LEN , 3 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_THRID_LEN ); REG64_FLD( PU_XSCOM_RCVED_STAT_REG_DEST_GROUPID , 13 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_DEST_GROUPID ); REG64_FLD( PU_XSCOM_RCVED_STAT_REG_DEST_GROUPID_LEN , 4 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_DEST_GROUPID_LEN ); REG64_FLD( PU_XSCOM_RCVED_STAT_REG_DEST_CHIPID , 17 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_DEST_CHIPID ); REG64_FLD( PU_XSCOM_RCVED_STAT_REG_DEST_CHIPID_LEN , 3 , SH_UNT , SH_ACS_SCOM_WCLRREG, SH_FLD_DEST_CHIPID_LEN ); REG64_FLD( PEC_XSTOP1_MASK_B , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MASK_B ); REG64_FLD( PEC_XSTOP1_UNUSED , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( PEC_XSTOP1_TRIGGER_OPCG_ON , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIGGER_OPCG_ON ); REG64_FLD( PEC_XSTOP1_WAIT_ALLWAYS , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_WAIT_ALLWAYS ); REG64_FLD( PEC_XSTOP1_PERV , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PERV ); REG64_FLD( PEC_XSTOP1_UNIT1 , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT1 ); REG64_FLD( PEC_XSTOP1_UNIT2 , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT2 ); REG64_FLD( PEC_XSTOP1_UNIT3 , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT3 ); REG64_FLD( PEC_XSTOP1_UNIT4 , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT4 ); REG64_FLD( PEC_XSTOP1_UNIT5 , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT5 ); REG64_FLD( PEC_XSTOP1_UNIT6 , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT6 ); REG64_FLD( PEC_XSTOP1_UNIT7 , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT7 ); REG64_FLD( PEC_XSTOP1_UNIT8 , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT8 ); REG64_FLD( PEC_XSTOP1_UNIT9 , 13 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT9 ); REG64_FLD( PEC_XSTOP1_UNIT10 , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT10 ); REG64_FLD( PEC_XSTOP1_WAIT_CYCLES , 48 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES ); REG64_FLD( PEC_XSTOP1_WAIT_CYCLES_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES_LEN ); REG64_FLD( PEC_XSTOP2_MASK_B , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MASK_B ); REG64_FLD( PEC_XSTOP2_UNUSED , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( PEC_XSTOP2_TRIGGER_OPCG_ON , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIGGER_OPCG_ON ); REG64_FLD( PEC_XSTOP2_WAIT_ALLWAYS , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_WAIT_ALLWAYS ); REG64_FLD( PEC_XSTOP2_PERV , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PERV ); REG64_FLD( PEC_XSTOP2_UNIT1 , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT1 ); REG64_FLD( PEC_XSTOP2_UNIT2 , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT2 ); REG64_FLD( PEC_XSTOP2_UNIT3 , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT3 ); REG64_FLD( PEC_XSTOP2_UNIT4 , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT4 ); REG64_FLD( PEC_XSTOP2_UNIT5 , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT5 ); REG64_FLD( PEC_XSTOP2_UNIT6 , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT6 ); REG64_FLD( PEC_XSTOP2_UNIT7 , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT7 ); REG64_FLD( PEC_XSTOP2_UNIT8 , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT8 ); REG64_FLD( PEC_XSTOP2_UNIT9 , 13 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT9 ); REG64_FLD( PEC_XSTOP2_UNIT10 , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT10 ); REG64_FLD( PEC_XSTOP2_WAIT_CYCLES , 48 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES ); REG64_FLD( PEC_XSTOP2_WAIT_CYCLES_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES_LEN ); REG64_FLD( PEC_XSTOP3_MASK_B , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_MASK_B ); REG64_FLD( PEC_XSTOP3_UNUSED , 1 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( PEC_XSTOP3_TRIGGER_OPCG_ON , 2 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_TRIGGER_OPCG_ON ); REG64_FLD( PEC_XSTOP3_WAIT_ALLWAYS , 3 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_WAIT_ALLWAYS ); REG64_FLD( PEC_XSTOP3_PERV , 4 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_PERV ); REG64_FLD( PEC_XSTOP3_UNIT1 , 5 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT1 ); REG64_FLD( PEC_XSTOP3_UNIT2 , 6 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT2 ); REG64_FLD( PEC_XSTOP3_UNIT3 , 7 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT3 ); REG64_FLD( PEC_XSTOP3_UNIT4 , 8 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT4 ); REG64_FLD( PEC_XSTOP3_UNIT5 , 9 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT5 ); REG64_FLD( PEC_XSTOP3_UNIT6 , 10 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT6 ); REG64_FLD( PEC_XSTOP3_UNIT7 , 11 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT7 ); REG64_FLD( PEC_XSTOP3_UNIT8 , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT8 ); REG64_FLD( PEC_XSTOP3_UNIT9 , 13 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT9 ); REG64_FLD( PEC_XSTOP3_UNIT10 , 14 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_UNIT10 ); REG64_FLD( PEC_XSTOP3_WAIT_CYCLES , 48 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES ); REG64_FLD( PEC_XSTOP3_WAIT_CYCLES_LEN , 12 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_WAIT_CYCLES_LEN ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE1_LEN ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE2 , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE2 ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE2_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE2_LEN ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE3 , 8 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE3 ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_RATE3_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE3_LEN ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_FWD_PROG_RATE2 , 14 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2 ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_FWD_PROG_RATE2_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2_LEN ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_CTL_TICK , 20 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CTL_TICK ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_CTL_TICK_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_CTL_TICK_LEN ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_INH0_TICK , 26 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_INH0_TICK ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_INH0_TICK_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_INH0_TICK_LEN ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_INH1_TICK , 32 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1 ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1_LEN ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2 ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2_LEN ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1 ); REG64_FLD( PU_NPU0_SM0_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM0, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_POCKET_RATE1_LEN ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_RATE2 , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_POCKET_RATE2 ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_RATE2_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_POCKET_RATE2_LEN ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_RATE3 , 8 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_POCKET_RATE3 ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_RATE3_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_POCKET_RATE3_LEN ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_FWD_PROG_RATE2 , 14 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2 ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_FWD_PROG_RATE2_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2_LEN ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_CTL_TICK , 20 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CTL_TICK ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_CTL_TICK_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_CTL_TICK_LEN ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_INH0_TICK , 26 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_INH0_TICK ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_INH0_TICK_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_INH0_TICK_LEN ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_INH1_TICK , 32 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1 ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1_LEN ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2 ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2_LEN ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1 ); REG64_FLD( PU_NPU1_SM2_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM2, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_RATE1_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_POCKET_RATE1_LEN ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_RATE2 , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_POCKET_RATE2 ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_RATE2_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_POCKET_RATE2_LEN ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_RATE3 , 8 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_POCKET_RATE3 ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_RATE3_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_POCKET_RATE3_LEN ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_FWD_PROG_RATE2 , 14 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2 ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_FWD_PROG_RATE2_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2_LEN ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_CTL_TICK , 20 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CTL_TICK ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_CTL_TICK_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_CTL_TICK_LEN ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_INH0_TICK , 26 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_INH0_TICK ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_INH0_TICK_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_INH0_TICK_LEN ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_INH1_TICK , 32 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1 ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1_LEN ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2 ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2_LEN ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1 ); REG64_FLD( PU_NPU2_SM3_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU2_SM3, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_POCKET_RATE1_LEN ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_RATE2 , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_POCKET_RATE2 ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_RATE2_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_POCKET_RATE2_LEN ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_RATE3 , 8 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_POCKET_RATE3 ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_RATE3_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_POCKET_RATE3_LEN ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_FWD_PROG_RATE2 , 14 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2 ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_FWD_PROG_RATE2_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2_LEN ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_CTL_TICK , 20 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CTL_TICK ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_CTL_TICK_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_CTL_TICK_LEN ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_INH0_TICK , 26 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_INH0_TICK ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_INH0_TICK_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_INH0_TICK_LEN ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_INH1_TICK , 32 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1 ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1_LEN ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2 ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2_LEN ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1 ); REG64_FLD( PU_NPU1_SM3_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM3, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POCKET_RATE1_LEN ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_RATE2 , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POCKET_RATE2 ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_RATE2_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POCKET_RATE2_LEN ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_RATE3 , 8 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POCKET_RATE3 ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_RATE3_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POCKET_RATE3_LEN ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_FWD_PROG_RATE2 , 14 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2 ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_FWD_PROG_RATE2_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2_LEN ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_CTL_TICK , 20 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CTL_TICK ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_CTL_TICK_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_CTL_TICK_LEN ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_INH0_TICK , 26 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_INH0_TICK ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_INH0_TICK_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_INH0_TICK_LEN ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_INH1_TICK , 32 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1 ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1_LEN ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2 ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2_LEN ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1 ); REG64_FLD( PU_NPU0_SM3_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM3, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_POCKET_RATE1_LEN ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_RATE2 , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_POCKET_RATE2 ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_RATE2_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_POCKET_RATE2_LEN ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_RATE3 , 8 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_POCKET_RATE3 ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_RATE3_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_POCKET_RATE3_LEN ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_FWD_PROG_RATE2 , 14 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2 ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_FWD_PROG_RATE2_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2_LEN ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_CTL_TICK , 20 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CTL_TICK ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_CTL_TICK_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_CTL_TICK_LEN ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_INH0_TICK , 26 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_INH0_TICK ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_INH0_TICK_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_INH0_TICK_LEN ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_INH1_TICK , 32 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1 ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1_LEN ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2 ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2_LEN ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1 ); REG64_FLD( PU_NPU1_SM1_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM1, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_RATE1_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POCKET_RATE1_LEN ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_RATE2 , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POCKET_RATE2 ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_RATE2_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POCKET_RATE2_LEN ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_RATE3 , 8 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POCKET_RATE3 ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_RATE3_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POCKET_RATE3_LEN ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_FWD_PROG_RATE2 , 14 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2 ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_FWD_PROG_RATE2_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2_LEN ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_CTL_TICK , 20 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CTL_TICK ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_CTL_TICK_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_CTL_TICK_LEN ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_INH0_TICK , 26 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_INH0_TICK ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_INH0_TICK_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_INH0_TICK_LEN ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_INH1_TICK , 32 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1 ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1_LEN ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2 ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2_LEN ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1 ); REG64_FLD( PU_NPU2_SM2_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU2_SM2, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_RATE1_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_POCKET_RATE1_LEN ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_RATE2 , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_POCKET_RATE2 ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_RATE2_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_POCKET_RATE2_LEN ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_RATE3 , 8 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_POCKET_RATE3 ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_RATE3_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_POCKET_RATE3_LEN ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_FWD_PROG_RATE2 , 14 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2 ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_FWD_PROG_RATE2_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2_LEN ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_CTL_TICK , 20 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CTL_TICK ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_CTL_TICK_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_CTL_TICK_LEN ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_INH0_TICK , 26 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_INH0_TICK ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_INH0_TICK_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_INH0_TICK_LEN ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_INH1_TICK , 32 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1 ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1_LEN ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2 ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2_LEN ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1 ); REG64_FLD( PU_NPU2_SM1_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU2_SM1, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_POCKET_RATE1_LEN ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_RATE2 , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_POCKET_RATE2 ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_RATE2_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_POCKET_RATE2_LEN ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_RATE3 , 8 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_POCKET_RATE3 ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_RATE3_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_POCKET_RATE3_LEN ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_FWD_PROG_RATE2 , 14 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2 ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_FWD_PROG_RATE2_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2_LEN ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_CTL_TICK , 20 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CTL_TICK ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_CTL_TICK_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_CTL_TICK_LEN ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_INH0_TICK , 26 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_INH0_TICK ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_INH0_TICK_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_INH0_TICK_LEN ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_INH1_TICK , 32 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1 ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1_LEN ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2 ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2_LEN ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1 ); REG64_FLD( PU_NPU0_SM2_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM2, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_RATE1_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE1_LEN ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_RATE2 , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE2 ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_RATE2_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE2_LEN ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_RATE3 , 8 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE3 ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_RATE3_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE3_LEN ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_FWD_PROG_RATE2 , 14 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2 ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_FWD_PROG_RATE2_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2_LEN ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_CTL_TICK , 20 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CTL_TICK ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_CTL_TICK_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_CTL_TICK_LEN ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_INH0_TICK , 26 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_INH0_TICK ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_INH0_TICK_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_INH0_TICK_LEN ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_INH1_TICK , 32 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1 ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1_LEN ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2 ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2_LEN ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1 ); REG64_FLD( PU_NPU2_SM0_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU2_SM0, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_POCKET_RATE1_LEN ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_RATE2 , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_POCKET_RATE2 ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_RATE2_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_POCKET_RATE2_LEN ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_RATE3 , 8 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_POCKET_RATE3 ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_RATE3_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_POCKET_RATE3_LEN ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_FWD_PROG_RATE2 , 14 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2 ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_FWD_PROG_RATE2_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2_LEN ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_CTL_TICK , 20 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CTL_TICK ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_CTL_TICK_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_CTL_TICK_LEN ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_INH0_TICK , 26 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_INH0_TICK ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_INH0_TICK_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_INH0_TICK_LEN ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_INH1_TICK , 32 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1 ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1_LEN ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2 ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2_LEN ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1 ); REG64_FLD( PU_NPU0_SM1_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU0_SM1, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_RATE1 , 0 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE1 ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE1_LEN ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_RATE2 , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE2 ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_RATE2_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE2_LEN ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_RATE3 , 8 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE3 ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_RATE3_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_POCKET_RATE3_LEN ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_FWD_PROG_RATE2 , 14 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2 ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_FWD_PROG_RATE2_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_FWD_PROG_RATE2_LEN ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_CTL_TICK , 20 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CTL_TICK ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_CTL_TICK_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_CTL_TICK_LEN ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_INH0_TICK , 26 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_INH0_TICK ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_INH0_TICK_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_INH0_TICK_LEN ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_INH1_TICK , 32 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_INH1_TICK ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_INH1_TICK_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_INH1_TICK_LEN ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_NV_RESP_RATE1 , 38 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1 ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_NV_RESP_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE1_LEN ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_NV_RESP_RATE2 , 40 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2 ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_NV_RESP_RATE2_LEN , 6 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_NV_RESP_RATE2_LEN ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_ND_RATE1 , 46 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1 ); REG64_FLD( PU_NPU1_SM0_XTIMER_CONFIG_POCKET_ND_RATE1_LEN , 2 , SH_UNT_PU_NPU1_SM0, SH_ACS_SCOM , SH_FLD_POCKET_ND_RATE1_LEN ); REG64_FLD( PEC_XTRA_TRACE_MODE_DATA , 0 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DATA ); REG64_FLD( PEC_XTRA_TRACE_MODE_DATA_LEN , 38 , SH_UNT_PEC , SH_ACS_SCOM , SH_FLD_DATA_LEN ); REG64_FLD( PU_XTRA_TRACE_MODE_DATA , 0 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA ); REG64_FLD( PU_XTRA_TRACE_MODE_DATA_LEN , 38 , SH_UNT , SH_ACS_SCOM , SH_FLD_DATA_LEN ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_ADDR , 15 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ADDR ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_ADDR_LEN , 37 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ADDR_LEN ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_FLAG_OTHER , 54 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_FLAG_OTHER ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_FLAG_PREF , 55 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_FLAG_PREF ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_FLAG_DMD , 56 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_FLAG_DMD ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_FLAG_MAP , 57 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_FLAG_MAP ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_FLAG_FENCE , 58 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_FLAG_FENCE ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_RETIRE , 59 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_RETIRE ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_IRQENA , 60 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_IRQENA ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_SECOND , 61 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_SECOND ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_TRIGGERED , 62 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_TRIGGERED ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISS_ENA , 63 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ENA ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISS2_ATRMISS_GPA , 27 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATRMISS_GPA ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISS2_ATRMISS_BDF , 28 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATRMISS_BDF ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISS2_ATRMISS_BDF_LEN , 16 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATRMISS_BDF_LEN ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISS2_ATRMISS_PASID , 44 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATRMISS_PASID ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISS2_ATRMISS_PASID_LEN , 20 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATRMISS_PASID_LEN ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_ADDR , 15 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATRMISS_ADDR ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_ADDR_LEN , 37 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATRMISS_ADDR_LEN ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_OTHER , 54 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATRMISS_FLAG_OTHER ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_PREF , 55 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATRMISS_FLAG_PREF ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_DMD , 56 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATRMISS_FLAG_DMD ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_MAP , 57 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATRMISS_FLAG_MAP ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_FLAG_FENCE , 58 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATRMISS_FLAG_FENCE ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_RETIRE , 59 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATRMISS_RETIRE ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_IRQENA , 60 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATRMISS_IRQENA ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_SECOND , 61 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATRMISS_SECOND ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_TRIGGERED , 62 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATRMISS_TRIGGERED ); REG64_FLD( PU_NPU_SM2_XTS_ATRMISSCLR_ATRMISS_ENA , 63 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATRMISS_ENA ); REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP0_LPARID , 52 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , SH_FLD_LPARID ); REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP0_LPARID_LEN , 12 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , SH_FLD_LPARID_LEN ); REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP1_LPARID , 52 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , SH_FLD_LPARID ); REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP1_LPARID_LEN , 12 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , SH_FLD_LPARID_LEN ); REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP2_LPARID , 52 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , SH_FLD_LPARID ); REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP2_LPARID_LEN , 12 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , SH_FLD_LPARID_LEN ); REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP3_LPARID , 52 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , SH_FLD_LPARID ); REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP3_LPARID_LEN , 12 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , SH_FLD_LPARID_LEN ); REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP4_LPARID , 52 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , SH_FLD_LPARID ); REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP4_LPARID_LEN , 12 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , SH_FLD_LPARID_LEN ); REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP5_LPARID , 52 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , SH_FLD_LPARID ); REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP5_LPARID_LEN , 12 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , SH_FLD_LPARID_LEN ); REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP6_LPARID , 52 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , SH_FLD_LPARID ); REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP6_LPARID_LEN , 12 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , SH_FLD_LPARID_LEN ); REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP7_LPARID , 52 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , SH_FLD_LPARID ); REG64_FLD( PU_NPU_SM3_XTS_ATSD_HYP7_LPARID_LEN , 12 , SH_UNT_PU_NPU_SM3, SH_ACS_SCOM , SH_FLD_LPARID_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_BRAZOS , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_BRAZOS ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_MMIOSD , 1 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_MMIOSD ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_BIG_RSP , 2 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_BIG_RSP ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_CHOP1G , 3 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_CHOP1G ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_DIS_NCNP , 4 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_DIS_NCNP ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_OVR_PM , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_OVR_PM ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TRY_ATR_RO , 6 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_TRY_ATR_RO ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_SPLURGE , 7 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_SPLURGE ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_LIM_PS , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_LIM_PS ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF2DMD , 9 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PREF2DMD ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREFEVOD , 10 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PREFEVOD ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_EAINJ , 11 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_EAINJ ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1 , 12 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED1 ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED1_LEN , 4 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED1_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_DEC_RATE , 16 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_TLBIE_DEC_RATE ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_DEC_RATE_LEN , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_TLBIE_DEC_RATE_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_INC_RATE , 24 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_TLBIE_INC_RATE ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_INC_RATE_LEN , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_TLBIE_INC_RATE_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_CNT_THRESH , 32 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_TLBIE_CNT_THRESH ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_TLBIE_CNT_THRESH_LEN , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_TLBIE_CNT_THRESH_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_UNUSED2 , 40 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED2 ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_TIMEOUT , 41 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PREF_TIMEOUT ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_TIMEOUT_LEN , 3 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PREF_TIMEOUT_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_DEPTH , 44 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PREF_DEPTH ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_DEPTH_LEN , 4 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PREF_DEPTH_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH0 , 48 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PREF_THRSH0 ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH0_LEN , 4 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PREF_THRSH0_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH1 , 52 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PREF_THRSH1 ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH1_LEN , 4 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PREF_THRSH1_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH2 , 56 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PREF_THRSH2 ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH2_LEN , 4 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PREF_THRSH2_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH3 , 60 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PREF_THRSH3 ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG_PREF_THRSH3_LEN , 4 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PREF_THRSH3_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_ENABLE , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_ENABLE ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_RESETMODE , 1 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_RESETMODE ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_FREEZEMODE , 2 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_FREEZEMODE ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_DISABLE_PMISC , 3 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_DISABLE_PMISC ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PMISC_MODE , 4 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_PMISC_MODE ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_CASCADE , 5 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_CASCADE ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_CASCADE_LEN , 3 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_CASCADE_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C0 , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_PRESCALE_C0 ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C0_LEN , 2 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_PRESCALE_C0_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C1 , 10 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_PRESCALE_C1 ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C1_LEN , 2 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_PRESCALE_C1_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C2 , 12 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_PRESCALE_C2 ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C2_LEN , 2 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_PRESCALE_C2_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C3 , 14 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_PRESCALE_C3 ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_PRESCALE_C3_LEN , 2 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_PRESCALE_C3_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT0 , 16 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_EVENT0 ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT0_LEN , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_EVENT0_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT1 , 24 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_EVENT1 ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT1_LEN , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_EVENT1_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT2 , 32 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_EVENT2 ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT2_LEN , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_EVENT2_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT3 , 40 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_EVENT3 ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_PERF_EVENT3_LEN , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_PERF_EVENT3_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_UNUSED , 48 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_UNUSED_LEN , 8 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_UNUSED_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_ATSD_TIMEOUT , 56 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATSD_TIMEOUT ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_ATSD_TIMEOUT_LEN , 4 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATSD_TIMEOUT_LEN ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_ATR_TIMEOUT , 60 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATR_TIMEOUT ); REG64_FLD( PU_NPU_SM2_XTS_CONFIG2_ATR_TIMEOUT_LEN , 4 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_ATR_TIMEOUT_LEN ); REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT0 , 0 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_CNT0 ); REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT0_LEN , 16 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_CNT0_LEN ); REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT1 , 16 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_CNT1 ); REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT1_LEN , 16 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_CNT1_LEN ); REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT2 , 32 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_CNT2 ); REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT2_LEN , 16 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_CNT2_LEN ); REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT3 , 48 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_CNT3 ); REG64_FLD( PU_NPU_SM2_XTS_PMU_CNT_CNT3_LEN , 16 , SH_UNT_PU_NPU_SM2, SH_ACS_SCOM , SH_FLD_CNT3_LEN ); #endif