/* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ /* $Source: chips/p9/procedures/hwp/perv/p9_sbe_tp_arrayinit.H $ */ /* */ /* IBM CONFIDENTIAL */ /* */ /* EKB Project */ /* */ /* COPYRIGHT 2015,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ /* The source code for this program is not published or otherwise */ /* divested of its trade secrets, irrespective of what has been */ /* deposited with the U.S. Copyright Office. */ /* */ /* IBM_PROLOG_END_TAG */ //------------------------------------------------------------------------------ /// @file p9_sbe_tp_arrayinit.H /// /// @brief SBE PRV Array Init Procedure //------------------------------------------------------------------------------ // *HWP HW Owner : Abhishek Agarwal // *HWP HW Backup Owner : Srinivas V Naga // *HWP FW Owner : sunil kumar // *HWP Team : Perv // *HWP Level : 2 // *HWP Consumed by : SBE //------------------------------------------------------------------------------ #ifndef _P9_SBE_TP_ARRAYINIT_H_ #define _P9_SBE_TP_ARRAYINIT_H_ #include typedef fapi2::ReturnCode (*p9_sbe_tp_arrayinit_FP_t)(const fapi2::Target&); /// @brief -- Array Init for PRV Cplt /// -- Scan0 of PRV Chiplet (except PIB/PCB) /// /// /// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target /// @return FAPI2_RC_SUCCESS if success, else error code. extern "C" { fapi2::ReturnCode p9_sbe_tp_arrayinit(const fapi2::Target& i_target_chip); } #endif