From edec9bde06d4a3e1c06fc15c9312318b9324d94c Mon Sep 17 00:00:00 2001 From: Raja Das Date: Wed, 7 Sep 2016 01:00:13 -0500 Subject: Stop Clocks for MPIPL (Core & Cache(EQ)) RTC: 156382 Change-Id: Ib3e8c29467aa7d3b6b85286e6f5ce154f0f28ad6 RTC: 156382 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29555 Tested-by: Jenkins Server Reviewed-by: Shakeeb A. Pasha B K Reviewed-by: Sachin Gupta Tested-by: FSP CI Jenkins --- src/build/Makefile | 5 + src/build/img_defs.mk | 8 + src/build/import_hwp_mk/istep2/Makefile | 2 +- src/build/import_hwp_mk/istep3/Makefile | 2 +- src/build/import_hwp_mk/istep4/Makefile | 2 +- src/build/import_hwp_mk/istep4/istep4files.mk | 1 + src/build/import_hwp_mk/istep5/Makefile | 2 +- src/build/import_hwp_mk/istepcommon/Makefile | 2 +- .../import_hwp_mk/istepcommon/istepcommonfiles.mk | 3 +- src/build/import_hwp_mk/istepmpipl/Makefile | 56 +++++ .../import_hwp_mk/istepmpipl/istepmpiplfiles.mk | 41 ++++ src/build/linkerscripts/linkseeprom.cmd | 2 +- .../chips/p9/procedures/hwp/cache/cachehcdfiles.mk | 2 + .../chips/p9/procedures/hwp/core/corehcdfiles.mk | 1 + .../p9/procedures/xml/error_info/hwpErrors.mk | 3 + src/sbefw/sbeSpMsg.H | 35 +++ src/sbefw/sbe_sp_intf.H | 24 +- src/sbefw/sbecmdiplcontrol.C | 66 ------ src/sbefw/sbecmdiplcontrol.H | 18 -- src/sbefw/sbecmdmpipl.C | 242 +++++++++++++++++++++ src/sbefw/sbecmdmpipl.H | 63 ++++++ src/sbefw/sbecmdparser.C | 6 + src/sbefw/sbecmdringaccess.C | 72 +----- src/sbefw/sbefapiutil.C | 96 ++++++++ src/sbefw/sbefapiutil.H | 62 ++++++ src/sbefw/sbefwfiles.mk | 2 + src/test/testcases/testStopClocks.py | 97 +++++++++ src/test/testcases/testStopClocks.xml | 28 +++ 28 files changed, 781 insertions(+), 162 deletions(-) create mode 100644 src/build/import_hwp_mk/istepmpipl/Makefile create mode 100644 src/build/import_hwp_mk/istepmpipl/istepmpiplfiles.mk create mode 100644 src/sbefw/sbecmdmpipl.C create mode 100644 src/sbefw/sbecmdmpipl.H create mode 100644 src/sbefw/sbefapiutil.C create mode 100644 src/sbefw/sbefapiutil.H create mode 100644 src/test/testcases/testStopClocks.py create mode 100755 src/test/testcases/testStopClocks.xml (limited to 'src') diff --git a/src/build/Makefile b/src/build/Makefile index 9bba17d6..1f7cdb6a 100644 --- a/src/build/Makefile +++ b/src/build/Makefile @@ -82,6 +82,11 @@ LIB_DIRS += -L$(OBJDIR-ISTEP5) ISTEP5LIB := $(OBJDIR-ISTEP5)/libistep5.a LLIBS += -listep5 +SUBDIRS += $(ISTEPMPIPL_INFRA_DIR) +LIB_DIRS += -L$(OBJDIR-ISTEPMPIPL) +ISTEPMPIPL := $(OBJDIR-ISTEPMPIPL)/libistepmpipl.a +LLIBS += -listepmpipl + SUBDIRS += $(ISTEPCOMMON_INFRA_DIR) LIB_DIRS += -L$(OBJDIR-ISTEPCOMMON) ISTEPCOMMON := $(OBJDIR-ISTEPCOMMON)/libistepcommon.a diff --git a/src/build/img_defs.mk b/src/build/img_defs.mk index ec099f4b..9c7c53aa 100644 --- a/src/build/img_defs.mk +++ b/src/build/img_defs.mk @@ -107,6 +107,10 @@ ifndef ISTEP5_INFRA_DIR export ISTEP5_INFRA_DIR = $(BUILD_DIR)/import_hwp_mk/istep5 endif +ifndef ISTEPMPIPL_INFRA_DIR +export ISTEPMPIPL_INFRA_DIR = $(BUILD_DIR)/import_hwp_mk/istepmpipl +endif + ifndef ISTEPCOMMON_INFRA_DIR export ISTEPCOMMON_INFRA_DIR = $(BUILD_DIR)/import_hwp_mk/istepcommon endif @@ -272,6 +276,10 @@ ifndef OBJDIR-ISTEP5 export OBJDIR-ISTEP5 = $(BASE_OBJDIR)/istep5 endif +ifndef OBJDIR-ISTEPMPIPL +export OBJDIR-ISTEPMPIPL = $(BASE_OBJDIR)/istepmpipl +endif + ifndef OBJDIR-ISTEPCOMMON export OBJDIR-ISTEPCOMMON = $(BASE_OBJDIR)/istepcommon endif diff --git a/src/build/import_hwp_mk/istep2/Makefile b/src/build/import_hwp_mk/istep2/Makefile index fd9317f0..06c3ab0a 100644 --- a/src/build/import_hwp_mk/istep2/Makefile +++ b/src/build/import_hwp_mk/istep2/Makefile @@ -6,6 +6,7 @@ # OpenPOWER sbe Project # # Contributors Listed Below - COPYRIGHT 2016 +# [+] International Business Machines Corp. # # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,7 +37,6 @@ GCC-CFLAGS += -mlongcall OBJSISTEP2 := $(addprefix $(OBJDIR-ISTEP2)/, $(ISTEP2_OBJECTS)) -#.PHONY: clean istep2 istep3 istep4 istep5 istepcommon all .PHONY: clean istep2 libistep2.a: istep2 diff --git a/src/build/import_hwp_mk/istep3/Makefile b/src/build/import_hwp_mk/istep3/Makefile index 8ea239c7..f692cf8c 100644 --- a/src/build/import_hwp_mk/istep3/Makefile +++ b/src/build/import_hwp_mk/istep3/Makefile @@ -6,6 +6,7 @@ # OpenPOWER sbe Project # # Contributors Listed Below - COPYRIGHT 2016 +# [+] International Business Machines Corp. # # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,7 +37,6 @@ GCC-CFLAGS += -mlongcall OBJSISTEP3 := $(addprefix $(OBJDIR-ISTEP3)/, $(ISTEP3_OBJECTS)) -#.PHONY: clean istep2 istep3 istep4 istep5 istepcommon all .PHONY: clean istep3 libistep3.a: istep3 diff --git a/src/build/import_hwp_mk/istep4/Makefile b/src/build/import_hwp_mk/istep4/Makefile index 4dc34fed..882d47f6 100644 --- a/src/build/import_hwp_mk/istep4/Makefile +++ b/src/build/import_hwp_mk/istep4/Makefile @@ -6,6 +6,7 @@ # OpenPOWER sbe Project # # Contributors Listed Below - COPYRIGHT 2016 +# [+] International Business Machines Corp. # # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,7 +37,6 @@ GCC-CFLAGS += -mlongcall OBJSISTEP4 := $(addprefix $(OBJDIR-ISTEP4)/, $(ISTEP4_OBJECTS)) -#.PHONY: clean istep2 istep3 istep4 istep5 istepcommon all .PHONY: clean istep4 libistep4.a: istep4 diff --git a/src/build/import_hwp_mk/istep4/istep4files.mk b/src/build/import_hwp_mk/istep4/istep4files.mk index de347d56..5fa151e0 100644 --- a/src/build/import_hwp_mk/istep4/istep4files.mk +++ b/src/build/import_hwp_mk/istep4/istep4files.mk @@ -6,6 +6,7 @@ # OpenPOWER sbe Project # # Contributors Listed Below - COPYRIGHT 2016 +# [+] International Business Machines Corp. # # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/src/build/import_hwp_mk/istep5/Makefile b/src/build/import_hwp_mk/istep5/Makefile index e4b8eb3f..ee1f2b51 100644 --- a/src/build/import_hwp_mk/istep5/Makefile +++ b/src/build/import_hwp_mk/istep5/Makefile @@ -6,6 +6,7 @@ # OpenPOWER sbe Project # # Contributors Listed Below - COPYRIGHT 2016 +# [+] International Business Machines Corp. # # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -34,7 +35,6 @@ export VPATH = $(PERV_SRCDIR):$(NEST_SRCDIR):$(CACHE_SRCDIR):$(CORE_SRCDIR):$(PM OBJSISTEP5 := $(addprefix $(OBJDIR-ISTEP5)/, $(ISTEP5_OBJECTS)) -#.PHONY: clean istep2 istep3 istep4 istep5 istepcommon all .PHONY: clean istep5 libistep5.a: istep5 diff --git a/src/build/import_hwp_mk/istepcommon/Makefile b/src/build/import_hwp_mk/istepcommon/Makefile index 645a3ce0..c4386526 100644 --- a/src/build/import_hwp_mk/istepcommon/Makefile +++ b/src/build/import_hwp_mk/istepcommon/Makefile @@ -6,6 +6,7 @@ # OpenPOWER sbe Project # # Contributors Listed Below - COPYRIGHT 2016 +# [+] International Business Machines Corp. # # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -34,7 +35,6 @@ export VPATH = $(PERV_SRCDIR):$(NEST_SRCDIR):$(CACHE_SRCDIR):$(CORE_SRCDIR):$(PM OBJSISTEPCOMMON := $(addprefix $(OBJDIR-ISTEPCOMMON)/, $(ISTEPCOMMON_OBJECTS)) -#.PHONY: clean istep2 istep3 istep4 istep5 istepcommon all .PHONY: clean istepcommon libistepcommon.a: istepcommon diff --git a/src/build/import_hwp_mk/istepcommon/istepcommonfiles.mk b/src/build/import_hwp_mk/istepcommon/istepcommonfiles.mk index 47505769..d93f768e 100644 --- a/src/build/import_hwp_mk/istepcommon/istepcommonfiles.mk +++ b/src/build/import_hwp_mk/istepcommon/istepcommonfiles.mk @@ -6,6 +6,7 @@ # OpenPOWER sbe Project # # Contributors Listed Below - COPYRIGHT 2016 +# [+] International Business Machines Corp. # # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,7 +24,7 @@ # IBM_PROLOG_END_TAG # @file istepCommonfiles.mk # -# @brief mk for including istepCommon object files +# @brief mk for including istepcommon object files # ########################################################################## # Object Files diff --git a/src/build/import_hwp_mk/istepmpipl/Makefile b/src/build/import_hwp_mk/istepmpipl/Makefile new file mode 100644 index 00000000..d9822f90 --- /dev/null +++ b/src/build/import_hwp_mk/istepmpipl/Makefile @@ -0,0 +1,56 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/build/import_hwp_mk/istepmpipl/Makefile $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# This Makefile compiles all of the hardware procedure code. See the +# "*.mk" file in this directory. + +#all generated files from this makefile will end up in obj/* +export SUB_OBJDIR = /istepmpipl + +include img_defs.mk +include istepmpiplfiles.mk + +export VPATH = $(PERV_SRCDIR):$(NEST_SRCDIR):$(CACHE_SRCDIR):$(CORE_SRCDIR):$(PM_SRCDIR):$(INITFILES_SRCDIR):$(LIB_SRCDIR) + +GCC-CFLAGS += -mlongcall + +OBJSISTEPMPIPL := $(addprefix $(OBJDIR-ISTEPMPIPL)/, $(ISTEPMPIPL_OBJECTS)) + +.PHONY: clean istepmpipl + +libistepmpipl.a: istepmpipl + $(AR) crs $(OBJDIR-ISTEPMPIPL)/libistepmpipl.a $(OBJDIR-ISTEPMPIPL)/*.o + +istepmpipl: $(OBJSISTEPMPIPL) + +$(OBJSISTEPMPIPL) $(OBJSISTEPMPIPL:.o=.d): | $(OBJDIR-ISTEPMPIPL) + +$(OBJDIR-ISTEPMPIPL): + mkdir -p $(OBJDIR-ISTEPMPIPL) + +clean: + rm -fr $(OBJDIR-ISTEPMPIPL) + +ifneq ($(MAKECMDGOALS),clean) +include $(OBJSISTEPMPIPL:.o=.d) +endif diff --git a/src/build/import_hwp_mk/istepmpipl/istepmpiplfiles.mk b/src/build/import_hwp_mk/istepmpipl/istepmpiplfiles.mk new file mode 100644 index 00000000..d2e99491 --- /dev/null +++ b/src/build/import_hwp_mk/istepmpipl/istepmpiplfiles.mk @@ -0,0 +1,41 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/build/import_hwp_mk/istepmpipl/istepmpiplfiles.mk $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# @file istepmpipl.mk +# +# @brief mk for including istepmpipl object files +# +########################################################################## +# Object Files +########################################################################## + +ISTEPMPIPL-CPP-SOURCES = p9_hcd_core_stopclocks.C +ISTEPMPIPL-CPP-SOURCES +=p9_hcd_cache_stopclocks.C +ISTEPMPIPL-CPP-SOURCES +=p9_hcd_l2_stopclocks.C +ISTEPMPIPL-C-SOURCES = +ISTEPMPIPL-S-SOURCES = + +ISTEPMPIPL_OBJECTS += $(ISTEPMPIPL-CPP-SOURCES:.C=.o) +ISTEPMPIPL_OBJECTS += $(ISTEPMPIPL-C-SOURCES:.c=.o) +ISTEPMPIPL_OBJECTS += $(ISTEPMPIPL-S-SOURCES:.S=.o) diff --git a/src/build/linkerscripts/linkseeprom.cmd b/src/build/linkerscripts/linkseeprom.cmd index ad478996..cb006676 100644 --- a/src/build/linkerscripts/linkseeprom.cmd +++ b/src/build/linkerscripts/linkseeprom.cmd @@ -98,7 +98,7 @@ SECTIONS //////////////////////////////// .text ALIGN(8): { _text_origin = .; _text_offset = . - _seeprom_origin; - *\libistep2.a:(.text* ) *\libistep3.a:(.text* ) *\libistep4.a:(.text* ) } > seeprom + *\libistep2.a:(.text* ) *\libistep3.a:(.text* ) *\libistep4.a:(.text* ) *\libistepmpipl.a:(.text* ) } > seeprom _text_size = . - _text_origin; //////////////////////////////// diff --git a/src/import/chips/p9/procedures/hwp/cache/cachehcdfiles.mk b/src/import/chips/p9/procedures/hwp/cache/cachehcdfiles.mk index 135972bc..3523c09c 100644 --- a/src/import/chips/p9/procedures/hwp/cache/cachehcdfiles.mk +++ b/src/import/chips/p9/procedures/hwp/cache/cachehcdfiles.mk @@ -46,6 +46,8 @@ CACHE-CPP-SOURCES += p9_hcd_cache_scominit.C CACHE-CPP-SOURCES += p9_hcd_cache_startclocks.C CACHE-CPP-SOURCES += p9_hcd_cache_chiplet_l3_dcc_setup.C CACHE-CPP-SOURCES += p9_hcd_cache_dpll_initf.C +CACHE-CPP-SOURCES += p9_hcd_cache_stopclocks.C +CACHE-CPP-SOURCES += p9_hcd_l2_stopclocks.C CACHE-C-SOURCES += CACHE-S-SOURCES += diff --git a/src/import/chips/p9/procedures/hwp/core/corehcdfiles.mk b/src/import/chips/p9/procedures/hwp/core/corehcdfiles.mk index feb937d5..3c3cbcc8 100644 --- a/src/import/chips/p9/procedures/hwp/core/corehcdfiles.mk +++ b/src/import/chips/p9/procedures/hwp/core/corehcdfiles.mk @@ -49,6 +49,7 @@ CORE-CPP-SOURCES += p9_hcd_core_startclocks.C # in PIBMEM for quiesce case, So compiling in nest makefile #CORE-CPP-SOURCES += p9_thread_control.C #CORE-CPP-SOURCES += p9_sbe_instruct_start.C +CORE-CPP-SOURCES += p9_hcd_core_stopclocks.C CORE-C-SOURCES += CORE-S-SOURCES += diff --git a/src/import/chips/p9/procedures/xml/error_info/hwpErrors.mk b/src/import/chips/p9/procedures/xml/error_info/hwpErrors.mk index 913b0939..05ea9771 100644 --- a/src/import/chips/p9/procedures/xml/error_info/hwpErrors.mk +++ b/src/import/chips/p9/procedures/xml/error_info/hwpErrors.mk @@ -65,3 +65,6 @@ ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_npll_initf_errors.xml ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_chiplet_pll_initf_errors.xml ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_scominit_errors.xml ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_sbe_plat_errors.xml +ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_hcd_core_stopclocks_errors.xml +ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_hcd_cache_stopclocks_errors.xml +ERROR_XML_FILES += $(PERV_CURR_DIR)/p9_hcd_l2_stopclocks_errors.xml diff --git a/src/sbefw/sbeSpMsg.H b/src/sbefw/sbeSpMsg.H index 38251632..b0bb0a09 100644 --- a/src/sbefw/sbeSpMsg.H +++ b/src/sbefw/sbeSpMsg.H @@ -530,6 +530,41 @@ typedef struct extern sbeCmdRespHdr_t g_sbeCmdRespHdr; + +/** + * @brief structure for Stop Clocks Chipop (0xA901) contents. + * + */ +typedef struct +{ + uint32_t targetType:16; + uint32_t reserved:8; + uint32_t chipletId:8; + + /** + * @brief Validate Target Type for MPIPL Stop Clocks ChipOp + * + * @return bool, true if validation is success, else false + */ + bool validateInputTargetType() + { + bool l_validatePassFlag = false; + switch(targetType) + { + case TARGET_CORE: + case TARGET_EQ: + l_validatePassFlag = true; + break; + + default: + SBE_ERROR(SBE_FUNC "Invalid TargetType[%d] ChipletId[%d] " + "by User",targetType,chipletId); + break; + } + return l_validatePassFlag; + } +}sbeStopClocksReqMsgHdr_t; + /** * @brief structure for Control Instruction Chipop (0xA701) contents. * diff --git a/src/sbefw/sbe_sp_intf.H b/src/sbefw/sbe_sp_intf.H index e58cb7bf..6c6bb8b5 100644 --- a/src/sbefw/sbe_sp_intf.H +++ b/src/sbefw/sbe_sp_intf.H @@ -166,6 +166,7 @@ enum sbeMpIplCommands { SBE_CMD_MPIPL_ENTER = 0x01, /* Enter MPIPL */ SBE_CMD_MPIPL_CONTINUE = 0x02, /* Continue MPIPL */ + SBE_CMD_MPIPL_STOPCLOCKS = 0x03, /* Stop Clocks */ }; /** @@ -274,6 +275,7 @@ enum GET_SBE_FREQUENCIES_SUPPPORTED = 0xA8000004, GET_SBE_STATE_SUPPPORTED = 0xA8000008, SBE_QUIESCE = 0xA8000010, + STOP_CLOCKS_MPIPL_SUPPORTED = 0xA9000004, }; /** @@ -361,8 +363,14 @@ enum sbeRegAccesRegType SBE_REG_ACCESS_FPR = 0x02, }; + +// Base Target Type offset maintined by SBE to be used across different chip-ops +// Need to avoid any duplicate target type since it is used to convert into FAPI +// target via file sbefapiutil.C + /* - * @brief enums for target types used in ring access chip op + * @brief enums for target types used in ring access chip op and + * in stop clocks chip ops */ typedef enum { @@ -370,7 +378,19 @@ typedef enum TARGET_EX = 0x0001, TARGET_PERV = 0x0002, TARGET_MCS = 0x0003, -} sbeRingTargetTypes_t; + TARGET_EQ = 0x0004, + TARGET_CORE = 0x0005, +} sbeTargetTypes_t; + +/** + * @brief Cache Chiplet Id Enum + */ +enum sbeCacheChipletId +{ + EQ_ID_0 = 0x10, + EQ_ID_MAX = 0x06, + EQ_ALL_CHIPLETS = 0xFF, +}; /* * @brief enums for access modes used in ring access chip op diff --git a/src/sbefw/sbecmdiplcontrol.C b/src/sbefw/sbecmdiplcontrol.C index 789d5374..43436512 100644 --- a/src/sbefw/sbecmdiplcontrol.C +++ b/src/sbefw/sbecmdiplcontrol.C @@ -754,70 +754,4 @@ void sbeDoContinuousIpl() #undef SBE_FUNC } -// TODO - RTC 133367 -//---------------------------------------------------------------------------- -uint32_t sbeEnterMpipl(uint8_t *i_pArg) -{ - #define SBE_FUNC " sbeEnterMpipl " - uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL; - uint32_t len = 0; - sbeRespGenHdr_t l_respHdr; - l_respHdr.init(); - - do - { - // Dequeue the EOT entry as no more data is expected. - l_rc = sbeUpFifoDeq_mult (len, NULL); - if ( l_rc != SBE_SEC_OPERATION_SUCCESSFUL ) - { - // Let command processor routine to handle the RC - break; - } - - // TODO via RTC:123696 MPIPL Related procedure/steps - // Can send FFDC if MPIPL procedure fails - l_rc = sbeDsSendRespHdr( l_respHdr ); - - // set state to MPIPL Wait - (void)SbeRegAccess::theSbeRegAccess(). - stateTransition(SBE_ENTER_MPIPL_EVENT); - - }while(0); - return l_rc; - #undef SBE_FUNC -} - -// TODO - RTC 133367 -//---------------------------------------------------------------------------- -uint32_t sbeContinueMpipl(uint8_t *i_pArg) -{ - #define SBE_FUNC " sbeContinueMpipl " - uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL; - uint32_t len = 0; - sbeRespGenHdr_t l_respHdr; - l_respHdr.init(); - - do - { - // Dequeue the EOT entry as no more data is expected. - l_rc = sbeUpFifoDeq_mult (len, NULL); - if ( l_rc != SBE_SEC_OPERATION_SUCCESSFUL ) - { - // Let command processor routine to handle the RC - break; - } - - l_rc = sbeDsSendRespHdr( l_respHdr); - - //TODO RTC-134278 Continue MPIPL Related procedure/steps - - // TODO - Once continue steps are over, it will trigger the - // istep5.2 and transition to runtime will happen - - }while(0); - - return l_rc; - #undef SBE_FUNC -} - diff --git a/src/sbefw/sbecmdiplcontrol.H b/src/sbefw/sbecmdiplcontrol.H index 3a084065..0aaa0684 100644 --- a/src/sbefw/sbecmdiplcontrol.H +++ b/src/sbefw/sbecmdiplcontrol.H @@ -58,24 +58,6 @@ uint32_t sbeHandleIstep(uint8_t *i_pArg); */ void sbeDoContinuousIpl(); -/** - * @brief Handles Sbe Enter Mpipl chip-op (0xA901) - * - * @param[in] i_pArg Buffer to be passed to the function (not used as of now) - * - * @return Rc from the FIFO access utility - */ -uint32_t sbeEnterMpipl(uint8_t *i_pArg); - -/** - * @brief Handles Sbe Continue Mpipl chip-op (0xA902) - * - * @param[in] i_pArg Buffer to be passed to the function (not used as of now) - * - * @return Rc from the FIFO access utility - */ -uint32_t sbeContinueMpipl(uint8_t *i_pArg); - /** * @brief Handles Sbe Get FFDC chip-op (0xA801) * diff --git a/src/sbefw/sbecmdmpipl.C b/src/sbefw/sbecmdmpipl.C new file mode 100644 index 00000000..b898852a --- /dev/null +++ b/src/sbefw/sbecmdmpipl.C @@ -0,0 +1,242 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/sbefw/sbecmdmpipl.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* + * @file: ppe/src/sbefw/sbecmdmpipl.C + * + * @brief This file contains the SBE MPIPL chipOps + * + */ + +#include "sbefifo.H" +#include "sbeSpMsg.H" +#include "sbe_sp_intf.H" +#include "sbetrace.H" +#include "sbeFifoMsgUtils.H" +#include "sbecmdmpipl.H" +#include "sberegaccess.H" +#include "sbefapiutil.H" + +#include "p9_hcd_core_stopclocks.H" +#include "p9_hcd_cache_stopclocks.H" +#include "fapi2.H" + +using namespace fapi2; + + +#ifdef SEEPROM_IMAGE +// Using function pointer to force long call. +p9_hcd_cache_stopclocks_FP_t p9_hcd_cache_stopclocks_hwp = &p9_hcd_cache_stopclocks; +p9_hcd_core_stopclocks_FP_t p9_hcd_core_stopclocks_hwp = &p9_hcd_core_stopclocks; +#endif + +// TODO - RTC 133367 +/////////////////////////////////////////////////////////////////////// +// @brief sbeEnterMpipl Sbe enter MPIPL function +// +// @return RC from the underlying FIFO utility +/////////////////////////////////////////////////////////////////////// +uint32_t sbeEnterMpipl(uint8_t *i_pArg) +{ + #define SBE_FUNC " sbeEnterMpipl " + SBE_ENTER(SBE_FUNC); + uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL; + uint32_t len = 0; + sbeRespGenHdr_t l_respHdr; + l_respHdr.init(); + + do + { + // Dequeue the EOT entry as no more data is expected. + l_rc = sbeUpFifoDeq_mult (len, NULL); + CHECK_SBE_RC_AND_BREAK_IF_NOT_SUCCESS(l_rc); + + // TODO via RTC:123696 MPIPL Related procedure/steps + // Can send FFDC if MPIPL procedure fails + l_rc = sbeDsSendRespHdr( l_respHdr ); + + // set state to MPIPL Wait + (void)SbeRegAccess::theSbeRegAccess(). + stateTransition(SBE_ENTER_MPIPL_EVENT); + + }while(0); + SBE_EXIT(SBE_FUNC); + return l_rc; + #undef SBE_FUNC +} + +// TODO - RTC 133367 +/////////////////////////////////////////////////////////////////////// +// @brief sbeContinueMpipl Sbe Continue MPIPL function +// +// @return RC from the underlying FIFO utility +/////////////////////////////////////////////////////////////////////// +uint32_t sbeContinueMpipl(uint8_t *i_pArg) +{ + #define SBE_FUNC " sbeContinueMpipl " + SBE_ENTER(SBE_FUNC); + uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL; + uint32_t len = 0; + sbeRespGenHdr_t l_respHdr; + l_respHdr.init(); + + do + { + // Dequeue the EOT entry as no more data is expected. + l_rc = sbeUpFifoDeq_mult (len, NULL); + CHECK_SBE_RC_AND_BREAK_IF_NOT_SUCCESS(l_rc); + + l_rc = sbeDsSendRespHdr( l_respHdr); + + //TODO RTC-134278 Continue MPIPL Related procedure/steps + + // TODO - Once continue steps are over, it will trigger the + // istep5.2 and transition to runtime will happen + + }while(0); + SBE_EXIT(SBE_FUNC); + return l_rc; + #undef SBE_FUNC +} + +/////////////////////////////////////////////////////////////////////// +// @brief sbeStopClocks Sbe Stop Clocks function +// +// @return RC from the underlying FIFO utility +// RTC-161679 : Stop Clocks Chip-op to handle Proc Chip Target +/////////////////////////////////////////////////////////////////////// +uint32_t sbeStopClocks(uint8_t *i_pArg) +{ + #define SBE_FUNC " sbeStopClocks" + SBE_ENTER(SBE_FUNC); + uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL; + uint32_t l_fapiRc = FAPI2_RC_SUCCESS; + uint32_t l_len = 0; + sbeResponseFfdc_t l_ffdc; + sbeRespGenHdr_t l_respHdr; + l_respHdr.init(); + sbeStopClocksReqMsgHdr_t l_reqMsg = {0}; + + do + { + // Get the TargetType and ChipletId from the command message + l_len = sizeof(sbeStopClocksReqMsgHdr_t)/sizeof(uint32_t); + l_rc = sbeUpFifoDeq_mult (l_len, (uint32_t *)&l_reqMsg); // EOT fetch + // If FIFO access failure + CHECK_SBE_RC_AND_BREAK_IF_NOT_SUCCESS(l_rc); + + SBE_INFO(SBE_FUNC "TargetType 0x%04X ChipletId 0x%02X", + l_reqMsg.targetType, l_reqMsg.chipletId); + + if(false == l_reqMsg.validateInputTargetType()) + { + l_respHdr.setStatus( SBE_PRI_INVALID_DATA, + SBE_SEC_INVALID_TARGET_TYPE_PASSED ); + break; + } + + uint64_t l_clk_regions = p9hcd::CLK_REGION_ALL_BUT_PLL_REFR; + uint8_t l_ex_select = p9hcd::BOTH_EX; + + if( (l_reqMsg.chipletId == SMT4_ALL_CORES) || + (l_reqMsg.chipletId == EQ_ALL_CHIPLETS) ) + { + Target l_procTgt = plat_getChipTarget(); + if(l_reqMsg.targetType == TARGET_CORE) + { + for (auto l_coreTgt : l_procTgt.getChildren()) + { + SBE_DEBUG(SBE_FUNC " Calling p9_hcd_core_stopclocks"); + SBE_EXEC_HWP(l_fapiRc, p9_hcd_core_stopclocks_hwp, l_coreTgt) + if(l_fapiRc != FAPI2_RC_SUCCESS) + { + // break from internal for loop + break; + } + } + } + else // Cache + { + for (auto l_eqTgt : l_procTgt.getChildren()) + { + SBE_DEBUG(SBE_FUNC " Calling p9_hcd_cache_stopclocks"); + SBE_EXEC_HWP(l_fapiRc, p9_hcd_cache_stopclocks_hwp, + l_eqTgt, + (p9hcd::P9_HCD_CLK_CTRL_CONSTANTS)l_clk_regions, + (p9hcd::P9_HCD_EX_CTRL_CONSTANTS)l_ex_select) + if(l_fapiRc != FAPI2_RC_SUCCESS) + { + // break from internal for loop + break; + } + } + } + } + else // for a single Core/Cache chiplet + { + // Construct the Target + fapi2::plat_target_handle_t l_tgtHndl = {0}; + // No Need to check the return here, it's already validated + sbeGetFapiTargetHandle( l_reqMsg.targetType, + l_reqMsg.chipletId, + l_tgtHndl ); + + if(l_reqMsg.targetType == TARGET_CORE) + { + SBE_DEBUG(SBE_FUNC " Calling p9_hcd_core_stopclocks"); + l_fapiRc = p9_hcd_core_stopclocks(l_tgtHndl); + } + else //Cache + { + SBE_DEBUG(SBE_FUNC " Calling p9_hcd_cache_stopclocks"); + l_fapiRc = p9_hcd_cache_stopclocks(l_tgtHndl, + (p9hcd::P9_HCD_CLK_CTRL_CONSTANTS)l_clk_regions, + (p9hcd::P9_HCD_EX_CTRL_CONSTANTS)l_ex_select); + } + } + + if( l_fapiRc != FAPI2_RC_SUCCESS ) + { + SBE_ERROR(SBE_FUNC" Stopclocks failed for TargetType [0x%04X] " + "ChipletId [0x%02X]", l_reqMsg.targetType, l_reqMsg.chipletId); + l_respHdr.setStatus( SBE_PRI_GENERIC_EXECUTION_FAILURE, + SBE_SEC_GENERIC_FAILURE_IN_EXECUTION); + l_ffdc.setRc(l_fapiRc); + break; + } + }while(0); + + // Create the Response to caller + // If there was a FIFO error, will skip sending the response, + // instead give the control back to the command processor thread + if(SBE_SEC_OPERATION_SUCCESSFUL == l_rc) + { + l_rc = sbeDsSendRespHdr( l_respHdr, &l_ffdc); + } + + SBE_EXIT(SBE_FUNC); + return l_rc; + #undef SBE_FUNC +} + + diff --git a/src/sbefw/sbecmdmpipl.H b/src/sbefw/sbecmdmpipl.H new file mode 100644 index 00000000..72d62927 --- /dev/null +++ b/src/sbefw/sbecmdmpipl.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/sbefw/sbecmdmpipl.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* + * @file: ppe/src/sbefw/sbecmdmpipl.H + * + * @brief This file contains the Interfaces for MPIPL chip-ops + * + */ + +#ifndef __SBEFW_SBECMDMPIPL_H +#define __SBEFW_SBECMDMPIPL_H + +#include + +/** + * @brief Handles Sbe Enter Mpipl chip-op (0xA901) + * + * @param[in] i_pArg Buffer to be passed to the function (not used as of now) + * + * @return Rc from the FIFO access utility + */ +uint32_t sbeEnterMpipl(uint8_t *i_pArg); + +/** + * @brief Handles Sbe Continue Mpipl chip-op (0xA902) + * + * @param[in] i_pArg Buffer to be passed to the function (not used as of now) + * + * @return Rc from the FIFO access utility + */ +uint32_t sbeContinueMpipl(uint8_t *i_pArg); + +/** + * @brief Handles Sbe Stop Clocks chip-op (0xA903) + * + * @param[in] i_pArg Buffer to be passed to the function (not used as of now) + * + * @return Rc from the FIFO access utility + */ +uint32_t sbeStopClocks(uint8_t *i_pArg); + +#endif /* __SBEFW_SBECMDMPIPL_H */ diff --git a/src/sbefw/sbecmdparser.C b/src/sbefw/sbecmdparser.C index 1b2235d0..9722fe4a 100644 --- a/src/sbefw/sbecmdparser.C +++ b/src/sbefw/sbecmdparser.C @@ -46,6 +46,7 @@ #include "sbe_host_intf.H" #include "sbestates.H" #include "sberegaccess.H" +#include "sbecmdmpipl.H" // Declaration static const uint16_t HARDWARE_FENCED_STATE = @@ -193,6 +194,11 @@ static sbeCmdStruct_t g_sbeMpiplCmdArray[] = SBE_FENCE_AT_RUNTIME|SBE_FENCE_AT_DUMPING, // Only allowed State is MPIPL }, + + {sbeStopClocks, + SBE_CMD_MPIPL_STOPCLOCKS, + HARDWARE_FENCED_STATE|SBE_FENCE_AT_DUMPING, + }, }; ////////////////////////////////////////////////////////////// diff --git a/src/sbefw/sbecmdringaccess.C b/src/sbefw/sbecmdringaccess.C index 7c2ccc1d..73466900 100644 --- a/src/sbefw/sbecmdringaccess.C +++ b/src/sbefw/sbecmdringaccess.C @@ -37,6 +37,7 @@ #include "sbeHostUtils.H" #include "sbeFifoMsgUtils.H" #include "sbeutil.H" +#include "sbefapiutil.H" #include "fapi2.H" #include "plat_hw_access.H" @@ -46,77 +47,10 @@ static const uint32_t SIZE_OF_LENGTH_INWORDS = 1; static const uint32_t NUM_WORDS_PER_GRANULE = 2; static const uint32_t GETRING_GRANULE_SIZE_IN_BITS = 64; -/*@brief - Map sbe ring access modes to fapi ring access modes - * - * @param[in] - i_ringMode - sbe ring access mode - * - * @return - l_fapiRingMode - fapi ring mode - */ -uint16_t sbeToFapiRingMode(uint16_t i_ringMode) -{ - uint16_t l_fapiRingMode = RING_MODE_HEADER_CHECK; - - if(i_ringMode & SBE_RING_MODE_SET_PULSE_NO_OPCG_COND) - { - l_fapiRingMode |= RING_MODE_SET_PULSE_NO_OPCG_COND; - } - if(i_ringMode & SBE_RING_MODE_NO_HEADER_CHECK) - { - l_fapiRingMode |= RING_MODE_NO_HEADER_CHECK; - } - if(i_ringMode & SBE_RING_MODE_SET_PULSE_NSL) - { - l_fapiRingMode |= RING_MODE_SET_PULSE_NSL; - } - if(i_ringMode & SBE_RING_MODE_SET_PULSE_SL) - { - l_fapiRingMode |= RING_MODE_SET_PULSE_SL; - } - if(i_ringMode & SBE_RING_MODE_SET_PULSE_ALL) - { - l_fapiRingMode |= RING_MODE_SET_PULSE_ALL; - } - return l_fapiRingMode; -} - -/*@brief - create fapi target handle for the target type - * - * @param[in] - i_taretType - sbe ring target type - * @param[in] - i_chipletId - chiplet id - * @param[out] - o_tgtHndl - fapi target handle - * - * @return - true - on success - * false - on failure - */ -bool sbeGetFapiTargetHandle(uint16_t i_targetType, - uint16_t i_chipletId, - fapi2::plat_target_handle_t &o_tgtHndl) -{ - bool l_rc = true; - o_tgtHndl = NULL; - switch(i_targetType) - { - case TARGET_EX: - o_tgtHndl = plat_getTargetHandleByChipletNumber - (i_chipletId); - break; - case TARGET_PERV: - o_tgtHndl = plat_getTargetHandleByChipletNumber - (i_chipletId); - break; - case TARGET_PROC_CHIP: - o_tgtHndl = plat_getChipTarget().get(); - break; - default: - l_rc = false; - break; - } - return l_rc; -} uint32_t sbePutRingFromImagePSU (uint8_t *i_pArg) { -#define SBE_FUNC " sbePutRingFromImagePSU " + #define SBE_FUNC " sbePutRingFromImagePSU " SBE_ENTER(SBE_FUNC); uint32_t l_rc = SBE_SEC_OPERATION_SUCCESSFUL; uint32_t l_fapiRc = FAPI2_RC_SUCCESS; @@ -172,7 +106,7 @@ uint32_t sbePutRingFromImagePSU (uint8_t *i_pArg) SBE_EXIT(SBE_FUNC); return l_rc; -#undef SBE_FUNC + #undef SBE_FUNC } ////////////////////////////////////////////////////// diff --git a/src/sbefw/sbefapiutil.C b/src/sbefw/sbefapiutil.C new file mode 100644 index 00000000..79fb46bb --- /dev/null +++ b/src/sbefw/sbefapiutil.C @@ -0,0 +1,96 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/sbefw/sbefapiutil.C $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* + * @file: ppe/src/sbefw/sbefapiutil.C + * + * @brief This file contains the SBE FAPI Utility + * + */ + +#include "sbefapiutil.H" + +using namespace fapi2; + +bool sbeGetFapiTargetHandle(uint16_t i_targetType, + uint16_t i_chipletId, + fapi2::plat_target_handle_t &o_tgtHndl) +{ + bool l_rc = true; + o_tgtHndl = NULL; + switch(i_targetType) + { + case TARGET_EX: + o_tgtHndl = plat_getTargetHandleByChipletNumber + (i_chipletId); + break; + case TARGET_PERV: + o_tgtHndl = plat_getTargetHandleByChipletNumber + (i_chipletId); + break; + case TARGET_EQ: + o_tgtHndl = plat_getTargetHandleByChipletNumber + (i_chipletId); + break; + case TARGET_CORE: + o_tgtHndl = plat_getTargetHandleByChipletNumber + (i_chipletId); + break; + case TARGET_PROC_CHIP: + o_tgtHndl = plat_getChipTarget().get(); + break; + default: + l_rc = false; + break; + } + return l_rc; +} + +uint16_t sbeToFapiRingMode(uint16_t i_ringMode) +{ + uint16_t l_fapiRingMode = RING_MODE_HEADER_CHECK; + + if(i_ringMode & SBE_RING_MODE_SET_PULSE_NO_OPCG_COND) + { + l_fapiRingMode |= RING_MODE_SET_PULSE_NO_OPCG_COND; + } + if(i_ringMode & SBE_RING_MODE_NO_HEADER_CHECK) + { + l_fapiRingMode |= RING_MODE_NO_HEADER_CHECK; + } + if(i_ringMode & SBE_RING_MODE_SET_PULSE_NSL) + { + l_fapiRingMode |= RING_MODE_SET_PULSE_NSL; + } + if(i_ringMode & SBE_RING_MODE_SET_PULSE_SL) + { + l_fapiRingMode |= RING_MODE_SET_PULSE_SL; + } + if(i_ringMode & SBE_RING_MODE_SET_PULSE_ALL) + { + l_fapiRingMode |= RING_MODE_SET_PULSE_ALL; + } + return l_fapiRingMode; +} + + diff --git a/src/sbefw/sbefapiutil.H b/src/sbefw/sbefapiutil.H new file mode 100644 index 00000000..4728807e --- /dev/null +++ b/src/sbefw/sbefapiutil.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/sbefw/sbefapiutil.H $ */ +/* */ +/* OpenPOWER sbe Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/* + * @file: ppe/src/sbefw/sbefapiutil.H + * + * @brief This file contains the SBE FAPI Utility + * + */ + +#ifndef __SBEFW_SBEFAPIUTIL_H +#define __SBEFW_SBEFAPIUTIL_H + +#include +#include "sbe_sp_intf.H" +#include "sbeutil.H" +#include "fapi2.H" +#include "plat_hw_access.H" + +/*@brief - create fapi target handle for the target type + * + * @param[in] - i_taretType - sbe target type + * @param[in] - i_chipletId - chiplet id + * @param[out] - o_tgtHndl - fapi target handle + * + * @return - true - on success + * false - on failure + */ +bool sbeGetFapiTargetHandle(uint16_t i_targetType, + uint16_t i_chipletId, + fapi2::plat_target_handle_t &o_tgtHndl); + +/*@brief - Map sbe ring access modes to fapi ring access modes + * + * @param[in] - i_ringMode - sbe ring access mode + * + * @return - l_fapiRingMode - fapi ring mode + */ +uint16_t sbeToFapiRingMode(uint16_t i_ringMode); + + +#endif /* __SBEFW_SBEFAPIUTIL_H */ diff --git a/src/sbefw/sbefwfiles.mk b/src/sbefw/sbefwfiles.mk index 80846adf..b82f09ab 100644 --- a/src/sbefw/sbefwfiles.mk +++ b/src/sbefw/sbefwfiles.mk @@ -42,6 +42,8 @@ SBEFW-CPP-SOURCES += sbecmdregaccess.C SBEFW-CPP-SOURCES += sbeFFDC.C SBEFW-CPP-SOURCES += sbecmdringaccess.C SBEFW-CPP-SOURCES += sbescom.C +SBEFW-CPP-SOURCES += sbecmdmpipl.C +SBEFW-CPP-SOURCES += sbefapiutil.C SBEFW-C-SOURCES = SBEFW-S-SOURCES = diff --git a/src/test/testcases/testStopClocks.py b/src/test/testcases/testStopClocks.py new file mode 100644 index 00000000..d81fdd37 --- /dev/null +++ b/src/test/testcases/testStopClocks.py @@ -0,0 +1,97 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/testcases/testStopClocks.py $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +import sys +sys.path.append("targets/p9_nimbus/sbeTest" ) +import testUtil +err = False +#from testWrite import * + +STOPCLOCK_CORE_TESTDATA = [0,0,0,0x5, + 0,0,0xA9,0x03, + 0x0,0x5,0x0,0x20] # target type/chiplet id + +STOPCLOCK_ALL_CORE_TESTDATA = [0,0,0,0x5, + 0,0,0xA9,0x03, + 0x0,0x5,0x0,0xFF] # target type/chiplet id + +STOPCLOCK_CORE_EXPDATA = [0xc0,0xde,0xa9,0x03, + 0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x03]; + +STOPCLOCK_EQ_TESTDATA = [0,0,0,0x5, + 0,0,0xA9,0x03, + 0x0,0x4,0x0,0x10] # target type/chiplet id + +STOPCLOCK_ALL_EQ_TESTDATA = [0,0,0,0x5, + 0,0,0xA9,0x03, + 0x0,0x4,0x0,0xFF] # target type/chiplet id + +STOPCLOCK_EQ_EXPDATA = [0xc0,0xde,0xa9,0x03, + 0x0,0x0,0x0,0x0, + 0x0,0x0,0x0,0x03]; + + +# MAIN Test Run Starts Here... +#------------------------------------------------- +def main( ): + testUtil.runCycles( 10000000 ) + + testUtil.writeUsFifo( STOPCLOCK_CORE_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( STOPCLOCK_CORE_EXPDATA ) + testUtil.runCycles( 10000000 ) + testUtil.readEot( ) + + testUtil.writeUsFifo( STOPCLOCK_ALL_CORE_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( STOPCLOCK_CORE_EXPDATA ) + testUtil.runCycles( 10000000 ) + testUtil.readEot( ) + + testUtil.runCycles( 10000000 ) + testUtil.writeUsFifo( STOPCLOCK_EQ_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( STOPCLOCK_EQ_EXPDATA ) + testUtil.runCycles( 10000000 ) + testUtil.readEot( ) + + testUtil.runCycles( 10000000 ) + testUtil.writeUsFifo( STOPCLOCK_ALL_EQ_TESTDATA ) + testUtil.writeEot( ) + testUtil.readDsFifo( STOPCLOCK_EQ_EXPDATA ) + testUtil.runCycles( 10000000 ) + testUtil.readEot( ) + +#------------------------------------------------- +# Calling all test code +#------------------------------------------------- +main() + +if err: + print ("\nTest Suite completed with error(s)") + #sys.exit(1) +else: + print ("\nTest Suite completed with no errors") + #sys.exit(0); + diff --git a/src/test/testcases/testStopClocks.xml b/src/test/testcases/testStopClocks.xml new file mode 100755 index 00000000..53725fff --- /dev/null +++ b/src/test/testcases/testStopClocks.xml @@ -0,0 +1,28 @@ + + + + + + + + + + + + + + + + + + + + + + + + + run-python-file targets/p9_nimbus/sbeTest/testStopClocks.py + yes + + -- cgit v1.2.1