From d41dd215698f5a8fc1a9f731bb9e08b15d1af724 Mon Sep 17 00:00:00 2001 From: Joe McGill Date: Tue, 9 May 2017 20:29:54 -0500 Subject: L3 updates -- p9_build_smp, p9_fbc_utils p9_build_smp: constrain FFDC collection at 16 chips (current max size for P9 based systems) scrub node references, replace with group clarify X link requirements based on pump mode review and complete callouts p9_fbc_utils: add feature attribute to support pb_init sampling on NDD2+ replace locally defined bit constants with SCOM header file constants Change-Id: Ibf9388eee0accd976e00718ad4f9bca485c5ec27 Original-Change-Id: Ib1f71488ffd07580a647709d9227112f7d73384f CQ: HW328175 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40308 Tested-by: Jenkins Server Reviewed-by: Thi N. Tran Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: DHRUVARAJ SUBHASH CHANDRAN Reviewed-by: Matt K. Light Reviewed-by: Jennifer A. Stofer --- .../xml/attribute_info/chip_ec_attributes.xml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'src') diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 05e9746e..b379f649 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -358,6 +358,24 @@ + + ATTR_CHIP_EC_FEATURE_HW328175 + TARGET_TYPE_PROC_CHIP + + HW328175 : PB mode register does not reflect steady-state value + of PB init + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + ATTR_CHIP_EC_FEATURE_HW367321 TARGET_TYPE_PROC_CHIP -- cgit v1.2.1