From 8a8152b3899d439e530cb3e514072caa92a232c5 Mon Sep 17 00:00:00 2001 From: Stephen Glancy Date: Fri, 12 Jan 2018 09:42:10 -0600 Subject: Updates custom RD CTR pattern Change-Id: I7a23b502626df75f371957345f18d788a534ba87 CQ:SW413773 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51872 Tested-by: FSP CI Jenkins Dev-Ready: STEPHEN GLANCY Reviewed-by: Louis Stermole Reviewed-by: ANDRE A. MARIN Reviewed-by: LUCAS W. MULKEY Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: Hostboot CI Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/69811 Reviewed-by: Sachin Gupta Tested-by: Sachin Gupta --- .../p9/procedures/xml/attribute_info/memory_mcs_attributes.xml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml index 5667e893..172fe90b 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml @@ -1981,13 +1981,13 @@ The first 0-15 bits are for PATTERN0, bits 16-32 are for PATTERN1. If this attribute is set to 0, using the default values of: - 0x13EC for PATTERN0 - 0x02FD for PATTERN1 + 0x8E8E for PATTERN0 + 0x2BC6 for PATTERN1 Set to default in eff_config uint32 - DEFAULT_PATTERN0 = 0xEA0C, DEFAULT_PATTERN1 = 0xA6C9 + DEFAULT_PATTERN0 = 0x8E8E, DEFAULT_PATTERN1 = 0x2BC6 2 custom_training_adv_patterns @@ -2013,7 +2013,7 @@ uint32 - DEFAULT_PATTERN0 = 0x13EC, DEFAULT_PATTERN1 = 0x02FD + DEFAULT_PATTERN0 = 0xEA0C, DEFAULT_PATTERN1 = 0xA6C9 2 custom_training_adv_backup_patterns -- cgit v1.2.1