From 898712503096decf08879f87894d06796df8ffe9 Mon Sep 17 00:00:00 2001 From: Joe McGill Date: Mon, 7 Nov 2016 08:17:13 -0600 Subject: p9_pba_coherent_utils -- correct LCO targeting in PBA SLVCTL Change-Id: I780b1b0d5068800b5be522219547d8a6584dde4c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32304 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: CHRISTINA L. GRAVES Reviewed-by: Dean Sanner Reviewed-by: Joseph J. McGill Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32305 Reviewed-by: Hostboot Team Tested-by: FSP CI Jenkins Reviewed-by: Sachin Gupta --- src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C b/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C index 6a91e66a..4f1836c1 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_pba_coherent_utils.C @@ -296,11 +296,11 @@ extern "C" if (l_operType == p9_PBA_oper_flag::LCO && !i_rnw) { FAPI_TRY(fapi2::getScom(i_ex_target, EX_L3_MODE_REG1, l3_mode_reg1), "Error reading from the L3 Mode Register"); - l3_mode_reg1.extractToRight(chiplet_number, 1, 5); + l3_mode_reg1.extractToRight(chiplet_number, 2, 4); } pba_slave_ctl_data.insertFromRight < PBA_SLVCTL_WRITE_TSIZE_START_BIT, - (PBA_SLVCTL_WRITE_TSIZE_END_BIT - PBA_SLVCTL_WRITE_TSIZE_START_BIT) + 1 > (chiplet_number); + (PBA_SLVCTL_WRITE_TSIZE_END_BIT - PBA_SLVCTL_WRITE_TSIZE_START_BIT) + 1 > (chiplet_number << 1); //set bits 36:49 to the ext addr extaddr = ((uint32_t) (i_address >> PBA_SLVCTL_EXTADDR_SHIFT)) & PBA_SLVCTL_EXTADDR_MASK; -- cgit v1.2.1