From 1008ef70a71fcfdec398ff30923d5025991c85f4 Mon Sep 17 00:00:00 2001 From: Shakeeb Date: Wed, 31 Aug 2016 15:15:19 -0500 Subject: SBE code restructure: cleanup Change-Id: I354cc79ba25b843fdb1a7524a19b8d0c41bd9051 RTC:159709 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29060 Tested-by: Jenkins Server Reviewed-by: Sachin Gupta Reviewed-by: AMIT J. TENDOLKAR --- src/test/framework/autocitest | 96 ++ src/test/framework/build-script | 72 ++ src/test/framework/check-copyright | 30 + src/test/framework/copyright-check.sh | 56 ++ src/test/framework/create-sandbox | 73 ++ src/test/framework/etc/patches/chip.act.patch | 146 +++ src/test/framework/etc/patches/patchlist.txt | 14 + src/test/framework/etc/patches/pervasive.act.patch | 28 + src/test/framework/etc/patches/powermgmt.act.patch | 1057 ++++++++++++++++++++ .../framework/etc/patches/standalone.simics.patch | 4 + src/test/framework/etc/workarounds.postsimsetup | 44 + src/test/framework/etc/workarounds.presimsetup | 31 + src/test/framework/populate-sandbox | 60 ++ src/test/framework/sbetest-start.sh | 38 + src/test/framework/setup-env | 84 ++ 15 files changed, 1833 insertions(+) create mode 100755 src/test/framework/autocitest create mode 100755 src/test/framework/build-script create mode 100755 src/test/framework/check-copyright create mode 100755 src/test/framework/copyright-check.sh create mode 100755 src/test/framework/create-sandbox create mode 100644 src/test/framework/etc/patches/chip.act.patch create mode 100644 src/test/framework/etc/patches/patchlist.txt create mode 100644 src/test/framework/etc/patches/pervasive.act.patch create mode 100644 src/test/framework/etc/patches/powermgmt.act.patch create mode 100644 src/test/framework/etc/patches/standalone.simics.patch create mode 100755 src/test/framework/etc/workarounds.postsimsetup create mode 100755 src/test/framework/etc/workarounds.presimsetup create mode 100755 src/test/framework/populate-sandbox create mode 100755 src/test/framework/sbetest-start.sh create mode 100755 src/test/framework/setup-env (limited to 'src/test/framework') diff --git a/src/test/framework/autocitest b/src/test/framework/autocitest new file mode 100755 index 00000000..3b7332b2 --- /dev/null +++ b/src/test/framework/autocitest @@ -0,0 +1,96 @@ +#!/bin/bash +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/framework/autocitest $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +################################################################################ +## Simics automation using run-fsp-it +################################################################################ + +## verbose is the default. +VERBOSE=" --verbose" +if [ "$1" = "--quiet" ] ; then + VERBOSE="" + shift +fi + +## +## set up +## +DRIVER="$1" ## backing tree +export bb=$DRIVER ## simulate a workon + +export SHELL="/bin/bash" ## Needed to fool workon to launch a bash + ## shell, which autosim expects. +NOWIN="--nowin" ## remote execution does not have a display + +## jenkins creates a new workspace for every compile. +## sbetest-start.sh will verify this and then export WORKSPACE_DIR for us. +SBXHOME=$SBEROOT + +if [ "$DRIVER" = "" ] ; then + echo "ERROR: you must specify a driver (backing tree) to run the tests with" + usage + exit 1 +fi + +## let's get set up +cd $SANDBOXROOT + +echo "$0" +echo "VERBOSE = $VERBOSE" +echo "NOWIN = $NOWIN" +echo "BACKING_TREE = $DRIVER" +echo "SANDBOXRC = $SANDBOXRC" +echo "SBXHOME = $SBXHOME" +echo "AUTOSIM_FFDC_XML = $AUTOSIM_FFDC_XML" +echo "current directory is " `pwd` + + +timestamp=`date +'%H:%M:%S'` +echo "$timestamp Starting SBE test..." + +# Check preconditions for run-fsp-it +# This is just workaround. It is expected +# that user already either have this file +# or tokens have been taken by klog command. +# This is just to make run-fsp-it work in user +# sandbox +if [ -z $RUNNING_UNDER_JENKINS ] +then + mkdir -p ~/private + if [ ! -f ~/private/.p ]; then + echo "Creating p file" + touch ~/private/.p + fi + + if [ ! -f ~/private/password ]; then + echo "Creating passwd file" + touch ~/private/password + echo "dummy" > ~/private/password + fi +fi + +execute_in_sandbox "run-fsp-it $NOWIN --machine $MACHINE $SBE_TEST_XML" "ppc" || exit -1 + +exit 0 + diff --git a/src/test/framework/build-script b/src/test/framework/build-script new file mode 100755 index 00000000..486a0ac9 --- /dev/null +++ b/src/test/framework/build-script @@ -0,0 +1,72 @@ +#!/bin/sh +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/framework/build-script $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +if [ -z $WORKSPACE ]; then + export WORKSPACE=`pwd` +fi + +if [ -z $SBEROOT ]; then + source "$WORKSPACE/env.bash" +fi + +source "$SBEROOT/src/test/framework/setup-env" + +# Check copyright. +#check-copyright > copyright.log 2>&1 & +#COPYRIGHT_PID=$! + + +# Build . +scl enable devtoolset-2 " bash -c \"make install\"" || exit -1 + +# Create simics sandbox. +create-sandbox > create-sandbox.log 2>&1 & +CREATESANDBOX_PID=$! + +# Check sandbox create completion. +wait $CREATESANDBOX_PID +if [ $? -eq 0 ]; then + cat create-sandbox.log +else + echo "----Sandbox creation failed." + cat create-sandbox.log + exit -1 +fi + +# Add SBE files to simics sandbox. +populate-sandbox || exit -1 + +sbetest-start.sh || exit -1 + +# Check copyright completion. +#wait $COPYRIGHT_PID +#if [ $? -eq 0 ]; then +# cat copyright.log +#else +# echo "----Copyright check failed." +# cat copyright.log +# exit -1 +#fi + diff --git a/src/test/framework/check-copyright b/src/test/framework/check-copyright new file mode 100755 index 00000000..bd893b39 --- /dev/null +++ b/src/test/framework/check-copyright @@ -0,0 +1,30 @@ +#!/bin/sh +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/framework/check-copyright $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +COPYRIGHT_CHECK=${SBEROOT}/src/test/framework/copyright-check.sh +COMMIT_CHECK=${SBEROOT}/src/tools/hooks/verify-commit + +$COPYRIGHT_CHECK || exit -1 +$COMMIT_CHECK || exit -1 diff --git a/src/test/framework/copyright-check.sh b/src/test/framework/copyright-check.sh new file mode 100755 index 00000000..ec305360 --- /dev/null +++ b/src/test/framework/copyright-check.sh @@ -0,0 +1,56 @@ +#!/bin/sh +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/framework/copyright-check.sh $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# +# Front end to addCopyright - script to check for copyright block during +# Gerrit checkin. +# + +export WORKSPACE_DIR=`pwd` +export ADDCOPYRIGHT=${WORKSPACE_DIR}/src/tools/hooks/addCopyright + +## run git show to get a list of checked in files +CHECKINFILES=`git show --pretty=format: --name-only -n1 | tr '\n' ' '` +## use git log to determine the year of the commit. +## Since commits have their copyright updated at the time they are +## committed, a commit might have a copyright date in its prolog of +## last year. Set the DATE_OVERRIDE variable to the 'validate' to allow +## slightly-old prologs (ie. ones corresponding to the date in the msg). +export DATE_OVERRIDE=`git log -n1 --date=short | grep "Date" | sed "s/Date: *//" | sed "s/-.*//"` + +echo "========================================================================" + +echo " Checking Copyright blocks for checked-in files:" +echo " $CHECKINFILES" +echo +$ADDCOPYRIGHT validate $CHECKINFILES --copyright-check + +if [ $? -eq 0 ]; then + echo "Copyright Check passed OK, $?" + exit 0 +else + echo "ERROR: $?" + exit 1 +fi diff --git a/src/test/framework/create-sandbox b/src/test/framework/create-sandbox new file mode 100755 index 00000000..add0a78b --- /dev/null +++ b/src/test/framework/create-sandbox @@ -0,0 +1,73 @@ +#!/bin/sh +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/framework/create-sandbox $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +echo "Creating ODE sandbox..." + +# Ensure backing build is accessible. +if [ ! -d "$BACKING_BUILD" ]; +then + echo "Cannot access the backing build: $BACKING_BUILD" + exit -1 +fi + +# Delete existing sandbox if it exists. +if [ -d "$SANDBOXBASE" ]; +then + echo "----Removing old sandbox." + mksb -undo -auto -rc $SANDBOXRC -dir $SANDBOXROOT -sb $SANDBOXNAME +fi +if [ -d "$SANDBOXBASE" ]; +then + rm -rf $SANDBOXBASE +fi + +# Create sandbox. +mksb -rc $SANDBOXRC -dir $SANDBOXROOT -back $BACKING_BUILD -sb $SANDBOXNAME \ + -m ppc -auto || exit -1 + +# workaround scripts expect $sb variable to be populated. +export sb=$SANDBOXBASE/src + +execute_in_sandbox "ecc --inject ${SBE_IMG_OUT_LOC}/sbe_seeprom.bin --output ${SBE_IMG_OUT_LOC}/sbe_seeprom.bin.ecc --p8 " "ppc" || exit -1 + +# Run presimsetup workarounds. +echo "----Running presimsetup workarounds." +if [ -f ${CITESTPATH}/etc/workarounds.presimsetup ]; +then + ${CITESTPATH}/etc/workarounds.presimsetup || exit -1 +fi + +# Run start_simics to populate simics directories. +echo "----Setting up simics." +execute_in_sandbox "start_simics -no_start -machine $MACHINE -batch_mode" \ + "ppc" || exit -1 + +# Run postsimsetup workarounds. +echo "----Running postsimsetup workarounds." +if [ -f ${CITESTPATH}/etc/workarounds.postsimsetup ]; +then + ${CITESTPATH}/etc/workarounds.postsimsetup || exit -1 +fi + diff --git a/src/test/framework/etc/patches/chip.act.patch b/src/test/framework/etc/patches/chip.act.patch new file mode 100644 index 00000000..0b9cf0f0 --- /dev/null +++ b/src/test/framework/etc/patches/chip.act.patch @@ -0,0 +1,146 @@ +184,240c184 +< # ========================================================================== +< # Actions for p9_adu_access and p9_adu_setup procedures +< # ========================================================================== +< #If a read/write is done to the ALTD_DATA Register set the ALTD_STATUS Register so things are as expected +< CAUSE_EFFECT{ +< LABEL=[ADU Read or write to set ALTD_STATUS Register] +< #If the data register is read +< WATCH_READ=[REG(0x00090004)] +< #If the data register is written +< WATCH=[REG(0x00090004)] +< +< #Set the ALTD_STATUS Register so these bits are set: +< #FBC_ALTD_BUSY = WAIT_CMD_ARBIT = WAIT_RESP = OVERRUN_ERR = AUTOINC_ERR = COMMAND_ERR = ADDRESS_ERR = COMMAND_HANG_ERR = DATA_HANG_ERR = PBINIT_MISSING = ECC_CE = ECC_UE = ECC_SUE = 0 +< EFFECT: TARGET=[REG(0x00090003)] OP=[BUF,AND] DATA=[LITERAL(64,001FDFFF FFFF1FFF)] +< EFFECT: TARGET=[REG(0x00090003)] OP=[BUF,OR] DATA=[LITERAL(64,30000000 00000000)] +< } +< +< #If a read/write is done to the ALTD_DATA Register and the Address only bit is not set then set the DATA_DONE bit to 1 +< CAUSE_EFFECT{ +< LABEL=[ADU Read or write to set ALTD_STATUS[DATA_DONE] bit] +< #If the data register is read +< WATCH_READ=[REG(0x00090004)] +< #If the data register is written +< WATCH=[REG(0x00090004)] +< CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6] +< +< #Set the DATA_DONE bit +< EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] +< } +< +< #If a read/write is done to the ALTD_DATA Register and the Data only bit is not set then set the ADDR_DONE bit to 1 +< CAUSE_EFFECT{ +< LABEL=[ADU Read or write to set ALTD_STATUS[ADDR_DONE] bit] +< #If the data register is read +< WATCH_READ=[REG(0x00090004)] +< #If the data register is written +< WATCH=[REG(0x00090004)] +< CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7] +< +< #Set the ADDR_DONE bit +< EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] +< } +< +< #If a read is done to the ALTD_CMD Register and it sets the lock set the ALTD_STATUS Register so the ALTD_STATUS_BUSY bit is set +< CAUSE_EFFECT{ +< LABEL=[ADU Write to set ALTD_STATUS_BUSY] +< WATCH=[REG(0x00090001)] +< CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[11] +< +< #Set the ALTD_STATUS Register so the ALTD_STATUS_BUSY bit is set +< EFFECT: TARGET=[REG(0x090003)] OP=[BIT,ON] BIT=[0] +< } +< #If a write is done to the ALD_CMD_REG to set the FBC_ALTD_START_OP bit it should turn FBC_ALTD_BUSY off +< CAUSE_EFFECT{ +< LABEL=[ADU Write to ALTD_CMD_REG to unset set ALTD_STATUS FBC_ALTD_BUSY bit] +< WATCH=[REG(0x00090001)] +< CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] +--- +> ### ADU ACTIONS - READ WRITE RESET ### +242,243c186,265 +< #Unset the ALTD_STATUS Register so the ALTD_STATUS_BUSY is unset +< EFFECT: TARGET=[REG(0x090003)] OP=[BIT,OFF] BIT=[0] +--- +> # Reset ALTD Status Reg +> CAUSE_EFFECT { +> LABEL=[RESET FSM ALTD Status Register] +> WATCH=[REG(0x00090001)] # ALTD_Cmd_Reg +> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[4] #Reset FSM bit +> EFFECT: TARGET=[REG(0x00090003)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)] +> } +> +> # ADU Transaction Complete Status - Busy Bit Low +> CAUSE_EFFECT { +> LABEL=[ALTD_BUSY Status Register Clear] +> WATCH=[REG(0x00090003)] # ALTD_Status_Reg +> CAUSE: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #FBC_ALTD_ADDR_DONE +> CAUSE: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] #FBC_ALTD_DATA_DONE +> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[19] #AUTO INCR Mode OFF +> +> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,OFF] BIT=[0] #BUSY Bit low +> } +> +> # Read without AutoIncr +> CAUSE_EFFECT{ +> LABEL=[READ Mainstore without AutoIncr] +> WATCH=[REG(0x00090001)] # ALTD_Cmd_Reg +> +> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] #start ADU Operation +> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[5] #READ ADU Operation +> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6] #addr Only Type Command +> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7] #data +> +> EFFECT: TARGET=[MODULE(readMainstore, 0x00090000)] OP=[MODULECALL] DATA=[REG(0x00090004)] # read the memory +> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #FBC_ALTD_ADDR_DONE +> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] #FBC_ALTD_DATA_DONE +> } +> +> # Read with AutoIncr +> CAUSE_EFFECT{ +> LABEL=[READ Mainstore with AutoIncr] +> WATCH_READ=[REG(0x00090004)] # ALTD_Data_reg +> +> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] #start ADU Operation +> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[5] #READ ADU Operation +> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6] #addr Only Type Command +> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7] #data +> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[19] #AutoInc bit on +> +> EFFECT: TARGET=[MODULE(readMainstore, 0x00090000)] OP=[MODULECALL] DATA=[REG(0x00090004)] # read the memory +> EFFECT: TARGET=[REG(0x00090000)] OP=[INCREMENT,MASK] INCVAL=[8] MASK=[LITERAL(64,00000000 0000FFFF)] # incr addr reg by 8 +> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #FBC_ALTD_ADDR_DONE +> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] #FBC_ALTD_DATA_DONE +> } +> +> # Write without AutoIncr +> CAUSE_EFFECT{ +> LABEL=[WRITE Mainstore without AutoIncr] +> WATCH=[REG(0x00090001)] # ALTD_Cmd_Reg +> WATCH=[REG(0x00090004)] # ALTD_Data_reg +> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] #start ADU Operation +> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[5] #WRITE ADU Operation +> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6] #addr Only Type Command +> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7] #data +> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[19] #AutoInc bit off +> EFFECT: TARGET=[MODULE(writeMainstore, 0x00090000)] OP=[MODULECALL] DATA=[REG(0x00090004)] # write the memory +> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #FBC_ALTD_ADDR_DONE +> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] #FBC_ALTD_DATA_DONE +> } +> +> # Write with AutoIncr +> CAUSE_EFFECT{ +> LABEL=[WRITE Mainstore with AutoIncr] +> WATCH=[REG(0x00090001)] # ALTD_Cmd_reg +> WATCH=[REG(0x00090004)] # ALTD_Data_reg +> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] #start ADU Operation +> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[5] #WRITE ADU Operation +> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6] #addr Only Type Command +> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7] #data +> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[19] #AutoInc bit on +> EFFECT: TARGET=[MODULE(writeMainstore, 0x00090000)] OP=[MODULECALL] DATA=[REG(0x00090004)] # write the memory +> EFFECT: TARGET=[REG(0x00090000)] OP=[INCREMENT,MASK] INCVAL=[8] MASK=[LITERAL(64, 00000000 0000FFFF)] # incr addr reg by 8 +> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #FBC_ALTD_ADDR_DONE +> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] #FBC_ALTD_DATA_DONE +265a288 +> EFFECT: TARGET=[MODULE(executeInstruction, MYCORE)] OP=[MODULECALL] DATA=[REG(MYCHIPLET, 0x00010A4F)] diff --git a/src/test/framework/etc/patches/patchlist.txt b/src/test/framework/etc/patches/patchlist.txt new file mode 100644 index 00000000..4fd0444a --- /dev/null +++ b/src/test/framework/etc/patches/patchlist.txt @@ -0,0 +1,14 @@ +# Example Format +#Brief description of the problem or reason for patch +#-RTC: Task/Story used to remove this patch +#-CQ: Defect/Req for checking the changes into fips910 +#-Files: list of files +#-Coreq: list of associated changes, e.g. workarounds.presimsetup + +RTC: 144728 +Files : pervasive.act.patch. Currently SUET does not support FSIMBOX KW. Once + support is in, remove this patch. + +RTC: 128984 +Files: chip.act.patch. Added call for executeInstruction module call. + p9.inst.patch. Added P9 specific commands for ramming. diff --git a/src/test/framework/etc/patches/pervasive.act.patch b/src/test/framework/etc/patches/pervasive.act.patch new file mode 100644 index 00000000..5531bef6 --- /dev/null +++ b/src/test/framework/etc/patches/pervasive.act.patch @@ -0,0 +1,28 @@ +55c55 +< WATCH=[REG(0x00050018)] +--- +> WATCH=[FSIMBOX(0x18)] +57c57 +< CAUSE: TARGET=[REG(0x00050018)] OP=[BIT,OFF] BIT=[12] +--- +> CAUSE: TARGET=[FSIMBOX(0x18)] OP=[BIT,OFF] BIT=[12] +59c59 +< CAUSE: TARGET=[REG(0x00050018)] OP=[BIT,OFF] BIT=[0] +--- +> CAUSE: TARGET=[FSIMBOX(0x18)] OP=[BIT,OFF] BIT=[0] +67c67 +< WATCH=[REG(0x00050018)] +--- +> WATCH=[FSIMBOX(0x18)] +69c69 +< CAUSE: TARGET=[REG(0x00050018)] OP=[BIT,OFF] BIT=[4] +--- +> CAUSE: TARGET=[FSIMBOX(0x18)] OP=[BIT,OFF] BIT=[4] +78c78 +< WATCH=[REG(0x00050018)] +--- +> WATCH=[FSIMBOX(0x18)] +80c80 +< CAUSE: TARGET=[REG(0x00050018)] OP=[BIT,OFF] BIT=[4] +--- +> CAUSE: TARGET=[FSIMBOX(0x18)] OP=[BIT,OFF] BIT=[4] diff --git a/src/test/framework/etc/patches/powermgmt.act.patch b/src/test/framework/etc/patches/powermgmt.act.patch new file mode 100644 index 00000000..efb03845 --- /dev/null +++ b/src/test/framework/etc/patches/powermgmt.act.patch @@ -0,0 +1,1057 @@ +43,112d42 +< ## Actions for Procedure - p9_pm_occ_control +< ## +< +< CAUSE_EFFECT { +< LABEL=[PPC405 HALT] +< WATCH=[REG(0x0006D006)] +< CAUSE: TARGET=[REG(0x0006D006)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 02000000 00000000)] +< #suet PPC405_UNHALT:tc1- EFFECT: TARGET=[REG(0x01010800)] OP=[BIT,OFF] BIT=[31] +< EFFECT: TARGET=[REG(0x01010800)] OP=[BIT,ON] BIT=[31] +< } +< +< ## +< ## Actions for Procedure - p9_pm_occ_gpe_init +< ## +< +< CAUSE_EFFECT { +< LABEL=[OCC GPE0 HALT] +< WATCH=[REG(0x00060010)] +< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,OFF] BIT=[1] +< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,OFF] BIT=[2] +< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,ON] BIT=[3] +< #suet OCCGPE0_HALT_FAIL:tc1- EFFECT: TARGET=[REG(0x00060021)] OP=[BIT,OFF] BIT=[0] +< EFFECT: TARGET=[REG(0x00060021)] OP=[BIT,ON] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[OCC GPE1 HALT] +< WATCH=[REG(0x00062010)] +< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,OFF] BIT=[1] +< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,OFF] BIT=[2] +< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,ON] BIT=[3] +< #suet OCCGPE1_HALT_FAIL:tc1- EFFECT: TARGET=[REG(0x00062021)] OP=[BIT,OFF] BIT=[0] +< EFFECT: TARGET=[REG(0x00062021)] OP=[BIT,ON] BIT=[0] +< } +< +< # Upon writing the PU_OCB_PIB_OCR[DBG_HALT} bit, set the OCCLFIR_PPC405_DBGSTOPACK_BIT. +< CAUSE_EFFECT { +< LABEL=[PPC405 SAFE_HALT] +< WATCH=[REG(00x0006D002)] +< CAUSE: TARGET=[REG(0x0006D002)] OP=[EQUALTO,BUF] DATA=[LITERAL(64, 00200000 00000000)] +< EFFECT: TARGET=[REG(0x01010800)] OP=[BIT,ON] BIT=[31] +< } +< +< +< ## +< ## Actions for Procedure - p9_pm_occ_gpe_init +< ## +< +< CAUSE_EFFECT { +< LABEL=[OCC GPE0 HALT] +< WATCH=[REG(0x00060010)] +< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,OFF] BIT=[1] +< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,OFF] BIT=[2] +< CAUSE: TARGET=[REG(0x00060010)] OP=[BIT,ON] BIT=[3] +< #suet OCCGPE0_HALT_FAIL:tc1- EFFECT: TARGET=[REG(0x00060021)] OP=[BIT,OFF] BIT=[0] +< EFFECT: TARGET=[REG(0x00060021)] OP=[BIT,ON] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[OCC GPE1 HALT] +< WATCH=[REG(0x00062010)] +< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,OFF] BIT=[1] +< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,OFF] BIT=[2] +< CAUSE: TARGET=[REG(0x00062010)] OP=[BIT,ON] BIT=[3] +< #suet OCCGPE1_HALT_FAIL:tc1- EFFECT: TARGET=[REG(0x00062021)] OP=[BIT,OFF] BIT=[0] +< EFFECT: TARGET=[REG(0x00062021)] OP=[BIT,ON] BIT=[0] +< } +< +< +< ## +134,409c64 +< +< ## Core0 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x200F0110)] +< CAUSE: TARGET=[REG(0x200F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x200F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x200F0110)] +< EFFECT: TARGET=[REG(0x200F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x200F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x200F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x200F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core0 End +< +< ## Core1 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x210F0110)] +< CAUSE: TARGET=[REG(0x210F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x210F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x210F0110)] +< EFFECT: TARGET=[REG(0x210F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x210F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x210F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x210F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core1 End +< +< ## Core2 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x220F0110)] +< CAUSE: TARGET=[REG(0x220F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x220F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x200F0110)] +< EFFECT: TARGET=[REG(0x220F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x220F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x220F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x220F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core2 End +< +< ## Core3 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x230F0110)] +< CAUSE: TARGET=[REG(0x230F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x230F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x230F0110)] +< EFFECT: TARGET=[REG(0x230F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x230F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x230F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x230F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core3 End +< +< ## Core4 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x240F0110)] +< CAUSE: TARGET=[REG(0x240F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x240F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x240F0110)] +< EFFECT: TARGET=[REG(0x240F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x240F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x240F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x240F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core4 End +< +< ## Core5 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x250F0110)] +< CAUSE: TARGET=[REG(0x250F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x250F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x250F0110)] +< EFFECT: TARGET=[REG(0x250F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x250F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x250F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x250F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core5 End +< +< ## Core6 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x260F0110)] +< CAUSE: TARGET=[REG(0x260F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x260F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x200F0110)] +< EFFECT: TARGET=[REG(0x260F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x260F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x260F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x260F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core6 End +< +< ## Core7 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x270F0110)] +< CAUSE: TARGET=[REG(0x270F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x270F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x270F0110)] +< EFFECT: TARGET=[REG(0x270F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x270F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x270F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x270F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core7 End +< +< ## Core8 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x280F0110)] +< CAUSE: TARGET=[REG(0x280F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x280F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x280F0110)] +< EFFECT: TARGET=[REG(0x280F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x280F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x280F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x200F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core8 End +< +< ## Core9 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x290F0110)] +< CAUSE: TARGET=[REG(0x290F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x290F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x290F0110)] +< EFFECT: TARGET=[REG(0x290F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x290F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x290F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x290F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core9 End +< +< ## Core10 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x2A0F0110)] +< CAUSE: TARGET=[REG(0x2A0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2A0F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2A0F0110)] +< EFFECT: TARGET=[REG(0x2A0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2A0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2A0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2A0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core10 End +< +< ## Core11 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x2B0F0110)] +< CAUSE: TARGET=[REG(0x2B0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2B0F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2B0F0110)] +< EFFECT: TARGET=[REG(0x2B0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2B0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2B0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2B0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core11 End +< +< ## Core12 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x2C0F0110)] +< CAUSE: TARGET=[REG(0x2C0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2C0F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2C0F0110)] +< EFFECT: TARGET=[REG(0x2C0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2C0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2C0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2C0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core12 End +< +< ## Core13 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x2D0F0110)] +< CAUSE: TARGET=[REG(0x2D0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2D0F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2D0F0110)] +< EFFECT: TARGET=[REG(0x2D0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2D0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2D0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2D0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core13 End +< +< ## Core14 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x2E0F0110)] +< CAUSE: TARGET=[REG(0x2E0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2E0F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2E0F0110)] +< EFFECT: TARGET=[REG(0x2E0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2E0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2E0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2E0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core14 End +< +< ## Core15 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x2F0F0110)] +< CAUSE: TARGET=[REG(0x2F0F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x2F0F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x2F0F0110)] +< EFFECT: TARGET=[REG(0x2F0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2F0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2F0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x2F0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core15 End +< +< ## Core16 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x300F0110)] +< CAUSE: TARGET=[REG(0x300F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x300F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x300F0110)] +< EFFECT: TARGET=[REG(0x300F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x300F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x300F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x300F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core16 End +< +< ## Core17 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x310F0110)] +< CAUSE: TARGET=[REG(0x310F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x310F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x310F0110)] +< EFFECT: TARGET=[REG(0x310F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x310F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x310F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x310F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core17 End +< +< ## Core18 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x320F0110)] +< CAUSE: TARGET=[REG(0x320F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x320F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x320F0110)] +< EFFECT: TARGET=[REG(0x320F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x320F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x320F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x320F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core18 End +< +< ## Core19 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x330F0110)] +< CAUSE: TARGET=[REG(0x330F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x330F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x330F0110)] +< EFFECT: TARGET=[REG(0x330F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x330F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x330F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x330F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core19 End +< +< ## Core20 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x340F0110)] +< CAUSE: TARGET=[REG(0x340F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x340F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x340F0110)] +< EFFECT: TARGET=[REG(0x340F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x340F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x340F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x340F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core20 End +< +< ## Core21 Start +< CAUSE_EFFECT { +--- +> CAUSE_EFFECT CHIPLETS ec { +411,478c66,89 +< WATCH=[REG(0x350F0110)] +< CAUSE: TARGET=[REG(0x350F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x350F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x350F0110)] +< EFFECT: TARGET=[REG(0x350F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x350F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x350F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x350F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core21 End +< +< ## Core22 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x360F0110)] +< CAUSE: TARGET=[REG(0x360F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x360F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x360F0110)] +< EFFECT: TARGET=[REG(0x360F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x360F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x360F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x360F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core22 End +< +< ## Core23 Start +< CAUSE_EFFECT { +< LABEL=[SSH_SRC_WRITE] +< WATCH=[REG(0x370F0110)] +< CAUSE: TARGET=[REG(0x370F0110)] OP=[EQUALTO,BUF] DATA=[REG(0x370F0110)] +< EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(0x370F0110)] +< EFFECT: TARGET=[REG(0x370F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x370F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x370F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< EFFECT: TARGET=[REG(0x370F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +< } +< ## Core23 End +< +< ## +< # Actions for Procedure - p9_block_wakeup_intr +< ## +< +< # Core Power Management Mode Register +< CAUSE_EFFECT { +< LABEL=[CPMMR Write OR of PPM Write Override] +< WATCH=[REG(0x290F0108)] +< CAUSE: TARGET=[REG(0x290F0108)] OP=[BIT,ON] BIT=[1] +< EFFECT: TARGET=[REG(0x290F0106)] OP=[BIT,ON] BIT=[1] +< } +< +< CAUSE_EFFECT { +< LABEL=[CPMMR Write CLEAR of PPM Write Override] +< WATCH=[REG(0x290F0107)] +< CAUSE: TARGET=[REG(0x290F0107)] OP=[BIT,ON] BIT=[1] +< EFFECT: TARGET=[REG(0x290F0106)] OP=[BIT,OFF] BIT=[1] +< } +< +< # General Power Management Mode Register +< CAUSE_EFFECT { +< LABEL=[GPMMR Write OR of Block Wakeup Events] +< WATCH=[REG(0x290F0102)] +< CAUSE: TARGET=[REG(0x290F0102)] OP=[BIT,ON] BIT=[6] +< EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,ON] BIT=[6] +< } +< +< CAUSE_EFFECT { +< LABEL=[GPMMR Write CLEAR of PPM Write Override] +< WATCH=[REG(0x290F0101)] +< CAUSE: TARGET=[REG(0x290F0101)] OP=[BIT,ON] BIT=[6] +< EFFECT: TARGET=[REG(0x290F0100)] OP=[BIT,OFF] BIT=[6] +--- +> WATCH=[REG(MYCHIPLET, 0x0F0110)] +> CAUSE: TARGET=[REG(MYCHIPLET, 0x0F0110)] OP=[EQUALTO,BUF] DATA=[REG(MYCHIPLET, 0x0F0110)] +> EFFECT: TARGET=[SSH(0x0)] OP=[EQUALTO,BUF] DATA=[REG(MYCHIPLET, 0x0F0110)] +> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0111)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0112)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0113)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0114)] OP=[EQUALTO,BUF] DATA=[SSH(0x0)] +> } +> +> ## Action triggered when all threads are idle +> # Used for istep 16 to have hostboot properly wake up on SBE-set PSU +> # interrupt as well as to have p9_sbe_check_master_stop15.C properly +> # execute in firmware simics. +> # TODO: RTC 147787 +> CAUSE_EFFECT CHIPLETS ec { +> LABEL=[Master Winkle LPCR] +> WATCH=[IDLESTATE(MYCHIPLET,0x0)] +> # look for stop15 +> CAUSE: TARGET=[IDLESTATE(MYCHIPLET,0x0)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(32,0F000000)] MASK=[LITERAL(32,FF000000)] +> # Restore LPCR for wake-up options. +> EFFECT: TARGET=[PROCREG(lpcr, MYCORE, 0)] OP=[BIT,ON] BIT=[17] +> EFFECT: TARGET=[PROCREG(lpcr, MYCORE, 0)] OP=[BIT,ON] BIT=[49] +> # Set required C_PPM_SSHOTR register required by procedure +> EFFECT: TARGET=[REG(0x200F0113)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,8BB00000 FFFFFFFF)] +514c125 +< ## Actions for p9_pm_ocb_init +--- +> # Actions for Procedure - p9_hcd_core_poweron / p9_hcd_cache_poweron +517,524c128,133 +< CAUSE_EFFECT { +< LABEL=[Channel 0 linear stream] +< WATCH=[REG(0x0006D013)] +< WATCH=[REG(0x0006D012)] +< CAUSE: TARGET=[REG(0x0006D013)] OP=[BIT,ON] BIT=[4] +< CAUSE: TARGET=[REG(0x0006D012)] OP=[BIT,ON] BIT=[5] +< EFFECT: TARGET=[REG(0x0006D011)] OP=[BIT,ON] BIT=[4] +< EFFECT: TARGET=[REG(0x0006D011)] OP=[BIT,OFF] BIT=[5] +--- +> CAUSE_EFFECT CHIPLETS ec cache { +> LABEL=[Power on core/cache vdd pfet then fsm is idle and sense is enabled] +> WATCH=[REG(MYCHIPLET, 0x0F011A)] +> CAUSE: TARGET=[REG(MYCHIPLET, 0x0F011A)] OP=[BIT,ON] BIT=[0] +> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0118)] OP=[BIT,ON] BIT=[42] +> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F011C)] OP=[BIT,ON] BIT=[0] +527,1071c136 +< CAUSE_EFFECT { +< LABEL=[Channel 1 linear stream] +< WATCH=[REG(0x0006D033)] +< WATCH=[REG(0x0006D032)] +< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[4] +< CAUSE: TARGET=[REG(0x0006D032)] OP=[BIT,ON] BIT=[5] +< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[4] +< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,OFF] BIT=[5] +< } +< +< CAUSE_EFFECT { +< LABEL=[Channel 1 circular push interupt enable] +< WATCH=[REG(0x0006D033)] +< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[3] +< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[4] +< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[5] +< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[3] +< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[4] +< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[5] +< } +< +< CAUSE_EFFECT { +< LABEL=[Channel 1 circular push interrupt disable] +< WATCH=[REG(0x0006D033)] +< WATCH=[REG(0x0006D032)] +< CAUSE: TARGET=[REG(0x0006D032)] OP=[BIT,ON] BIT=[3] +< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[4] +< CAUSE: TARGET=[REG(0x0006D033)] OP=[BIT,ON] BIT=[5] +< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,OFF] BIT=[3] +< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[4] +< EFFECT: TARGET=[REG(0x0006D031)] OP=[BIT,ON] BIT=[5] +< } +< +< CAUSE_EFFECT { +< LABEL=[Channel 2 linear stream] +< WATCH=[REG(0x0006D053)] +< WATCH=[REG(0x0006D052)] +< CAUSE: TARGET=[REG(0x0006D053)] OP=[BIT,ON] BIT=[4] +< CAUSE: TARGET=[REG(0x0006D052)] OP=[BIT,ON] BIT=[5] +< EFFECT: TARGET=[REG(0x0006D051)] OP=[BIT,ON] BIT=[4] +< EFFECT: TARGET=[REG(0x0006D051)] OP=[BIT,OFF] BIT=[5] +< } +< +< CAUSE_EFFECT { +< LABEL=[Channel 3 linear stream] +< WATCH=[REG(0x0006D073)] +< WATCH=[REG(0x0006D072)] +< CAUSE: TARGET=[REG(0x0006D073)] OP=[BIT,ON] BIT=[4] +< CAUSE: TARGET=[REG(0x0006D072)] OP=[BIT,ON] BIT=[5] +< EFFECT: TARGET=[REG(0x0006D071)] OP=[BIT,ON] BIT=[4] +< EFFECT: TARGET=[REG(0x0006D071)] OP=[BIT,OFF] BIT=[5] +< ## Actions for Procedure - p9_setup_evid +< ## +< +< CAUSE_EFFECT { +< LABEL=[AVSBus Write data register 0B] +< WATCH=[REG(0x0006C718)] +< CAUSE: TARGET=[REG(0x0006C718)] OP=[BIT,ON] BIT=[1] +< EFFECT: TARGET=[REG(0x0006C716)] OP=[BIT,ON] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[AVSBus Status register 0B] +< WATCH_READ=[REG(0x0006C716)] +< CAUSE: TARGET=[REG(0x0006C716)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x0006C716)] OP=[BIT,OFF] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[AVSBus Write data register 1B] +< WATCH=[REG(0x0006C738)] +< CAUSE: TARGET=[REG(0x0006C738)] OP=[BIT,ON] BIT=[1] +< EFFECT: TARGET=[REG(0x0006C736)] OP=[BIT,ON] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[AVSBus Status register 1B] +< WATCH_READ=[REG(0x0006C736)] +< CAUSE: TARGET=[REG(0x0006C736)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x0006C736)] OP=[BIT,OFF] BIT=[0] +< } +< +< ## Core 0 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x200F011A)] +< CAUSE: TARGET=[REG(0x200F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x200F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x200F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 0 End +< ## Core 1 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x210F011A)] +< CAUSE: TARGET=[REG(0x210F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x210F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x210F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 1 End +< ## Core 2 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x220F011A)] +< CAUSE: TARGET=[REG(0x220F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x220F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x220F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 2 End +< ## Core 3 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x230F011A)] +< CAUSE: TARGET=[REG(0x230F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x230F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x230F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 3 End +< ## Core 4 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x240F011A)] +< CAUSE: TARGET=[REG(0x240F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x240F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x240F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 4 End +< ## Core 5 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x250F011A)] +< CAUSE: TARGET=[REG(0x250F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x250F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x250F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 5 End +< ## Core 6 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x260F011A)] +< CAUSE: TARGET=[REG(0x260F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x260F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x260F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 6 End +< ## Core 7 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x270F011A)] +< CAUSE: TARGET=[REG(0x270F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x270F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x270F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 7 End +< ## Core 8 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x280F011A)] +< CAUSE: TARGET=[REG(0x280F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x280F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x280F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 8 End +< ## Core 9 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x290F011A)] +< CAUSE: TARGET=[REG(0x290F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x290F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x290F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 9 End +< ## Core 10 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x2a0F011A)] +< CAUSE: TARGET=[REG(0x2a0F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x2a0F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x2a0F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 10 End +< ## Core 11 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x2b0F011A)] +< CAUSE: TARGET=[REG(0x2b0F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x2b0F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x2b0F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 11 End +< ## Core 12 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x2c0F011A)] +< CAUSE: TARGET=[REG(0x2c0F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x2c0F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x2c0F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 12 End +< ## Core 13 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x2d0F011A)] +< CAUSE: TARGET=[REG(0x2d0F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x2d0F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x2d0F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 13 End +< ## Core 14 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x2e0F011A)] +< CAUSE: TARGET=[REG(0x2e0F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x2e0F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x2e0F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 14 End +< ## Core 15 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x2f0F011A)] +< CAUSE: TARGET=[REG(0x2f0F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x2f0F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x2f0F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 15 End +< ## Core 16 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x300F011A)] +< CAUSE: TARGET=[REG(0x300F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x300F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x300F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 16 End +< ## Core 17 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x310F011A)] +< CAUSE: TARGET=[REG(0x310F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x310F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x310F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 17 End +< ## Core 18 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x320F011A)] +< CAUSE: TARGET=[REG(0x320F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x320F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x320F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 18 End +< ## Core 19 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x330F011A)] +< CAUSE: TARGET=[REG(0x330F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x330F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x330F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 19 End +< ## Core 20 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x340F011A)] +< CAUSE: TARGET=[REG(0x340F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x340F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x340F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 20 End +< ## Core 21 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x350F011A)] +< CAUSE: TARGET=[REG(0x350F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x350F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x350F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 21 End +< ## Core 22 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x360F011A)] +< CAUSE: TARGET=[REG(0x360F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x360F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x360F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 22 End +< ## Core 23 Start +< +< ## +< # Actions for Procedure - p9_hcd_core_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on core vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x370F011A)] +< CAUSE: TARGET=[REG(0x370F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x370F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x370F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< # Core 23 End +< ## EQ 0 Start +< +< ## +< # Actions for Procedure - p9_hcd_cache_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x100F011A)] +< CAUSE: TARGET=[REG(0x100F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x100F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x100F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x100F011A)] +< CAUSE: TARGET=[REG(0x100F011A)] OP=[BIT,ON] BIT=[2] +< EFFECT: TARGET=[REG(0x100F0118)] OP=[BIT,ON] BIT=[50] +< EFFECT: TARGET=[REG(0x100F011C)] OP=[BIT,ON] BIT=[2] +< } +< +< ## EQ 0 End +< +< ## EQ 1 Start +< +< ## +< # Actions for Procedure - p9_hcd_cache_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x110F011A)] +< CAUSE: TARGET=[REG(0x110F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x110F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x110F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x110F011A)] +< CAUSE: TARGET=[REG(0x110F011A)] OP=[BIT,ON] BIT=[2] +< EFFECT: TARGET=[REG(0x110F0118)] OP=[BIT,ON] BIT=[50] +< EFFECT: TARGET=[REG(0x110F011C)] OP=[BIT,ON] BIT=[2] +< } +< +< ## EQ 1 End +< +< ## EQ 2 Start +< +< ## +< # Actions for Procedure - p9_hcd_cache_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x120F011A)] +< CAUSE: TARGET=[REG(0x120F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x120F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x120F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x120F011A)] +< CAUSE: TARGET=[REG(0x120F011A)] OP=[BIT,ON] BIT=[2] +< EFFECT: TARGET=[REG(0x120F0118)] OP=[BIT,ON] BIT=[50] +< EFFECT: TARGET=[REG(0x120F011C)] OP=[BIT,ON] BIT=[2] +< } +< +< ## EQ 2 End +< +< ## EQ 3 Start +< +< ## +< # Actions for Procedure - p9_hcd_cache_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x130F011A)] +< CAUSE: TARGET=[REG(0x130F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x130F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x130F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x130F011A)] +< CAUSE: TARGET=[REG(0x130F011A)] OP=[BIT,ON] BIT=[2] +< EFFECT: TARGET=[REG(0x130F0118)] OP=[BIT,ON] BIT=[50] +< EFFECT: TARGET=[REG(0x130F011C)] OP=[BIT,ON] BIT=[2] +< } +< +< ## EQ 3 End +< +< ## EQ 4 Start +< +< ## +< # Actions for Procedure - p9_hcd_cache_poweron +< ## +< +< CAUSE_EFFECT { +--- +> CAUSE_EFFECT CHIPLETS cache { +1073,1084c138,141 +< WATCH=[REG(0x140F011A)] +< CAUSE: TARGET=[REG(0x140F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x140F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x140F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x140F011A)] +< CAUSE: TARGET=[REG(0x140F011A)] OP=[BIT,ON] BIT=[2] +< EFFECT: TARGET=[REG(0x140F0118)] OP=[BIT,ON] BIT=[50] +< EFFECT: TARGET=[REG(0x140F011C)] OP=[BIT,ON] BIT=[2] +--- +> WATCH=[REG(MYCHIPLET, 0x0F011A)] +> CAUSE: TARGET=[REG(MYCHIPLET, 0x0F011A)] OP=[BIT,ON] BIT=[2] +> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F0118)] OP=[BIT,ON] BIT=[50] +> EFFECT: TARGET=[REG(MYCHIPLET, 0x0F011C)] OP=[BIT,ON] BIT=[2] +1087,1112d143 +< ## EQ 4 End +< +< ## EQ 5 Start +< +< ## +< # Actions for Procedure - p9_hcd_cache_poweron +< ## +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vdd pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x150F011A)] +< CAUSE: TARGET=[REG(0x150F011A)] OP=[BIT,ON] BIT=[0] +< EFFECT: TARGET=[REG(0x150F0118)] OP=[BIT,ON] BIT=[42] +< EFFECT: TARGET=[REG(0x150F011C)] OP=[BIT,ON] BIT=[0] +< } +< +< CAUSE_EFFECT { +< LABEL=[Power on cache vcs pfet then fsm is idle and sense is enabled] +< WATCH=[REG(0x150F011A)] +< CAUSE: TARGET=[REG(0x150F011A)] OP=[BIT,ON] BIT=[2] +< EFFECT: TARGET=[REG(0x150F0118)] OP=[BIT,ON] BIT=[50] +< EFFECT: TARGET=[REG(0x150F011C)] OP=[BIT,ON] BIT=[2] +< } +< +< ## EQ 5 End +< diff --git a/src/test/framework/etc/patches/standalone.simics.patch b/src/test/framework/etc/patches/standalone.simics.patch new file mode 100644 index 00000000..bdc40fd8 --- /dev/null +++ b/src/test/framework/etc/patches/standalone.simics.patch @@ -0,0 +1,4 @@ +52c52 +< ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "00000000_00000000" 64 +--- +> ($hb_masterproc).proc_chip.invoke parallel_store SCOM 0x5003A "80000000_00000000" 64 diff --git a/src/test/framework/etc/workarounds.postsimsetup b/src/test/framework/etc/workarounds.postsimsetup new file mode 100755 index 00000000..ac7f3a29 --- /dev/null +++ b/src/test/framework/etc/workarounds.postsimsetup @@ -0,0 +1,44 @@ +#!/bin/sh +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/framework/etc/workarounds.postsimsetup $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +## Workarounds that are run after start_simics is executed for the first time +## to setup the sandbox +## + +### Example applying a patch to cec-chip files +#echo "+++ Updating something wonderful in a simics file" +#mkdir -p $sb/simu/data/cec-chip/ +#cp $BACKING_BUILD/src/simu/data/cec-chip/base_cec_chip_file $sb/simu/data/cec-chip +#patch -p0 $sb/simu/data/cec-chip/base_cec_chip_file $SBEROOT/src/build/citest/etc/patches/my_patch_File + +# NOTE: The below patch removes mailbox settings in standalone.simics (comes +# from HB) that cause the SBE to run in plck mode. For our CI, we need the SBE +# to be in istep mode. This patch is likely never going to be removed as long as +# we need our CI to run in istep mode. +echo "+++ Patching standalone.simics" +mkdir -p $SANDBOXBASE/obj/ppc/simu/scripts/hbfw +cp $BACKING_BUILD/obj/ppc/simu/scripts/hbfw/standalone.simics $SANDBOXBASE/obj/ppc/simu/scripts/hbfw +patch -p0 $SANDBOXBASE/obj/ppc/simu/scripts/hbfw/standalone.simics $SBEROOT/src/test/framework/etc/patches/standalone.simics.patch + diff --git a/src/test/framework/etc/workarounds.presimsetup b/src/test/framework/etc/workarounds.presimsetup new file mode 100755 index 00000000..e863b07d --- /dev/null +++ b/src/test/framework/etc/workarounds.presimsetup @@ -0,0 +1,31 @@ +#!/bin/sh +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/framework/etc/workarounds.presimsetup $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +#### Examples #### +#echo "+++ Some message about why you need to do this." +#mkdir -p $sb/simu/data +#egrep -v "WSALIAS DEFAULT FIPSLEVEL|WSALIAS DEFAULT SIMICSLEVEL" $BACKING_BUILD/src/simu/data/simicsInfo > $sb/simu/data/simicsInfo +#echo "WSALIAS DEFAULT FIPSLEVEL env/gfwb/simics-4.2.0/simics-4.2.83/fips/fld36/fi120201a700.42" >> $sb/simu/data/simicsInfo +#echo "WSALIAS DEFAULT SIMICSLEVEL env/vtechb/simics-4.2.0/simics-4.2.83/bin" >> $sb/simu/data/simicsInfo diff --git a/src/test/framework/populate-sandbox b/src/test/framework/populate-sandbox new file mode 100755 index 00000000..729b61fa --- /dev/null +++ b/src/test/framework/populate-sandbox @@ -0,0 +1,60 @@ +#!/bin/sh +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/framework/populate-sandbox $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# Ensure sandbox exists (create-sandbox has been called). +if [ -z $SANDBOXBASE ]; +then + echo "SANDBOXBASE variable uninitialized.." + exit -1 +fi + +if [ ! -d "$SANDBOXBASE" ]; +then + echo "Cannot find sandbox: $SANDBOXBASE" + exit -1 +fi + +# Create test directory. +mkdir -p $SBETESTDIR || exit -1 + +# Create test directory. +mkdir -p $SBEFW_IMG_DIR || exit -1 + +# Copy sbe binaries +cp $SBEROOT/images/*.bin $SBEFW_IMG_DIR/ || exit -1 +cp $SBEROOT/images/simics.tar $SBEFW_DIR/ || exit -1 +# Compile sbe code in sandbox to copy binaries at right place +echo "---Setup sandbox for sbe binaries." + +execute_in_sandbox "cd $SBEFW_DIR; mk -a" \ + "ppc" || exit -1 + +execute_in_sandbox "cd $SBEFW_DIR; mk install_all" \ + "ppc" || exit -1 + + +# Copy test files. +cp -r $SBEROOT/src/test/testcases/* $SBETESTDIR/ || exit -1 + diff --git a/src/test/framework/sbetest-start.sh b/src/test/framework/sbetest-start.sh new file mode 100755 index 00000000..a0d7f27a --- /dev/null +++ b/src/test/framework/sbetest-start.sh @@ -0,0 +1,38 @@ +#!/bin/sh +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/framework/sbetest-start.sh $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +if [ -z $SBE_CI_ENV_SETUP ]; +then + unset $SANDBOXBASE + unset $SANDBOXNAME + source "$SBEROOT/src/test/framework/setup-env" +fi + +# Front end to autocitest - script to execute unit tests under simics. +# +## when jenkins runs it will create a workspace with the built code tree +## and drop us into it. +autocitest ${BACKING_BUILD} + +exit $? diff --git a/src/test/framework/setup-env b/src/test/framework/setup-env new file mode 100755 index 00000000..6de2d8fd --- /dev/null +++ b/src/test/framework/setup-env @@ -0,0 +1,84 @@ +#!/bin/sh +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/test/framework/setup-env $ +# +# OpenPOWER sbe Project +# +# Contributors Listed Below - COPYRIGHT 2015,2016 +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +export CITESTPATH=${SBEROOT}/src/test/framework +export PATH=${CITESTPATH}:${PATH} + +# If we are running under Jenkins we need to pick a random-ish sandbox name +# so that the autoipl tools do not have a /tmp name collision. +if [ -z $JOB_NAME -o -z $BUILD_NUMBER ]; +then + SBECI_SANDBOX="test_sb" +else + export RUNNING_UNDER_JENKINS=1 + SBECI_SANDBOX=`echo $JOB_NAME $BUILD_NUMBER | md5sum | head -c10` +fi + +# Setup sandbox location variables. +if [ -z $SANDBOXROOT ]; +then + export SANDBOXROOT=${SBEROOT} +fi + +if [ -z $SANDBOXNAME ] || [ "$RUNNING_UNDER_JENKINS" = "1" ]; +then + export SANDBOXNAME=${SBECI_SANDBOX} +fi + +export SANDBOXBASE=${SANDBOXROOT}/${SANDBOXNAME} + +if [ -z $SANDBOXRC ]; +then + export SANDBOXRC=${SANDBOXROOT}/sbesandboxrc +fi +# Useful utility function. +execute_in_sandbox() +{ + WORKON_CMD="workon -rc ${SANDBOXRC} -sb ${SANDBOXNAME} -m $2 " + echo $1 > ${SANDBOXBASE}/src/sandbox_execute_cmd + chmod 700 ${SANDBOXBASE}/src/sandbox_execute_cmd + + TEST="${WORKON_CMD} -c ./sandbox_execute_cmd " + echo $TEST + ${WORKON_CMD} -c ./sandbox_execute_cmd + + if [ $? -ne 0 ]; then + return 1 + fi + + rm ${SANDBOXBASE}/src/sandbox_execute_cmd +} +export -f execute_in_sandbox + +# Setup machine type. +export MACHINE=${MACHINE:-$DEFAULT_MACHINE} + +export SBETESTDIR=$SANDBOXBASE/simics/targets/p9_nimbus/sbeTest +export SBEFW_DIR=$SANDBOXBASE/src/sbei/sbfw/ +export SBEFW_IMG_DIR=$SANDBOXBASE/src/sbei/sbfw/img +export AUTOSIM_FFDC_XML=$SBETESTDIR/ffdc.xml +export SBE_TEST_XML=$SBETESTDIR/test.xml +# Indicate we setup the CI environment. +export SBE_CI_ENV_SETUP=1 -- cgit v1.2.1