From 9b7838172f0bbce5fc90c5626664facafc9ecfef Mon Sep 17 00:00:00 2001 From: Raja Das Date: Thu, 15 Feb 2018 04:49:54 -0600 Subject: SBE Regression - Allowed invalid scom via MBOX3 bit 12 for Test team Change-Id: Ia47255b6c89dfe7554e5ddc2a3954a2c939fc58b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54111 Tested-by: Jenkins Server Reviewed-by: Shakeeb A. Pasha B K Tested-by: FSP CI Jenkins Reviewed-by: Sachin Gupta --- src/sbefw/core/sberegaccess.C | 34 ++++++++++++++++++++++++---------- src/sbefw/core/sberegaccess.H | 30 ++++++++++++++++++++++++++---- src/sbefw/core/sbescom.C | 16 +++++++++++----- 3 files changed, 61 insertions(+), 19 deletions(-) (limited to 'src/sbefw') diff --git a/src/sbefw/core/sberegaccess.C b/src/sbefw/core/sberegaccess.C index 03ffd852..1ac5deac 100644 --- a/src/sbefw/core/sberegaccess.C +++ b/src/sbefw/core/sberegaccess.C @@ -5,7 +5,8 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ +/* [+] International Business Machines Corp. */ /* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ @@ -135,7 +136,7 @@ uint32_t SbeRegAccess::init() #define SBE_FUNC "SbeRegAccess::SbeRegAccess " static bool l_initDone = false; uint32_t rc = 0; - uint64_t l_mbx8 = 0; + do { if(l_initDone) @@ -150,16 +151,14 @@ uint32_t SbeRegAccess::init() rc); break; } - // Read Mailbox register 8 to check if the mailbox registers 3 and 6 are - // valid - rc = getscom_abs(PERV_SCRATCH_REGISTER_8_SCOM, &l_mbx8); + // Read Mailbox register 8 to check if mbox registers 3 and 6 are valid + rc = getscom_abs(PERV_SCRATCH_REGISTER_8_SCOM, &iv_mbx8); if(PCB_ERROR_NONE != rc) { - SBE_ERROR(SBE_FUNC"Failed reading mailbox reg 7, RC: 0x%08X. ", - rc); + SBE_ERROR(SBE_FUNC"Failed reading mailbox reg 8, RC: 0x%08X. ", rc); break; } - if(l_mbx8 & SBE_MBX8_MBX3_VALID_MASK) + if(iv_mbx3_valid) { // Read MBX3 rc = getscom_abs(PERV_SCRATCH_REGISTER_3_SCOM, &iv_mbx3); @@ -178,7 +177,7 @@ uint32_t SbeRegAccess::init() l_attr); iv_mbx3 = ((uint64_t) l_attr ) << 32; } - if(l_mbx8 & SBE_MBX8_MBX6_VALID_MASK) + if(iv_mbx6_valid) { // Read MBX6 rc = getscom_abs(PERV_SCRATCH_REGISTER_6_SCOM, &iv_mbx6); @@ -212,7 +211,7 @@ uint32_t SbeRegAccess::init() } while(false); SBE_INFO(SBE_FUNC"Read mailbox registers: mbx8: 0x%08X, mbx3: 0x%08X, " - "mbx6: 0x%08X", (uint32_t)(l_mbx8 >> 32), + "mbx6: 0x%08X", (uint32_t)(iv_mbx8 >> 32), (uint32_t)(iv_mbx3 >> 32), (uint32_t)(iv_mbx6 >> 32)); l_initDone = true; return rc; @@ -354,3 +353,18 @@ uint32_t SbeRegAccess::updateAsyncFFDCBit( bool i_on ) #undef SBE_FUNC } +bool SbeRegAccess::isSbeRegressionBit() +{ + #define SBE_FUNC "SbeRegAccess::isSbeRegressionBit" + bool isDisableInvalidScomAddrCheck = false; + uint8_t readData; + fapi2::Target FAPI_SYSTEM; + + FAPI_ATTR_GET(fapi2::ATTR_SECURITY_MODE, FAPI_SYSTEM, readData); + if((iv_mbx3_valid) && !readData && iv_disableInvalidScomAddrCheck) + { + isDisableInvalidScomAddrCheck = true; + } + return isDisableInvalidScomAddrCheck; + #undef SBE_FUNC +} diff --git a/src/sbefw/core/sberegaccess.H b/src/sbefw/core/sberegaccess.H index a51f6e81..cff354b3 100644 --- a/src/sbefw/core/sberegaccess.H +++ b/src/sbefw/core/sberegaccess.H @@ -248,12 +248,21 @@ class SbeRegAccess * */ uint32_t updateAsyncFFDCBit( bool i_on ); + + /** + * @brief Check if Invalid Scom Addr Check is not required + * + * @return true - skip invalid scom address check + * false - do invalid scom address check + */ + bool isSbeRegressionBit(); + private: /** * @brief Constructor */ - SbeRegAccess() : iv_mbx3(0), iv_mbx6(0), iv_messagingReg(0) + SbeRegAccess() : iv_mbx3(0), iv_mbx6(0), iv_messagingReg(0), iv_mbx8(0) {} union @@ -266,7 +275,9 @@ class SbeRegAccess uint64_t iv_fspAttached : 1; uint64_t iv_collectFFDC : 1; uint64_t iv_sendFFDC : 1; - uint64_t iv_mbx3DontCare : 26; + uint64_t iv_mbx3DontCare1 : 6; + uint64_t iv_disableInvalidScomAddrCheck : 1; + uint64_t iv_mbx3DontCare : 19; uint64_t iv_mbx3Unused : 32; }; uint64_t iv_mbx3; @@ -301,10 +312,21 @@ class SbeRegAccess uint64_t iv_messagingReg; }; + union + { + struct + { + uint64_t iv_mbox8Reserve1 : 2; + uint64_t iv_mbx3_valid : 1; + uint64_t iv_mbox8Reserve2 : 2; + uint64_t iv_mbx6_valid : 1; + uint64_t iv_mbox8Reserve3 : 58; + }; + uint64_t iv_mbx8; + }; + // Bit masks defining bits in the above registers that the SBE is // interested in - static const uint64_t SBE_MBX8_MBX3_VALID_MASK = 0x2000000000000000ULL; - static const uint64_t SBE_MBX8_MBX6_VALID_MASK = 0x0400000000000000ULL; static const uint64_t SBE_DEV_ID_C4_PIN_MASK = 0x0000000000800000ULL; static const uint64_t SBE_PERV_DEVICE_ID_REG_BIT58_MASK = 0x0000000000000020ULL; static SbeRegAccess cv_instance; diff --git a/src/sbefw/core/sbescom.C b/src/sbefw/core/sbescom.C index e03f8412..cd2f0ca1 100644 --- a/src/sbefw/core/sbescom.C +++ b/src/sbefw/core/sbescom.C @@ -30,6 +30,7 @@ #include "plat_target.H" #include "sbescom.H" #include "sbeSecurity.H" +#include "sberegaccess.H" using namespace fapi2; /** @@ -88,12 +89,17 @@ void checkIndirectAndDoScom( const bool i_isRead, // SBE throws data storage exception if Master ID field is not 0. Also // we halt sbe for SBE address space errors. So check these registers // at top level so that we do not halt SBE in these cases. - if(( i_addr & SCOM_SBE_ADDR_MASK) || ( i_addr & SCOM_MASTER_ID_MASK )) + + // Override bit check for invalid Scom Addr check + if(!SbeRegAccess::theSbeRegAccess().isSbeRegressionBit()) { - SBE_ERROR(SBE_FUNC "Invalid scom"); - o_hdr->setStatus(SBE_PRI_USER_ERROR, - SBE_SEC_INVALID_ADDRESS_PASSED); - break; + if(( i_addr & SCOM_SBE_ADDR_MASK) || ( i_addr & SCOM_MASTER_ID_MASK )) + { + SBE_ERROR(SBE_FUNC "Invalid scom"); + o_hdr->setStatus(SBE_PRI_USER_ERROR, + SBE_SEC_INVALID_ADDRESS_PASSED); + break; + } } #endif // __ALLOW_INVALID_SCOMS__ // If the indirect scom bit is 0, then doing a regular scom -- cgit v1.2.1