From ee19a0c9e042e3b459a53f5cfdf037a1ca4219b0 Mon Sep 17 00:00:00 2001 From: Anusha Reddy Rangareddygari Date: Wed, 15 Mar 2017 07:25:46 +0100 Subject: literal definitions instead of constants in the optimized procs Change-Id: I761ec79dc173465cd502844b6e2da7eff7dd800c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37954 Tested-by: Jenkins Server Tested-by: Hostboot CI Tested-by: PPE CI Reviewed-by: Soma Bhanutej Reviewed-by: SRINIVAS V. POLISETTY Reviewed-by: PARVATHI RACHAKONDA Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38024 Reviewed-by: Hostboot Team Tested-by: FSP CI Jenkins Reviewed-by: Sachin Gupta --- .../procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C | 26 ++++----- .../p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C | 64 +++++++++++----------- .../procedures/hwp/perv/p9_sbe_nest_startclocks.C | 29 +++++----- .../hwp/perv/p9_sbe_startclock_chiplets.C | 8 +-- 4 files changed, 65 insertions(+), 62 deletions(-) (limited to 'src/import') diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C index 357133b8..36e31acf 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_pll_setup.C @@ -102,7 +102,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const { uint32_t l_chipletID = mc.getChipletNumber(); - if( l_chipletID == 7 || l_chipletID == 8 ) + if( l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID ) { FAPI_DBG("Drop PDLY bypass"); FAPI_TRY(p9_sbe_chiplet_pll_setup_mc_pdly_dcc_bypass(mc, true, false)); @@ -120,7 +120,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const // PCIe uint32_t l_chipletID = pcie.getChipletNumber(); - if( l_chipletID >= 13 && l_chipletID <= 15 ) + if( l_chipletID >= PCI0_CHIPLET_ID && l_chipletID <= PCI2_CHIPLET_ID ) { FAPI_DBG("call clock start stop module and drop syncclk muxsel"); FAPI_TRY(p9_sbe_chiplet_pll_setup_strt_pci_nsl_drp_synclk_mux( pcie )); @@ -134,8 +134,8 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const // OBUS, XBUS, MC uint32_t l_chipletID = targ.getChipletNumber(); - if(l_chipletID == 6 || (l_chipletID >= 9 && l_chipletID <= 12) || - ((!l_read_attr) && (l_chipletID == 7 || l_chipletID == 8)) ) + if(l_chipletID == XB_CHIPLET_ID || (l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID) || + ((!l_read_attr) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID)) ) { FAPI_DBG("release pll test enable for except pcie"); FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_test_enable(targ)); @@ -147,9 +147,9 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const // OBUS, XBUS, PCIe, MC uint32_t l_chipletID = targ.getChipletNumber(); - if(l_chipletID == 6 || (l_chipletID >= 9 && l_chipletID <= 12) || - (l_chipletID >= 13 && l_chipletID <= 15) || - ((!l_read_attr) && (l_chipletID == 7 || l_chipletID == 8)) ) + if(l_chipletID == XB_CHIPLET_ID || (l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID) || + (l_chipletID >= PCI0_CHIPLET_ID && l_chipletID <= PCI2_CHIPLET_ID) || + ((!l_read_attr) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID)) ) { FAPI_DBG("Release PLL reset"); FAPI_TRY(p9_sbe_chiplet_pll_setup_pll_reset(targ)); @@ -161,7 +161,7 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const // PCIe uint32_t l_chipletID = pcie.getChipletNumber(); - if( l_chipletID >= 13 && l_chipletID <= 15 ) + if( l_chipletID >= PCI0_CHIPLET_ID && l_chipletID <= PCI2_CHIPLET_ID ) { FAPI_DBG("Check pll lock for pcie"); FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pll_lock(pcie, true)); @@ -173,8 +173,8 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const // OBUS, XBUS, MC uint32_t l_chipletID = targ.getChipletNumber(); - if(l_chipletID == 6 || (l_chipletID >= 9 && l_chipletID <= 12) || - ((!l_read_attr) && (l_chipletID == 7 || l_chipletID == 8)) ) + if(l_chipletID == XB_CHIPLET_ID || (l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID) || + ((!l_read_attr) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID)) ) { FAPI_DBG("check pll lock for Mc,Xb,Ob"); FAPI_TRY(p9_sbe_chiplet_pll_setup_check_pll_lock(targ, false)); @@ -187,9 +187,9 @@ fapi2::ReturnCode p9_sbe_chiplet_pll_setup(const // OBUS, XBUS, PCIe, MC uint32_t l_chipletID = targ.getChipletNumber(); - if(l_chipletID == 6 || (l_chipletID >= 9 && l_chipletID <= 12) || - (l_chipletID >= 13 && l_chipletID <= 15) || - ((!l_read_attr) && (l_chipletID == 7 || l_chipletID == 8)) ) + if(l_chipletID == XB_CHIPLET_ID || (l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID) || + (l_chipletID >= PCI0_CHIPLET_ID && l_chipletID <= PCI2_CHIPLET_ID) || + ((!l_read_attr) && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID)) ) { FAPI_TRY(p9_sbe_chiplet_pll_setup_function(targ, l_bypass)); } diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C index 02850609..2492bce4 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C @@ -172,7 +172,7 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const { uint32_t l_chipletID = obus.getChipletNumber(); - if(l_chipletID >= 9 && l_chipletID <= 12) + if(l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID) { FAPI_TRY(p9_sbe_chiplet_reset_all_obus_scan0(obus)); } @@ -222,7 +222,7 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const // responsive. Wait until clocks are started up in hostboot uint32_t l_chipletID = targ.getChipletNumber(); - if((l_chipletID >= 7 && l_chipletID <= 8) && (!l_mc_sync_mode)) + if((l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID) && (!l_mc_sync_mode)) { continue; } @@ -250,19 +250,19 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const uint32_t l_chipletID = targ.getChipletNumber(); // MC & XBUS - if((l_chipletID >= 7 && l_chipletID <= 8) || (l_chipletID == 6)) + if((l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID) || (l_chipletID == XB_CHIPLET_ID )) { FAPI_DBG("Mux settings for Mc/Xbus chiplet"); FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_MC_XBUS(targ, l_read_attr)); } // OBUS - else if(l_chipletID >= 9 && l_chipletID <= 12) + else if(l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID) { FAPI_DBG("Mux settings for OB chiplet"); FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_obus(targ, l_read_attr)); } // PCI - else if(l_chipletID >= 13 && l_chipletID <= 15) + else if(l_chipletID >= PCI0_CHIPLET_ID && l_chipletID <= PCI2_CHIPLET_ID) { FAPI_DBG("Mux settings for Pcie chiplet"); FAPI_TRY(p9_sbe_chiplet_reset_clk_mux_pcie(targ, l_read_attr)); @@ -276,7 +276,7 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const { uint32_t l_chipletID = targ.getChipletNumber(); - if(l_chipletID >= 2 && l_chipletID <= 5) + if(l_chipletID >= N0_CHIPLET_ID && l_chipletID <= N3_CHIPLET_ID) { continue; } @@ -293,13 +293,13 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const FAPI_DBG("PLL Setup : Enable pll"); FAPI_TRY(p9_sbe_chiplet_reset_pll_setup(targ, true)); - if(l_chipletID == 5) + if(l_chipletID == N3_CHIPLET_ID) { FAPI_DBG("Drop clk async reset for N3 chiplet"); FAPI_TRY(p9_sbe_chiplet_reset_nest_ob_async_reset(targ)); } - if(l_chipletID >= 7 && l_chipletID <= 8) + if(l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID) { FAPI_DBG("Drop clk async reset for Mc chiplet"); FAPI_TRY(p9_sbe_chiplet_reset_mc_async_reset_setup(targ, true)); @@ -321,7 +321,7 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const // MC uint32_t l_chipletID = targ.getChipletNumber(); - if(l_chipletID >= 7 && l_chipletID <= 8) + if(l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID) { FAPI_DBG("Raise clk async reset for Mc chiplet"); FAPI_TRY(p9_sbe_chiplet_reset_mc_async_reset_setup(targ, false)); @@ -333,7 +333,7 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const // OBUS uint32_t l_chipletID = targ.getChipletNumber(); - if(l_chipletID >= 9 && l_chipletID <= 12) + if(l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID) { FAPI_DBG("Drop clk async reset for N3, Mc and Obus chiplets"); FAPI_TRY(p9_sbe_chiplet_reset_nest_ob_async_reset(targ)); @@ -345,7 +345,7 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const //MC uint32_t l_chipletID = targ.getChipletNumber(); - if(l_chipletID >= 7 && l_chipletID <= 8) + if(l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID) { FAPI_DBG("Drop clk_div_bypass for Mc chiplet"); FAPI_TRY(p9_sbe_chiplet_reset_div_clk_bypass(targ)); @@ -379,7 +379,7 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const { uint32_t l_chipletID = targ.getChipletNumber(); - if(l_chipletID >= 7 && l_chipletID <= 8) + if(l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID) { continue; } @@ -393,7 +393,7 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const { uint32_t l_chipletID = targ.getChipletNumber(); - if(l_chipletID >= 2 && l_chipletID <= 5) + if(l_chipletID >= N0_CHIPLET_ID && l_chipletID <= N3_CHIPLET_ID) { continue; } @@ -411,7 +411,7 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const //PCI uint32_t l_chipletID = targ.getChipletNumber(); - if(l_chipletID >= 13 && l_chipletID <= 15) + if(l_chipletID >= PCI0_CHIPLET_ID && l_chipletID <= PCI2_CHIPLET_ID) { FAPI_DBG("Setup IOP Logic for PCIe"); FAPI_TRY(p9_sbe_chiplet_reset_setup_iop_logic(targ)); @@ -430,7 +430,8 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const // NEST MC uint32_t l_chipletID = targ.getChipletNumber(); - if((l_chipletID >= 2 && l_chipletID <= 5) || (l_chipletID >= 7 && l_chipletID <= 8)) + if((l_chipletID >= N0_CHIPLET_ID && l_chipletID <= N3_CHIPLET_ID) || + (l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID)) { FAPI_TRY(p9_sbe_chiplet_reset_opcg_cnfg_scan_ratio(targ)); } @@ -443,7 +444,7 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const // NEST uint32_t l_chipletID = targ.getChipletNumber(); - if(l_chipletID >= 2 && l_chipletID <= 5) + if(l_chipletID >= N0_CHIPLET_ID && l_chipletID <= N3_CHIPLET_ID) { FAPI_TRY(p9_sbe_chiplet_reset_opcg_cnfg_scan_ratio(targ)); } @@ -532,27 +533,28 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup( uint32_t l_chipletID = i_target_cplt.getChipletNumber(); // MC Perv Targets || PCI Perv Targets - if((l_chipletID >= 7 && l_chipletID < 9) || (l_chipletID >= 13 && l_chipletID < 16)) + if((l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID) || (l_chipletID >= PCI0_CHIPLET_ID + && l_chipletID <= PCI2_CHIPLET_ID)) { i_reg0_val = p9SbeChipletReset::HANG_PULSE_0X10; i_reg6_val = p9SbeChipletReset::HANG_PULSE_0X10; } // OBUS & XBUS Perv Targets - else if((l_chipletID == 6) || (l_chipletID >= 9 && l_chipletID < 13)) + else if((l_chipletID == XB_CHIPLET_ID) || (l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID)) { i_reg0_val = p9SbeChipletReset::HANG_PULSE_0X10; i_reg1_val = p9SbeChipletReset::HANG_PULSE_0X04; i_reg6_val = p9SbeChipletReset::HANG_PULSE_0X10; } // Core Perv Target - else if(l_chipletID >= 0x20 && l_chipletID < 0x38) + else if(l_chipletID >= EC0_CHIPLET_ID && l_chipletID <= EC23_CHIPLET_ID) { i_reg0_val = p9SbeChipletReset::HANG_PULSE_0X10; i_reg5_val = p9SbeChipletReset::HANG_PULSE_0X06; i_reg6_val = p9SbeChipletReset::HANG_PULSE_0X10; } // Cache Perv Target - else if(l_chipletID >= 0x10 && l_chipletID < 0x16) + else if(l_chipletID >= EQ0_CHIPLET_ID && l_chipletID <= EQ5_CHIPLET_ID) { i_reg0_val = p9SbeChipletReset::HANG_PULSE_0X10; i_reg1_val = p9SbeChipletReset::HANG_PULSE_0X01; @@ -564,7 +566,7 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup( } // NEST Perv Target - else if(l_chipletID >= 2 && l_chipletID < 6) + else if(l_chipletID >= N0_CHIPLET_ID && l_chipletID <= N3_CHIPLET_ID) { i_reg0_val = p9SbeChipletReset::HANG_PULSE_0X10; i_reg5_val = p9SbeChipletReset::HANG_PULSE_0X06; @@ -642,7 +644,7 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup( } // Core Perv Target - if(l_chipletID >= 0x20 && l_chipletID < 0x38) + if(l_chipletID >= EC0_CHIPLET_ID && l_chipletID <= EC23_CHIPLET_ID) { //Setting HANG_PULSE_1_REG register value (Setting all fields) //HANG_PULSE_1_REG.HANG_PULSE_REG_1 = p9SbeChipletReset::HANG_PULSE_0X1A @@ -652,7 +654,7 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_all_cplt_hang_cnt_setup( } // NEST Perv Target - if(l_chipletID >= 2 && l_chipletID < 6) + if(l_chipletID >= N0_CHIPLET_ID && l_chipletID <= N3_CHIPLET_ID) { // Collecting partial good and chiplet unit position attribute FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, i_target_cplt, @@ -786,7 +788,7 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_clk_mux_MC_XBUS( FAPI_TRY(fapi2::getScom(i_target_chiplet, PERV_NET_CTRL1, l_data64)); //NET_CTRL1.PLL_CLKIN_SEL = i_clk_mux_value.getBit<3>() - if(l_chipletID >= 7 && l_chipletID < 9) //MC + if(l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID) //MC { l_data64.writeBit(i_clk_mux_value.getBit<3>()); } @@ -1080,27 +1082,27 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_setup( uint32_t l_chipletID = i_target_chiplet.getChipletNumber(); // Core - if(l_chipletID >= 0x20 && l_chipletID <= 0x37) + if(l_chipletID >= EC0_CHIPLET_ID && l_chipletID <= EC23_CHIPLET_ID) { i_mc_grp1_val = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0; i_mc_grp2_val = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP1; i_mc_grp3_val = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP3; } // Nest/Obus/PCI/Xbus - else if((l_chipletID == 6) || (l_chipletID >= 9 && l_chipletID <= 12) || - (l_chipletID >= 13 && l_chipletID <= 15) || - (l_chipletID >= 2 && l_chipletID <= 5)) + else if((l_chipletID == XB_CHIPLET_ID) || (l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID) || + (l_chipletID >= PCI0_CHIPLET_ID && l_chipletID <= PCI2_CHIPLET_ID) || + (l_chipletID >= N0_CHIPLET_ID && l_chipletID <= N3_CHIPLET_ID)) { i_mc_grp1_val = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0; } // MC - else if(l_chipletID >= 7 && l_chipletID <= 8) + else if(l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID) { i_mc_grp1_val = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0; i_mc_grp2_val = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP2; } // Cache - else if(l_chipletID >= 0x10 && l_chipletID <= 0x15) + else if(l_chipletID >= EQ0_CHIPLET_ID && l_chipletID <= EQ5_CHIPLET_ID) { i_mc_grp1_val = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP0; i_mc_grp2_val = p9SbeChipletReset::MCGR_CNFG_SETTING_GROUP4; @@ -1128,7 +1130,7 @@ static fapi2::ReturnCode p9_sbe_chiplet_reset_mc_setup( } // Only For Cache - if(l_chipletID >= 0x10 && l_chipletID <= 0x15) + if(l_chipletID >= EQ0_CHIPLET_ID && l_chipletID <= EQ5_CHIPLET_ID) { uint16_t l_attr_pg = 0; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PG, i_target_chiplet, l_attr_pg)); diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C index 3b89b8ff..d37166de 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_nest_startclocks.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2016 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -91,7 +91,7 @@ fapi2::ReturnCode p9_sbe_nest_startclocks(const // NEST WEST for (auto& nest : l_perv_nest_mc_func) { - if(nest.getChipletNumber() == 5) + if(nest.getChipletNumber() == N3_CHIPLET_ID) { FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(nest, REGIONS_ALL_EXCEPT_VITAL_NESTPLL, l_n3_clock_regions)); @@ -107,10 +107,11 @@ fapi2::ReturnCode p9_sbe_nest_startclocks(const { uint32_t l_chipletID = perv.getChipletNumber(); - if( ((l_chipletID == 5) && (l_pg_vector.getBit<1>() == 1)) || - ((l_chipletID == 2 || l_chipletID == 3 || l_chipletID == 4) && (l_pg_vector.getBit<5>() == 1)) || - (l_read_attr && ((l_chipletID == 7) && (l_pg_vector.getBit<5>() == 1))) || - (l_read_attr && (l_chipletID == 8) && (l_pg_vector.getBit<3>() == 1)) ) + if( ((l_chipletID == N3_CHIPLET_ID) && (l_pg_vector.getBit<1>() == 1)) || + ((l_chipletID == N0_CHIPLET_ID || l_chipletID == N1_CHIPLET_ID || l_chipletID == N2_CHIPLET_ID) + && (l_pg_vector.getBit<5>() == 1)) || + (l_read_attr && ((l_chipletID == MC01_CHIPLET_ID) && (l_pg_vector.getBit<5>() == 1))) || + (l_read_attr && (l_chipletID == MC23_CHIPLET_ID) && (l_pg_vector.getBit<3>() == 1)) ) { FAPI_DBG("Drop chiplet fence for N3 // N0,N1,N2 // MC"); FAPI_TRY(p9_sbe_nest_startclocks_nest_fence_drop(perv)); @@ -121,7 +122,7 @@ fapi2::ReturnCode p9_sbe_nest_startclocks(const { uint32_t l_chipletID = perv.getChipletNumber(); - if(!l_read_attr && (l_chipletID == 7 || l_chipletID == 8)) + if(!l_read_attr && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID)) { continue; } @@ -139,7 +140,7 @@ fapi2::ReturnCode p9_sbe_nest_startclocks(const { uint32_t l_chipletID = perv.getChipletNumber(); - if(l_chipletID == 2 || l_chipletID == 3 || l_chipletID == 4) + if(l_chipletID == N0_CHIPLET_ID || l_chipletID == N1_CHIPLET_ID || l_chipletID == N2_CHIPLET_ID) { FAPI_DBG("Regions value: %#018lX", l_clock_regions); FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(perv, @@ -150,7 +151,7 @@ fapi2::ReturnCode p9_sbe_nest_startclocks(const DONT_STARTMASTER, l_clock_regions, CLOCK_TYPES)); } - if(l_chipletID == 5) + if(l_chipletID == N3_CHIPLET_ID) { FAPI_TRY(p9_sbe_common_clock_start_stop(perv, CLOCK_CMD, DONT_STARTSLAVE, STARTMASTER, l_n3_clock_regions, CLOCK_TYPES)); @@ -161,7 +162,7 @@ fapi2::ReturnCode p9_sbe_nest_startclocks(const { uint32_t l_chipletID = perv.getChipletNumber(); - if(l_chipletID == 2 || l_chipletID == 3 || l_chipletID == 4) + if(l_chipletID == N0_CHIPLET_ID || l_chipletID == N1_CHIPLET_ID || l_chipletID == N2_CHIPLET_ID) { FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16(perv, REGIONS_ALL_EXCEPT_VITAL_NESTPLL, l_ccstatus_regions)); @@ -172,7 +173,7 @@ fapi2::ReturnCode p9_sbe_nest_startclocks(const l_ccstatus_regions, CLOCK_TYPES)); } - if(l_chipletID == 5) + if(l_chipletID == N3_CHIPLET_ID) { FAPI_DBG("Call clockstatus check function for N3"); FAPI_TRY(p9_sbe_common_check_cc_status_function(perv, CLOCK_CMD, @@ -185,7 +186,7 @@ fapi2::ReturnCode p9_sbe_nest_startclocks(const // MC uint32_t l_chipletID = perv.getChipletNumber(); - if( l_read_attr && (l_chipletID == 7 || l_chipletID == 8) ) + if( l_read_attr && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID) ) { FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(perv, REGIONS_ALL_EXCEPT_VITAL_NESTPLL, l_clock_regions)); @@ -201,12 +202,12 @@ fapi2::ReturnCode p9_sbe_nest_startclocks(const { uint32_t l_chipletID = perv.getChipletNumber(); - if(l_chipletID == 5 && l_read_flush_attr) + if(l_chipletID == N3_CHIPLET_ID && l_read_flush_attr) { continue; } - if(!l_read_attr && (l_chipletID == 7 || l_chipletID == 8)) + if(!l_read_attr && (l_chipletID == MC01_CHIPLET_ID || l_chipletID == MC23_CHIPLET_ID)) { continue; } diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C index 5829359a..c85cea34 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_startclock_chiplets.C @@ -189,16 +189,16 @@ fapi2::ReturnCode p9_sbe_startclock_chiplets(const // XBUS, OBUS, PCIe uint32_t l_chipletID = targ.getChipletNumber(); - if(((l_chipletID == 6) && (l_pg_vector.getBit<2>() == 1)) || - ((l_chipletID >= 9 && l_chipletID <= 12) && (l_pg_vector.getBit<3>() == 1)) || - ((l_chipletID >= 13 && l_chipletID <= 15) && (l_pg_vector.getBit<4>() == 1))) + if(((l_chipletID == XB_CHIPLET_ID) && (l_pg_vector.getBit<2>() == 1)) || + ((l_chipletID >= OB0_CHIPLET_ID && l_chipletID <= OB3_CHIPLET_ID) && (l_pg_vector.getBit<3>() == 1)) || + ((l_chipletID >= PCI0_CHIPLET_ID && l_chipletID <= PCI2_CHIPLET_ID) && (l_pg_vector.getBit<4>() == 1))) { FAPI_DBG("Drop chiplet fence for XB // OBUS // PCIe"); FAPI_TRY(p9_sbe_startclock_chiplets_fence_drop(targ)); } // skip dropping flushmode inhbit if PCIE chiplet - if (!(l_chipletID >= 13) && (l_chipletID <= 15)) + if (!(l_chipletID >= PCI0_CHIPLET_ID) && (l_chipletID <= PCI2_CHIPLET_ID)) { FAPI_DBG("call sbe_common_flushmode for xbus, obus chiplets"); FAPI_TRY(p9_sbe_common_flushmode(targ)); -- cgit v1.2.1