From d548b0c2ecac66b0d0afc7a65f9a1bdfdb734ab2 Mon Sep 17 00:00:00 2001 From: Soma BhanuTej Date: Thu, 29 Sep 2016 02:51:13 -0400 Subject: Fixing MC & EP attr_pg for sc model config - p9_sbe_attr.xml Change-Id: I32cbda6253d63573229dc65a97103158c892b8b5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30455 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Martin Gloff Reviewed-by: Sachin Gupta Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30456 Reviewed-by: Hostboot Team --- .../chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/import') diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml index f38be59b..2cd6df38 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml @@ -128,7 +128,7 @@ partial good. If this bit is 1, the region is bad, else it is good. Bits 0,1,2 are don't care. For nimbus, pervasive chiplets 10 and 11 are not used (OB1 and OB2), therefore the value for them is 0xFFFF --> - ATTR_PG + ATTR_PG 0xFFFF 0xE07D 0xE03F @@ -136,8 +136,8 @@ 0xE03F 0xE01F 0xE44D - 0xE0FD - 0xE0FD + 0xE1FD + 0xE1FD 0xE1FD 0xFFFF 0xFFFF @@ -148,7 +148,7 @@ 0xE001 0xE001 0xE001 - 0xE288 + 0xE289 0xE001 0xE001 0xFFFF -- cgit v1.2.1