From 618c88eba551a9a971b8873a3ec1e9a13230f93e Mon Sep 17 00:00:00 2001 From: Andre Marin Date: Fri, 28 Apr 2017 17:15:31 -0500 Subject: Add DLL workaround and unit tests Change-Id: I142ecd417abb92f4f8ec7d3748563b30359c486d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39673 Tested-by: Jenkins Server Reviewed-by: STEPHEN GLANCY Tested-by: PPE CI Dev-Ready: ANDRE A. MARIN Tested-by: Hostboot CI Reviewed-by: Matt K. Light Reviewed-by: Thi N. Tran Reviewed-by: Louis Stermole Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39726 Reviewed-by: Hostboot Team Tested-by: FSP CI Jenkins Reviewed-by: Sachin Gupta --- .../xml/attribute_info/chip_ec_attributes.xml | 127 ++++++++++++--------- 1 file changed, 73 insertions(+), 54 deletions(-) (limited to 'src/import') diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 7d4c58e6..3830464d 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -2702,15 +2702,11 @@ - - - - ATTR_CHIP_EC_FEATURE_MSS_UT_EC_NIMBUS_LESS_THAN_TWO_OH + ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE TARGET_TYPE_PROC_CHIP - Attribute used only for memory subsystem unit tests. Tells us whether - the chip EC we're running on is less than 2.0 and we're on a Nimbus + Data integrity issue requires us to disable clockgate in read array for Nimbus DD1.0 @@ -2724,11 +2720,10 @@ - ATTR_CHIP_EC_FEATURE_MCBIST_END_OF_RANK + ATTR_CHIP_EC_FEATURE_HW400075 TARGET_TYPE_PROC_CHIP - MCBIST has a bug where it won't detect the end of a rank properly for - a 1R DIMM during super-fast read. + Addresses issue where MDI bit was getting wrong values with threadmill and transactional data resulting in coherency issues. @@ -2742,10 +2737,10 @@ - ATTR_CHIP_EC_FEATURE_MSS_WR_VREF + ATTR_CHIP_EC_FEATURE_HW398139 TARGET_TYPE_PROC_CHIP - In DD1 Nimbus in the WR VREF algorithm, certain work-arounds are needed + Avoid powerbus early hangs by enabling prefetch drops to break out of fairness issue with prefetch ops @@ -2759,10 +2754,10 @@ - ATTR_CHIP_EC_FEATURE_MSS_DQS_POLARITY + ATTR_CHIP_EC_FEATURE_HW400932 TARGET_TYPE_PROC_CHIP - For Monza DDR port 2, one pair of DQS P/N is swapped polarity. + ATAG info corruption on presp issue requires us to disable clockgate for Nimbus DD1.0 @@ -2776,10 +2771,10 @@ - ATTR_CHIP_EC_FEATURE_MSS_VREF_DAC + ATTR_CHIP_EC_FEATURE_HW401780 TARGET_TYPE_PROC_CHIP - VREF DAC work-around for Nimbus DD1.0 + Need AMO caching disabled for multiple defects until Nimbus DD2.0 @@ -2793,10 +2788,10 @@ - ATTR_CHIP_EC_FEATURE_MSS_WAT_DEBUG_ATTN + ATTR_CHIP_EC_FEATURE_HW406577 TARGET_TYPE_PROC_CHIP - WAT Debug Attention work-around for Nimbus DD1.0 + Noise window disabled in DD1 because continually reocurring intermittent UE's can cause us to hang on refreshes. @@ -2809,11 +2804,15 @@ + + + - ATTR_CHIP_EC_FEATURE_MSS_HW392781_RDARRAY_CLKGATE + ATTR_CHIP_EC_FEATURE_MCBIST_END_OF_RANK TARGET_TYPE_PROC_CHIP - Data integrity issue requires us to disable clockgate in read array for Nimbus DD1.0 + MCBIST has a bug where it won't detect the end of a rank properly for + a 1R DIMM during super-fast read. @@ -2827,10 +2826,10 @@ - ATTR_CHIP_EC_FEATURE_HW400075 + ATTR_CHIP_EC_FEATURE_MSS_WAT_DEBUG_ATTN TARGET_TYPE_PROC_CHIP - Addresses issue where MDI bit was getting wrong values with threadmill and transactional data resulting in coherency issues. + WAT Debug Attention work-around for Nimbus DD1.0 @@ -2844,10 +2843,11 @@ - ATTR_CHIP_EC_FEATURE_HW398139 + ATTR_CHIP_EC_FEATURE_MSS_UT_EC_NIMBUS_LESS_THAN_TWO_OH TARGET_TYPE_PROC_CHIP - Avoid powerbus early hangs by enabling prefetch drops to break out of fairness issue with prefetch ops + Attribute used only for memory subsystem unit tests. Tells us whether + the chip EC we're running on is less than 2.0 and we're on a Nimbus @@ -2861,10 +2861,10 @@ - ATTR_CHIP_EC_FEATURE_HW384794 + ATTR_CHIP_EC_FEATURE_MSS_WR_VREF TARGET_TYPE_PROC_CHIP - Workaround for defect where clock enables to PHY were incorrectly driven + In DD1 Nimbus in the WR VREF algorithm, certain work-arounds are needed @@ -2878,10 +2878,10 @@ - ATTR_CHIP_EC_FEATURE_HW375732 + ATTR_CHIP_EC_FEATURE_MSS_DQS_POLARITY TARGET_TYPE_PROC_CHIP - Workaround for Data mismatch discovered by Geyzer at certain async frequency ratios + For Monza DDR port 2, one pair of DQS P/N is swapped polarity. @@ -2895,12 +2895,10 @@ - ATTR_CHIP_EC_FEATURE_MSS_TRAINING_BAD_BITS + ATTR_CHIP_EC_FEATURE_MSS_VREF_DAC TARGET_TYPE_PROC_CHIP - For Nimbus pre DD1.02 we want to pass DDR training if we see 'correctable' - errors. This isn't the case for post-DD1.02 where we want to pass/fail - training based on the results from the PHY itself + VREF DAC work-around for Nimbus DD1.0 @@ -2914,10 +2912,12 @@ - ATTR_CHIP_EC_FEATURE_HW400932 + ATTR_CHIP_EC_FEATURE_MSS_TRAINING_BAD_BITS TARGET_TYPE_PROC_CHIP - ATAG info corruption on presp issue requires us to disable clockgate for Nimbus DD1.0 + For Nimbus pre DD1.02 we want to pass DDR training if we see 'correctable' + errors. This isn't the case for post-DD1.02 where we want to pass/fail + training based on the results from the PHY itself @@ -2931,10 +2931,10 @@ - ATTR_CHIP_EC_FEATURE_HW401780 + ATTR_CHIP_EC_FEATURE_MSS_CHECK_DISABLE_HW_VREF_CAL TARGET_TYPE_PROC_CHIP - Need AMO caching disabled for multiple defects until Nimbus DD2.0 + In below DD2 Nimbus, the HW VREF calibration needs to be checked against the chip subversion to see if it can be run. @@ -2948,10 +2948,10 @@ - ATTR_CHIP_EC_FEATURE_HW406577 + ATTR_CHIP_EC_FEATURE_MSS_RUN_RD_CTR_WORKAROUND TARGET_TYPE_PROC_CHIP - Noise window disabled in DD1 because continually reocurring intermittent UE's can cause us to hang on refreshes. + In below DD2 Nimbus, a workaround after read centering might need to be run. @@ -2965,10 +2965,12 @@ - ATTR_CHIP_EC_FEATURE_MSS_CHECK_DISABLE_HW_VREF_CAL + ATTR_CHIP_EC_FEATURE_MSS_ODT_CONFIG TARGET_TYPE_PROC_CHIP - In below DD2 Nimbus, the HW VREF calibration needs to be checked against the chip subversion to see if it can be run. + For Nimbus pre DD2.** we need to swap ODT2 and ODT3 values in the + DDRPHY_SEQ_ODT_RD/WR_CONFIG registers due to a PHY erratum. + Post DD2.** will have a hardware enabled fix for this (HW389360). @@ -2982,10 +2984,11 @@ - ATTR_CHIP_EC_FEATURE_MSS_RUN_RD_CTR_WORKAROUND + ATTR_CHIP_EC_FEATURE_MSS_BLUE_WATERFALL_ADJUST TARGET_TYPE_PROC_CHIP - In below DD2 Nimbus, a workaround after read centering might need to be run. + In DD1.** Nimbus, the blue waterfall can calibrate to an incorrect value. In DD2 Nimbus, + This isn't the case as the HW will not allow this calibration value @@ -2999,12 +3002,10 @@ - ATTR_CHIP_EC_FEATURE_MSS_ODT_CONFIG + ATTR_CHIP_EC_FEATURE_MSS_CHECK_DIABLE_RD_VREF_CAL_VREFSENSE TARGET_TYPE_PROC_CHIP - For Nimbus pre DD2.** we need to swap ODT2 and ODT3 values in the - DDRPHY_SEQ_ODT_RD/WR_CONFIG registers due to a PHY erratum. - Post DD2.** will have a hardware enabled fix for this (HW389360). + In below DD2 Nimbus, the RD VREF cal VREF sense needs to be checked against the chip subversion to see if it should be run. @@ -3018,11 +3019,10 @@ - ATTR_CHIP_EC_FEATURE_MSS_BLUE_WATERFALL_ADJUST + ATTR_CHIP_EC_FEATURE_MSS_DLL_WORKAROUND TARGET_TYPE_PROC_CHIP - In DD1.** Nimbus, the blue waterfall can calibrate to an incorrect value. In DD2 Nimbus, - This isn't the case as the HW will not allow this calibration value + Run DLL workaround algorithm to fix bad voltage settings pre DD2.0 @@ -3053,12 +3053,32 @@ + + + - ATTR_CHIP_EC_FEATURE_MSS_CHECK_DIABLE_RD_VREF_CAL_VREFSENSE + ATTR_CHIP_EC_FEATURE_HW384794 TARGET_TYPE_PROC_CHIP - In below DD2 Nimbus, the RD VREF cal VREF sense needs to be checked against the chip subversion to see if it should be run. + Workaround for defect where clock enables to PHY were incorrectly driven + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + + + ATTR_CHIP_EC_FEATURE_HW375732 + TARGET_TYPE_PROC_CHIP + + Workaround for Data mismatch discovered by Geyzer at certain async frequency ratios @@ -3173,6 +3193,7 @@ + ATTR_CHIP_EC_FEATURE_HW399466 TARGET_TYPE_PROC_CHIP @@ -3190,6 +3211,7 @@ + ATTR_CHIP_EC_FEATURE_HW355538 TARGET_TYPE_PROC_CHIP @@ -3207,6 +3229,7 @@ + ATTR_CHIP_EC_FEATURE_NEW_MC_DD2_SETTINGS TARGET_TYPE_PROC_CHIP @@ -3224,10 +3247,6 @@ - - - - ATTR_CHIP_EC_FEATURE_DD1_ANALOG -- cgit v1.2.1