From 60fa6f5edfbdbba77c3e72fc1964cb2e22d394c0 Mon Sep 17 00:00:00 2001 From: "Luke C. Murray" Date: Tue, 5 Dec 2017 15:18:23 -0600 Subject: Enabling L2 64B store prediction Turning on the 64B store prediction inside the L2. This is a performance fix. Change-Id: I2e91747e2cf420ffa50efeb73b8876e54c89b8d6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50531 Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Hostboot CI Tested-by: FSP CI Jenkins Reviewed-by: Jenny Huynh Reviewed-by: Joseph J. McGill Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50542 Reviewed-by: Sachin Gupta --- .../xml/attribute_info/chip_ec_attributes.xml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'src/import') diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index 17eac69a..ccca23da 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -2465,6 +2465,23 @@ + + ATTR_CHIP_EC_FEATURE_DISABLE_64B_STORE> + TARGET_TYPE_PROC_CHIP + + Nimbus DD1 only: don't set 64B store, dials didn't exist + + + + ENUM_ATTR_NAME_NIMBUS + + 0x20 + LESS_THAN + + + + + ATTR_CHIP_EC_FEATURE_DISABLE_TLBIE_PACING> TARGET_TYPE_PROC_CHIP -- cgit v1.2.1