From 2edbcc69ae72dc0f4bb6862cdb0730e0b76d5588 Mon Sep 17 00:00:00 2001 From: Andre Marin Date: Wed, 27 Feb 2019 13:58:49 -0600 Subject: Add attribute engine algorithm for eff_config and pre_eff_config Change-Id: I2c89e6da17511462afbc661680d19df18a4708f4 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72962 Tested-by: FSP CI Jenkins Reviewed-by: Louis Stermole Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: Hostboot CI Reviewed-by: STEPHEN GLANCY Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80986 Reviewed-by: RAJA DAS Tested-by: RAJA DAS --- .../memory/lib/utils/shared/mss_generic_consts.H | 28 +++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) (limited to 'src/import/generic/memory/lib/utils') diff --git a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H index 4820624c..3e2a4808 100644 --- a/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H +++ b/src/import/generic/memory/lib/utils/shared/mss_generic_consts.H @@ -105,7 +105,7 @@ enum generic_ffdc_codes SET_ATTR_HYBRID = 0x1002, SET_ATTR_HYBRID_MEDIA = 0x1003, SET_ATTR_MASTER_RANKS = 0x1004, - PRE_DATA_ENGINE_CTOR = 0x1005, + SET_ATTR_RANKS_CONFIGED = 0x1005, GET_FIELD = 0x1006, READ_SPD_FIELD = 0x1007, BASE_CFG_PARAM_SELECT = 0x1008, @@ -144,9 +144,31 @@ enum generic_ffdc_codes SET_HYBRID_MEDIA = 0x1028, SET_MRANKS = 0x1029, SET_DIMM_RANKS_CNFG = 0x1039, - - // SPD fields function codes DDIMM_RAWCARD_DECODE = 0x103a, + SET_DRAM_WIDTH = 0x1040, + + SET_SI_VREF_DRAM_WR = 0x1041, + SET_SI_MC_RCV_IMP_DQ_DQS = 0x1042, + SET_SI_MC_DRV_IMP_DQ_DQS_PULL_UP = 0x1043, + SET_SI_MC_DRV_IMP_DQ_DQS_PULL_DOWN = 0x1044, + SET_SI_MC_DRV_SLEW_RATE_DQ_DQS = 0x1045, + SET_SI_MC_DRV_IMP_CMD_ADDR = 0x10466, + SET_SI_MC_DRV_SLEW_RATE_CMD_ADDR = 0x1047, + SET_SI_MC_DRV_IMP_CLK = 0x1048, + SET_SI_MC_DRV_SLEW_RATE_CLK = 0x1049, + SET_SI_MC_RCV_IMP_ALERT_N = 0x1050, + SET_SI_DRAM_RTT_NOM = 0x1051, + SET_SI_DRAM_RTT_WR = 0x1052, + SET_SI_DRAM_RTT_PARK = 0x1053, + SET_SI_DRAM_PREAMBLE = 0x1054, + SET_SI_MC_DRV_EQ_DQ_DQS = 0x1055, + SET_SI_DRAM_DRV_IMP_DQ_DQS = 0x1056, + SET_SI_VREF_DQ_TRAIN_RANGE = 0x1057, + SET_SI_VREF_DQ_TRAIN_VALUE = 0x1058, + SET_SI_ODT_WR = 0x1059, + SET_SI_ODT_RD = 0x1060, + SET_SI_GEARDOWN_MODE = 0x1061, + PRE_DATA_ENGINE_CTOR = 0x1062 }; /// -- cgit v1.2.3